cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__OS2__)
  44 #define INCL_DOS
  45 #include <os2.h>
  46 #elif defined(__AMIGAOS4__)
  47 #include <proto/exec.h>
  48 #endif
  49
  50 /* Thanks to the FreeBSD project for some of this cpuid code, and
  51  * help understanding how to use it.  Thanks to the Mesa
  52  * team for SSE support detection and more cpu detect code.
  53  */
  54
  55 /* I believe this code works.  However, it has only been used on a PII and PIII */
  56
  57 static void check_os_katmai_support( void );
  58
  59 // return TRUE if cpuid supported
  60 static int has_cpuid(void)
  61 {
  62 // code from libavcodec:
  63 #if ARCH_X86_64
  64    return 1;
  65 #else
  66    long a, c;
  67    __asm__ volatile (
  68        /* See if CPUID instruction is supported ... */
  69        /* ... Get copies of EFLAGS into eax and ecx */
  70        "pushfl\n\t"
  71        "pop %0\n\t"
  72        "mov %0, %1\n\t"
  73
  74        /* ... Toggle the ID bit in one copy and store */
  75        /*     to the EFLAGS reg */
  76        "xor $0x200000, %0\n\t"
  77        "push %0\n\t"
  78        "popfl\n\t"
  79
  80        /* ... Get the (hopefully modified) EFLAGS */
  81        "pushfl\n\t"
  82        "pop %0\n\t"
  83        : "=a" (a), "=c" (c)
  84        :
  85        : "cc"
  86        );
  87
  88    return a != c;
  89 #endif
  90 }
  91
  92 void
  93 do_cpuid(unsigned int ax, unsigned int *p)
  94 {
  95 // code from libavcodec:
  96     __asm__ volatile
  97         ("mov %%"REG_b", %%"REG_S"\n\t"
  98          "cpuid\n\t"
  99          "xchg %%"REG_b", %%"REG_S
 100          : "=a" (p[0]), "=S" (p[1]),
 101            "=c" (p[2]), "=d" (p[3])
 102          : "0" (ax));
 103 }
 104
 105 void GetCpuCaps( CpuCaps *caps)
 106 {
 107     unsigned int regs[4];
 108     unsigned int regs2[4];
 109
 110     memset(caps, 0, sizeof(*caps));
 111     caps->isX86=1;
 112     caps->cl_size=32; /* default */
 113     if (!has_cpuid()) {
 114         mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 115         return;
 116     }
 117     do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 118     mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 119             (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 120     if (regs[0]>=0x00000001)
 121     {
 122         char *tmpstr, *ptmpstr;
 123         unsigned cl_size;
 124
 125         do_cpuid(0x00000001, regs2);
 126
 127         caps->cpuType=(regs2[0] >> 8)&0xf;
 128         caps->cpuModel=(regs2[0] >> 4)&0xf;
 129
 130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 131 // System Instructions, Table 3-2: Effective family computation, page 120.
 132         if(caps->cpuType==0xf){
 133             // use extended family (P4, IA64, K8)
 134             caps->cpuType=0xf+((regs2[0]>>20)&255);
 135         }
 136         if(caps->cpuType==0xf || caps->cpuType==6)
 137             caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 138
 139         caps->cpuStepping=regs2[0] & 0xf;
 140
 141         // general feature flags:
 142         caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 143         caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 144         caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 145         caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 146         caps->hasSSE3 = (regs2[2] & 1);        // 0x0000001
 147         caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 148         caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 149         cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 150         if(cl_size) caps->cl_size = cl_size;
 151
 152         ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 153         while(*ptmpstr == ' ')    // strip leading spaces
 154             ptmpstr++;
 155         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 156         free(tmpstr);
 157         mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 158                caps->cpuType, caps->cpuModel, caps->cpuStepping);
 159
 160     }
 161     do_cpuid(0x80000000, regs);
 162     if (regs[0]>=0x80000001) {
 163         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 164         do_cpuid(0x80000001, regs2);
 165         caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 166         caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 167         caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 168         caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 169         caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 170     }
 171     if(regs[0]>=0x80000006)
 172     {
 173         do_cpuid(0x80000006, regs2);
 174         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 175         caps->cl_size  = regs2[2] & 0xFF;
 176     }
 177     mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 178 #if 0
 179     mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 180            gCpuCaps.hasMMX,
 181            gCpuCaps.hasMMX2,
 182            gCpuCaps.hasSSE,
 183            gCpuCaps.hasSSE2,
 184            gCpuCaps.has3DNow,
 185            gCpuCaps.has3DNowExt);
 186 #endif
 187
 188         /* FIXME: Does SSE2 need more OS support, too? */
 189         if (caps->hasSSE)
 190             check_os_katmai_support();
 191         if (!caps->hasSSE)
 192             caps->hasSSE2 = 0;
 193 //          caps->has3DNow=1;
 194 //          caps->hasMMX2 = 0;
 195 //          caps->hasMMX = 0;
 196
 197 #if !CONFIG_RUNTIME_CPUDETECT
 198 #if !HAVE_MMX
 199         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 200         caps->hasMMX=0;
 201 #endif
 202 #if !HAVE_MMX2
 203         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 204         caps->hasMMX2=0;
 205 #endif
 206 #if !HAVE_SSE
 207         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 208         caps->hasSSE=0;
 209 #endif
 210 #if !HAVE_SSE2
 211         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 212         caps->hasSSE2=0;
 213 #endif
 214 #if !HAVE_AMD3DNOW
 215         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 216         caps->has3DNow=0;
 217 #endif
 218 #if !HAVE_AMD3DNOWEXT
 219         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 220         caps->has3DNowExt=0;
 221 #endif
 222 #endif  // CONFIG_RUNTIME_CPUDETECT
 223 }
 224
 225 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 226     char vendor[13];
 227     char *retname;
 228     int i;
 229
 230     if (NULL==(retname=malloc(256))) {
 231         mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 232         exit(1);
 233     }
 234     retname[0] = '\0';
 235
 236     sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 237
 238     do_cpuid(0x80000000,regs);
 239     if (regs[0] >= 0x80000004)
 240     {
 241         // CPU has built-in namestring
 242         for (i = 0x80000002; i <= 0x80000004; i++)
 243         {
 244             do_cpuid(i, regs);
 245             strncat(retname, (char*)regs, 16);
 246         }
 247     }
 248     return retname;
 249 }
 250
 251 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 252 static void sigill_handler_sse( int signal, struct sigcontext sc )
 253 {
 254    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 255
 256    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 257     * instructions are 3 bytes long.  We must increment the instruction
 258     * pointer manually to avoid repeated execution of the offending
 259     * instruction.
 260     *
 261     * If the SIGILL is caused by a divide-by-zero when unmasked
 262     * exceptions aren't supported, the SIMD FPU status and control
 263     * word will be restored at the end of the test, so we don't need
 264     * to worry about doing it here.  Besides, we may not be able to...
 265     */
 266    sc.eip += 3;
 267
 268    gCpuCaps.hasSSE=0;
 269 }
 270 #endif /* __linux__ && _POSIX_SOURCE */
 271
 272 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
 273 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 274 {
 275     if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 276         mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 277         ep->ContextRecord->Eip +=3;
 278         gCpuCaps.hasSSE=0;
 279         return EXCEPTION_CONTINUE_EXECUTION;
 280     }
 281     return EXCEPTION_CONTINUE_SEARCH;
 282 }
 283 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 284
 285 #ifdef __OS2__
 286 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD       p1,
 287                                   PEXCEPTIONREGISTRATIONRECORD p2,
 288                                   PCONTEXTRECORD               p3,
 289                                   PVOID                        p4)
 290 {
 291     if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 292         mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 293
 294         p3->ctx_RegEip += 3;
 295         gCpuCaps.hasSSE = 0;
 296
 297         return XCPT_CONTINUE_EXECUTION;
 298     }
 299     return XCPT_CONTINUE_SEARCH;
 300 }
 301 #endif
 302
 303 /* If we're running on a processor that can do SSE, let's see if we
 304  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 305  * haven't been configured for a Pentium III but are running on one,
 306  * and RedHat patched 2.2 kernels that have broken exception handling
 307  * support for user space apps that do SSE.
 308  */
 309
 310 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 311 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 312 #elif defined(__APPLE__)
 313 #define SSE_SYSCTL_NAME "hw.optional.sse"
 314 #endif
 315
 316 static void check_os_katmai_support( void )
 317 {
 318 #if ARCH_X86_64
 319     gCpuCaps.hasSSE=1;
 320     gCpuCaps.hasSSE2=1;
 321 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 322     int has_sse=0, ret;
 323     size_t len=sizeof(has_sse);
 324
 325     ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 326     if (ret || !has_sse)
 327         gCpuCaps.hasSSE=0;
 328
 329 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 330 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 331     int has_sse, has_sse2, ret, mib[2];
 332     size_t varlen;
 333
 334     mib[0] = CTL_MACHDEP;
 335     mib[1] = CPU_SSE;
 336     varlen = sizeof(has_sse);
 337
 338     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 339     ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 340     gCpuCaps.hasSSE = ret >= 0 && has_sse;
 341     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 342
 343     mib[1] = CPU_SSE2;
 344     varlen = sizeof(has_sse2);
 345     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 346     ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 347     gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 348     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 349 #else
 350     gCpuCaps.hasSSE = 0;
 351     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 352 #endif
 353 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 354     LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 355     if ( gCpuCaps.hasSSE ) {
 356         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 357         exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 358         __asm__ volatile ("xorps %xmm0, %xmm0");
 359         SetUnhandledExceptionFilter(exc_fil);
 360         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 361     }
 362 #elif defined(__OS2__)
 363     EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 364     if ( gCpuCaps.hasSSE ) {
 365         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 366         DosSetExceptionHandler( &RegRec );
 367         __asm__ volatile ("xorps %xmm0, %xmm0");
 368         DosUnsetExceptionHandler( &RegRec );
 369         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 370     }
 371 #elif defined(__linux__)
 372 #if defined(_POSIX_SOURCE)
 373     struct sigaction saved_sigill;
 374
 375     /* Save the original signal handlers.
 376      */
 377     sigaction( SIGILL, NULL, &saved_sigill );
 378
 379     signal( SIGILL, (void (*)(int))sigill_handler_sse );
 380
 381     /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 382      * supports the extended FPU save and restore required for SSE.  If
 383      * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 384      * doesn't support Streaming SIMD Exceptions, even if the processor
 385      * does.
 386      */
 387     if ( gCpuCaps.hasSSE ) {
 388         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 389
 390 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 391         __asm__ volatile ("xorps %xmm0, %xmm0");
 392
 393         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 394     }
 395
 396     /* Restore the original signal handlers.
 397      */
 398     sigaction( SIGILL, &saved_sigill, NULL );
 399
 400     /* If we've gotten to here and the XMM CPUID bit is still set, we're
 401      * safe to go ahead and hook out the SSE code throughout Mesa.
 402      */
 403     mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 404 #else
 405     /* We can't use POSIX signal handling to test the availability of
 406      * SSE, so we disable it by default.
 407      */
 408     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 409     gCpuCaps.hasSSE=0;
 410 #endif /* _POSIX_SOURCE */
 411 #else
 412     /* Do nothing on other platforms for now.
 413      */
 414     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 415     gCpuCaps.hasSSE=0;
 416 #endif /* __linux__ */
 417 }
 418 #else /* ARCH_X86 */
 419
 420 #ifdef __APPLE__
 421 #include <sys/sysctl.h>
 422 #elif defined(__AMIGAOS4__)
 423 /* nothing */
 424 #else
 425 #include <signal.h>
 426 #include <setjmp.h>
 427
 428 static sigjmp_buf jmpbuf;
 429 static volatile sig_atomic_t canjump = 0;
 430
 431 static void sigill_handler (int sig)
 432 {
 433     if (!canjump) {
 434         signal (sig, SIG_DFL);
 435         raise (sig);
 436     }
 437
 438     canjump = 0;
 439     siglongjmp (jmpbuf, 1);
 440 }
 441 #endif /* __APPLE__ */
 442
 443 void GetCpuCaps( CpuCaps *caps)
 444 {
 445     caps->cpuType=0;
 446     caps->cpuModel=0;
 447     caps->cpuStepping=0;
 448     caps->hasMMX=0;
 449     caps->hasMMX2=0;
 450     caps->has3DNow=0;
 451     caps->has3DNowExt=0;
 452     caps->hasSSE=0;
 453     caps->hasSSE2=0;
 454     caps->hasSSE3=0;
 455     caps->hasSSSE3=0;
 456     caps->hasSSE4a=0;
 457     caps->isX86=0;
 458     caps->hasAltiVec = 0;
 459 #if HAVE_ALTIVEC
 460 #ifdef __APPLE__
 461 /*
 462   rip-off from ffmpeg altivec detection code.
 463   this code also appears on Apple's AltiVec pages.
 464  */
 465     {
 466         int sels[2] = {CTL_HW, HW_VECTORUNIT};
 467         int has_vu = 0;
 468         size_t len = sizeof(has_vu);
 469         int err;
 470
 471         err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 472
 473         if (err == 0)
 474             if (has_vu != 0)
 475                 caps->hasAltiVec = 1;
 476     }
 477 #elif defined(__AMIGAOS4__)
 478     ULONG result = 0;
 479
 480     GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 481     if (result == VECTORTYPE_ALTIVEC)
 482         caps->hasAltiVec = 1;
 483 #else
 484 /* no Darwin, do it the brute-force way */
 485 /* this is borrowed from the libmpeg2 library */
 486     {
 487         signal (SIGILL, sigill_handler);
 488         if (sigsetjmp (jmpbuf, 1)) {
 489             signal (SIGILL, SIG_DFL);
 490         } else {
 491             canjump = 1;
 492
 493         __asm__ volatile ("mtspr 256, %0\n\t"
 494                           "vand %%v0, %%v0, %%v0"
 495                           :
 496                           : "r" (-1));
 497
 498         signal (SIGILL, SIG_DFL);
 499         caps->hasAltiVec = 1;
 500         }
 501     }
 502 #endif /* __APPLE__ */
 503     mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 504 #endif /* HAVE_ALTIVEC */
 505
 506     if (ARCH_IA64)
 507         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 508
 509     if (ARCH_SPARC)
 510         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 511
 512     if (ARCH_ARM)
 513         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 514
 515     if (ARCH_PPC)
 516         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 517
 518     if (ARCH_ALPHA)
 519         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 520
 521     if (ARCH_MIPS)
 522         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
 523
 524     if (ARCH_PA_RISC)
 525         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 526
 527     if (ARCH_S390)
 528         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 529
 530     if (ARCH_S390X)
 531         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 532
 533     if (ARCH_VAX)
 534         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 535
 536     if (ARCH_XTENSA)
 537         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 538 }
 539 #endif /* !ARCH_X86 */