cpuinfo.c

   1 /* small utility to extract CPU information
   2    Used by configure to set CPU optimization levels on some operating
   3    systems where /proc/cpuinfo is non-existent or unreliable. */
   4
   5 #include <stdio.h>
   6 #include <sys/time.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #ifdef __MINGW32__
  12 #define MISSING_USLEEP
  13 #include <windows.h>
  14 #define sleep(t) Sleep(1000*t);
  15 #endif
  16
  17 #ifdef __BEOS__
  18 #define usleep(t) snooze(t)
  19 #endif
  20
  21 #ifdef M_UNIX
  22 typedef long long int64_t;
  23 #define MISSING_USLEEP
  24 #else
  25 #include <inttypes.h>
  26 #endif
  27
  28 #define CPUID_FEATURE_DEF(bit, desc, description) \
  29   { bit, desc }
  30
  31 typedef struct cpuid_regs {
  32   unsigned int eax;
  33   unsigned int ebx;
  34   unsigned int ecx;
  35   unsigned int edx;
  36 } cpuid_regs_t;
  37
  38 static cpuid_regs_t
  39 cpuid(int func) {
  40   cpuid_regs_t regs;
  41 #define CPUID   ".byte 0x0f, 0xa2; "
  42 #ifdef __x86_64__
  43   __asm__("mov %%rbx, %%rsi\n\t"
  44 #else
  45   __asm__("mov %%ebx, %%esi\n\t"
  46 #endif
  47       CPUID"\n\t"
  48 #ifdef __x86_64__
  49       "xchg %%rsi, %%rbx\n\t"
  50 #else
  51       "xchg %%esi, %%ebx\n\t"
  52 #endif
  53       : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
  54       : "0" (func));
  55   return regs;
  56 }
  57
  58
  59 static int64_t
  60 rdtsc(void)
  61 {
  62   uint64_t i;
  63 #define RDTSC   ".byte 0x0f, 0x31; "
  64   __asm__ volatile (RDTSC : "=A"(i) : );
  65   return i;
  66 }
  67
  68 static const char*
  69 brandname(int i)
  70 {
  71   static const char* brandmap[] = {
  72     NULL,
  73     "Intel(R) Celeron(R) processor",
  74     "Intel(R) Pentium(R) III processor",
  75     "Intel(R) Pentium(R) III Xeon(tm) processor",
  76     "Intel(R) Pentium(R) III processor",
  77     NULL,
  78     "Mobile Intel(R) Pentium(R) III processor-M",
  79     "Mobile Intel(R) Celeron(R) processor"
  80   };
  81
  82   if (i >= sizeof(brandmap))
  83     return NULL;
  84   else
  85     return brandmap[i];
  86 }
  87
  88 static void
  89 store32(char *d, unsigned int v)
  90 {
  91   d[0] =  v        & 0xff;
  92   d[1] = (v >>  8) & 0xff;
  93   d[2] = (v >> 16) & 0xff;
  94   d[3] = (v >> 24) & 0xff;
  95 }
  96
  97
  98 int
  99 main(void)
 100 {
 101   cpuid_regs_t regs, regs_ext;
 102   char idstr[13];
 103   unsigned max_cpuid;
 104   unsigned max_ext_cpuid;
 105   unsigned int amd_flags;
 106   unsigned int amd_flags2;
 107   const char *model_name = NULL;
 108   int i;
 109   char processor_name[49];
 110
 111   regs = cpuid(0);
 112   max_cpuid = regs.eax;
 113   /* printf("%d CPUID function codes\n", max_cpuid+1); */
 114
 115   store32(idstr+0, regs.ebx);
 116   store32(idstr+4, regs.edx);
 117   store32(idstr+8, regs.ecx);
 118   idstr[12] = 0;
 119   printf("vendor_id\t: %s\n", idstr);
 120
 121   regs_ext = cpuid((1<<31) + 0);
 122   max_ext_cpuid = regs_ext.eax;
 123   if (max_ext_cpuid >= (1<<31) + 1) {
 124     regs_ext = cpuid((1<<31) + 1);
 125     amd_flags = regs_ext.edx;
 126     amd_flags2 = regs_ext.ecx;
 127
 128     if (max_ext_cpuid >= (1<<31) + 4) {
 129       for (i = 2; i <= 4; i++) {
 130         regs_ext = cpuid((1<<31) + i);
 131         store32(processor_name + (i-2)*16, regs_ext.eax);
 132         store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
 133         store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
 134         store32(processor_name + (i-2)*16 + 12, regs_ext.edx);
 135       }
 136       processor_name[48] = 0;
 137       model_name = processor_name;
 138       while (*model_name == ' ') {
 139         model_name++;
 140       }
 141     }
 142   } else {
 143     amd_flags = 0;
 144     amd_flags2 = 0;
 145   }
 146
 147   if (max_cpuid >= 1) {
 148     static struct {
 149       int bit;
 150       char *desc;
 151     } cap[] = {
 152       CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"),
 153       CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"),
 154       CPUID_FEATURE_DEF(2, "de", "Debugging Extension"),
 155       CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"),
 156       CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"),
 157       CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"),
 158       CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"),
 159       CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"),
 160       CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"),
 161       CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"),
 162       CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"),
 163       CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"),
 164       CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"),
 165       CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"),
 166       CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"),
 167       CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"),
 168       CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"),
 169       CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"),
 170       CPUID_FEATURE_DEF(19, "clflush", "CFLUSH instruction"),
 171       CPUID_FEATURE_DEF(21, "dts", "Debug Store"),
 172       CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"),
 173       CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"),
 174       CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"),
 175       CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"),
 176       CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"),
 177       CPUID_FEATURE_DEF(27, "ss", "Self Snoop"),
 178       CPUID_FEATURE_DEF(28, "ht", "Multi-threading"),
 179       CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"),
 180       CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"),
 181       CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."),
 182       { -1 }
 183     };
 184     static struct {
 185       int bit;
 186       char *desc;
 187     } cap2[] = {
 188       CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"),
 189       CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"),
 190       CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"),
 191       CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"),
 192       CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"),
 193       CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"),
 194       CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
 195       CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
 196       CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
 197       CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
 198       CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"),
 199       CPUID_FEATURE_DEF(15, "pdcm", "Perf/Debug Capability MSR"),
 200       CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"),
 201       CPUID_FEATURE_DEF(19, "sse4_1", "SSE4.1 Extensions"),
 202       CPUID_FEATURE_DEF(20, "sse4_2", "SSE4.2 Extensions"),
 203       CPUID_FEATURE_DEF(23, "popcnt", "Pop Count Instruction"),
 204       { -1 }
 205     };
 206     static struct {
 207       int bit;
 208       char *desc;
 209     } cap_amd[] = {
 210       CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
 211       CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
 212       CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
 213       CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
 214       CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
 215       CPUID_FEATURE_DEF(26, "pdpe1gb", "PDP Entry for 1GiB Page"),
 216       CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
 217       CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
 218       CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
 219       CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
 220       { -1 }
 221     };
 222     static struct {
 223       int bit;
 224       char *desc;
 225     } cap_amd2[] = {
 226       CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
 227       CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
 228       CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
 229       CPUID_FEATURE_DEF(3, "extapic", "Extended APIC Space"),
 230       CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"),
 231       CPUID_FEATURE_DEF(5, "abm", "Advanced Bit Manipulation"),
 232       CPUID_FEATURE_DEF(6, "sse4a", "SSE4A Extensions"),
 233       CPUID_FEATURE_DEF(7, "misalignsse", "Misaligned SSE Mode"),
 234       CPUID_FEATURE_DEF(8, "3dnowprefetch", "3DNow! Prefetch/PrefetchW"),
 235       CPUID_FEATURE_DEF(9, "osvw", "OS Visible Workaround"),
 236       CPUID_FEATURE_DEF(10, "ibs", "Instruction Based Sampling"),
 237       CPUID_FEATURE_DEF(11, "sse5", "SSE5 Extensions"),
 238       CPUID_FEATURE_DEF(12, "skinit", "SKINIT, STGI, and DEV Support"),
 239       CPUID_FEATURE_DEF(13, "wdt", "Watchdog Timer Support"),
 240       { -1 }
 241     };
 242     unsigned int family, model, stepping;
 243
 244     regs = cpuid(1);
 245     family = (regs.eax >> 8) & 0xf;
 246     model = (regs.eax >> 4) & 0xf;
 247     stepping = regs.eax & 0xf;
 248
 249     if (family == 0xf)
 250       family += (regs.eax >> 20) & 0xff;
 251     if (family == 0xf || family == 6)
 252       model += ((regs.eax >> 16) & 0xf) << 4;
 253
 254     printf("cpu family\t: %d\n"
 255            "model\t\t: %d\n"
 256            "stepping\t: %d\n" ,
 257            family,
 258            model,
 259            stepping);
 260
 261     if (strstr(idstr, "Intel") && !model_name) {
 262       if (family == 6 && model == 0xb && stepping == 1)
 263         model_name = "Intel (R) Celeron (R) processor";
 264       else
 265         model_name = brandname(regs.ebx & 0xf);
 266     }
 267
 268     printf("flags\t\t:");
 269     for (i = 0; cap[i].bit >= 0; i++) {
 270       if (regs.edx & (1 << cap[i].bit)) {
 271         printf(" %s", cap[i].desc);
 272       }
 273     }
 274     for (i = 0; cap2[i].bit >= 0; i++) {
 275       if (regs.ecx & (1 << cap2[i].bit)) {
 276         printf(" %s", cap2[i].desc);
 277       }
 278     }
 279     /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
 280        it is not indicated by a CPUID feature bit, so we
 281        have to check the family, model and stepping instead. */
 282     if (strstr(idstr, "AMD") &&
 283         family == 5 &&
 284         (model >= 9 || (model == 8 && stepping >= 8)))
 285       printf(" %s", "k6_mtrr");
 286     /* similar for cyrix_arr. */
 287     if (strstr(idstr, "Cyrix") &&
 288         (family == 5 && (model < 4 || family == 6)))
 289       printf(" %s", "cyrix_arr");
 290     /* as well as centaur_mcr. */
 291     if (strstr(idstr, "Centaur") &&
 292         family == 5)
 293       printf(" %s", "centaur_mcr");
 294
 295     for (i = 0; cap_amd[i].bit >= 0; i++) {
 296       if (amd_flags & (1 << cap_amd[i].bit)) {
 297         printf(" %s", cap_amd[i].desc);
 298       }
 299     }
 300     for (i = 0; cap_amd2[i].bit >= 0; i++) {
 301       if (amd_flags2 & (1 << cap_amd2[i].bit)) {
 302         printf(" %s", cap_amd2[i].desc);
 303       }
 304     }
 305     printf("\n");
 306
 307     if (regs.edx & (1 << 4)) {
 308       int64_t tsc_start, tsc_end;
 309       struct timeval tv_start, tv_end;
 310       int usec_delay;
 311
 312       tsc_start = rdtsc();
 313       gettimeofday(&tv_start, NULL);
 314 #ifdef  MISSING_USLEEP
 315       sleep(1);
 316 #else
 317       usleep(100000);
 318 #endif
 319       tsc_end = rdtsc();
 320       gettimeofday(&tv_end, NULL);
 321
 322       usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec)
 323         + (tv_end.tv_usec - tv_start.tv_usec);
 324
 325       printf("cpu MHz\t\t: %.3f\n",
 326              (double)(tsc_end-tsc_start) / usec_delay);
 327     }
 328   }
 329
 330   printf("model name\t: ");
 331   if (model_name)
 332     printf("%s\n", model_name);
 333   else
 334     printf("Unknown %s CPU\n", idstr);
 335 }