cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #if defined(__MINGW32__) || defined(__CYGWIN__)
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __OS2__
  37 #define INCL_DOS
  38 #include <os2.h>
  39 #endif
  40
  41 #ifdef __AMIGAOS4__
  42 #include <proto/exec.h>
  43 #endif
  44
  45 /* Thanks to the FreeBSD project for some of this cpuid code, and
  46  * help understanding how to use it.  Thanks to the Mesa
  47  * team for SSE support detection and more cpu detect code.
  48  */
  49
  50 /* I believe this code works.  However, it has only been used on a PII and PIII */
  51
  52 static void check_os_katmai_support( void );
  53
  54 // return TRUE if cpuid supported
  55 static int has_cpuid(void)
  56 {
  57         long a, c;
  58
  59 // code from libavcodec:
  60     __asm__ volatile (
  61                           /* See if CPUID instruction is supported ... */
  62                           /* ... Get copies of EFLAGS into eax and ecx */
  63                           "pushf\n\t"
  64                           "pop %0\n\t"
  65                           "mov %0, %1\n\t"
  66
  67                           /* ... Toggle the ID bit in one copy and store */
  68                           /*     to the EFLAGS reg */
  69                           "xor $0x200000, %0\n\t"
  70                           "push %0\n\t"
  71                           "popf\n\t"
  72
  73                           /* ... Get the (hopefully modified) EFLAGS */
  74                           "pushf\n\t"
  75                           "pop %0\n\t"
  76                           : "=a" (a), "=c" (c)
  77                           :
  78                           : "cc"
  79                           );
  80
  81         return a != c;
  82 }
  83
  84 static void
  85 do_cpuid(unsigned int ax, unsigned int *p)
  86 {
  87 #if 0
  88         __asm__ volatile(
  89         "cpuid;"
  90         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  91         :  "0" (ax)
  92         );
  93 #else
  94 // code from libavcodec:
  95     __asm__ volatile
  96         ("mov %%"REG_b", %%"REG_S"\n\t"
  97          "cpuid\n\t"
  98          "xchg %%"REG_b", %%"REG_S
  99          : "=a" (p[0]), "=S" (p[1]),
 100            "=c" (p[2]), "=d" (p[3])
 101          : "0" (ax));
 102 #endif
 103
 104 }
 105
 106 void GetCpuCaps( CpuCaps *caps)
 107 {
 108         unsigned int regs[4];
 109         unsigned int regs2[4];
 110
 111         memset(caps, 0, sizeof(*caps));
 112         caps->isX86=1;
 113         caps->cl_size=32; /* default */
 114         if (!has_cpuid()) {
 115             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 116             return;
 117         }
 118         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 119         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 120                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 121         if (regs[0]>=0x00000001)
 122         {
 123                 char *tmpstr, *ptmpstr;
 124                 unsigned cl_size;
 125
 126                 do_cpuid(0x00000001, regs2);
 127
 128                 caps->cpuType=(regs2[0] >> 8)&0xf;
 129                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 130
 131 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 132 // System Instructions, Table 3-2: Effective family computation, page 120.
 133                 if(caps->cpuType==0xf){
 134                     // use extended family (P4, IA64, K8)
 135                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 136                 }
 137                 if(caps->cpuType==0xf || caps->cpuType==6)
 138                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 139
 140                 caps->cpuStepping=regs2[0] & 0xf;
 141
 142                 // general feature flags:
 143                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 144                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 145                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 146                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 147                 caps->hasSSSE3 = (regs2[3] & (1 << 9 )) >>  9; // 0x0000200
 148                 caps->hasSSE4a = (regs2[3] & (1 << 6 )) >>  6; // 0x0000040
 149                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 150                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 151                 if(cl_size) caps->cl_size = cl_size;
 152
 153                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 154                 while(*ptmpstr == ' ')        // strip leading spaces
 155                     ptmpstr++;
 156                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
 157                 free(tmpstr);
 158                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
 159                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 160
 161         }
 162         do_cpuid(0x80000000, regs);
 163         if (regs[0]>=0x80000001) {
 164                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 165                 do_cpuid(0x80000001, regs2);
 166                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 167                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 168                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 169                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 170         }
 171         if(regs[0]>=0x80000006)
 172         {
 173                 do_cpuid(0x80000006, regs2);
 174                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 175                 caps->cl_size  = regs2[2] & 0xFF;
 176         }
 177         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 178 #if 0
 179         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 180                 gCpuCaps.hasMMX,
 181                 gCpuCaps.hasMMX2,
 182                 gCpuCaps.hasSSE,
 183                 gCpuCaps.hasSSE2,
 184                 gCpuCaps.has3DNow,
 185                 gCpuCaps.has3DNowExt );
 186 #endif
 187
 188                 /* FIXME: Does SSE2 need more OS support, too? */
 189 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 190   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 191   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 192   || defined(__OS2__)
 193                 if (caps->hasSSE)
 194                         check_os_katmai_support();
 195                 if (!caps->hasSSE)
 196                         caps->hasSSE2 = 0;
 197 #else
 198                 caps->hasSSE=0;
 199                 caps->hasSSE2 = 0;
 200 #endif
 201 //              caps->has3DNow=1;
 202 //              caps->hasMMX2 = 0;
 203 //              caps->hasMMX = 0;
 204
 205 #ifndef RUNTIME_CPUDETECT
 206 #ifndef HAVE_MMX
 207         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 208         caps->hasMMX=0;
 209 #endif
 210 #ifndef HAVE_MMX2
 211         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 212         caps->hasMMX2=0;
 213 #endif
 214 #ifndef HAVE_SSE
 215         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 216         caps->hasSSE=0;
 217 #endif
 218 #ifndef HAVE_SSE2
 219         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 220         caps->hasSSE2=0;
 221 #endif
 222 #ifndef HAVE_3DNOW
 223         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 224         caps->has3DNow=0;
 225 #endif
 226 #ifndef HAVE_3DNOWEX
 227         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 228         caps->has3DNowExt=0;
 229 #endif
 230 #endif  // RUNTIME_CPUDETECT
 231 }
 232
 233
 234 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 235 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 236 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 237 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 238 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 239 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 240
 241 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 242 #include "cputable.h" /* get cpuname and cpuvendors */
 243         char vendor[13];
 244         char *retname;
 245         int i;
 246
 247         if (NULL==(retname=malloc(256))) {
 248                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 249                 exit(1);
 250         }
 251
 252         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 253
 254         do_cpuid(0x80000000,regs);
 255         if (regs[0] >= 0x80000004)
 256         {
 257                 // CPU has built-in namestring
 258                 retname[0] = '\0';
 259                 for (i = 0x80000002; i <= 0x80000004; i++)
 260                 {
 261                         do_cpuid(i, regs);
 262                         strncat(retname, (char*)regs, 16);
 263                 }
 264                 return retname;
 265         }
 266
 267         for(i=0; i<MAX_VENDORS; i++){
 268                 if(!strcmp(cpuvendors[i].string,vendor)){
 269                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 270                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 271                         } else {
 272                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 273                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 274                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 275                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 276                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 277                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 278                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 279                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 280                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 281                         }
 282                 }
 283         }
 284         retname[255] = 0;
 285
 286         //printf("Detected CPU: %s\n", retname);
 287         return retname;
 288 }
 289
 290 #undef CPUID_EXTFAMILY
 291 #undef CPUID_EXTMODEL
 292 #undef CPUID_TYPE
 293 #undef CPUID_FAMILY
 294 #undef CPUID_MODEL
 295 #undef CPUID_STEPPING
 296
 297
 298 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64)
 299 static void sigill_handler_sse( int signal, struct sigcontext sc )
 300 {
 301    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 302
 303    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 304     * instructions are 3 bytes long.  We must increment the instruction
 305     * pointer manually to avoid repeated execution of the offending
 306     * instruction.
 307     *
 308     * If the SIGILL is caused by a divide-by-zero when unmasked
 309     * exceptions aren't supported, the SIMD FPU status and control
 310     * word will be restored at the end of the test, so we don't need
 311     * to worry about doing it here.  Besides, we may not be able to...
 312     */
 313    sc.eip += 3;
 314
 315    gCpuCaps.hasSSE=0;
 316 }
 317 #endif /* __linux__ && _POSIX_SOURCE */
 318
 319 #if defined(__MINGW32__) || defined(__CYGWIN__)
 320 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 321 {
 322    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 323       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 324       ep->ContextRecord->Eip +=3;
 325       gCpuCaps.hasSSE=0;
 326           return EXCEPTION_CONTINUE_EXECUTION;
 327    }
 328    return EXCEPTION_CONTINUE_SEARCH;
 329 }
 330 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 331
 332 #ifdef __OS2__
 333 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 334                                    PEXCEPTIONREGISTRATIONRECORD p2,
 335                                    PCONTEXTRECORD               p3,
 336                                    PVOID                        p4 )
 337 {
 338    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 339       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 340
 341       p3->ctx_RegEip += 3;
 342       gCpuCaps.hasSSE = 0;
 343
 344       return XCPT_CONTINUE_EXECUTION;
 345    }
 346    return XCPT_CONTINUE_SEARCH;
 347 }
 348 #endif
 349
 350 /* If we're running on a processor that can do SSE, let's see if we
 351  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 352  * haven't been configured for a Pentium III but are running on one,
 353  * and RedHat patched 2.2 kernels that have broken exception handling
 354  * support for user space apps that do SSE.
 355  */
 356
 357 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 358 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 359 #elif defined(__APPLE__)
 360 #define SSE_SYSCTL_NAME "hw.optional.sse"
 361 #endif
 362
 363 static void check_os_katmai_support( void )
 364 {
 365 #ifdef ARCH_X86_64
 366    gCpuCaps.hasSSE=1;
 367    gCpuCaps.hasSSE2=1;
 368 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 369    int has_sse=0, ret;
 370    size_t len=sizeof(has_sse);
 371
 372    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 373    if (ret || !has_sse)
 374       gCpuCaps.hasSSE=0;
 375
 376 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 377 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 378    int has_sse, has_sse2, ret, mib[2];
 379    size_t varlen;
 380
 381    mib[0] = CTL_MACHDEP;
 382    mib[1] = CPU_SSE;
 383    varlen = sizeof(has_sse);
 384
 385    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 386    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 387    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 388    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 389
 390    mib[1] = CPU_SSE2;
 391    varlen = sizeof(has_sse2);
 392    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 393    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 394    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 395    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 396 #else
 397    gCpuCaps.hasSSE = 0;
 398    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 399 #endif
 400 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 401    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 402    if ( gCpuCaps.hasSSE ) {
 403       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 404       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 405       __asm__ volatile ("xorps %xmm0, %xmm0");
 406       SetUnhandledExceptionFilter(exc_fil);
 407       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 408    }
 409 #elif defined(__OS2__)
 410    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 411    if ( gCpuCaps.hasSSE ) {
 412       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 413       DosSetExceptionHandler( &RegRec );
 414       __asm__ volatile ("xorps %xmm0, %xmm0");
 415       DosUnsetExceptionHandler( &RegRec );
 416       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 417    }
 418 #elif defined(__linux__)
 419 #if defined(_POSIX_SOURCE)
 420    struct sigaction saved_sigill;
 421
 422    /* Save the original signal handlers.
 423     */
 424    sigaction( SIGILL, NULL, &saved_sigill );
 425
 426    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 427
 428    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 429     * supports the extended FPU save and restore required for SSE.  If
 430     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 431     * doesn't support Streaming SIMD Exceptions, even if the processor
 432     * does.
 433     */
 434    if ( gCpuCaps.hasSSE ) {
 435       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 436
 437 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 438       __asm__ volatile ("xorps %xmm0, %xmm0");
 439
 440       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 441    }
 442
 443    /* Restore the original signal handlers.
 444     */
 445    sigaction( SIGILL, &saved_sigill, NULL );
 446
 447    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 448     * safe to go ahead and hook out the SSE code throughout Mesa.
 449     */
 450    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 451 #else
 452    /* We can't use POSIX signal handling to test the availability of
 453     * SSE, so we disable it by default.
 454     */
 455    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 456    gCpuCaps.hasSSE=0;
 457 #endif /* _POSIX_SOURCE */
 458 #else
 459    /* Do nothing on other platforms for now.
 460     */
 461    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 462    gCpuCaps.hasSSE=0;
 463 #endif /* __linux__ */
 464 }
 465 #else /* ARCH_X86 */
 466
 467 #ifdef __APPLE__
 468 #include <sys/sysctl.h>
 469 #elif __AMIGAOS4__
 470 /* nothing */
 471 #else
 472 #include <signal.h>
 473 #include <setjmp.h>
 474
 475 static sigjmp_buf jmpbuf;
 476 static volatile sig_atomic_t canjump = 0;
 477
 478 static void sigill_handler (int sig)
 479 {
 480     if (!canjump) {
 481         signal (sig, SIG_DFL);
 482         raise (sig);
 483     }
 484
 485     canjump = 0;
 486     siglongjmp (jmpbuf, 1);
 487 }
 488 #endif /* __APPLE__ */
 489
 490 void GetCpuCaps( CpuCaps *caps)
 491 {
 492         caps->cpuType=0;
 493         caps->cpuModel=0;
 494         caps->cpuStepping=0;
 495         caps->hasMMX=0;
 496         caps->hasMMX2=0;
 497         caps->has3DNow=0;
 498         caps->has3DNowExt=0;
 499         caps->hasSSE=0;
 500         caps->hasSSE2=0;
 501         caps->hasSSSE3=0;
 502         caps->hasSSE4a=0;
 503         caps->isX86=0;
 504         caps->hasAltiVec = 0;
 505 #ifdef HAVE_ALTIVEC
 506 #ifdef __APPLE__
 507 /*
 508   rip-off from ffmpeg altivec detection code.
 509   this code also appears on Apple's AltiVec pages.
 510  */
 511         {
 512                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 513                 int has_vu = 0;
 514                 size_t len = sizeof(has_vu);
 515                 int err;
 516
 517                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 518
 519                 if (err == 0)
 520                         if (has_vu != 0)
 521                                 caps->hasAltiVec = 1;
 522         }
 523 #elif __AMIGAOS4__
 524         ULONG result = 0;
 525
 526         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 527         if (result == VECTORTYPE_ALTIVEC)
 528                 caps->hasAltiVec = 1;
 529 #else
 530 /* no Darwin, do it the brute-force way */
 531 /* this is borrowed from the libmpeg2 library */
 532         {
 533           signal (SIGILL, sigill_handler);
 534           if (sigsetjmp (jmpbuf, 1)) {
 535             signal (SIGILL, SIG_DFL);
 536           } else {
 537             canjump = 1;
 538
 539             __asm__ volatile ("mtspr 256, %0\n\t"
 540                           "vand %%v0, %%v0, %%v0"
 541                           :
 542                           : "r" (-1));
 543
 544             signal (SIGILL, SIG_DFL);
 545             caps->hasAltiVec = 1;
 546           }
 547         }
 548 #endif /* __APPLE__ */
 549         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 550 #endif /* HAVE_ALTIVEC */
 551
 552 #ifdef ARCH_IA64
 553         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 554 #endif
 555
 556 #ifdef ARCH_SPARC
 557         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 558 #endif
 559
 560 #ifdef ARCH_ARMV4L
 561         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 562 #endif
 563
 564 #ifdef ARCH_POWERPC
 565         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 566 #endif
 567
 568 #ifdef ARCH_ALPHA
 569         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 570 #endif
 571
 572 #ifdef ARCH_SGI_MIPS
 573         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 574 #endif
 575
 576 #ifdef ARCH_PA_RISC
 577         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 578 #endif
 579
 580 #ifdef ARCH_S390
 581         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 582 #endif
 583
 584 #ifdef ARCH_S390X
 585         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 586 #endif
 587
 588 #ifdef ARCH_VAX
 589         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 590 #endif
 591
 592 #ifdef ARCH_XTENSA
 593         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" );
 594 #endif
 595 }
 596 #endif /* !ARCH_X86 */