vidix/pci.c

   1 /*
   2    (C) 2002 - library implementation by Nick Kyrshev
   3    XFree86 3.3.3 scanpci.c, modified for GATOS/win/gfxdump by Øyvind Aabling.
   4  */
   5 /* $XConsortium: scanpci.c /main/25 1996/10/27 11:48:40 kaleb $ */
   6 /*
   7  *  name:             scanpci.c
   8  *
   9  *  purpose:          This program will scan for and print details of
  10  *                    devices on the PCI bus.
  11
  12  *  author:           Robin Cutshaw (robin@xfree86.org)
  13  *
  14  *  supported O/S's:  SVR4, UnixWare, SCO, Solaris,
  15  *                    FreeBSD, NetBSD, 386BSD, BSDI BSD/386,
  16  *                    Linux, Mach/386, ISC
  17  *                    DOS (WATCOM 9.5 compiler)
  18  *
  19  *  compiling:        [g]cc scanpci.c -o scanpci
  20  *                    for SVR4 (not Solaris), UnixWare use:
  21  *                        [g]cc -DSVR4 scanpci.c -o scanpci
  22  *                    for DOS, watcom 9.5:
  23  *                        wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c
  24  *                        and link with PharLap or other dos extender for exe
  25  *
  26  */
  27
  28 /* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ */
  29
  30 /*
  31  * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
  32  *
  33  * Permission to use, copy, modify, distribute, and sell this software and its
  34  * documentation for any purpose is hereby granted without fee, provided that
  35  * the above copyright notice appear in all copies and that both that
  36  * copyright notice and this permission notice appear in supporting
  37  * documentation, and that the names of the above listed copyright holder(s)
  38  * not be used in advertising or publicity pertaining to distribution of
  39  * the software without specific, written prior permission.  The above listed
  40  * copyright holder(s) make(s) no representations about the suitability of this
  41  * software for any purpose.  It is provided "as is" without express or
  42  * implied warranty.
  43  *
  44  * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
  45  * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  46  * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
  47  * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
  48  * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
  49  * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
  50  * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  51  *
  52  */
  53
  54 #include "dha.h"
  55 #include "config.h"
  56 #include <errno.h>
  57 #include <string.h>
  58 #include <stdio.h>
  59 #ifdef __unix__
  60 #define __USE_UNIX98
  61 #include <unistd.h>
  62 #endif
  63 #include "AsmMacros.h"
  64 /* OS depended stuff */
  65 #if defined (__linux__)
  66 #include "sysdep/pci_linux.c"
  67 #elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) || defined(__DragonFly__)
  68 #include "sysdep/pci_freebsd.c"
  69 #elif defined (__386BSD__)
  70 #include "sysdep/pci_386bsd.c"
  71 #elif defined (__NetBSD__)
  72 #include "sysdep/pci_netbsd.c"
  73 #elif defined (__OpenBSD__)
  74 #include "sysdep/pci_openbsd.c"
  75 #elif defined (__bsdi__)
  76 #include "sysdep/pci_bsdi.c"
  77 #elif defined (Lynx)
  78 #include "sysdep/pci_lynx.c"
  79 #elif defined (MACH386)
  80 #include "sysdep/pci_mach386.c"
  81 #elif defined (__SVR4)
  82 #if !defined(SVR4)
  83 #define SVR4
  84 #endif
  85 #include "sysdep/pci_svr4.c"
  86 #elif defined (SCO)
  87 #include "sysdep/pci_sco.c"
  88 #elif defined (ISC)
  89 #include "sysdep/pci_isc.c"
  90 #elif defined (__EMX__)
  91 #include "sysdep/pci_os2.c"
  92 #elif defined (_WIN32) || defined(__CYGWIN__)
  93 #include "sysdep/pci_win32.c"
  94 #ifdef __MINGW32__
  95 #define ENOTSUP 134             /* Not supported */
  96 #endif
  97 #endif
  98
  99 #if defined(Lynx) && defined(__powerpc__)
 100 /* let's mimick the Linux Alpha stuff for LynxOS so we don't have
 101  * to change too much code
 102  */
 103 #include <smem.h>
 104
 105 static unsigned char *pciConfBase;
 106
 107 static __inline__ unsigned long
 108 static swapl(unsigned long val)
 109 {
 110         unsigned char *p = (unsigned char *)&val;
 111         return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0);
 112 }
 113
 114
 115 #define BUS(tag) (((tag)>>16)&0xff)
 116 #define DFN(tag) (((tag)>>8)&0xff)
 117
 118 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
 119 #define PCIBIOS_SUCCESSFUL              0x00
 120
 121 int pciconfig_read(
 122           unsigned char bus,
 123           unsigned char dev,
 124           unsigned char offset,
 125           int len,              /* unused, alway 4 */
 126           unsigned long *val)
 127 {
 128         unsigned long _val;
 129         unsigned long *ptr;
 130
 131         dev >>= 3;
 132         if (bus || dev >= 16) {
 133                 *val = 0xFFFFFFFF;
 134                 return PCIBIOS_DEVICE_NOT_FOUND;
 135         } else {
 136                 ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
 137                 _val = swapl(*ptr);
 138         }
 139         *val = _val;
 140         return PCIBIOS_SUCCESSFUL;
 141 }
 142
 143 int pciconfig_write(
 144           unsigned char bus,
 145           unsigned char dev,
 146           unsigned char offset,
 147           int len,              /* unused, alway 4 */
 148           unsigned long val)
 149 {
 150         unsigned long _val;
 151         unsigned long *ptr;
 152
 153         dev >>= 3;
 154         _val = swapl(val);
 155         if (bus || dev >= 16) {
 156                 return PCIBIOS_DEVICE_NOT_FOUND;
 157         } else {
 158                 ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
 159                 *ptr = _val;
 160         }
 161         return PCIBIOS_SUCCESSFUL;
 162 }
 163 #endif /* defined(Lynx) && defined(__powerpc__) */
 164
 165 #if !defined(__powerpc__)
 166 struct pci_config_reg {
 167     /* start of official PCI config space header */
 168     union {
 169         unsigned long device_vendor;
 170         struct {
 171             unsigned short vendor;
 172             unsigned short device;
 173         } dv;
 174     } dv_id;
 175 #define _device_vendor dv_id.device_vendor
 176 #define _vendor dv_id.dv.vendor
 177 #define _device dv_id.dv.device
 178     union {
 179         unsigned long status_command;
 180         struct {
 181             unsigned short command;
 182             unsigned short status;
 183         } sc;
 184     } stat_cmd;
 185 #define _status_command stat_cmd.status_command
 186 #define _command stat_cmd.sc.command
 187 #define _status  stat_cmd.sc.status
 188     union {
 189         unsigned long class_revision;
 190         struct {
 191             unsigned char rev_id;
 192             unsigned char prog_if;
 193             unsigned char sub_class;
 194             unsigned char base_class;
 195         } cr;
 196     } class_rev;
 197 #define _class_revision class_rev.class_revision
 198 #define _rev_id     class_rev.cr.rev_id
 199 #define _prog_if    class_rev.cr.prog_if
 200 #define _sub_class  class_rev.cr.sub_class
 201 #define _base_class class_rev.cr.base_class
 202     union {
 203         unsigned long bist_header_latency_cache;
 204         struct {
 205             unsigned char cache_line_size;
 206             unsigned char latency_timer;
 207             unsigned char header_type;
 208             unsigned char bist;
 209         } bhlc;
 210     } bhlc;
 211 #define _bist_header_latency_cache bhlc.bist_header_latency_cache
 212 #define _cache_line_size bhlc.bhlc.cache_line_size
 213 #define _latency_timer   bhlc.bhlc.latency_timer
 214 #define _header_type     bhlc.bhlc.header_type
 215 #define _bist            bhlc.bhlc.bist
 216     union {
 217         struct {
 218             unsigned long dv_base0;
 219             unsigned long dv_base1;
 220             unsigned long dv_base2;
 221             unsigned long dv_base3;
 222             unsigned long dv_base4;
 223             unsigned long dv_base5;
 224         } dv;
 225         struct {
 226             unsigned long bg_rsrvd[2];
 227             unsigned char primary_bus_number;
 228             unsigned char secondary_bus_number;
 229             unsigned char subordinate_bus_number;
 230             unsigned char secondary_latency_timer;
 231             unsigned char io_base;
 232             unsigned char io_limit;
 233             unsigned short secondary_status;
 234             unsigned short mem_base;
 235             unsigned short mem_limit;
 236             unsigned short prefetch_mem_base;
 237             unsigned short prefetch_mem_limit;
 238         } bg;
 239     } bc;
 240 #define _base0                          bc.dv.dv_base0
 241 #define _base1                          bc.dv.dv_base1
 242 #define _base2                          bc.dv.dv_base2
 243 #define _base3                          bc.dv.dv_base3
 244 #define _base4                          bc.dv.dv_base4
 245 #define _base5                          bc.dv.dv_base5
 246 #define _primary_bus_number             bc.bg.primary_bus_number
 247 #define _secondary_bus_number           bc.bg.secondary_bus_number
 248 #define _subordinate_bus_number         bc.bg.subordinate_bus_number
 249 #define _secondary_latency_timer        bc.bg.secondary_latency_timer
 250 #define _io_base                        bc.bg.io_base
 251 #define _io_limit                       bc.bg.io_limit
 252 #define _secondary_status               bc.bg.secondary_status
 253 #define _mem_base                       bc.bg.mem_base
 254 #define _mem_limit                      bc.bg.mem_limit
 255 #define _prefetch_mem_base              bc.bg.prefetch_mem_base
 256 #define _prefetch_mem_limit             bc.bg.prefetch_mem_limit
 257     unsigned long rsvd1;
 258     unsigned long rsvd2;
 259     unsigned long _baserom;
 260     unsigned long rsvd3;
 261     unsigned long rsvd4;
 262     union {
 263         unsigned long max_min_ipin_iline;
 264         struct {
 265             unsigned char int_line;
 266             unsigned char int_pin;
 267             unsigned char min_gnt;
 268             unsigned char max_lat;
 269         } mmii;
 270     } mmii;
 271 #define _max_min_ipin_iline mmii.max_min_ipin_iline
 272 #define _int_line mmii.mmii.int_line
 273 #define _int_pin  mmii.mmii.int_pin
 274 #define _min_gnt  mmii.mmii.min_gnt
 275 #define _max_lat  mmii.mmii.max_lat
 276     /* I don't know how accurate or standard this is (DHD) */
 277     union {
 278         unsigned long user_config;
 279         struct {
 280             unsigned char user_config_0;
 281             unsigned char user_config_1;
 282             unsigned char user_config_2;
 283             unsigned char user_config_3;
 284         } uc;
 285     } uc;
 286 #define _user_config uc.user_config
 287 #define _user_config_0 uc.uc.user_config_0
 288 #define _user_config_1 uc.uc.user_config_1
 289 #define _user_config_2 uc.uc.user_config_2
 290 #define _user_config_3 uc.uc.user_config_3
 291     /* end of official PCI config space header */
 292     unsigned long _pcibusidx;
 293     unsigned long _pcinumbus;
 294     unsigned long _pcibuses[16];
 295     unsigned short _configtype;   /* config type found                   */
 296     unsigned short _ioaddr;       /* config type 1 - private I/O addr    */
 297     unsigned long _cardnum;       /* config type 2 - private card number */
 298 };
 299 #else
 300 /* ppc is big endian, swapping bytes is not quite enough
 301  * to interpret the PCI config registers...
 302  */
 303 struct pci_config_reg {
 304     /* start of official PCI config space header */
 305     union {
 306         unsigned long device_vendor;
 307         struct {
 308             unsigned short device;
 309             unsigned short vendor;
 310         } dv;
 311     } dv_id;
 312 #define _device_vendor dv_id.device_vendor
 313 #define _vendor dv_id.dv.vendor
 314 #define _device dv_id.dv.device
 315     union {
 316         unsigned long status_command;
 317         struct {
 318             unsigned short status;
 319             unsigned short command;
 320         } sc;
 321     } stat_cmd;
 322 #define _status_command stat_cmd.status_command
 323 #define _command stat_cmd.sc.command
 324 #define _status  stat_cmd.sc.status
 325     union {
 326         unsigned long class_revision;
 327         struct {
 328             unsigned char base_class;
 329             unsigned char sub_class;
 330             unsigned char prog_if;
 331             unsigned char rev_id;
 332         } cr;
 333     } class_rev;
 334 #define _class_revision class_rev.class_revision
 335 #define _rev_id     class_rev.cr.rev_id
 336 #define _prog_if    class_rev.cr.prog_if
 337 #define _sub_class  class_rev.cr.sub_class
 338 #define _base_class class_rev.cr.base_class
 339     union {
 340         unsigned long bist_header_latency_cache;
 341         struct {
 342             unsigned char bist;
 343             unsigned char header_type;
 344             unsigned char latency_timer;
 345             unsigned char cache_line_size;
 346         } bhlc;
 347     } bhlc;
 348 #define _bist_header_latency_cache bhlc.bist_header_latency_cache
 349 #define _cache_line_size bhlc.bhlc.cache_line_size
 350 #define _latency_timer   bhlc.bhlc.latency_timer
 351 #define _header_type     bhlc.bhlc.header_type
 352 #define _bist            bhlc.bhlc.bist
 353     union {
 354         struct {
 355             unsigned long dv_base0;
 356             unsigned long dv_base1;
 357             unsigned long dv_base2;
 358             unsigned long dv_base3;
 359             unsigned long dv_base4;
 360             unsigned long dv_base5;
 361         } dv;
 362 /* ?? */
 363         struct {
 364             unsigned long bg_rsrvd[2];
 365
 366             unsigned char secondary_latency_timer;
 367             unsigned char subordinate_bus_number;
 368             unsigned char secondary_bus_number;
 369             unsigned char primary_bus_number;
 370
 371             unsigned short secondary_status;
 372             unsigned char io_limit;
 373             unsigned char io_base;
 374
 375             unsigned short mem_limit;
 376             unsigned short mem_base;
 377
 378             unsigned short prefetch_mem_limit;
 379             unsigned short prefetch_mem_base;
 380         } bg;
 381     } bc;
 382 #define _base0                          bc.dv.dv_base0
 383 #define _base1                          bc.dv.dv_base1
 384 #define _base2                          bc.dv.dv_base2
 385 #define _base3                          bc.dv.dv_base3
 386 #define _base4                          bc.dv.dv_base4
 387 #define _base5                          bc.dv.dv_base5
 388 #define _primary_bus_number             bc.bg.primary_bus_number
 389 #define _secondary_bus_number           bc.bg.secondary_bus_number
 390 #define _subordinate_bus_number         bc.bg.subordinate_bus_number
 391 #define _secondary_latency_timer        bc.bg.secondary_latency_timer
 392 #define _io_base                        bc.bg.io_base
 393 #define _io_limit                       bc.bg.io_limit
 394 #define _secondary_status               bc.bg.secondary_status
 395 #define _mem_base                       bc.bg.mem_base
 396 #define _mem_limit                      bc.bg.mem_limit
 397 #define _prefetch_mem_base              bc.bg.prefetch_mem_base
 398 #define _prefetch_mem_limit             bc.bg.prefetch_mem_limit
 399     unsigned long rsvd1;
 400     unsigned long rsvd2;
 401     unsigned long _baserom;
 402     unsigned long rsvd3;
 403     unsigned long rsvd4;
 404     union {
 405         unsigned long max_min_ipin_iline;
 406         struct {
 407             unsigned char max_lat;
 408             unsigned char min_gnt;
 409             unsigned char int_pin;
 410             unsigned char int_line;
 411         } mmii;
 412     } mmii;
 413 #define _max_min_ipin_iline mmii.max_min_ipin_iline
 414 #define _int_line mmii.mmii.int_line
 415 #define _int_pin  mmii.mmii.int_pin
 416 #define _min_gnt  mmii.mmii.min_gnt
 417 #define _max_lat  mmii.mmii.max_lat
 418     /* I don't know how accurate or standard this is (DHD) */
 419     union {
 420         unsigned long user_config;
 421         struct {
 422             unsigned char user_config_3;
 423             unsigned char user_config_2;
 424             unsigned char user_config_1;
 425             unsigned char user_config_0;
 426         } uc;
 427     } uc;
 428 #define _user_config uc.user_config
 429 #define _user_config_0 uc.uc.user_config_0
 430 #define _user_config_1 uc.uc.user_config_1
 431 #define _user_config_2 uc.uc.user_config_2
 432 #define _user_config_3 uc.uc.user_config_3
 433     /* end of official PCI config space header */
 434     unsigned long _pcibusidx;
 435     unsigned long _pcinumbus;
 436     unsigned long _pcibuses[16];
 437     unsigned short _ioaddr;       /* config type 1 - private I/O addr    */
 438     unsigned short _configtype;   /* config type found                   */
 439     unsigned long _cardnum;       /* config type 2 - private card number */
 440 };
 441 #endif /* !defined(__powerpc__) */
 442
 443 #define NF ((void (*)())NULL), { 0.0, 0, 0, NULL }
 444 #define PCI_MULTIFUNC_DEV       0x80
 445 #define PCI_ID_REG              0x00
 446 #define PCI_CMD_STAT_REG        0x04
 447 #define PCI_CLASS_REG           0x08
 448 #define PCI_HEADER_MISC         0x0C
 449 #define PCI_MAP_REG_START       0x10
 450 #define PCI_MAP_ROM_REG         0x30
 451 #define PCI_INTERRUPT_REG       0x3C
 452 #define PCI_REG_USERCONFIG      0x40
 453
 454 static int pcibus=-1, pcicard=-1, pcifunc=-1 ;
 455 /*static struct pci_device *pcidev=NULL ;*/
 456
 457 #if defined(__alpha__)
 458 #define PCI_EN 0x00000000
 459 #else
 460 #define PCI_EN 0x80000000
 461 #endif
 462
 463 #define PCI_MODE1_ADDRESS_REG           0xCF8
 464 #define PCI_MODE1_DATA_REG              0xCFC
 465
 466 #define PCI_MODE2_ENABLE_REG            0xCF8
 467 #ifdef PC98
 468 #define PCI_MODE2_FORWARD_REG           0xCF9
 469 #else
 470 #define PCI_MODE2_FORWARD_REG           0xCFA
 471 #endif
 472
 473 /* cpu depended stuff */
 474 #ifndef CONFIG_SVGAHELPER
 475 #if defined(__alpha__)
 476 #include "sysdep/pci_alpha.c"
 477 #elif defined(__ia64__)
 478 #include "sysdep/pci_ia64.c"
 479 #elif defined(__sparc__)
 480 #include "sysdep/pci_sparc.c"
 481 #elif defined( __arm32__ )
 482 #include "sysdep/pci_arm32.c"
 483 #elif defined(__powerpc__)
 484 #include "sysdep/pci_powerpc.c"
 485 #elif defined(__x86_64__) || defined(__sh__)
 486 /* Nothing here right now */
 487 #else
 488 #include "sysdep/pci_x86.c"
 489 #endif
 490 #endif /*CONFIG_SVGAHELPER */
 491
 492 static pciinfo_t *pci_lst;
 493
 494 static void identify_card(struct pci_config_reg *pcr, int idx)
 495 {
 496   /* local overflow test */
 497   if (idx>=MAX_PCI_DEVICES) return ;
 498
 499   pci_lst[idx].bus     = pcibus ;
 500   pci_lst[idx].card    = pcicard ;
 501   pci_lst[idx].func    = pcifunc ;
 502   pci_lst[idx].command = pcr->_status_command & 0xFFFF;
 503   pci_lst[idx].vendor  = pcr->_vendor ;
 504   pci_lst[idx].device  = pcr->_device ;
 505   pci_lst[idx].base0   = 0xFFFFFFFF ;
 506   pci_lst[idx].base1   = 0xFFFFFFFF ;
 507   pci_lst[idx].base2   = 0xFFFFFFFF ;
 508   pci_lst[idx].baserom = 0x000C0000 ;
 509   if (pcr->_base0) pci_lst[idx].base0 = pcr->_base0 &
 510                      ((pcr->_base0&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
 511   if (pcr->_base1) pci_lst[idx].base1 = pcr->_base1 &
 512                      ((pcr->_base1&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
 513   if (pcr->_base2) pci_lst[idx].base2 = pcr->_base2 &
 514                      ((pcr->_base2&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
 515   if (pcr->_baserom) pci_lst[idx].baserom = pcr->_baserom ;
 516 }
 517
 518 /*main(int argc, char *argv[])*/
 519 int pci_scan(pciinfo_t *pci_list,unsigned *num_pci)
 520 {
 521     unsigned int idx = 0;
 522     struct pci_config_reg pcr;
 523     int do_mode1_scan = 0;
 524 #if !defined(__alpha__) && !defined(__powerpc__)
 525     int do_mode2_scan = 0;
 526 #endif
 527     int func, hostbridges=0;
 528     int ret = -1;
 529
 530     pci_lst = pci_list;
 531     *num_pci = 0;
 532
 533     ret = enable_os_io();
 534     if (ret != 0)
 535         return ret;
 536
 537     if((pcr._configtype = pci_config_type()) == 0xFFFF) return ENODEV;
 538
 539     /* Try pci config 1 probe first */
 540
 541     if ((pcr._configtype == 1) || do_mode1_scan) {
 542     /*printf("\nPCI probing configuration type 1\n");*/
 543
 544     pcr._ioaddr = 0xFFFF;
 545
 546     pcr._pcibuses[0] = 0;
 547     pcr._pcinumbus = 1;
 548     pcr._pcibusidx = 0;
 549
 550     do {
 551         /*printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);*/
 552
 553         for (pcr._cardnum = 0x0; pcr._cardnum < MAX_PCI_DEVICES_PER_BUS;
 554                 pcr._cardnum += 0x1) {
 555           func = 0;
 556           do { /* loop over the different functions, if present */
 557             pcr._device_vendor = pci_get_vendor(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum,
 558                                                 func);
 559             if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
 560                 break;   /* nothing there */
 561
 562             /*printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n",
 563                 pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func,
 564                 pcr._vendor, pcr._device);*/
 565             pcibus = pcr._pcibuses[pcr._pcibusidx];
 566             pcicard = pcr._cardnum;
 567             pcifunc = func;
 568
 569             pcr._status_command = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 570                                         pcr._cardnum,func,PCI_CMD_STAT_REG);
 571             pcr._class_revision = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 572                                         pcr._cardnum,func,PCI_CLASS_REG);
 573             pcr._bist_header_latency_cache = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 574                                         pcr._cardnum,func,PCI_HEADER_MISC);
 575             pcr._base0 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 576                                         pcr._cardnum,func,PCI_MAP_REG_START);
 577             pcr._base1 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 578                                         pcr._cardnum,func,PCI_MAP_REG_START+4);
 579             pcr._base2 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 580                                         pcr._cardnum,func,PCI_MAP_REG_START+8);
 581             pcr._base3 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 582                                         pcr._cardnum,func,PCI_MAP_REG_START+0x0C);
 583             pcr._base4 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 584                                         pcr._cardnum,func,PCI_MAP_REG_START+0x10);
 585             pcr._base5 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 586                                         pcr._cardnum,func,PCI_MAP_REG_START+0x14);
 587             pcr._baserom = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 588                                         pcr._cardnum,func,PCI_MAP_ROM_REG);
 589             pcr._max_min_ipin_iline = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 590                                         pcr._cardnum,func,PCI_INTERRUPT_REG);
 591             pcr._user_config = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
 592                                         pcr._cardnum,func,PCI_REG_USERCONFIG);
 593             /* check for pci-pci bridges */
 594 #define PCI_CLASS_MASK          0xff000000
 595 #define PCI_SUBCLASS_MASK       0x00ff0000
 596 #define PCI_CLASS_BRIDGE        0x06000000
 597 #define PCI_SUBCLASS_BRIDGE_PCI 0x00040000
 598             switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) {
 599                 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI:
 600                     if (pcr._secondary_bus_number > 0) {
 601                         pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
 602                     }
 603                         break;
 604                 case PCI_CLASS_BRIDGE:
 605                     if ( ++hostbridges > 1) {
 606                         pcr._pcibuses[pcr._pcinumbus] = pcr._pcinumbus;
 607                         pcr._pcinumbus++;
 608                     }
 609                         break;
 610                 default:
 611                         break;
 612             }
 613             if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) {
 614                 /* not a multi function device */
 615                 func = 8;
 616             } else {
 617                 func++;
 618             }
 619
 620             if (idx++ >= MAX_PCI_DEVICES)
 621                 continue;
 622
 623             identify_card(&pcr, (*num_pci)++);
 624           } while( func < 8 );
 625         }
 626     } while (++pcr._pcibusidx < pcr._pcinumbus);
 627     }
 628
 629 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sh__)
 630     /* Now try pci config 2 probe (deprecated) */
 631
 632     if ((pcr._configtype == 2) || do_mode2_scan) {
 633     outb(PCI_MODE2_ENABLE_REG, 0xF1);
 634     outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 635
 636     /*printf("\nPCI probing configuration type 2\n");*/
 637
 638     pcr._pcibuses[0] = 0;
 639     pcr._pcinumbus = 1;
 640     pcr._pcibusidx = 0;
 641     idx = 0;
 642
 643     do {
 644         for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){
 645             outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
 646             pcr._device_vendor = inl(pcr._ioaddr);
 647             outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 648
 649             if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
 650                 continue;
 651             if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0))
 652                 continue;  /* catch ASUS P55TP4XE motherboards */
 653
 654             /*printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n",
 655                 pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor,
 656                 pcr._device);*/
 657             pcibus = pcr._pcibuses[pcr._pcibusidx] ;
 658             pcicard = pcr._ioaddr ; pcifunc = 0 ;
 659
 660             outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
 661             pcr._status_command = inl(pcr._ioaddr + 0x04);
 662             pcr._class_revision = inl(pcr._ioaddr + 0x08);
 663             pcr._bist_header_latency_cache = inl(pcr._ioaddr + 0x0C);
 664             pcr._base0 = inl(pcr._ioaddr + 0x10);
 665             pcr._base1 = inl(pcr._ioaddr + 0x14);
 666             pcr._base2 = inl(pcr._ioaddr + 0x18);
 667             pcr._base3 = inl(pcr._ioaddr + 0x1C);
 668             pcr._base4 = inl(pcr._ioaddr + 0x20);
 669             pcr._base5 = inl(pcr._ioaddr + 0x24);
 670             pcr._baserom = inl(pcr._ioaddr + 0x30);
 671             pcr._max_min_ipin_iline = inl(pcr._ioaddr + 0x3C);
 672             pcr._user_config = inl(pcr._ioaddr + 0x40);
 673             outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 674
 675             /* check for pci-pci bridges (currently we only know Digital) */
 676             if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001))
 677                 if (pcr._secondary_bus_number > 0)
 678                     pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
 679
 680             if (idx++ >= MAX_PCI_DEVICES)
 681                 continue;
 682
 683             identify_card(&pcr, (*num_pci)++);
 684         }
 685     } while (++pcr._pcibusidx < pcr._pcinumbus);
 686
 687     outb(PCI_MODE2_ENABLE_REG, 0x00);
 688     }
 689
 690 #endif /* !__alpha__ && !__powerpc__ && !__sh__ */
 691
 692     disable_os_io();
 693
 694     return 0 ;
 695
 696 }
 697
 698 #if !defined(ENOTSUP)
 699 #if defined(EOPNOTSUPP)
 700 #define ENOTSUP EOPNOTSUPP
 701 #else
 702 #warning "ENOTSUP nor EOPNOTSUPP defined!"
 703 #endif
 704 #endif
 705
 706 int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func,
 707                     unsigned char cmd, int len, unsigned long *val)
 708 {
 709     int ret;
 710
 711     if (len != 4)
 712     {
 713         fprintf(stderr,"pci_config_read: Reading non-dword not supported!\n");
 714         return ENOTSUP;
 715     }
 716
 717     ret = enable_os_io();
 718     if (ret != 0)
 719         return ret;
 720     ret = pci_config_read_long(bus, dev, func, cmd);
 721     disable_os_io();
 722
 723     *val = ret;
 724     return 0;
 725 }
 726
 727 int enable_app_io( void )
 728 {
 729   return enable_os_io();
 730 }
 731
 732 int disable_app_io( void )
 733 {
 734   return disable_os_io();
 735 }