1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
19 # g floating point register returned in r0:r1 for soft-float mode
21 # len:number describe the maximun length in bytes of the instruction
22 # number is a positive integer
24 # cost:number describe how many cycles are needed to complete the instruction (unused)
26 # clob:spec describe if the instruction clobbers registers or has special needs
28 # spec can be one of the following characters:
29 # c clobbers caller-save registers
30 # r 'reserves' the destination register until a later instruction unreserves it
31 # used mostly to set output registers in function calls
33 # flags:spec describe if the instruction uses or sets the flags (unused)
35 # spec can be one of the following chars:
38 # m uses and modifies the flags
40 # res:spec describe what units are used in the processor (unused)
42 # delay: describe delay slots (unused)
44 # the required specifiers are: len, clob (if registers are clobbered), the registers
45 # specifiers if the registers are actually used, flags (when scheduling is implemented).
47 # See the code in mini-x86.c for more details on how the specifiers are used.
89 call: dest:a clob:c len:20
119 ldind.i1: dest:i len:8
120 ldind.u1: dest:i len:8
121 ldind.i2: dest:i len:8
122 ldind.u2: dest:i len:8
123 ldind.i4: dest:i len:8
124 ldind.u4: dest:i len:8
126 ldind.i: dest:i len:8
129 ldind.ref: dest:i len:8
130 stind.ref: src1:b src2:i
131 stind.i1: src1:b src2:i
132 stind.i2: src1:b src2:i
133 stind.i4: src1:b src2:i
135 stind.r4: src1:b src2:f
136 stind.r8: src1:b src2:f
137 add: dest:i src1:i src2:i len:4
138 sub: dest:i src1:i src2:i len:4
139 mul: dest:i src1:i src2:i len:4
140 div: dest:i src1:i src2:i len:40
141 div.un: dest:i src1:i src2:i len:16
142 rem: dest:i src1:i src2:i len:48
143 rem.un: dest:i src1:i src2:i len:24
144 and: dest:i src1:i src2:i len:4
145 or: dest:i src1:i src2:i len:4
146 xor: dest:i src1:i src2:i len:4
147 shl: dest:i src1:i src2:i len:4
148 shr: dest:i src1:i src2:i len:4
149 shr.un: dest:i src1:i src2:i len:4
150 neg: dest:i src1:i len:4
151 not: dest:i src1:i len:4
152 conv.i1: dest:i src1:i len:8
153 conv.i2: dest:i src1:i len:8
154 conv.i4: dest:i src1:i len:4
156 conv.r4: dest:f src1:i len:36
157 conv.r8: dest:f src1:i len:36
158 conv.u4: dest:i src1:i
167 conv.r.un: dest:f src1:i len:56
170 op_rethrow: src1:i len:20
220 ckfinite: dest:f src1:f len:24
223 conv.u2: dest:i src1:i len:8
224 conv.u1: dest:i src1:i len:4
225 conv.i: dest:i src1:i len:4
228 add.ovf: dest:i src1:i src2:i len:16
229 add.ovf.un: dest:i src1:i src2:i len:16
230 mul.ovf: dest:i src1:i src2:i len:16
231 # this opcode is handled specially in the code generator
232 mul.ovf.un: dest:i src1:i src2:i len:16
233 sub.ovf: dest:i src1:i src2:i len:16
234 sub.ovf.un: dest:i src1:i src2:i len:16
235 add_ovf_carry: dest:i src1:i src2:i len:16
236 sub_ovf_carry: dest:i src1:i src2:i len:16
237 add_ovf_un_carry: dest:i src1:i src2:i len:16
238 sub_ovf_un_carry: dest:i src1:i src2:i len:16
239 start_handler: len:20
244 conv.u: dest:i src1:i len:4
256 cgt.un: dest:i len:12
258 clt.un: dest:i len:12
267 localloc: dest:i src1:i len:60
290 compare: src1:i src2:i len:4
291 compare_imm: src1:i len:12
292 fcompare: src1:f src2:f len:12
296 oparglist: src1:i len:12
300 setret: dest:a src1:i len:4
301 setlret: src1:i src2:i len:12
302 setreg: dest:i src1:i len:4 clob:r
303 setregimm: dest:i len:16 clob:r
304 setfreg: dest:f src1:f len:4 clob:r
305 checkthis: src1:b len:4
306 voidcall: len:20 clob:c
307 voidcall_reg: src1:i len:8 clob:c
308 voidcall_membase: src1:b len:12 clob:c
309 fcall: dest:g len:20 clob:c
310 fcall_reg: dest:g src1:i len:8 clob:c
311 fcall_membase: dest:g src1:b len:12 clob:c
312 lcall: dest:l len:20 clob:c
313 lcall_reg: dest:l src1:i len:8 clob:c
314 lcall_membase: dest:l src1:b len:12 clob:c
316 vcall_reg: src1:i len:8 clob:c
317 vcall_membase: src1:b len:12 clob:c
318 call_reg: dest:a src1:i len:8 clob:c
319 call_membase: dest:a src1:b len:12 clob:c
321 iconst: dest:i len:16
323 r4const: dest:f len:20
324 r8const: dest:f len:20
329 store_membase_imm: dest:b len:20
330 store_membase_reg: dest:b src1:i len:20
331 storei1_membase_imm: dest:b len:20
332 storei1_membase_reg: dest:b src1:i len:12
333 storei2_membase_imm: dest:b len:20
334 storei2_membase_reg: dest:b src1:i len:12
335 storei4_membase_imm: dest:b len:20
336 storei4_membase_reg: dest:b src1:i len:20
337 storei8_membase_imm: dest:b
338 storei8_membase_reg: dest:b src1:i
339 storer4_membase_reg: dest:b src1:f len:12
340 storer8_membase_reg: dest:b src1:f len:12
341 store_memindex: dest:b src1:i src2:i len:4
342 storei1_memindex: dest:b src1:i src2:i len:4
343 storei2_memindex: dest:b src1:i src2:i len:4
344 storei4_memindex: dest:b src1:i src2:i len:4
345 load_membase: dest:i src1:b len:20
346 loadi1_membase: dest:i src1:b len:4
347 loadu1_membase: dest:i src1:b len:4
348 loadi2_membase: dest:i src1:b len:4
349 loadu2_membase: dest:i src1:b len:4
350 loadi4_membase: dest:i src1:b len:4
351 loadu4_membase: dest:i src1:b len:4
352 loadi8_membase: dest:i src1:b
353 loadr4_membase: dest:f src1:b len:4
354 loadr8_membase: dest:f src1:b len:4
355 load_memindex: dest:i src1:b src2:i len:4
356 loadi1_memindex: dest:i src1:b src2:i len:4
357 loadu1_memindex: dest:i src1:b src2:i len:4
358 loadi2_memindex: dest:i src1:b src2:i len:4
359 loadu2_memindex: dest:i src1:b src2:i len:4
360 loadi4_memindex: dest:i src1:b src2:i len:4
361 loadu4_memindex: dest:i src1:b src2:i len:4
362 loadu4_mem: dest:i len:8
363 move: dest:i src1:i len:4
364 fmove: dest:f src1:f len:4
365 add_imm: dest:i src1:i len:12
366 sub_imm: dest:i src1:i len:12
367 mul_imm: dest:i src1:i len:12
368 # there is no actual support for division or reminder by immediate
369 # we simulate them, though (but we need to change the burg rules
370 # to allocate a symbolic reg for src2)
371 div_imm: dest:i src1:i src2:i len:20
372 div_un_imm: dest:i src1:i src2:i len:12
373 rem_imm: dest:i src1:i src2:i len:28
374 rem_un_imm: dest:i src1:i src2:i len:16
375 and_imm: dest:i src1:i len:12
376 or_imm: dest:i src1:i len:12
377 xor_imm: dest:i src1:i len:12
378 shl_imm: dest:i src1:i len:8
379 shr_imm: dest:i src1:i len:8
380 shr_un_imm: dest:i src1:i len:8
382 cond_exc_ne_un: len:8
384 cond_exc_lt_un: len:8
386 cond_exc_gt_un: len:8
388 cond_exc_ge_un: len:8
390 cond_exc_le_un: len:8
421 long_conv_to_ovf_i: dest:i src1:i src2:i len:30
429 long_conv_to_ovf_i1_un:
430 long_conv_to_ovf_i2_un:
431 long_conv_to_ovf_i4_un:
432 long_conv_to_ovf_i8_un:
433 long_conv_to_ovf_u1_un:
434 long_conv_to_ovf_u2_un:
435 long_conv_to_ovf_u4_un:
436 long_conv_to_ovf_u8_un:
437 long_conv_to_ovf_i_un:
438 long_conv_to_ovf_u_un:
452 long_conv_to_r_un: dest:f src1:i src2:i len:37
469 float_beq: src1:f src2:f len:20
470 float_bne_un: src1:f src2:f len:20
471 float_blt: src1:f src2:f len:20
472 float_blt_un: src1:f src2:f len:20
473 float_bgt: src1:f src2:f len:20
474 float_btg_un: src1:f src2:f len:20
475 float_bge: src1:f src2:f len:20
476 float_bge_un: src1:f src2:f len:20
477 float_ble: src1:f src2:f len:20
478 float_ble_un: src1:f src2:f len:20
479 float_add: dest:f src1:f src2:f len:4
480 float_sub: dest:f src1:f src2:f len:4
481 float_mul: dest:f src1:f src2:f len:4
482 float_div: dest:f src1:f src2:f len:4
483 float_div_un: dest:f src1:f src2:f len:4
484 float_rem: dest:f src1:f src2:f len:16
485 float_rem_un: dest:f src1:f src2:f len:16
486 float_neg: dest:f src1:f len:4
487 float_not: dest:f src1:f len:4
488 float_conv_to_i1: dest:i src1:f len:40
489 float_conv_to_i2: dest:i src1:f len:40
490 float_conv_to_i4: dest:i src1:f len:40
491 float_conv_to_i8: dest:l src1:f len:40
492 float_conv_to_r4: dest:f src1:f len:4
494 float_conv_to_u4: dest:i src1:f len:40
495 float_conv_to_u8: dest:l src1:f len:40
496 float_conv_to_u2: dest:i src1:f len:40
497 float_conv_to_u1: dest:i src1:f len:40
498 float_conv_to_i: dest:i src1:f len:40
507 float_conv_to_ovf_i1_un:
508 float_conv_to_ovf_i2_un:
509 float_conv_to_ovf_i4_un:
510 float_conv_to_ovf_i8_un:
511 float_conv_to_ovf_u1_un:
512 float_conv_to_ovf_u2_un:
513 float_conv_to_ovf_u4_un:
514 float_conv_to_ovf_u8_un:
515 float_conv_to_ovf_i_un:
516 float_conv_to_ovf_u_un:
517 float_conv_to_ovf_i1:
518 float_conv_to_ovf_u1:
519 float_conv_to_ovf_i2:
520 float_conv_to_ovf_u2:
521 float_conv_to_ovf_i4:
522 float_conv_to_ovf_u4:
523 float_conv_to_ovf_i8:
524 float_conv_to_ovf_u8:
525 float_ceq: dest:i src1:f src2:f len:16
526 float_cgt: dest:i src1:f src2:f len:16
527 float_cgt_un: dest:i src1:f src2:f len:20
528 float_clt: dest:i src1:f src2:f len:16
529 float_clt_un: dest:i src1:f src2:f len:20
530 float_conv_to_u: dest:i src1:f len:36
532 op_endfilter: src1:i len:16
533 aot_const: dest:i len:8
534 sqrt: dest:f src1:f len:4
535 adc: dest:i src1:i src2:i len:4
536 addcc: dest:i src1:i src2:i len:4
537 subcc: dest:i src1:i src2:i len:4
538 adc_imm: dest:i src1:i len:12
539 addcc_imm: dest:i src1:i len:12
540 subcc_imm: dest:i src1:i len:12
541 sbb: dest:i src1:i src2:i len:4
542 sbb_imm: dest:i src1:i len:12
544 arm_rsbs_imm: dest:i src1:i len:4
545 arm_rsc_imm: dest:i src1:i len:4
546 op_bigmul: len:8 dest:l src1:i src2:i
547 op_bigmul_un: len:8 dest:l src1:i src2:i
548 tls_get: len:8 dest:i