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1 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
2 # Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
3 # Licensed under the MIT license. See LICENSE file in the project root for full license information.
4 # arm cpu description file
5 # this file is read by genmdesc to pruduce a table with all the relevant information
6 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
7 # and other parts of the arch-dependent part of mini.
8 #
9 # An opcode name is followed by a colon and optional specifiers.
10 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
11 # Here is a description of the specifiers valid for this file and their possible values.
12 #
13 # dest:register describes the destination register of an instruction
14 # src1:register describes the first source register of an instruction
15 # src2:register describes the second source register of an instruction
16 #
17 # register may have the following values:
18 # i integer register
19 # a r0 register (first argument/result reg)
20 # b base register (used in address references)
21 # f floating point register
22 # g floating point register returned in r0:r1 for soft-float mode
23 #
24 # len:number describe the maximun length in bytes of the instruction
25 # number is a positive integer
26 #
27 # cost:number describe how many cycles are needed to complete the instruction (unused)
28 #
29 # clob:spec describe if the instruction clobbers registers or has special needs
30 #
31 # spec can be one of the following characters:
32 # c clobbers caller-save registers
33 # r 'reserves' the destination register until a later instruction unreserves it
34 # used mostly to set output registers in function calls
35 #
36 # flags:spec describe if the instruction uses or sets the flags (unused)
37 #
38 # spec can be one of the following chars:
39 # s sets the flags
40 # u uses the flags
41 # m uses and modifies the flags
42 #
43 # res:spec describe what units are used in the processor (unused)
44 #
45 # delay: describe delay slots (unused)
46 #
47 # the required specifiers are: len, clob (if registers are clobbered), the registers
48 # specifiers if the registers are actually used, flags (when scheduling is implemented).
49 #
50 # See the code in mini-x86.c for more details on how the specifiers are used.
51 #
52 nop: len:4
53 relaxed_nop: len:4
54 break: len:4
55 br: len:16
56 switch: src1:i len:12
57 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
58 # since the corresponding sigctx structures are not well defined.
59 seq_point: len:52 clob:c
60 il_seq_point: len:0
62 throw: src1:i len:24
63 rethrow: src1:i len:20
64 start_handler: len:20
65 endfinally: len:32
66 call_handler: len:16 clob:c
67 endfilter: src1:i len:16
68 get_ex_obj: dest:i len:16
70 ckfinite: dest:f src1:f len:112
71 ceq: dest:i len:12
72 cgt: dest:i len:12
73 cgt.un: dest:i len:12
74 clt: dest:i len:12
75 clt.un: dest:i len:12
76 localloc: dest:i src1:i len:60
77 compare: src1:i src2:i len:4
78 compare_imm: src1:i len:12
79 fcompare: src1:f src2:f len:12
80 rcompare: src1:f src2:f len:12
81 oparglist: src1:i len:12
82 setlret: src1:i src2:i len:12
83 checkthis: src1:b len:4
84 call: dest:a clob:c len:20
85 call_reg: dest:a src1:i len:8 clob:c
86 call_membase: dest:a src1:b len:30 clob:c
87 voidcall: len:20 clob:c
88 voidcall_reg: src1:i len:8 clob:c
89 voidcall_membase: src1:b len:24 clob:c
90 fcall: dest:g len:28 clob:c
91 fcall_reg: dest:g src1:i len:16 clob:c
92 fcall_membase: dest:g src1:b len:30 clob:c
93 rcall: dest:g len:28 clob:c
94 rcall_reg: dest:g src1:i len:16 clob:c
95 rcall_membase: dest:g src1:b len:30 clob:c
96 lcall: dest:l len:20 clob:c
97 lcall_reg: dest:l src1:i len:8 clob:c
98 lcall_membase: dest:l src1:b len:24 clob:c
99 vcall: len:64 clob:c
100 vcall_reg: src1:i len:64 clob:c
101 vcall_membase: src1:b len:70 clob:c
102 tailcall: len:160 clob:c
103 iconst: dest:i len:16
104 r4const: dest:f len:24
105 r8const: dest:f len:20
106 label: len:0
107 store_membase_imm: dest:b len:20
108 store_membase_reg: dest:b src1:i len:20
109 storei1_membase_imm: dest:b len:20
110 storei1_membase_reg: dest:b src1:i len:12
111 storei2_membase_imm: dest:b len:20
112 storei2_membase_reg: dest:b src1:i len:12
113 storei4_membase_imm: dest:b len:20
114 storei4_membase_reg: dest:b src1:i len:20
115 storei8_membase_imm: dest:b
116 storei8_membase_reg: dest:b src1:i
117 storer4_membase_reg: dest:b src1:f len:60
118 storer8_membase_reg: dest:b src1:f len:24
119 store_memindex: dest:b src1:i src2:i len:4
120 storei1_memindex: dest:b src1:i src2:i len:4
121 storei2_memindex: dest:b src1:i src2:i len:4
122 storei4_memindex: dest:b src1:i src2:i len:4
123 load_membase: dest:i src1:b len:20
124 loadi1_membase: dest:i src1:b len:4
125 loadu1_membase: dest:i src1:b len:4
126 loadi2_membase: dest:i src1:b len:4
127 loadu2_membase: dest:i src1:b len:4
128 loadi4_membase: dest:i src1:b len:4
129 loadu4_membase: dest:i src1:b len:4
130 loadi8_membase: dest:i src1:b
131 loadr4_membase: dest:f src1:b len:56
132 loadr8_membase: dest:f src1:b len:24
133 load_memindex: dest:i src1:b src2:i len:4
134 loadi1_memindex: dest:i src1:b src2:i len:4
135 loadu1_memindex: dest:i src1:b src2:i len:4
136 loadi2_memindex: dest:i src1:b src2:i len:4
137 loadu2_memindex: dest:i src1:b src2:i len:4
138 loadi4_memindex: dest:i src1:b src2:i len:4
139 loadu4_memindex: dest:i src1:b src2:i len:4
140 loadu4_mem: dest:i len:8
141 move: dest:i src1:i len:4
142 fmove: dest:f src1:f len:4
143 move_f_to_i4: dest:i src1:f len:28
144 move_i4_to_f: dest:f src1:i len:8
145 add_imm: dest:i src1:i len:12
146 sub_imm: dest:i src1:i len:12
147 mul_imm: dest:i src1:i len:12
148 and_imm: dest:i src1:i len:12
149 or_imm: dest:i src1:i len:12
150 xor_imm: dest:i src1:i len:12
151 shl_imm: dest:i src1:i len:8
152 shr_imm: dest:i src1:i len:8
153 shr_un_imm: dest:i src1:i len:8
154 cond_exc_eq: len:8
155 cond_exc_ne_un: len:8
156 cond_exc_lt: len:8
157 cond_exc_lt_un: len:8
158 cond_exc_gt: len:8
159 cond_exc_gt_un: len:8
160 cond_exc_ge: len:8
161 cond_exc_ge_un: len:8
162 cond_exc_le: len:8
163 cond_exc_le_un: len:8
164 cond_exc_ov: len:12
165 cond_exc_no: len:8
166 cond_exc_c: len:12
167 cond_exc_nc: len:8
168 #float_beq: src1:f src2:f len:20
169 #float_bne_un: src1:f src2:f len:20
170 #float_blt: src1:f src2:f len:20
171 #float_blt_un: src1:f src2:f len:20
172 #float_bgt: src1:f src2:f len:20
173 #float_bgt_un: src1:f src2:f len:20
174 #float_bge: src1:f src2:f len:20
175 #float_bge_un: src1:f src2:f len:20
176 #float_ble: src1:f src2:f len:20
177 #float_ble_un: src1:f src2:f len:20
178 float_add: dest:f src1:f src2:f len:4
179 float_sub: dest:f src1:f src2:f len:4
180 float_mul: dest:f src1:f src2:f len:4
181 float_div: dest:f src1:f src2:f len:4
182 float_div_un: dest:f src1:f src2:f len:4
183 float_rem: dest:f src1:f src2:f len:16
184 float_rem_un: dest:f src1:f src2:f len:16
185 float_neg: dest:f src1:f len:4
186 float_not: dest:f src1:f len:4
187 float_conv_to_i1: dest:i src1:f len:88
188 float_conv_to_i2: dest:i src1:f len:88
189 float_conv_to_i4: dest:i src1:f len:88
190 float_conv_to_i8: dest:l src1:f len:88
191 float_conv_to_r4: dest:f src1:f len:8
192 float_conv_to_u4: dest:i src1:f len:88
193 float_conv_to_u8: dest:l src1:f len:88
194 float_conv_to_u2: dest:i src1:f len:88
195 float_conv_to_u1: dest:i src1:f len:88
196 float_conv_to_i: dest:i src1:f len:40
197 float_ceq: dest:i src1:f src2:f len:16
198 float_cgt: dest:i src1:f src2:f len:16
199 float_cgt_un: dest:i src1:f src2:f len:20
200 float_clt: dest:i src1:f src2:f len:16
201 float_clt_un: dest:i src1:f src2:f len:20
202 float_cneq: dest:y src1:f src2:f len:20
203 float_cge: dest:y src1:f src2:f len:20
204 float_cle: dest:y src1:f src2:f len:20
205 float_conv_to_u: dest:i src1:f len:36
207 # R4 opcodes
208 rmove: dest:f src1:f len:4
209 r4_conv_to_i1: dest:i src1:f len:88
210 r4_conv_to_i2: dest:i src1:f len:88
211 r4_conv_to_i4: dest:i src1:f len:88
212 r4_conv_to_u1: dest:i src1:f len:88
213 r4_conv_to_u2: dest:i src1:f len:88
214 r4_conv_to_u4: dest:i src1:f len:88
215 r4_conv_to_r4: dest:f src1:f len:16
216 r4_conv_to_r8: dest:f src1:f len:16
217 r4_add: dest:f src1:f src2:f len:4
218 r4_sub: dest:f src1:f src2:f len:4
219 r4_mul: dest:f src1:f src2:f len:4
220 r4_div: dest:f src1:f src2:f len:4
221 r4_rem: dest:f src1:f src2:f len:16
222 r4_neg: dest:f src1:f len:4
223 r4_ceq: dest:i src1:f src2:f len:16
224 r4_cgt: dest:i src1:f src2:f len:16
225 r4_cgt_un: dest:i src1:f src2:f len:20
226 r4_clt: dest:i src1:f src2:f len:16
227 r4_clt_un: dest:i src1:f src2:f len:20
228 r4_cneq: dest:y src1:f src2:f len:20
229 r4_cge: dest:y src1:f src2:f len:20
230 r4_cle: dest:y src1:f src2:f len:20
232 setfret: src1:f len:12
233 aot_const: dest:i len:16
234 objc_get_selector: dest:i len:32
235 sqrt: dest:f src1:f len:4
236 adc: dest:i src1:i src2:i len:4
237 addcc: dest:i src1:i src2:i len:4
238 subcc: dest:i src1:i src2:i len:4
239 adc_imm: dest:i src1:i len:12
240 addcc_imm: dest:i src1:i len:12
241 subcc_imm: dest:i src1:i len:12
242 sbb: dest:i src1:i src2:i len:4
243 sbb_imm: dest:i src1:i len:12
244 br_reg: src1:i len:8
245 bigmul: len:8 dest:l src1:i src2:i
246 bigmul_un: len:8 dest:l src1:i src2:i
247 tls_get: len:24 dest:i clob:c
248 tls_get_reg: len:28 dest:i src1:i clob:c
249 tls_set: len:24 src1:i clob:c
250 tls_set_reg: len:28 src1:i src2:i clob:c
252 # 32 bit opcodes
253 int_add: dest:i src1:i src2:i len:4
254 int_sub: dest:i src1:i src2:i len:4
255 int_mul: dest:i src1:i src2:i len:4
256 int_div: dest:i src1:i src2:i len:4
257 int_div_un: dest:i src1:i src2:i len:4
258 int_rem: dest:i src1:i src2:i len:8
259 int_rem_un: dest:i src1:i src2:i len:8
260 int_and: dest:i src1:i src2:i len:4
261 int_or: dest:i src1:i src2:i len:4
262 int_xor: dest:i src1:i src2:i len:4
263 int_shl: dest:i src1:i src2:i len:4
264 int_shr: dest:i src1:i src2:i len:4
265 int_shr_un: dest:i src1:i src2:i len:4
266 int_neg: dest:i src1:i len:4
267 int_not: dest:i src1:i len:4
268 int_conv_to_i1: dest:i src1:i len:8
269 int_conv_to_i2: dest:i src1:i len:8
270 int_conv_to_i4: dest:i src1:i len:4
271 int_conv_to_r4: dest:f src1:i len:84
272 int_conv_to_r8: dest:f src1:i len:84
273 int_conv_to_u4: dest:i src1:i
274 int_conv_to_r_un: dest:f src1:i len:56
275 int_conv_to_u2: dest:i src1:i len:8
276 int_conv_to_u1: dest:i src1:i len:4
277 int_beq: len:16
278 int_bge: len:16
279 int_bgt: len:16
280 int_ble: len:16
281 int_blt: len:16
282 int_bne_un: len:16
283 int_bge_un: len:16
284 int_bgt_un: len:16
285 int_ble_un: len:16
286 int_blt_un: len:16
287 int_add_ovf: dest:i src1:i src2:i len:16
288 int_add_ovf_un: dest:i src1:i src2:i len:16
289 int_mul_ovf: dest:i src1:i src2:i len:16
290 int_mul_ovf_un: dest:i src1:i src2:i len:16
291 int_sub_ovf: dest:i src1:i src2:i len:16
292 int_sub_ovf_un: dest:i src1:i src2:i len:16
293 add_ovf_carry: dest:i src1:i src2:i len:16
294 sub_ovf_carry: dest:i src1:i src2:i len:16
295 add_ovf_un_carry: dest:i src1:i src2:i len:16
296 sub_ovf_un_carry: dest:i src1:i src2:i len:16
298 arm_rsbs_imm: dest:i src1:i len:4
299 arm_rsc_imm: dest:i src1:i len:4
301 # Linear IR opcodes
302 dummy_use: src1:i len:0
303 dummy_store: len:0
304 dummy_iconst: dest:i len:0
305 dummy_r8const: dest:f len:0
306 not_reached: len:0
307 not_null: src1:i len:0
309 int_adc: dest:i src1:i src2:i len:4
310 int_addcc: dest:i src1:i src2:i len:4
311 int_subcc: dest:i src1:i src2:i len:4
312 int_sbb: dest:i src1:i src2:i len:4
313 int_adc_imm: dest:i src1:i len:12
314 int_sbb_imm: dest:i src1:i len:12
316 int_add_imm: dest:i src1:i len:12
317 int_sub_imm: dest:i src1:i len:12
318 int_mul_imm: dest:i src1:i len:12
319 int_div_imm: dest:i src1:i len:20
320 int_div_un_imm: dest:i src1:i len:12
321 int_rem_imm: dest:i src1:i len:28
322 int_rem_un_imm: dest:i src1:i len:16
323 int_and_imm: dest:i src1:i len:12
324 int_or_imm: dest:i src1:i len:12
325 int_xor_imm: dest:i src1:i len:12
326 int_shl_imm: dest:i src1:i len:8
327 int_shr_imm: dest:i src1:i len:8
328 int_shr_un_imm: dest:i src1:i len:8
330 int_ceq: dest:i len:12
331 int_cgt: dest:i len:12
332 int_cgt_un: dest:i len:12
333 int_clt: dest:i len:12
334 int_clt_un: dest:i len:12
336 int_cneq: dest:i len:12
337 int_cge: dest:i len:12
338 int_cle: dest:i len:12
339 int_cge_un: dest:i len:12
340 int_cle_un: dest:i len:12
342 cond_exc_ieq: len:16
343 cond_exc_ine_un: len:16
344 cond_exc_ilt: len:16
345 cond_exc_ilt_un: len:16
346 cond_exc_igt: len:16
347 cond_exc_igt_un: len:16
348 cond_exc_ige: len:16
349 cond_exc_ige_un: len:16
350 cond_exc_ile: len:16
351 cond_exc_ile_un: len:16
352 cond_exc_iov: len:20
353 cond_exc_ino: len:16
354 cond_exc_ic: len:20
355 cond_exc_inc: len:16
357 icompare: src1:i src2:i len:4
358 icompare_imm: src1:i len:12
360 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
362 vcall2: len:64 clob:c
363 vcall2_reg: src1:i len:64 clob:c
364 vcall2_membase: src1:b len:64 clob:c
365 dyn_call: src1:i src2:i len:252 clob:c
367 # This is different from the original JIT opcodes
368 float_beq: len:32
369 float_bne_un: len:32
370 float_blt: len:32
371 float_blt_un: len:32
372 float_bgt: len:32
373 float_bgt_un: len:32
374 float_bge: len:32
375 float_bge_un: len:32
376 float_ble: len:32
377 float_ble_un: len:32
379 liverange_start: len:0
380 liverange_end: len:0
381 gc_liveness_def: len:0
382 gc_liveness_use: len:0
383 gc_spill_slot_liveness_def: len:0
384 gc_param_slot_liveness_def: len:0
385 gc_safe_point: clob:c src1:i len:40
387 atomic_add_i4: dest:i src1:i src2:i len:64
388 atomic_exchange_i4: dest:i src1:i src2:i len:64
389 atomic_cas_i4: dest:i src1:i src2:i src3:i len:64
390 memory_barrier: len:8 clob:a
391 atomic_load_i1: dest:i src1:b len:28
392 atomic_load_u1: dest:i src1:b len:28
393 atomic_load_i2: dest:i src1:b len:28
394 atomic_load_u2: dest:i src1:b len:28
395 atomic_load_i4: dest:i src1:b len:28
396 atomic_load_u4: dest:i src1:b len:28
397 atomic_load_r4: dest:f src1:b len:80
398 atomic_load_r8: dest:f src1:b len:32
399 atomic_store_i1: dest:b src1:i len:28
400 atomic_store_u1: dest:b src1:i len:28
401 atomic_store_i2: dest:b src1:i len:28
402 atomic_store_u2: dest:b src1:i len:28
403 atomic_store_i4: dest:b src1:i len:28
404 atomic_store_u4: dest:b src1:i len:28
405 atomic_store_r4: dest:b src1:f len:80
406 atomic_store_r8: dest:b src1:f len:32
408 generic_class_init: src1:a len:44 clob:c