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[win32] Fix some compilation warnings (#15956)
[mono-project.git] / mono / mini / mini-x86.c
blobe820e47939e2e1d3ea75c983e08723916353ad88
1 /**
2 * \file
3 * x86 backend for the Mono code generator
4 *
5 * Authors:
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
8 * Patrik Torstensson
9 *
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
14 */
15 #include "mini.h"
16 #include <string.h>
17 #include <math.h>
18 #ifdef HAVE_UNISTD_H
19 #include <unistd.h>
20 #endif
21
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
36
37 #include "mini-x86.h"
38 #include "cpu-x86.h"
39 #include "ir-emit.h"
40 #include "mini-gc.h"
41 #include "aot-runtime.h"
42 #include "mini-runtime.h"
43
44 #ifndef TARGET_WIN32
45 #ifdef MONO_XEN_OPT
46 static gboolean optimize_for_xen = TRUE;
47 #else
48 #define optimize_for_xen 0
49 #endif
50 #endif
51
52 static GENERATE_TRY_GET_CLASS_WITH_CACHE (math, "System", "Math")
53
54
55 /* The single step trampoline */
56 static gpointer ss_trampoline;
57
58 /* The breakpoint trampoline */
59 static gpointer bp_trampoline;
60
61 #define ARGS_OFFSET 8
62
63 #ifdef TARGET_WIN32
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
66 #else
67 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
68 #endif
69
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
71
72 #define OP_SEQ_POINT_BP_OFFSET 7
73
74 const char*
75 mono_arch_regname (int reg)
76 {
77 switch (reg) {
78 case X86_EAX: return "%eax";
79 case X86_EBX: return "%ebx";
80 case X86_ECX: return "%ecx";
81 case X86_EDX: return "%edx";
82 case X86_ESP: return "%esp";
83 case X86_EBP: return "%ebp";
84 case X86_EDI: return "%edi";
85 case X86_ESI: return "%esi";
86 }
87 return "unknown";
88 }
89
90 const char*
91 mono_arch_fregname (int reg)
92 {
93 switch (reg) {
94 case 0:
95 return "%fr0";
96 case 1:
97 return "%fr1";
98 case 2:
99 return "%fr2";
100 case 3:
101 return "%fr3";
102 case 4:
103 return "%fr4";
104 case 5:
105 return "%fr5";
106 case 6:
107 return "%fr6";
108 case 7:
109 return "%fr7";
110 default:
111 return "unknown";
112 }
113 }
114
115 const char *
116 mono_arch_xregname (int reg)
117 {
118 switch (reg) {
119 case 0:
120 return "%xmm0";
121 case 1:
122 return "%xmm1";
123 case 2:
124 return "%xmm2";
125 case 3:
126 return "%xmm3";
127 case 4:
128 return "%xmm4";
129 case 5:
130 return "%xmm5";
131 case 6:
132 return "%xmm6";
133 case 7:
134 return "%xmm7";
135 default:
136 return "unknown";
137 }
138 }
139
140 void
141 mono_x86_patch (unsigned char* code, gpointer target)
142 {
143 x86_patch (code, (unsigned char*)target);
144 }
145
146 #define FLOAT_PARAM_REGS 0
147
148 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
149
150 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
151 {
152 if (!sig->pinvoke)
153 return NULL;
154
155 switch (sig->call_convention) {
156 case MONO_CALL_THISCALL:
157 return thiscall_param_regs;
158 default:
159 return NULL;
160 }
161 }
162
163 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
164 #define SMALL_STRUCTS_IN_REGS
165 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
166 #endif
167
168 static void inline
169 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
170 {
171 ainfo->offset = *stack_size;
172
173 if (!param_regs || param_regs [*gr] == X86_NREG) {
174 ainfo->storage = ArgOnStack;
175 ainfo->nslots = 1;
176 (*stack_size) += sizeof (target_mgreg_t);
177 }
178 else {
179 ainfo->storage = ArgInIReg;
180 ainfo->reg = param_regs [*gr];
181 (*gr) ++;
182 }
183 }
184
185 static void inline
186 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
187 {
188 ainfo->offset = *stack_size;
189
190 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
191
192 ainfo->storage = ArgOnStack;
193 (*stack_size) += sizeof (target_mgreg_t) * 2;
194 ainfo->nslots = 2;
195 }
196
197 static void inline
198 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
199 {
200 ainfo->offset = *stack_size;
201
202 if (*gr >= FLOAT_PARAM_REGS) {
203 ainfo->storage = ArgOnStack;
204 (*stack_size) += is_double ? 8 : 4;
205 ainfo->nslots = is_double ? 2 : 1;
206 }
207 else {
208 /* A double register */
209 if (is_double)
210 ainfo->storage = ArgInDoubleSSEReg;
211 else
212 ainfo->storage = ArgInFloatSSEReg;
213 ainfo->reg = *gr;
214 (*gr) += 1;
215 }
216 }
217
218
219 static void
220 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
221 gboolean is_return,
222 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
223 {
224 guint32 size;
225 MonoClass *klass;
226
227 klass = mono_class_from_mono_type_internal (type);
228 size = mini_type_stack_size_full (m_class_get_byval_arg (klass), NULL, sig->pinvoke);
229
230 #if defined(TARGET_WIN32)
231 /*
232 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
233 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
234 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
235 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
236 * it must be represented in call and cannot be dropped.
237 */
238 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
239 /* Empty structs (1 byte size) needs to be represented in a stack slot */
240 ainfo->pass_empty_struct = TRUE;
241 size = 1;
242 }
243 #endif
244
245 #ifdef SMALL_STRUCTS_IN_REGS
246 if (sig->pinvoke && is_return) {
247 MonoMarshalType *info;
248
249 info = mono_marshal_load_type_info (klass);
250 g_assert (info);
251
252 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
253
254 /* Ignore empty struct return value, if used. */
255 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
256 ainfo->storage = ArgValuetypeInReg;
257 return;
258 }
259
260 /*
261 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
262 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
263 * This is different compared to for example float or double return types (not in struct) that will be returned
264 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
265 *
266 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
267 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
268 * This means that structs with one float or double will be returned in ST(0). For more details,
269 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
270 */
271 #if !defined(TARGET_WIN32)
272
273 /* Special case structs with only a float member */
274 if (info->num_fields == 1) {
275 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
276 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
277 ainfo->storage = ArgValuetypeInReg;
278 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
279 return;
280 }
281 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
282 ainfo->storage = ArgValuetypeInReg;
283 ainfo->pair_storage [0] = ArgOnFloatFpStack;
284 return;
285 }
286 }
287 #endif
288
289 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
290 ainfo->storage = ArgValuetypeInReg;
291 ainfo->pair_storage [0] = ArgInIReg;
292 ainfo->pair_regs [0] = return_regs [0];
293 if (info->native_size > 4) {
294 ainfo->pair_storage [1] = ArgInIReg;
295 ainfo->pair_regs [1] = return_regs [1];
296 }
297 return;
298 }
299 }
300 #endif
301
302 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
303 g_assert (size <= 4);
304 ainfo->storage = ArgValuetypeInReg;
305 ainfo->reg = param_regs [*gr];
306 (*gr)++;
307 return;
308 }
309
310 ainfo->offset = *stack_size;
311 ainfo->storage = ArgOnStack;
312 *stack_size += ALIGN_TO (size, sizeof (target_mgreg_t));
313 ainfo->nslots = ALIGN_TO (size, sizeof (target_mgreg_t)) / sizeof (target_mgreg_t);
314 }
315
316 /*
317 * get_call_info:
318 *
319 * Obtain information about a call according to the calling convention.
320 * For x86 ELF, see the "System V Application Binary Interface Intel386
321 * Architecture Processor Supplment, Fourth Edition" document for more
322 * information.
323 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
324 */
325 static CallInfo*
326 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
327 {
328 guint32 i, gr, fr, pstart;
329 const guint32 *param_regs;
330 MonoType *ret_type;
331 int n = sig->hasthis + sig->param_count;
332 guint32 stack_size = 0;
333 gboolean is_pinvoke = sig->pinvoke;
334
335 gr = 0;
336 fr = 0;
337 cinfo->nargs = n;
338
339 param_regs = callconv_param_regs(sig);
340
341 /* return value */
342 {
343 ret_type = mini_get_underlying_type (sig->ret);
344 switch (ret_type->type) {
345 case MONO_TYPE_I1:
346 case MONO_TYPE_U1:
347 case MONO_TYPE_I2:
348 case MONO_TYPE_U2:
349 case MONO_TYPE_I4:
350 case MONO_TYPE_U4:
351 case MONO_TYPE_I:
352 case MONO_TYPE_U:
353 case MONO_TYPE_PTR:
354 case MONO_TYPE_FNPTR:
355 case MONO_TYPE_OBJECT:
356 cinfo->ret.storage = ArgInIReg;
357 cinfo->ret.reg = X86_EAX;
358 break;
359 case MONO_TYPE_U8:
360 case MONO_TYPE_I8:
361 cinfo->ret.storage = ArgInIReg;
362 cinfo->ret.reg = X86_EAX;
363 cinfo->ret.is_pair = TRUE;
364 break;
365 case MONO_TYPE_R4:
366 cinfo->ret.storage = ArgOnFloatFpStack;
367 break;
368 case MONO_TYPE_R8:
369 cinfo->ret.storage = ArgOnDoubleFpStack;
370 break;
371 case MONO_TYPE_GENERICINST:
372 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
373 cinfo->ret.storage = ArgInIReg;
374 cinfo->ret.reg = X86_EAX;
375 break;
376 }
377 if (mini_is_gsharedvt_type (ret_type)) {
378 cinfo->ret.storage = ArgOnStack;
379 cinfo->vtype_retaddr = TRUE;
380 break;
381 }
382 /* Fall through */
383 case MONO_TYPE_VALUETYPE:
384 case MONO_TYPE_TYPEDBYREF: {
385 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
386
387 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
388 if (cinfo->ret.storage == ArgOnStack) {
389 cinfo->vtype_retaddr = TRUE;
390 /* The caller passes the address where the value is stored */
391 }
392 break;
393 }
394 case MONO_TYPE_VAR:
395 case MONO_TYPE_MVAR:
396 g_assert (mini_is_gsharedvt_type (ret_type));
397 cinfo->ret.storage = ArgOnStack;
398 cinfo->vtype_retaddr = TRUE;
399 break;
400 case MONO_TYPE_VOID:
401 cinfo->ret.storage = ArgNone;
402 break;
403 default:
404 g_error ("Can't handle as return value 0x%x", ret_type->type);
405 }
406 }
407
408 pstart = 0;
409 /*
410 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
411 * the first argument, allowing 'this' to be always passed in the first arg reg.
412 * Also do this if the first argument is a reference type, since virtual calls
413 * are sometimes made using calli without sig->hasthis set, like in the delegate
414 * invoke wrappers.
415 */
416 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
417 if (sig->hasthis) {
418 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
419 } else {
420 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
421 pstart = 1;
422 }
423 cinfo->vret_arg_offset = stack_size;
424 add_general (&gr, NULL, &stack_size, &cinfo->ret);
425 cinfo->vret_arg_index = 1;
426 } else {
427 /* this */
428 if (sig->hasthis)
429 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
430
431 if (cinfo->vtype_retaddr)
432 add_general (&gr, NULL, &stack_size, &cinfo->ret);
433 }
434
435 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
436 fr = FLOAT_PARAM_REGS;
437
438 /* Emit the signature cookie just before the implicit arguments */
439 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
440 }
441
442 for (i = pstart; i < sig->param_count; ++i) {
443 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
444 MonoType *ptype;
445
446 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
447 /* We allways pass the sig cookie on the stack for simplicity */
448 /*
449 * Prevent implicit arguments + the sig cookie from being passed
450 * in registers.
451 */
452 fr = FLOAT_PARAM_REGS;
453
454 /* Emit the signature cookie just before the implicit arguments */
455 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
456 }
457
458 if (sig->params [i]->byref) {
459 add_general (&gr, param_regs, &stack_size, ainfo);
460 continue;
461 }
462 ptype = mini_get_underlying_type (sig->params [i]);
463 switch (ptype->type) {
464 case MONO_TYPE_I1:
465 case MONO_TYPE_U1:
466 add_general (&gr, param_regs, &stack_size, ainfo);
467 break;
468 case MONO_TYPE_I2:
469 case MONO_TYPE_U2:
470 add_general (&gr, param_regs, &stack_size, ainfo);
471 break;
472 case MONO_TYPE_I4:
473 case MONO_TYPE_U4:
474 add_general (&gr, param_regs, &stack_size, ainfo);
475 break;
476 case MONO_TYPE_I:
477 case MONO_TYPE_U:
478 case MONO_TYPE_PTR:
479 case MONO_TYPE_FNPTR:
480 case MONO_TYPE_OBJECT:
481 add_general (&gr, param_regs, &stack_size, ainfo);
482 break;
483 case MONO_TYPE_GENERICINST:
484 if (!mono_type_generic_inst_is_valuetype (ptype)) {
485 add_general (&gr, param_regs, &stack_size, ainfo);
486 break;
487 }
488 if (mini_is_gsharedvt_type (ptype)) {
489 /* gsharedvt arguments are passed by ref */
490 add_general (&gr, param_regs, &stack_size, ainfo);
491 g_assert (ainfo->storage == ArgOnStack);
492 ainfo->storage = ArgGSharedVt;
493 break;
494 }
495 /* Fall through */
496 case MONO_TYPE_VALUETYPE:
497 case MONO_TYPE_TYPEDBYREF:
498 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
499 break;
500 case MONO_TYPE_U8:
501 case MONO_TYPE_I8:
502 add_general_pair (&gr, param_regs, &stack_size, ainfo);
503 break;
504 case MONO_TYPE_R4:
505 add_float (&fr, &stack_size, ainfo, FALSE);
506 break;
507 case MONO_TYPE_R8:
508 add_float (&fr, &stack_size, ainfo, TRUE);
509 break;
510 case MONO_TYPE_VAR:
511 case MONO_TYPE_MVAR:
512 /* gsharedvt arguments are passed by ref */
513 g_assert (mini_is_gsharedvt_type (ptype));
514 add_general (&gr, param_regs, &stack_size, ainfo);
515 g_assert (ainfo->storage == ArgOnStack);
516 ainfo->storage = ArgGSharedVt;
517 break;
518 default:
519 g_error ("unexpected type 0x%x", ptype->type);
520 g_assert_not_reached ();
521 }
522 }
523
524 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
525 fr = FLOAT_PARAM_REGS;
526
527 /* Emit the signature cookie just before the implicit arguments */
528 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
529 }
530
531 if (cinfo->vtype_retaddr) {
532 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
533 cinfo->callee_stack_pop = 4;
534 } else if (CALLCONV_IS_STDCALL (sig)) {
535 /* Have to compensate for the stack space popped by the native callee */
536 cinfo->callee_stack_pop = stack_size;
537 }
538
539 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
540 cinfo->need_stack_align = TRUE;
541 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
542 stack_size += cinfo->stack_align_amount;
543 }
544
545 cinfo->stack_usage = stack_size;
546 cinfo->reg_usage = gr;
547 cinfo->freg_usage = fr;
548 return cinfo;
549 }
550
551 static CallInfo*
552 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
553 {
554 int n = sig->hasthis + sig->param_count;
555 CallInfo *cinfo;
556
557 if (mp)
558 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
559 else
560 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
561
562 return get_call_info_internal (cinfo, sig);
563 }
564
565 static gboolean storage_in_ireg (ArgStorage storage)
566 {
567 return (storage == ArgInIReg || storage == ArgValuetypeInReg);
568 }
569
570 /*
571 * mono_arch_get_argument_info:
572 * @csig: a method signature
573 * @param_count: the number of parameters to consider
574 * @arg_info: an array to store the result infos
575 *
576 * Gathers information on parameters such as size, alignment and
577 * padding. arg_info should be large enought to hold param_count + 1 entries.
578 *
579 * Returns the size of the argument area on the stack.
580 * This should be signal safe, since it is called from
581 * mono_arch_unwind_frame ().
582 * FIXME: The metadata calls might not be signal safe.
583 */
584 int
585 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
586 {
587 int len, k, args_size = 0;
588 int size, pad;
589 guint32 align;
590 int offset = 8;
591 CallInfo *cinfo;
592 int prev_stackarg;
593 int num_regs;
594
595 /* Avoid g_malloc as it is not signal safe */
596 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
597 cinfo = (CallInfo*)g_alloca (len);
598 memset (cinfo, 0, len);
599
600 cinfo = get_call_info_internal (cinfo, csig);
601
602 arg_info [0].offset = offset;
603
604 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
605 args_size += sizeof (target_mgreg_t);
606 offset += 4;
607 }
608
609 if (csig->hasthis && !storage_in_ireg (cinfo->args [0].storage)) {
610 args_size += sizeof (target_mgreg_t);
611 offset += 4;
612 }
613
614 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
615 /* Emitted after this */
616 args_size += sizeof (target_mgreg_t);
617 offset += 4;
618 }
619
620 arg_info [0].size = args_size;
621 prev_stackarg = 0;
622
623 for (k = 0; k < param_count; k++) {
624 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
625
626 if (storage_in_ireg (cinfo->args [csig->hasthis + k].storage)) {
627 /* not in stack, we'll give it an offset at the end */
628 arg_info [k + 1].pad = 0;
629 arg_info [k + 1].size = size;
630 } else {
631 /* ignore alignment for now */
632 align = 1;
633
634 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
635 arg_info [prev_stackarg].pad = pad;
636 args_size += size;
637 arg_info [k + 1].pad = 0;
638 arg_info [k + 1].size = size;
639 offset += pad;
640 arg_info [k + 1].offset = offset;
641 offset += size;
642 prev_stackarg = k + 1;
643 }
644
645 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
646 /* Emitted after the first arg */
647 args_size += sizeof (target_mgreg_t);
648 offset += 4;
649 }
650 }
651
652 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
653 align = MONO_ARCH_FRAME_ALIGNMENT;
654 else
655 align = 4;
656 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
657 arg_info [k].pad = pad;
658
659 /* Add offsets for any reg parameters */
660 num_regs = 0;
661 if (csig->hasthis && storage_in_ireg (cinfo->args [0].storage))
662 arg_info [0].offset = args_size + 4 * num_regs++;
663 for (k=0; k < param_count; k++) {
664 if (storage_in_ireg (cinfo->args[csig->hasthis + k].storage)) {
665 arg_info [k + 1].offset = args_size + 4 * num_regs++;
666 }
667 }
668
669 return args_size;
670 }
671
672 #ifndef DISABLE_JIT
673
674 gboolean
675 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
676 {
677 g_assert (caller_sig);
678 g_assert (callee_sig);
679
680 // Direct AOT calls usually go through the PLT/GOT.
681 // Unless we can determine here if is_direct_callable will return TRUE?
682 // But the PLT/GOT is addressed with nonvolatile ebx, which
683 // gets restored before the jump.
684 // See https://github.com/mono/mono/commit/f5373adc8a89d4b0d1d549fdd6d9adc3ded4b400
685 // See https://github.com/mono/mono/issues/11265
686 if (!virtual_ && cfg->compile_aot && !cfg->full_aot)
687 return FALSE;
688
689 CallInfo *caller_info = get_call_info (NULL, caller_sig);
690 CallInfo *callee_info = get_call_info (NULL, callee_sig);
691
692 /*
693 * Tailcalls with more callee stack usage than the caller cannot be supported, since
694 * the extra stack space would be left on the stack after the tailcall.
695 */
696 gboolean res = IS_SUPPORTED_TAILCALL (callee_info->stack_usage <= caller_info->stack_usage)
697 && IS_SUPPORTED_TAILCALL (caller_info->ret.storage == callee_info->ret.storage);
698 if (!res && !mono_tailcall_print_enabled ())
699 goto exit;
700
701 // Limit stack_usage to 1G.
702 res &= IS_SUPPORTED_TAILCALL (callee_info->stack_usage < (1 << 30));
703 res &= IS_SUPPORTED_TAILCALL (caller_info->stack_usage < (1 << 30));
704
705 exit:
706 g_free (caller_info);
707 g_free (callee_info);
708
709 return res;
710 }
711
712 #endif
713
714 /*
715 * Initialize the cpu to execute managed code.
716 */
717 void
718 mono_arch_cpu_init (void)
719 {
720 /* spec compliance requires running with double precision */
721 #ifndef _MSC_VER
722 guint16 fpcw;
723
724 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
725 fpcw &= ~X86_FPCW_PRECC_MASK;
726 fpcw |= X86_FPCW_PREC_DOUBLE;
727 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
728 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
729 #else
730 _control87 (_PC_53, MCW_PC);
731 #endif
732 }
733
734 /*
735 * Initialize architecture specific code.
736 */
737 void
738 mono_arch_init (void)
739 {
740 if (!mono_aot_only)
741 bp_trampoline = mini_get_breakpoint_trampoline ();
742 }
743
744 /*
745 * Cleanup architecture specific code.
746 */
747 void
748 mono_arch_cleanup (void)
749 {
750 }
751
752 /*
753 * This function returns the optimizations supported on this cpu.
754 */
755 guint32
756 mono_arch_cpu_optimizations (guint32 *exclude_mask)
757 {
758 guint32 opts = 0;
759
760 *exclude_mask = 0;
761
762 if (mono_hwcap_x86_has_cmov) {
763 opts |= MONO_OPT_CMOV;
764
765 if (mono_hwcap_x86_has_fcmov)
766 opts |= MONO_OPT_FCMOV;
767 else
768 *exclude_mask |= MONO_OPT_FCMOV;
769 } else {
770 *exclude_mask |= MONO_OPT_CMOV;
771 }
772
773 if (mono_hwcap_x86_has_sse2)
774 opts |= MONO_OPT_SSE2;
775 else
776 *exclude_mask |= MONO_OPT_SSE2;
777
778 #ifdef MONO_ARCH_SIMD_INTRINSICS
779 /*SIMD intrinsics require at least SSE2.*/
780 if (!mono_hwcap_x86_has_sse2)
781 *exclude_mask |= MONO_OPT_SIMD;
782 #endif
783
784 return opts;
785 }
786
787 /*
788 * This function test for all SSE functions supported.
789 *
790 * Returns a bitmask corresponding to all supported versions.
791 *
792 */
793 guint32
794 mono_arch_cpu_enumerate_simd_versions (void)
795 {
796 guint32 sse_opts = 0;
797
798 if (mono_hwcap_x86_has_sse1)
799 sse_opts |= SIMD_VERSION_SSE1;
800
801 if (mono_hwcap_x86_has_sse2)
802 sse_opts |= SIMD_VERSION_SSE2;
803
804 if (mono_hwcap_x86_has_sse3)
805 sse_opts |= SIMD_VERSION_SSE3;
806
807 if (mono_hwcap_x86_has_ssse3)
808 sse_opts |= SIMD_VERSION_SSSE3;
809
810 if (mono_hwcap_x86_has_sse41)
811 sse_opts |= SIMD_VERSION_SSE41;
812
813 if (mono_hwcap_x86_has_sse42)
814 sse_opts |= SIMD_VERSION_SSE42;
815
816 if (mono_hwcap_x86_has_sse4a)
817 sse_opts |= SIMD_VERSION_SSE4a;
818
819 return sse_opts;
820 }
821
822 /*
823 * Determine whenever the trap whose info is in SIGINFO is caused by
824 * integer overflow.
825 */
826 gboolean
827 mono_arch_is_int_overflow (void *sigctx, void *info)
828 {
829 MonoContext ctx;
830 guint8* ip;
831
832 mono_sigctx_to_monoctx (sigctx, &ctx);
833
834 ip = (guint8*)ctx.eip;
835
836 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
837 gint32 reg;
838
839 /* idiv REG */
840 switch (x86_modrm_rm (ip [1])) {
841 case X86_EAX:
842 reg = ctx.eax;
843 break;
844 case X86_ECX:
845 reg = ctx.ecx;
846 break;
847 case X86_EDX:
848 reg = ctx.edx;
849 break;
850 case X86_EBX:
851 reg = ctx.ebx;
852 break;
853 case X86_ESI:
854 reg = ctx.esi;
855 break;
856 case X86_EDI:
857 reg = ctx.edi;
858 break;
859 default:
860 g_assert_not_reached ();
861 reg = -1;
862 }
863
864 if (reg == -1)
865 return TRUE;
866 }
867
868 return FALSE;
869 }
870
871 GList *
872 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
873 {
874 GList *vars = NULL;
875 int i;
876
877 for (i = 0; i < cfg->num_varinfo; i++) {
878 MonoInst *ins = cfg->varinfo [i];
879 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
880
881 /* unused vars */
882 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
883 continue;
884
885 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
886 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
887 continue;
888
889 /* we dont allocate I1 to registers because there is no simply way to sign extend
890 * 8bit quantities in caller saved registers on x86 */
891 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
892 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
893 g_assert (i == vmv->idx);
894 vars = g_list_prepend (vars, vmv);
895 }
896 }
897
898 vars = mono_varlist_sort (cfg, vars, 0);
899
900 return vars;
901 }
902
903 GList *
904 mono_arch_get_global_int_regs (MonoCompile *cfg)
905 {
906 GList *regs = NULL;
907
908 /* we can use 3 registers for global allocation */
909 regs = g_list_prepend (regs, (gpointer)X86_EBX);
910 regs = g_list_prepend (regs, (gpointer)X86_ESI);
911 regs = g_list_prepend (regs, (gpointer)X86_EDI);
912
913 return regs;
914 }
915
916 /*
917 * mono_arch_regalloc_cost:
918 *
919 * Return the cost, in number of memory references, of the action of
920 * allocating the variable VMV into a register during global register
921 * allocation.
922 */
923 guint32
924 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
925 {
926 MonoInst *ins = cfg->varinfo [vmv->idx];
927
928 if (cfg->method->save_lmf)
929 /* The register is already saved */
930 return (ins->opcode == OP_ARG) ? 1 : 0;
931 else
932 /* push+pop+possible load if it is an argument */
933 return (ins->opcode == OP_ARG) ? 3 : 2;
934 }
935
936 static void
937 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
938 {
939 static int inited = FALSE;
940 static int count = 0;
941
942 if (cfg->arch.need_stack_frame_inited) {
943 g_assert (cfg->arch.need_stack_frame == flag);
944 return;
945 }
946
947 cfg->arch.need_stack_frame = flag;
948 cfg->arch.need_stack_frame_inited = TRUE;
949
950 if (flag)
951 return;
952
953 if (!inited) {
954 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
955 inited = TRUE;
956 }
957 ++count;
958
959 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
960 }
961
962 static gboolean
963 needs_stack_frame (MonoCompile *cfg)
964 {
965 MonoMethodSignature *sig;
966 MonoMethodHeader *header;
967 gboolean result = FALSE;
968
969 #if defined (__APPLE__)
970 /*OSX requires stack frame code to have the correct alignment. */
971 return TRUE;
972 #endif
973
974 if (cfg->arch.need_stack_frame_inited)
975 return cfg->arch.need_stack_frame;
976
977 header = cfg->header;
978 sig = mono_method_signature_internal (cfg->method);
979
980 if (cfg->disable_omit_fp)
981 result = TRUE;
982 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
983 result = TRUE;
984 else if (cfg->method->save_lmf)
985 result = TRUE;
986 else if (cfg->stack_offset)
987 result = TRUE;
988 else if (cfg->param_area)
989 result = TRUE;
990 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAILCALL))
991 result = TRUE;
992 else if (header->num_clauses)
993 result = TRUE;
994 else if (sig->param_count + sig->hasthis)
995 result = TRUE;
996 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
997 result = TRUE;
998
999 set_needs_stack_frame (cfg, result);
1000
1001 return cfg->arch.need_stack_frame;
1002 }
1003
1004 /*
1005 * Set var information according to the calling convention. X86 version.
1006 * The locals var stuff should most likely be split in another method.
1007 */
1008 void
1009 mono_arch_allocate_vars (MonoCompile *cfg)
1010 {
1011 MonoMethodSignature *sig;
1012 MonoInst *inst;
1013 guint32 locals_stack_size, locals_stack_align;
1014 int i, offset;
1015 gint32 *offsets;
1016 CallInfo *cinfo;
1017
1018 sig = mono_method_signature_internal (cfg->method);
1019
1020 if (!cfg->arch.cinfo)
1021 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1022 cinfo = cfg->arch.cinfo;
1023
1024 cfg->frame_reg = X86_EBP;
1025 offset = 0;
1026
1027 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1028 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1029 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1030 }
1031
1032 /* Reserve space to save LMF and caller saved registers */
1033
1034 if (cfg->method->save_lmf) {
1035 /* The LMF var is allocated normally */
1036 } else {
1037 if (cfg->used_int_regs & (1 << X86_EBX)) {
1038 offset += 4;
1039 }
1040
1041 if (cfg->used_int_regs & (1 << X86_EDI)) {
1042 offset += 4;
1043 }
1044
1045 if (cfg->used_int_regs & (1 << X86_ESI)) {
1046 offset += 4;
1047 }
1048 }
1049
1050 switch (cinfo->ret.storage) {
1051 case ArgValuetypeInReg:
1052 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1053 offset += 8;
1054 cfg->ret->opcode = OP_REGOFFSET;
1055 cfg->ret->inst_basereg = X86_EBP;
1056 cfg->ret->inst_offset = - offset;
1057 break;
1058 default:
1059 break;
1060 }
1061
1062 /* Allocate a local for any register arguments that need them. */
1063 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1064 ArgInfo *ainfo = &cinfo->args [i];
1065 inst = cfg->args [i];
1066 if (inst->opcode != OP_REGVAR && storage_in_ireg (ainfo->storage)) {
1067 offset += 4;
1068 cfg->args[i]->opcode = OP_REGOFFSET;
1069 cfg->args[i]->inst_basereg = X86_EBP;
1070 cfg->args[i]->inst_offset = - offset;
1071 }
1072 }
1073
1074 /* Allocate locals */
1075 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1076 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1077 char *mname = mono_method_full_name (cfg->method, TRUE);
1078 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1079 g_free (mname);
1080 return;
1081 }
1082 if (locals_stack_align) {
1083 int prev_offset = offset;
1084
1085 offset += (locals_stack_align - 1);
1086 offset &= ~(locals_stack_align - 1);
1087
1088 while (prev_offset < offset) {
1089 prev_offset += 4;
1090 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1091 }
1092 }
1093 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1094 cfg->locals_max_stack_offset = - offset;
1095 /*
1096 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1097 * have locals larger than 8 bytes we need to make sure that
1098 * they have the appropriate offset.
1099 */
1100 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1101 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (target_mgreg_t) * 2;
1102 offset += extra_size;
1103 locals_stack_size += extra_size;
1104 }
1105 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1106 if (offsets [i] != -1) {
1107 MonoInst *inst = cfg->varinfo [i];
1108 inst->opcode = OP_REGOFFSET;
1109 inst->inst_basereg = X86_EBP;
1110 inst->inst_offset = - (offset + offsets [i]);
1111 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1112 }
1113 }
1114 offset += locals_stack_size;
1115
1116
1117 /*
1118 * Allocate arguments+return value
1119 */
1120
1121 switch (cinfo->ret.storage) {
1122 case ArgOnStack:
1123 if (cfg->vret_addr) {
1124 /*
1125 * In the new IR, the cfg->vret_addr variable represents the
1126 * vtype return value.
1127 */
1128 cfg->vret_addr->opcode = OP_REGOFFSET;
1129 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1130 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1131 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1132 printf ("vret_addr =");
1133 mono_print_ins (cfg->vret_addr);
1134 }
1135 } else {
1136 cfg->ret->opcode = OP_REGOFFSET;
1137 cfg->ret->inst_basereg = X86_EBP;
1138 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1139 }
1140 break;
1141 case ArgValuetypeInReg:
1142 break;
1143 case ArgInIReg:
1144 cfg->ret->opcode = OP_REGVAR;
1145 cfg->ret->inst_c0 = cinfo->ret.reg;
1146 cfg->ret->dreg = cinfo->ret.reg;
1147 break;
1148 case ArgNone:
1149 case ArgOnFloatFpStack:
1150 case ArgOnDoubleFpStack:
1151 break;
1152 default:
1153 g_assert_not_reached ();
1154 }
1155
1156 if (sig->call_convention == MONO_CALL_VARARG) {
1157 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1158 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1159 }
1160
1161 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1162 ArgInfo *ainfo = &cinfo->args [i];
1163 inst = cfg->args [i];
1164 if (inst->opcode != OP_REGVAR) {
1165 if (storage_in_ireg (ainfo->storage)) {
1166 /* We already allocated locals for register arguments. */
1167 } else {
1168 inst->opcode = OP_REGOFFSET;
1169 inst->inst_basereg = X86_EBP;
1170 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1171 }
1172 }
1173 }
1174
1175 cfg->stack_offset = offset;
1176 }
1177
1178 void
1179 mono_arch_create_vars (MonoCompile *cfg)
1180 {
1181 MonoType *sig_ret;
1182 MonoMethodSignature *sig;
1183 CallInfo *cinfo;
1184
1185 sig = mono_method_signature_internal (cfg->method);
1186
1187 if (!cfg->arch.cinfo)
1188 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1189 cinfo = cfg->arch.cinfo;
1190
1191 sig_ret = mini_get_underlying_type (sig->ret);
1192
1193 if (cinfo->ret.storage == ArgValuetypeInReg)
1194 cfg->ret_var_is_local = TRUE;
1195 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1196 cfg->vret_addr = mono_compile_create_var (cfg, mono_get_int_type (), OP_ARG);
1197 }
1198
1199 if (cfg->gen_sdb_seq_points) {
1200 MonoInst *ins;
1201
1202 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1203 ins->flags |= MONO_INST_VOLATILE;
1204 cfg->arch.ss_tramp_var = ins;
1205
1206 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1207 ins->flags |= MONO_INST_VOLATILE;
1208 cfg->arch.bp_tramp_var = ins;
1209 }
1210
1211 if (cfg->method->save_lmf) {
1212 cfg->create_lmf_var = TRUE;
1213 cfg->lmf_ir = TRUE;
1214 }
1215
1216 cfg->arch_eh_jit_info = 1;
1217 }
1218
1219 /*
1220 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1221 * so we try to do it just once when we have multiple fp arguments in a row.
1222 * We don't use this mechanism generally because for int arguments the generated code
1223 * is slightly bigger and new generation cpus optimize away the dependency chains
1224 * created by push instructions on the esp value.
1225 * fp_arg_setup is the first argument in the execution sequence where the esp register
1226 * is modified.
1227 */
1228 static G_GNUC_UNUSED int
1229 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1230 {
1231 int fp_space = 0;
1232 MonoType *t;
1233
1234 for (; start_arg < sig->param_count; ++start_arg) {
1235 t = mini_get_underlying_type (sig->params [start_arg]);
1236 if (!t->byref && t->type == MONO_TYPE_R8) {
1237 fp_space += sizeof (double);
1238 *fp_arg_setup = start_arg;
1239 } else {
1240 break;
1241 }
1242 }
1243 return fp_space;
1244 }
1245
1246 static void
1247 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1248 {
1249 MonoMethodSignature *tmp_sig;
1250 int sig_reg;
1251
1252 /*
1253 * mono_ArgIterator_Setup assumes the signature cookie is
1254 * passed first and all the arguments which were before it are
1255 * passed on the stack after the signature. So compensate by
1256 * passing a different signature.
1257 */
1258 tmp_sig = mono_metadata_signature_dup (call->signature);
1259 tmp_sig->param_count -= call->signature->sentinelpos;
1260 tmp_sig->sentinelpos = 0;
1261 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1262
1263 if (cfg->compile_aot) {
1264 sig_reg = mono_alloc_ireg (cfg);
1265 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1266 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1267 } else {
1268 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1269 }
1270 }
1271
1272 #ifdef ENABLE_LLVM
1273 LLVMCallInfo*
1274 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1275 {
1276 int i, n;
1277 CallInfo *cinfo;
1278 ArgInfo *ainfo;
1279 LLVMCallInfo *linfo;
1280 MonoType *t, *sig_ret;
1281
1282 n = sig->param_count + sig->hasthis;
1283
1284 cinfo = get_call_info (cfg->mempool, sig);
1285 sig_ret = sig->ret;
1286
1287 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1288
1289 /*
1290 * LLVM always uses the native ABI while we use our own ABI, the
1291 * only difference is the handling of vtypes:
1292 * - we only pass/receive them in registers in some cases, and only
1293 * in 1 or 2 integer registers.
1294 */
1295 if (cinfo->ret.storage == ArgValuetypeInReg) {
1296 if (sig->pinvoke) {
1297 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1298 cfg->disable_llvm = TRUE;
1299 return linfo;
1300 }
1301
1302 cfg->exception_message = g_strdup ("vtype ret in call");
1303 cfg->disable_llvm = TRUE;
1304 /*
1305 linfo->ret.storage = LLVMArgVtypeInReg;
1306 for (j = 0; j < 2; ++j)
1307 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1308 */
1309 }
1310
1311 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1312 /* Vtype returned using a hidden argument */
1313 linfo->ret.storage = LLVMArgVtypeRetAddr;
1314 linfo->vret_arg_index = cinfo->vret_arg_index;
1315 }
1316
1317 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1318 // FIXME:
1319 cfg->exception_message = g_strdup ("vtype ret in call");
1320 cfg->disable_llvm = TRUE;
1321 }
1322
1323 for (i = 0; i < n; ++i) {
1324 ainfo = cinfo->args + i;
1325
1326 if (i >= sig->hasthis)
1327 t = sig->params [i - sig->hasthis];
1328 else
1329 t = mono_get_int_type ();
1330
1331 linfo->args [i].storage = LLVMArgNone;
1332
1333 switch (ainfo->storage) {
1334 case ArgInIReg:
1335 linfo->args [i].storage = LLVMArgNormal;
1336 break;
1337 case ArgInDoubleSSEReg:
1338 case ArgInFloatSSEReg:
1339 linfo->args [i].storage = LLVMArgNormal;
1340 break;
1341 case ArgOnStack:
1342 if (mini_type_is_vtype (t)) {
1343 if (mono_class_value_size (mono_class_from_mono_type_internal (t), NULL) == 0)
1344 /* LLVM seems to allocate argument space for empty structures too */
1345 linfo->args [i].storage = LLVMArgNone;
1346 else
1347 linfo->args [i].storage = LLVMArgVtypeByVal;
1348 } else {
1349 linfo->args [i].storage = LLVMArgNormal;
1350 }
1351 break;
1352 case ArgValuetypeInReg:
1353 if (sig->pinvoke) {
1354 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1355 cfg->disable_llvm = TRUE;
1356 return linfo;
1357 }
1358
1359 cfg->exception_message = g_strdup ("vtype arg");
1360 cfg->disable_llvm = TRUE;
1361 /*
1362 linfo->args [i].storage = LLVMArgVtypeInReg;
1363 for (j = 0; j < 2; ++j)
1364 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1365 */
1366 break;
1367 case ArgGSharedVt:
1368 linfo->args [i].storage = LLVMArgGSharedVt;
1369 break;
1370 default:
1371 cfg->exception_message = g_strdup ("ainfo->storage");
1372 cfg->disable_llvm = TRUE;
1373 break;
1374 }
1375 }
1376
1377 return linfo;
1378 }
1379 #endif
1380
1381 static void
1382 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1383 {
1384 if (cfg->compute_gc_maps) {
1385 MonoInst *def;
1386
1387 /* Needs checking if the feature will be enabled again */
1388 g_assert_not_reached ();
1389
1390 /* On x86, the offsets are from the sp value before the start of the call sequence */
1391 if (t == NULL)
1392 t = mono_get_int_type ();
1393 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1394 }
1395 }
1396
1397 void
1398 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1399 {
1400 MonoType *sig_ret;
1401 MonoInst *arg, *in;
1402 MonoMethodSignature *sig;
1403 int i, j, n;
1404 CallInfo *cinfo;
1405 int sentinelpos = 0, sp_offset = 0;
1406
1407 sig = call->signature;
1408 n = sig->param_count + sig->hasthis;
1409 sig_ret = mini_get_underlying_type (sig->ret);
1410
1411 cinfo = get_call_info (cfg->mempool, sig);
1412 call->call_info = cinfo;
1413
1414 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1415 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1416
1417 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1418 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1419 /*
1420 * Tell the JIT to use a more efficient calling convention: call using
1421 * OP_CALL, compute the result location after the call, and save the
1422 * result there.
1423 */
1424 call->vret_in_reg = TRUE;
1425 #if defined (__APPLE__)
1426 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1427 call->vret_in_reg_fp = TRUE;
1428 #endif
1429 if (call->vret_var)
1430 NULLIFY_INS (call->vret_var);
1431 }
1432 }
1433
1434 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1435
1436 /* Handle the case where there are no implicit arguments */
1437 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1438 emit_sig_cookie (cfg, call, cinfo);
1439 sp_offset = cinfo->sig_cookie.offset;
1440 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1441 }
1442
1443 /* Arguments are pushed in the reverse order */
1444 for (i = n - 1; i >= 0; i --) {
1445 ArgInfo *ainfo = cinfo->args + i;
1446 MonoType *orig_type, *t;
1447 int argsize;
1448
1449 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1450 MonoInst *vtarg;
1451
1452 /* Push the vret arg before the first argument */
1453 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1454 vtarg->type = STACK_MP;
1455 vtarg->inst_destbasereg = X86_ESP;
1456 vtarg->sreg1 = call->vret_var->dreg;
1457 vtarg->inst_offset = cinfo->ret.offset;
1458 MONO_ADD_INS (cfg->cbb, vtarg);
1459 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1460 }
1461
1462 if (i >= sig->hasthis)
1463 t = sig->params [i - sig->hasthis];
1464 else
1465 t = mono_get_int_type ();
1466 orig_type = t;
1467 t = mini_get_underlying_type (t);
1468
1469 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1470
1471 in = call->args [i];
1472 arg->cil_code = in->cil_code;
1473 arg->sreg1 = in->dreg;
1474 arg->type = in->type;
1475
1476 g_assert (in->dreg != -1);
1477
1478 if (ainfo->storage == ArgGSharedVt) {
1479 arg->opcode = OP_OUTARG_VT;
1480 arg->sreg1 = in->dreg;
1481 arg->klass = in->klass;
1482 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1483 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1484 sp_offset += 4;
1485 MONO_ADD_INS (cfg->cbb, arg);
1486 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1487 guint32 align;
1488 guint32 size;
1489
1490 g_assert (in->klass);
1491
1492 if (t->type == MONO_TYPE_TYPEDBYREF) {
1493 size = MONO_ABI_SIZEOF (MonoTypedRef);
1494 align = sizeof (target_mgreg_t);
1495 }
1496 else {
1497 size = mini_type_stack_size_full (m_class_get_byval_arg (in->klass), &align, sig->pinvoke);
1498 }
1499
1500 if (size > 0 || ainfo->pass_empty_struct) {
1501 arg->opcode = OP_OUTARG_VT;
1502 arg->sreg1 = in->dreg;
1503 arg->klass = in->klass;
1504 arg->backend.size = size;
1505 arg->inst_p0 = call;
1506 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1507 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1508
1509 MONO_ADD_INS (cfg->cbb, arg);
1510 if (ainfo->storage != ArgValuetypeInReg) {
1511 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1512 }
1513 }
1514 } else {
1515 switch (ainfo->storage) {
1516 case ArgOnStack:
1517 if (!t->byref) {
1518 if (t->type == MONO_TYPE_R4) {
1519 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1520 argsize = 4;
1521 } else if (t->type == MONO_TYPE_R8) {
1522 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1523 argsize = 8;
1524 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1525 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1526 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1527 argsize = 4;
1528 } else {
1529 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1530 argsize = 4;
1531 }
1532 } else {
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1534 argsize = 4;
1535 }
1536 break;
1537 case ArgInIReg:
1538 arg->opcode = OP_MOVE;
1539 arg->dreg = ainfo->reg;
1540 MONO_ADD_INS (cfg->cbb, arg);
1541 argsize = 0;
1542 break;
1543 default:
1544 g_assert_not_reached ();
1545 }
1546
1547 if (cfg->compute_gc_maps) {
1548 if (argsize == 4) {
1549 /* FIXME: The == STACK_OBJ check might be fragile ? */
1550 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1551 /* this */
1552 if (call->need_unbox_trampoline)
1553 /* The unbox trampoline transforms this into a managed pointer */
1554 emit_gc_param_slot_def (cfg, ainfo->offset, m_class_get_this_arg (mono_defaults.int_class));
1555 else
1556 emit_gc_param_slot_def (cfg, ainfo->offset, mono_get_object_type ());
1557 } else {
1558 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1559 }
1560 } else {
1561 /* i8/r8 */
1562 for (j = 0; j < argsize; j += 4)
1563 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1564 }
1565 }
1566 }
1567
1568 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1569 /* Emit the signature cookie just before the implicit arguments */
1570 emit_sig_cookie (cfg, call, cinfo);
1571 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1572 }
1573 }
1574
1575 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1576 MonoInst *vtarg;
1577
1578 if (cinfo->ret.storage == ArgValuetypeInReg) {
1579 /* Already done */
1580 }
1581 else if (cinfo->ret.storage == ArgInIReg) {
1582 NOT_IMPLEMENTED;
1583 /* The return address is passed in a register */
1584 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1585 vtarg->sreg1 = call->inst.dreg;
1586 vtarg->dreg = mono_alloc_ireg (cfg);
1587 MONO_ADD_INS (cfg->cbb, vtarg);
1588
1589 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1590 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1591 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1592 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1593 }
1594 }
1595
1596 call->stack_usage = cinfo->stack_usage;
1597 call->stack_align_amount = cinfo->stack_align_amount;
1598 }
1599
1600 void
1601 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1602 {
1603 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1604 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1605 int size = ins->backend.size;
1606
1607 if (ainfo->storage == ArgValuetypeInReg) {
1608 int dreg = mono_alloc_ireg (cfg);
1609 switch (size) {
1610 case 1:
1611 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1612 break;
1613 case 2:
1614 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1615 break;
1616 case 4:
1617 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1618 break;
1619 case 3: /* FIXME */
1620 default:
1621 g_assert_not_reached ();
1622 }
1623 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1624 }
1625 else {
1626 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1627 /* Pass by addr */
1628 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1629 } else if (size <= 4) {
1630 int dreg = mono_alloc_ireg (cfg);
1631 if (ainfo->pass_empty_struct) {
1632 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1633 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1634 } else {
1635 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1636 }
1637 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1638 } else if (size <= 20) {
1639 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1640 } else {
1641 // FIXME: Code growth
1642 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1643 }
1644 }
1645 }
1646
1647 void
1648 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1649 {
1650 MonoType *ret = mini_get_underlying_type (mono_method_signature_internal (method)->ret);
1651
1652 if (!ret->byref) {
1653 if (ret->type == MONO_TYPE_R4) {
1654 if (COMPILE_LLVM (cfg))
1655 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1656 /* Nothing to do */
1657 return;
1658 } else if (ret->type == MONO_TYPE_R8) {
1659 if (COMPILE_LLVM (cfg))
1660 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1661 /* Nothing to do */
1662 return;
1663 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1664 if (COMPILE_LLVM (cfg))
1665 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1666 else {
1667 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1668 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1669 }
1670 return;
1671 }
1672 }
1673
1674 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1675 }
1676
1677 #define EMIT_COND_BRANCH(ins,cond,sign) \
1678 if (ins->inst_true_bb->native_offset) { \
1679 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1680 } else { \
1681 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1682 if ((cfg->opt & MONO_OPT_BRANCH) && \
1683 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1684 x86_branch8 (code, cond, 0, sign); \
1685 else \
1686 x86_branch32 (code, cond, 0, sign); \
1687 }
1688
1689 /*
1690 * Emit an exception if condition is fail and
1691 * if possible do a directly branch to target
1692 */
1693 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1694 do { \
1695 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1696 if (tins == NULL) { \
1697 mono_add_patch_info (cfg, code - cfg->native_code, \
1698 MONO_PATCH_INFO_EXC, exc_name); \
1699 x86_branch32 (code, cond, 0, signed); \
1700 } else { \
1701 EMIT_COND_BRANCH (tins, cond, signed); \
1702 } \
1703 } while (0);
1704
1705 #define EMIT_FPCOMPARE(code) do { \
1706 x86_fcompp (code); \
1707 x86_fnstsw (code); \
1708 } while (0);
1709
1710 static guint8*
1711 x86_align_and_patch (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1712 {
1713 gboolean needs_paddings = TRUE;
1714 guint32 pad_size;
1715 MonoJumpInfo *jinfo = NULL;
1716
1717 if (cfg->abs_patches) {
1718 jinfo = (MonoJumpInfo*)g_hash_table_lookup (cfg->abs_patches, data);
1719 if (jinfo && (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR
1720 || jinfo->type == MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR))
1721 needs_paddings = FALSE;
1722 }
1723
1724 if (cfg->compile_aot)
1725 needs_paddings = FALSE;
1726 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1727 This is required for code patching to be safe on SMP machines.
1728 */
1729 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1730 if (needs_paddings && pad_size)
1731 x86_padding (code, 4 - pad_size);
1732
1733 mono_add_patch_info (cfg, code - cfg->native_code, (MonoJumpInfoType)patch_type, data);
1734
1735 return code;
1736 }
1737
1738 static guint8*
1739 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1740 {
1741 code = x86_align_and_patch (cfg, code, patch_type, data);
1742
1743 x86_call_code (code, 0);
1744
1745 return code;
1746 }
1747
1748 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1749
1750 /*
1751 * mono_peephole_pass_1:
1752 *
1753 * Perform peephole opts which should/can be performed before local regalloc
1754 */
1755 void
1756 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1757 {
1758 MonoInst *ins, *n;
1759
1760 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1761 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1762
1763 switch (ins->opcode) {
1764 case OP_IADD_IMM:
1765 case OP_ADD_IMM:
1766 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1767 /*
1768 * X86_LEA is like ADD, but doesn't have the
1769 * sreg1==dreg restriction.
1770 */
1771 ins->opcode = OP_X86_LEA_MEMBASE;
1772 ins->inst_basereg = ins->sreg1;
1773 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1774 ins->opcode = OP_X86_INC_REG;
1775 break;
1776 case OP_SUB_IMM:
1777 case OP_ISUB_IMM:
1778 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1779 ins->opcode = OP_X86_LEA_MEMBASE;
1780 ins->inst_basereg = ins->sreg1;
1781 ins->inst_imm = -ins->inst_imm;
1782 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1783 ins->opcode = OP_X86_DEC_REG;
1784 break;
1785 case OP_COMPARE_IMM:
1786 case OP_ICOMPARE_IMM:
1787 /* OP_COMPARE_IMM (reg, 0)
1788 * -->
1789 * OP_X86_TEST_NULL (reg)
1790 */
1791 if (!ins->inst_imm)
1792 ins->opcode = OP_X86_TEST_NULL;
1793 break;
1794 case OP_X86_COMPARE_MEMBASE_IMM:
1795 /*
1796 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1797 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1798 * -->
1799 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1800 * OP_COMPARE_IMM reg, imm
1801 *
1802 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1803 */
1804 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1805 ins->inst_basereg == last_ins->inst_destbasereg &&
1806 ins->inst_offset == last_ins->inst_offset) {
1807 ins->opcode = OP_COMPARE_IMM;
1808 ins->sreg1 = last_ins->sreg1;
1809
1810 /* check if we can remove cmp reg,0 with test null */
1811 if (!ins->inst_imm)
1812 ins->opcode = OP_X86_TEST_NULL;
1813 }
1814
1815 break;
1816 case OP_X86_PUSH_MEMBASE:
1817 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1818 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1819 ins->inst_basereg == last_ins->inst_destbasereg &&
1820 ins->inst_offset == last_ins->inst_offset) {
1821 ins->opcode = OP_X86_PUSH;
1822 ins->sreg1 = last_ins->sreg1;
1823 }
1824 break;
1825 }
1826
1827 mono_peephole_ins (bb, ins);
1828 }
1829 }
1830
1831 void
1832 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1833 {
1834 MonoInst *ins, *n;
1835
1836 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1837 switch (ins->opcode) {
1838 case OP_ICONST:
1839 /* reg = 0 -> XOR (reg, reg) */
1840 /* XOR sets cflags on x86, so we cant do it always */
1841 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1842 MonoInst *ins2;
1843
1844 ins->opcode = OP_IXOR;
1845 ins->sreg1 = ins->dreg;
1846 ins->sreg2 = ins->dreg;
1847
1848 /*
1849 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1850 * since it takes 3 bytes instead of 7.
1851 */
1852 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1853 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1854 ins2->opcode = OP_STORE_MEMBASE_REG;
1855 ins2->sreg1 = ins->dreg;
1856 }
1857 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1858 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1859 ins2->sreg1 = ins->dreg;
1860 }
1861 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1862 /* Continue iteration */
1863 }
1864 else
1865 break;
1866 }
1867 }
1868 break;
1869 case OP_IADD_IMM:
1870 case OP_ADD_IMM:
1871 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1872 ins->opcode = OP_X86_INC_REG;
1873 break;
1874 case OP_ISUB_IMM:
1875 case OP_SUB_IMM:
1876 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1877 ins->opcode = OP_X86_DEC_REG;
1878 break;
1879 }
1880
1881 mono_peephole_ins (bb, ins);
1882 }
1883 }
1884
1885 #define NEW_INS(cfg,ins,dest,op) do { \
1886 MONO_INST_NEW ((cfg), (dest), (op)); \
1887 (dest)->cil_code = (ins)->cil_code; \
1888 mono_bblock_insert_before_ins (bb, ins, (dest)); \
1889 } while (0)
1890
1891 /*
1892 * mono_arch_lowering_pass:
1893 *
1894 * Converts complex opcodes into simpler ones so that each IR instruction
1895 * corresponds to one machine instruction.
1896 */
1897 void
1898 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1899 {
1900 MonoInst *ins, *next;
1901
1902 /*
1903 * FIXME: Need to add more instructions, but the current machine
1904 * description can't model some parts of the composite instructions like
1905 * cdq.
1906 */
1907 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1908 switch (ins->opcode) {
1909 case OP_IREM_IMM:
1910 case OP_IDIV_IMM:
1911 case OP_IDIV_UN_IMM:
1912 case OP_IREM_UN_IMM:
1913 /*
1914 * Keep the cases where we could generated optimized code, otherwise convert
1915 * to the non-imm variant.
1916 */
1917 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1918 break;
1919 mono_decompose_op_imm (cfg, bb, ins);
1920 break;
1921 #ifdef MONO_ARCH_SIMD_INTRINSICS
1922 case OP_EXPAND_I1: {
1923 MonoInst *temp;
1924 int temp_reg1 = mono_alloc_ireg (cfg);
1925 int temp_reg2 = mono_alloc_ireg (cfg);
1926 int original_reg = ins->sreg1;
1927
1928 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
1929 temp->sreg1 = original_reg;
1930 temp->dreg = temp_reg1;
1931
1932 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
1933 temp->sreg1 = temp_reg1;
1934 temp->dreg = temp_reg2;
1935 temp->inst_imm = 8;
1936
1937 NEW_INS (cfg, ins, temp, OP_IOR);
1938 temp->sreg1 = temp->dreg = temp_reg2;
1939 temp->sreg2 = temp_reg1;
1940
1941 ins->opcode = OP_EXPAND_I2;
1942 ins->sreg1 = temp_reg2;
1943 }
1944 break;
1945 #endif
1946 default:
1947 break;
1948 }
1949 }
1950
1951 bb->max_vreg = cfg->next_vreg;
1952 }
1953
1954 static const int
1955 branch_cc_table [] = {
1956 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1957 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1958 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1959 };
1960
1961 /* Maps CMP_... constants to X86_CC_... constants */
1962 static const int
1963 cc_table [] = {
1964 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1965 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1966 };
1967
1968 static const int
1969 cc_signed_table [] = {
1970 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1971 FALSE, FALSE, FALSE, FALSE
1972 };
1973
1974 static unsigned char*
1975 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1976 {
1977 #define XMM_TEMP_REG 0
1978 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1979 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1980 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1981 /* optimize by assigning a local var for this use so we avoid
1982 * the stack manipulations */
1983 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1984 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1985 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1986 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1987 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1988 if (size == 1)
1989 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1990 else if (size == 2)
1991 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1992 return code;
1993 }
1994 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1995 x86_fnstcw_membase(code, X86_ESP, 0);
1996 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1997 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1998 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1999 x86_fldcw_membase (code, X86_ESP, 2);
2000 if (size == 8) {
2001 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2002 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2003 x86_pop_reg (code, dreg);
2004 /* FIXME: need the high register
2005 * x86_pop_reg (code, dreg_high);
2006 */
2007 } else {
2008 x86_push_reg (code, X86_EAX); // SP = SP - 4
2009 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2010 x86_pop_reg (code, dreg);
2011 }
2012 x86_fldcw_membase (code, X86_ESP, 0);
2013 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2014
2015 if (size == 1)
2016 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2017 else if (size == 2)
2018 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2019 return code;
2020 }
2021
2022 static unsigned char*
2023 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2024 {
2025 int sreg = tree->sreg1;
2026 int need_touch = FALSE;
2027
2028 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2029 need_touch = TRUE;
2030 #endif
2031
2032 if (need_touch) {
2033 guint8* br[5];
2034
2035 /*
2036 * Under Windows:
2037 * If requested stack size is larger than one page,
2038 * perform stack-touch operation
2039 */
2040 /*
2041 * Generate stack probe code.
2042 * Under Windows, it is necessary to allocate one page at a time,
2043 * "touching" stack after each successful sub-allocation. This is
2044 * because of the way stack growth is implemented - there is a
2045 * guard page before the lowest stack page that is currently commited.
2046 * Stack normally grows sequentially so OS traps access to the
2047 * guard page and commits more pages when needed.
2048 */
2049 x86_test_reg_imm (code, sreg, ~0xFFF);
2050 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2051
2052 br[2] = code; /* loop */
2053 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2054 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2055
2056 /*
2057 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2058 * that follows only initializes the last part of the area.
2059 */
2060 /* Same as the init code below with size==0x1000 */
2061 if (tree->flags & MONO_INST_INIT) {
2062 x86_push_reg (code, X86_EAX);
2063 x86_push_reg (code, X86_ECX);
2064 x86_push_reg (code, X86_EDI);
2065 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2066 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2067 if (cfg->param_area)
2068 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2069 else
2070 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2071 x86_cld (code);
2072 x86_prefix (code, X86_REP_PREFIX);
2073 x86_stosl (code);
2074 x86_pop_reg (code, X86_EDI);
2075 x86_pop_reg (code, X86_ECX);
2076 x86_pop_reg (code, X86_EAX);
2077 }
2078
2079 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2080 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2081 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2082 x86_patch (br[3], br[2]);
2083 x86_test_reg_reg (code, sreg, sreg);
2084 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2085 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2086
2087 br[1] = code; x86_jump8 (code, 0);
2088
2089 x86_patch (br[0], code);
2090 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2091 x86_patch (br[1], code);
2092 x86_patch (br[4], code);
2093 }
2094 else
2095 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2096
2097 if (tree->flags & MONO_INST_INIT) {
2098 int offset = 0;
2099 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2100 x86_push_reg (code, X86_EAX);
2101 offset += 4;
2102 }
2103 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2104 x86_push_reg (code, X86_ECX);
2105 offset += 4;
2106 }
2107 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2108 x86_push_reg (code, X86_EDI);
2109 offset += 4;
2110 }
2111
2112 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2113 x86_mov_reg_reg (code, X86_ECX, sreg);
2114 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2115
2116 if (cfg->param_area)
2117 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2118 else
2119 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2120 x86_cld (code);
2121 x86_prefix (code, X86_REP_PREFIX);
2122 x86_stosl (code);
2123
2124 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2125 x86_pop_reg (code, X86_EDI);
2126 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2127 x86_pop_reg (code, X86_ECX);
2128 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2129 x86_pop_reg (code, X86_EAX);
2130 }
2131 return code;
2132 }
2133
2134
2135 static guint8*
2136 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2137 {
2138 /* Move return value to the target register */
2139 switch (ins->opcode) {
2140 case OP_CALL:
2141 case OP_CALL_REG:
2142 case OP_CALL_MEMBASE:
2143 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2144 break;
2145 default:
2146 break;
2147 }
2148
2149 return code;
2150 }
2151
2152 #ifdef TARGET_MACH
2153 static int tls_gs_offset;
2154 #endif
2155
2156 gboolean
2157 mono_arch_have_fast_tls (void)
2158 {
2159 #ifdef TARGET_MACH
2160 static gboolean have_fast_tls = FALSE;
2161 static gboolean inited = FALSE;
2162 guint32 *ins;
2163
2164 if (mini_debug_options.use_fallback_tls)
2165 return FALSE;
2166 if (inited)
2167 return have_fast_tls;
2168
2169 ins = (guint32*)pthread_getspecific;
2170 /*
2171 * We're looking for these two instructions:
2172 *
2173 * mov 0x4(%esp),%eax
2174 * mov %gs:[offset](,%eax,4),%eax
2175 */
2176 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2177 tls_gs_offset = ins [2];
2178 inited = TRUE;
2179
2180 return have_fast_tls;
2181 #elif defined(TARGET_ANDROID)
2182 return FALSE;
2183 #else
2184 if (mini_debug_options.use_fallback_tls)
2185 return FALSE;
2186 return TRUE;
2187 #endif
2188 }
2189
2190 static guint8*
2191 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2192 {
2193 #if defined (TARGET_MACH)
2194 x86_prefix (code, X86_GS_PREFIX);
2195 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2196 #elif defined (TARGET_WIN32)
2197 /*
2198 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2199 * Journal and/or a disassembly of the TlsGet () function.
2200 */
2201 x86_prefix (code, X86_FS_PREFIX);
2202 x86_mov_reg_mem (code, dreg, 0x18, 4);
2203 if (tls_offset < 64) {
2204 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2205 } else {
2206 guint8 *buf [16];
2207
2208 g_assert (tls_offset < 0x440);
2209 /* Load TEB->TlsExpansionSlots */
2210 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2211 x86_test_reg_reg (code, dreg, dreg);
2212 buf [0] = code;
2213 x86_branch (code, X86_CC_EQ, code, TRUE);
2214 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2215 x86_patch (buf [0], code);
2216 }
2217 #else
2218 if (optimize_for_xen) {
2219 x86_prefix (code, X86_GS_PREFIX);
2220 x86_mov_reg_mem (code, dreg, 0, 4);
2221 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2222 } else {
2223 x86_prefix (code, X86_GS_PREFIX);
2224 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2225 }
2226 #endif
2227 return code;
2228 }
2229
2230 static guint8*
2231 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2232 {
2233 #if defined (TARGET_MACH)
2234 x86_prefix (code, X86_GS_PREFIX);
2235 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2236 #elif defined (TARGET_WIN32)
2237 g_assert_not_reached ();
2238 #else
2239 x86_prefix (code, X86_GS_PREFIX);
2240 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2241 #endif
2242 return code;
2243 }
2244
2245 /*
2246 * emit_setup_lmf:
2247 *
2248 * Emit code to initialize an LMF structure at LMF_OFFSET.
2249 */
2250 static guint8*
2251 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2252 {
2253 /* save all caller saved regs */
2254 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (target_mgreg_t));
2255 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2256 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (target_mgreg_t));
2257 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2258 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (target_mgreg_t));
2259 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2260 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (target_mgreg_t));
2261
2262 /* save the current IP */
2263 if (cfg->compile_aot) {
2264 /* This pushes the current ip */
2265 x86_call_imm (code, 0);
2266 x86_pop_reg (code, X86_EAX);
2267 } else {
2268 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2269 x86_mov_reg_imm (code, X86_EAX, 0);
2270 }
2271 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (target_mgreg_t));
2272
2273 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2274 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2275 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2276 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2277 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2278 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2279 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2280 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2281 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2282
2283 return code;
2284 }
2285
2286 #ifdef TARGET_WIN32
2287
2288 #define TEB_LAST_ERROR_OFFSET 0x34
2289
2290 static guint8*
2291 emit_get_last_error (guint8* code, int dreg)
2292 {
2293 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
2294 x86_prefix (code, X86_FS_PREFIX);
2295 x86_mov_reg_mem (code, dreg, TEB_LAST_ERROR_OFFSET, sizeof (guint32));
2296 return code;
2297 }
2298
2299 #else
2300
2301 static guint8*
2302 emit_get_last_error (guint8* code, int dreg)
2303 {
2304 g_assert_not_reached ();
2305 }
2306
2307 #endif
2308
2309 /* benchmark and set based on cpu */
2310 #define LOOP_ALIGNMENT 8
2311 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2312
2313 #ifndef DISABLE_JIT
2314 void
2315 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2316 {
2317 MonoInst *ins;
2318 MonoCallInst *call;
2319 guint8 *code = cfg->native_code + cfg->code_len;
2320
2321 if (cfg->opt & MONO_OPT_LOOP) {
2322 int pad, align = LOOP_ALIGNMENT;
2323 /* set alignment depending on cpu */
2324 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2325 pad = align - pad;
2326 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2327 x86_padding (code, pad);
2328 cfg->code_len += pad;
2329 bb->native_offset = cfg->code_len;
2330 }
2331 }
2332
2333 if (cfg->verbose_level > 2)
2334 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2335
2336 int cpos = bb->max_offset;
2337
2338 set_code_cursor (cfg, code);
2339
2340 mono_debug_open_block (cfg, bb, code - cfg->native_code);
2341
2342 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2343 x86_breakpoint (code);
2344
2345 MONO_BB_FOR_EACH_INS (bb, ins) {
2346 const guint offset = code - cfg->native_code;
2347 set_code_cursor (cfg, code);
2348 int max_len = ins_get_size (ins->opcode);
2349 code = realloc_code (cfg, max_len);
2350
2351 if (cfg->debug_info)
2352 mono_debug_record_line_number (cfg, ins, offset);
2353
2354 switch (ins->opcode) {
2355 case OP_BIGMUL:
2356 x86_mul_reg (code, ins->sreg2, TRUE);
2357 break;
2358 case OP_BIGMUL_UN:
2359 x86_mul_reg (code, ins->sreg2, FALSE);
2360 break;
2361 case OP_X86_SETEQ_MEMBASE:
2362 case OP_X86_SETNE_MEMBASE:
2363 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2364 ins->inst_basereg, ins->inst_offset, TRUE);
2365 break;
2366 case OP_STOREI1_MEMBASE_IMM:
2367 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2368 break;
2369 case OP_STOREI2_MEMBASE_IMM:
2370 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2371 break;
2372 case OP_STORE_MEMBASE_IMM:
2373 case OP_STOREI4_MEMBASE_IMM:
2374 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2375 break;
2376 case OP_STOREI1_MEMBASE_REG:
2377 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2378 break;
2379 case OP_STOREI2_MEMBASE_REG:
2380 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2381 break;
2382 case OP_STORE_MEMBASE_REG:
2383 case OP_STOREI4_MEMBASE_REG:
2384 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2385 break;
2386 case OP_STORE_MEM_IMM:
2387 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2388 break;
2389 case OP_LOADU4_MEM:
2390 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2391 break;
2392 case OP_LOAD_MEM:
2393 case OP_LOADI4_MEM:
2394 /* These are created by the cprop pass so they use inst_imm as the source */
2395 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2396 break;
2397 case OP_LOADU1_MEM:
2398 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2399 break;
2400 case OP_LOADU2_MEM:
2401 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2402 break;
2403 case OP_LOAD_MEMBASE:
2404 case OP_LOADI4_MEMBASE:
2405 case OP_LOADU4_MEMBASE:
2406 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2407 break;
2408 case OP_LOADU1_MEMBASE:
2409 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2410 break;
2411 case OP_LOADI1_MEMBASE:
2412 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2413 break;
2414 case OP_LOADU2_MEMBASE:
2415 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2416 break;
2417 case OP_LOADI2_MEMBASE:
2418 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2419 break;
2420 case OP_ICONV_TO_I1:
2421 case OP_SEXT_I1:
2422 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2423 break;
2424 case OP_ICONV_TO_I2:
2425 case OP_SEXT_I2:
2426 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2427 break;
2428 case OP_ICONV_TO_U1:
2429 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2430 break;
2431 case OP_ICONV_TO_U2:
2432 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2433 break;
2434 case OP_COMPARE:
2435 case OP_ICOMPARE:
2436 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2437 break;
2438 case OP_COMPARE_IMM:
2439 case OP_ICOMPARE_IMM:
2440 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2441 break;
2442 case OP_X86_COMPARE_MEMBASE_REG:
2443 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2444 break;
2445 case OP_X86_COMPARE_MEMBASE_IMM:
2446 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2447 break;
2448 case OP_X86_COMPARE_MEMBASE8_IMM:
2449 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2450 break;
2451 case OP_X86_COMPARE_REG_MEMBASE:
2452 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2453 break;
2454 case OP_X86_COMPARE_MEM_IMM:
2455 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2456 break;
2457 case OP_X86_TEST_NULL:
2458 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2459 break;
2460 case OP_X86_ADD_MEMBASE_IMM:
2461 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2462 break;
2463 case OP_X86_ADD_REG_MEMBASE:
2464 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2465 break;
2466 case OP_X86_SUB_MEMBASE_IMM:
2467 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2468 break;
2469 case OP_X86_SUB_REG_MEMBASE:
2470 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2471 break;
2472 case OP_X86_AND_MEMBASE_IMM:
2473 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2474 break;
2475 case OP_X86_OR_MEMBASE_IMM:
2476 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2477 break;
2478 case OP_X86_XOR_MEMBASE_IMM:
2479 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2480 break;
2481 case OP_X86_ADD_MEMBASE_REG:
2482 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2483 break;
2484 case OP_X86_SUB_MEMBASE_REG:
2485 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2486 break;
2487 case OP_X86_AND_MEMBASE_REG:
2488 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2489 break;
2490 case OP_X86_OR_MEMBASE_REG:
2491 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2492 break;
2493 case OP_X86_XOR_MEMBASE_REG:
2494 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2495 break;
2496 case OP_X86_INC_MEMBASE:
2497 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2498 break;
2499 case OP_X86_INC_REG:
2500 x86_inc_reg (code, ins->dreg);
2501 break;
2502 case OP_X86_DEC_MEMBASE:
2503 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2504 break;
2505 case OP_X86_DEC_REG:
2506 x86_dec_reg (code, ins->dreg);
2507 break;
2508 case OP_X86_MUL_REG_MEMBASE:
2509 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2510 break;
2511 case OP_X86_AND_REG_MEMBASE:
2512 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2513 break;
2514 case OP_X86_OR_REG_MEMBASE:
2515 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2516 break;
2517 case OP_X86_XOR_REG_MEMBASE:
2518 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2519 break;
2520 case OP_BREAK:
2521 x86_breakpoint (code);
2522 break;
2523 case OP_RELAXED_NOP:
2524 x86_prefix (code, X86_REP_PREFIX);
2525 x86_nop (code);
2526 break;
2527 case OP_HARD_NOP:
2528 x86_nop (code);
2529 break;
2530 case OP_NOP:
2531 case OP_DUMMY_USE:
2532 case OP_DUMMY_ICONST:
2533 case OP_DUMMY_R8CONST:
2534 case OP_DUMMY_R4CONST:
2535 case OP_NOT_REACHED:
2536 case OP_NOT_NULL:
2537 break;
2538 case OP_IL_SEQ_POINT:
2539 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2540 break;
2541 case OP_SEQ_POINT: {
2542 int i;
2543
2544 if (cfg->compile_aot)
2545 NOT_IMPLEMENTED;
2546
2547 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2548
2549 /*
2550 * We do this _before_ the breakpoint, so single stepping after
2551 * a breakpoint is hit will step to the next IL offset.
2552 */
2553 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2554 MonoInst *var = cfg->arch.ss_tramp_var;
2555 guint8 *br [1];
2556
2557 g_assert (var);
2558 g_assert (var->opcode == OP_REGOFFSET);
2559 /* Load ss_tramp_var */
2560 /* This is equal to &ss_trampoline */
2561 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (target_mgreg_t));
2562 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (target_mgreg_t));
2563 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2564 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2565 x86_call_reg (code, X86_ECX);
2566 x86_patch (br [0], code);
2567 }
2568
2569 /*
2570 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2571 * This means we have to put the loading of bp_tramp_var after the offset.
2572 */
2573
2574 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2575
2576 MonoInst *var = cfg->arch.bp_tramp_var;
2577
2578 g_assert (var);
2579 g_assert (var->opcode == OP_REGOFFSET);
2580 /* Load the address of the bp trampoline */
2581 /* This needs to be constant size */
2582 guint8 *start = code;
2583 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2584 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2585 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2586 x86_padding (code, size);
2587 }
2588 /*
2589 * A placeholder for a possible breakpoint inserted by
2590 * mono_arch_set_breakpoint ().
2591 */
2592 for (i = 0; i < 2; ++i)
2593 x86_nop (code);
2594 /*
2595 * Add an additional nop so skipping the bp doesn't cause the ip to point
2596 * to another IL offset.
2597 */
2598 x86_nop (code);
2599 break;
2600 }
2601 case OP_ADDCC:
2602 case OP_IADDCC:
2603 case OP_IADD:
2604 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2605 break;
2606 case OP_ADC:
2607 case OP_IADC:
2608 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2609 break;
2610 case OP_ADDCC_IMM:
2611 case OP_ADD_IMM:
2612 case OP_IADD_IMM:
2613 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2614 break;
2615 case OP_ADC_IMM:
2616 case OP_IADC_IMM:
2617 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2618 break;
2619 case OP_SUBCC:
2620 case OP_ISUBCC:
2621 case OP_ISUB:
2622 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2623 break;
2624 case OP_SBB:
2625 case OP_ISBB:
2626 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2627 break;
2628 case OP_SUBCC_IMM:
2629 case OP_SUB_IMM:
2630 case OP_ISUB_IMM:
2631 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2632 break;
2633 case OP_SBB_IMM:
2634 case OP_ISBB_IMM:
2635 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2636 break;
2637 case OP_IAND:
2638 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2639 break;
2640 case OP_AND_IMM:
2641 case OP_IAND_IMM:
2642 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2643 break;
2644 case OP_IDIV:
2645 case OP_IREM:
2646 /*
2647 * The code is the same for div/rem, the allocator will allocate dreg
2648 * to RAX/RDX as appropriate.
2649 */
2650 if (ins->sreg2 == X86_EDX) {
2651 /* cdq clobbers this */
2652 x86_push_reg (code, ins->sreg2);
2653 x86_cdq (code);
2654 x86_div_membase (code, X86_ESP, 0, TRUE);
2655 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2656 } else {
2657 x86_cdq (code);
2658 x86_div_reg (code, ins->sreg2, TRUE);
2659 }
2660 break;
2661 case OP_IDIV_UN:
2662 case OP_IREM_UN:
2663 if (ins->sreg2 == X86_EDX) {
2664 x86_push_reg (code, ins->sreg2);
2665 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2666 x86_div_membase (code, X86_ESP, 0, FALSE);
2667 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2668 } else {
2669 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2670 x86_div_reg (code, ins->sreg2, FALSE);
2671 }
2672 break;
2673 case OP_DIV_IMM:
2674 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2675 x86_cdq (code);
2676 x86_div_reg (code, ins->sreg2, TRUE);
2677 break;
2678 case OP_IREM_IMM: {
2679 int power = mono_is_power_of_two (ins->inst_imm);
2680
2681 g_assert (ins->sreg1 == X86_EAX);
2682 g_assert (ins->dreg == X86_EAX);
2683 g_assert (power >= 0);
2684
2685 if (power == 1) {
2686 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2687 x86_cdq (code);
2688 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2689 /*
2690 * If the divident is >= 0, this does not nothing. If it is positive, it
2691 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2692 */
2693 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2694 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2695 } else if (power == 0) {
2696 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2697 } else {
2698 /* Based on gcc code */
2699
2700 /* Add compensation for negative dividents */
2701 x86_cdq (code);
2702 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2703 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2704 /* Compute remainder */
2705 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2706 /* Remove compensation */
2707 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2708 }
2709 break;
2710 }
2711 case OP_IOR:
2712 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2713 break;
2714 case OP_OR_IMM:
2715 case OP_IOR_IMM:
2716 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2717 break;
2718 case OP_IXOR:
2719 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2720 break;
2721 case OP_XOR_IMM:
2722 case OP_IXOR_IMM:
2723 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2724 break;
2725 case OP_ISHL:
2726 g_assert (ins->sreg2 == X86_ECX);
2727 x86_shift_reg (code, X86_SHL, ins->dreg);
2728 break;
2729 case OP_ISHR:
2730 g_assert (ins->sreg2 == X86_ECX);
2731 x86_shift_reg (code, X86_SAR, ins->dreg);
2732 break;
2733 case OP_SHR_IMM:
2734 case OP_ISHR_IMM:
2735 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2736 break;
2737 case OP_SHR_UN_IMM:
2738 case OP_ISHR_UN_IMM:
2739 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2740 break;
2741 case OP_ISHR_UN:
2742 g_assert (ins->sreg2 == X86_ECX);
2743 x86_shift_reg (code, X86_SHR, ins->dreg);
2744 break;
2745 case OP_SHL_IMM:
2746 case OP_ISHL_IMM:
2747 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2748 break;
2749 case OP_LSHL: {
2750 guint8 *jump_to_end;
2751
2752 /* handle shifts below 32 bits */
2753 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2754 x86_shift_reg (code, X86_SHL, ins->sreg1);
2755
2756 x86_test_reg_imm (code, X86_ECX, 32);
2757 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2758
2759 /* handle shift over 32 bit */
2760 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2761 x86_clear_reg (code, ins->sreg1);
2762
2763 x86_patch (jump_to_end, code);
2764 }
2765 break;
2766 case OP_LSHR: {
2767 guint8 *jump_to_end;
2768
2769 /* handle shifts below 32 bits */
2770 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2771 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2772
2773 x86_test_reg_imm (code, X86_ECX, 32);
2774 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2775
2776 /* handle shifts over 31 bits */
2777 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2778 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2779
2780 x86_patch (jump_to_end, code);
2781 }
2782 break;
2783 case OP_LSHR_UN: {
2784 guint8 *jump_to_end;
2785
2786 /* handle shifts below 32 bits */
2787 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2788 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2789
2790 x86_test_reg_imm (code, X86_ECX, 32);
2791 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2792
2793 /* handle shifts over 31 bits */
2794 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2795 x86_clear_reg (code, ins->backend.reg3);
2796
2797 x86_patch (jump_to_end, code);
2798 }
2799 break;
2800 case OP_LSHL_IMM:
2801 if (ins->inst_imm >= 32) {
2802 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2803 x86_clear_reg (code, ins->sreg1);
2804 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2805 } else {
2806 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2807 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2808 }
2809 break;
2810 case OP_LSHR_IMM:
2811 if (ins->inst_imm >= 32) {
2812 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2813 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2814 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2815 } else {
2816 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2817 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2818 }
2819 break;
2820 case OP_LSHR_UN_IMM:
2821 if (ins->inst_imm >= 32) {
2822 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2823 x86_clear_reg (code, ins->backend.reg3);
2824 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2825 } else {
2826 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2827 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2828 }
2829 break;
2830 case OP_INOT:
2831 x86_not_reg (code, ins->sreg1);
2832 break;
2833 case OP_INEG:
2834 x86_neg_reg (code, ins->sreg1);
2835 break;
2836
2837 case OP_IMUL:
2838 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2839 break;
2840 case OP_MUL_IMM:
2841 case OP_IMUL_IMM:
2842 switch (ins->inst_imm) {
2843 case 2:
2844 /* MOV r1, r2 */
2845 /* ADD r1, r1 */
2846 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2847 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2848 break;
2849 case 3:
2850 /* LEA r1, [r2 + r2*2] */
2851 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2852 break;
2853 case 5:
2854 /* LEA r1, [r2 + r2*4] */
2855 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2856 break;
2857 case 6:
2858 /* LEA r1, [r2 + r2*2] */
2859 /* ADD r1, r1 */
2860 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2861 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2862 break;
2863 case 9:
2864 /* LEA r1, [r2 + r2*8] */
2865 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2866 break;
2867 case 10:
2868 /* LEA r1, [r2 + r2*4] */
2869 /* ADD r1, r1 */
2870 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2871 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2872 break;
2873 case 12:
2874 /* LEA r1, [r2 + r2*2] */
2875 /* SHL r1, 2 */
2876 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2877 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2878 break;
2879 case 25:
2880 /* LEA r1, [r2 + r2*4] */
2881 /* LEA r1, [r1 + r1*4] */
2882 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2883 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2884 break;
2885 case 100:
2886 /* LEA r1, [r2 + r2*4] */
2887 /* SHL r1, 2 */
2888 /* LEA r1, [r1 + r1*4] */
2889 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2890 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2891 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2892 break;
2893 default:
2894 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2895 break;
2896 }
2897 break;
2898 case OP_IMUL_OVF:
2899 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2900 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2901 break;
2902 case OP_IMUL_OVF_UN: {
2903 /* the mul operation and the exception check should most likely be split */
2904 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2905 /*g_assert (ins->sreg2 == X86_EAX);
2906 g_assert (ins->dreg == X86_EAX);*/
2907 if (ins->sreg2 == X86_EAX) {
2908 non_eax_reg = ins->sreg1;
2909 } else if (ins->sreg1 == X86_EAX) {
2910 non_eax_reg = ins->sreg2;
2911 } else {
2912 /* no need to save since we're going to store to it anyway */
2913 if (ins->dreg != X86_EAX) {
2914 saved_eax = TRUE;
2915 x86_push_reg (code, X86_EAX);
2916 }
2917 x86_mov_reg_reg (code, X86_EAX, ins->sreg1);
2918 non_eax_reg = ins->sreg2;
2919 }
2920 if (ins->dreg == X86_EDX) {
2921 if (!saved_eax) {
2922 saved_eax = TRUE;
2923 x86_push_reg (code, X86_EAX);
2924 }
2925 } else {
2926 saved_edx = TRUE;
2927 x86_push_reg (code, X86_EDX);
2928 }
2929 x86_mul_reg (code, non_eax_reg, FALSE);
2930 /* save before the check since pop and mov don't change the flags */
2931 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2932 if (saved_edx)
2933 x86_pop_reg (code, X86_EDX);
2934 if (saved_eax)
2935 x86_pop_reg (code, X86_EAX);
2936 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2937 break;
2938 }
2939 case OP_ICONST:
2940 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2941 break;
2942 case OP_AOTCONST:
2943 g_assert_not_reached ();
2944 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2945 x86_mov_reg_imm (code, ins->dreg, 0);
2946 break;
2947 case OP_JUMP_TABLE:
2948 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2949 x86_mov_reg_imm (code, ins->dreg, 0);
2950 break;
2951 case OP_LOAD_GOTADDR:
2952 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2953 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2954 break;
2955 case OP_GOT_ENTRY:
2956 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2957 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2958 break;
2959 case OP_X86_PUSH_GOT_ENTRY:
2960 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2961 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2962 break;
2963 case OP_MOVE:
2964 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2965 break;
2966
2967 case OP_TAILCALL_PARAMETER:
2968 // This opcode helps compute sizes, i.e.
2969 // of the subsequent OP_TAILCALL, but contributes no code.
2970 g_assert (ins->next);
2971 break;
2972
2973 case OP_TAILCALL:
2974 case OP_TAILCALL_MEMBASE:
2975 case OP_TAILCALL_REG: {
2976 call = (MonoCallInst*)ins;
2977 int pos = 0, i;
2978 gboolean const tailcall_membase = ins->opcode == OP_TAILCALL_MEMBASE;
2979 gboolean const tailcall_reg = (ins->opcode == OP_TAILCALL_REG);
2980 int const sreg1 = ins->sreg1;
2981 gboolean const sreg1_ecx = sreg1 == X86_ECX;
2982 gboolean const tailcall_membase_ecx = tailcall_membase && sreg1_ecx;
2983 gboolean const tailcall_membase_not_ecx = tailcall_membase && !sreg1_ecx;
2984
2985 max_len += (call->stack_usage - call->stack_align_amount) / sizeof (target_mgreg_t) * ins_get_size (OP_TAILCALL_PARAMETER);
2986 code = realloc_code (cfg, max_len);
2987
2988 ins->flags |= MONO_INST_GC_CALLSITE;
2989 ins->backend.pc_offset = code - cfg->native_code;
2990
2991 g_assert (!cfg->method->save_lmf);
2992
2993 // Ecx is volatile, not used for parameters, or rgctx/imt (edx).
2994 // It is also not used for return value, though that does not matter.
2995 // Ecx is preserved across the tailcall formation.
2996 //
2997 // Eax could also be used here at the cost of a push/pop moving the parameters.
2998 // Edx must be preserved as it is rgctx/imt.
2999 //
3000 // If ecx happens to be the base of the tailcall_membase, then
3001 // just end with jmp [ecx+offset] -- one instruction.
3002 // if ecx is not the base, then move ecx, [reg+offset] and later jmp [ecx] -- two instructions.
3003
3004 if (tailcall_reg) {
3005 g_assert (sreg1 > -1);
3006 x86_mov_reg_reg (code, X86_ECX, sreg1);
3007 } else if (tailcall_membase_not_ecx) {
3008 g_assert (sreg1 > -1);
3009 x86_mov_reg_membase (code, X86_ECX, sreg1, ins->inst_offset, 4);
3010 }
3011
3012 /* restore callee saved registers */
3013 for (i = 0; i < X86_NREG; ++i)
3014 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3015 pos -= 4;
3016 if (cfg->used_int_regs & (1 << X86_ESI)) {
3017 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3018 pos += 4;
3019 }
3020 if (cfg->used_int_regs & (1 << X86_EDI)) {
3021 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3022 pos += 4;
3023 }
3024 if (cfg->used_int_regs & (1 << X86_EBX)) {
3025 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3026 pos += 4;
3027 }
3028
3029 /* Copy arguments on the stack to our argument area */
3030 // FIXME use rep mov for constant code size, before nonvolatiles
3031 // restored, first saving esi, edi into volatiles
3032 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3033 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3034 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3035 }
3036
3037 /* restore ESP/EBP */
3038 x86_leave (code);
3039
3040 if (tailcall_membase_ecx) {
3041 x86_jump_membase (code, X86_ECX, ins->inst_offset);
3042 } else if (tailcall_reg || tailcall_membase_not_ecx) {
3043 x86_jump_reg (code, X86_ECX);
3044 } else {
3045 // FIXME Patch data instead of code.
3046 code = x86_align_and_patch (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3047 x86_jump32 (code, 0);
3048 }
3049
3050 ins->flags |= MONO_INST_GC_CALLSITE;
3051 break;
3052 }
3053 case OP_CHECK_THIS:
3054 /* ensure ins->sreg1 is not NULL
3055 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3056 * cmp DWORD PTR [eax], 0
3057 */
3058 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3059 break;
3060 case OP_ARGLIST: {
3061 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3062 x86_push_reg (code, hreg);
3063 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3064 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3065 x86_pop_reg (code, hreg);
3066 break;
3067 }
3068 case OP_FCALL:
3069 case OP_LCALL:
3070 case OP_VCALL:
3071 case OP_VCALL2:
3072 case OP_VOIDCALL:
3073 case OP_CALL:
3074 case OP_FCALL_REG:
3075 case OP_LCALL_REG:
3076 case OP_VCALL_REG:
3077 case OP_VCALL2_REG:
3078 case OP_VOIDCALL_REG:
3079 case OP_CALL_REG:
3080 case OP_FCALL_MEMBASE:
3081 case OP_LCALL_MEMBASE:
3082 case OP_VCALL_MEMBASE:
3083 case OP_VCALL2_MEMBASE:
3084 case OP_VOIDCALL_MEMBASE:
3085 case OP_CALL_MEMBASE: {
3086 CallInfo *cinfo;
3087
3088 call = (MonoCallInst*)ins;
3089 cinfo = call->call_info;
3090
3091 switch (ins->opcode) {
3092 case OP_FCALL:
3093 case OP_LCALL:
3094 case OP_VCALL:
3095 case OP_VCALL2:
3096 case OP_VOIDCALL:
3097 case OP_CALL: {
3098 const MonoJumpInfoTarget patch = mono_call_to_patch (call);
3099 code = emit_call (cfg, code, patch.type, patch.target);
3100 break;
3101 }
3102 case OP_FCALL_REG:
3103 case OP_LCALL_REG:
3104 case OP_VCALL_REG:
3105 case OP_VCALL2_REG:
3106 case OP_VOIDCALL_REG:
3107 case OP_CALL_REG:
3108 x86_call_reg (code, ins->sreg1);
3109 break;
3110 case OP_FCALL_MEMBASE:
3111 case OP_LCALL_MEMBASE:
3112 case OP_VCALL_MEMBASE:
3113 case OP_VCALL2_MEMBASE:
3114 case OP_VOIDCALL_MEMBASE:
3115 case OP_CALL_MEMBASE:
3116 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3117 break;
3118 default:
3119 g_assert_not_reached ();
3120 break;
3121 }
3122 ins->flags |= MONO_INST_GC_CALLSITE;
3123 ins->backend.pc_offset = code - cfg->native_code;
3124 if (cinfo->callee_stack_pop) {
3125 /* Have to compensate for the stack space popped by the callee */
3126 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3127 }
3128 code = emit_move_return_value (cfg, ins, code);
3129 break;
3130 }
3131 case OP_X86_LEA:
3132 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3133 break;
3134 case OP_X86_LEA_MEMBASE:
3135 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3136 break;
3137 case OP_X86_XCHG:
3138 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3139 break;
3140 case OP_LOCALLOC:
3141 /* keep alignment */
3142 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3143 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3144 code = mono_emit_stack_alloc (cfg, code, ins);
3145 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3146 if (cfg->param_area)
3147 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3148 break;
3149 case OP_LOCALLOC_IMM: {
3150 guint32 size = ins->inst_imm;
3151 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3152
3153 if (ins->flags & MONO_INST_INIT) {
3154 /* FIXME: Optimize this */
3155 x86_mov_reg_imm (code, ins->dreg, size);
3156 ins->sreg1 = ins->dreg;
3157
3158 code = mono_emit_stack_alloc (cfg, code, ins);
3159 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3160 } else {
3161 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3162 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3163 }
3164 if (cfg->param_area)
3165 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3166 break;
3167 }
3168 case OP_THROW: {
3169 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3170 x86_push_reg (code, ins->sreg1);
3171 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3172 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_throw_exception));
3173 ins->flags |= MONO_INST_GC_CALLSITE;
3174 ins->backend.pc_offset = code - cfg->native_code;
3175 break;
3176 }
3177 case OP_RETHROW: {
3178 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3179 x86_push_reg (code, ins->sreg1);
3180 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3181 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_rethrow_exception));
3182 ins->flags |= MONO_INST_GC_CALLSITE;
3183 ins->backend.pc_offset = code - cfg->native_code;
3184 break;
3185 }
3186 case OP_CALL_HANDLER:
3187 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3188 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3189 x86_call_imm (code, 0);
3190 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
3191 mono_cfg_add_try_hole (cfg, ((MonoLeaveClause *) tmp->data)->clause, code, bb);
3192 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3193 break;
3194 case OP_START_HANDLER: {
3195 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3196 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3197 if (cfg->param_area)
3198 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3199 break;
3200 }
3201 case OP_ENDFINALLY: {
3202 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3203 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3204 x86_ret (code);
3205 break;
3206 }
3207 case OP_ENDFILTER: {
3208 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3209 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3210 /* The local allocator will put the result into EAX */
3211 x86_ret (code);
3212 break;
3213 }
3214 case OP_GET_EX_OBJ:
3215 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
3216 break;
3217
3218 case OP_LABEL:
3219 ins->inst_c0 = code - cfg->native_code;
3220 break;
3221 case OP_BR:
3222 if (ins->inst_target_bb->native_offset) {
3223 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3224 } else {
3225 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3226 if ((cfg->opt & MONO_OPT_BRANCH) &&
3227 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3228 x86_jump8 (code, 0);
3229 else
3230 x86_jump32 (code, 0);
3231 }
3232 break;
3233 case OP_BR_REG:
3234 x86_jump_reg (code, ins->sreg1);
3235 break;
3236 case OP_ICNEQ:
3237 case OP_ICGE:
3238 case OP_ICLE:
3239 case OP_ICGE_UN:
3240 case OP_ICLE_UN:
3241
3242 case OP_CEQ:
3243 case OP_CLT:
3244 case OP_CLT_UN:
3245 case OP_CGT:
3246 case OP_CGT_UN:
3247 case OP_CNE:
3248 case OP_ICEQ:
3249 case OP_ICLT:
3250 case OP_ICLT_UN:
3251 case OP_ICGT:
3252 case OP_ICGT_UN:
3253 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3254 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3255 break;
3256 case OP_COND_EXC_EQ:
3257 case OP_COND_EXC_NE_UN:
3258 case OP_COND_EXC_LT:
3259 case OP_COND_EXC_LT_UN:
3260 case OP_COND_EXC_GT:
3261 case OP_COND_EXC_GT_UN:
3262 case OP_COND_EXC_GE:
3263 case OP_COND_EXC_GE_UN:
3264 case OP_COND_EXC_LE:
3265 case OP_COND_EXC_LE_UN:
3266 case OP_COND_EXC_IEQ:
3267 case OP_COND_EXC_INE_UN:
3268 case OP_COND_EXC_ILT:
3269 case OP_COND_EXC_ILT_UN:
3270 case OP_COND_EXC_IGT:
3271 case OP_COND_EXC_IGT_UN:
3272 case OP_COND_EXC_IGE:
3273 case OP_COND_EXC_IGE_UN:
3274 case OP_COND_EXC_ILE:
3275 case OP_COND_EXC_ILE_UN:
3276 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char*)ins->inst_p1);
3277 break;
3278 case OP_COND_EXC_OV:
3279 case OP_COND_EXC_NO:
3280 case OP_COND_EXC_C:
3281 case OP_COND_EXC_NC:
3282 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), (const char*)ins->inst_p1);
3283 break;
3284 case OP_COND_EXC_IOV:
3285 case OP_COND_EXC_INO:
3286 case OP_COND_EXC_IC:
3287 case OP_COND_EXC_INC:
3288 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), (const char*)ins->inst_p1);
3289 break;
3290 case OP_IBEQ:
3291 case OP_IBNE_UN:
3292 case OP_IBLT:
3293 case OP_IBLT_UN:
3294 case OP_IBGT:
3295 case OP_IBGT_UN:
3296 case OP_IBGE:
3297 case OP_IBGE_UN:
3298 case OP_IBLE:
3299 case OP_IBLE_UN:
3300 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3301 break;
3302
3303 case OP_CMOV_IEQ:
3304 case OP_CMOV_IGE:
3305 case OP_CMOV_IGT:
3306 case OP_CMOV_ILE:
3307 case OP_CMOV_ILT:
3308 case OP_CMOV_INE_UN:
3309 case OP_CMOV_IGE_UN:
3310 case OP_CMOV_IGT_UN:
3311 case OP_CMOV_ILE_UN:
3312 case OP_CMOV_ILT_UN:
3313 g_assert (ins->dreg == ins->sreg1);
3314 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3315 break;
3316
3317 /* floating point opcodes */
3318 case OP_R8CONST: {
3319 double d = *(double *)ins->inst_p0;
3320
3321 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3322 x86_fldz (code);
3323 } else if (d == 1.0) {
3324 x86_fld1 (code);
3325 } else {
3326 if (cfg->compile_aot) {
3327 guint32 *val = (guint32*)&d;
3328 x86_push_imm (code, val [1]);
3329 x86_push_imm (code, val [0]);
3330 x86_fld_membase (code, X86_ESP, 0, TRUE);
3331 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3332 }
3333 else {
3334 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3335 x86_fld (code, NULL, TRUE);
3336 }
3337 }
3338 break;
3339 }
3340 case OP_R4CONST: {
3341 float f = *(float *)ins->inst_p0;
3342
3343 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3344 x86_fldz (code);
3345 } else if (f == 1.0) {
3346 x86_fld1 (code);
3347 } else {
3348 if (cfg->compile_aot) {
3349 guint32 val = *(guint32*)&f;
3350 x86_push_imm (code, val);
3351 x86_fld_membase (code, X86_ESP, 0, FALSE);
3352 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3353 }
3354 else {
3355 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3356 x86_fld (code, NULL, FALSE);
3357 }
3358 }
3359 break;
3360 }
3361 case OP_STORER8_MEMBASE_REG:
3362 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3363 break;
3364 case OP_LOADR8_MEMBASE:
3365 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3366 break;
3367 case OP_STORER4_MEMBASE_REG:
3368 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3369 break;
3370 case OP_LOADR4_MEMBASE:
3371 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3372 break;
3373 case OP_ICONV_TO_R4:
3374 x86_push_reg (code, ins->sreg1);
3375 x86_fild_membase (code, X86_ESP, 0, FALSE);
3376 /* Change precision */
3377 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3378 x86_fld_membase (code, X86_ESP, 0, FALSE);
3379 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3380 break;
3381 case OP_ICONV_TO_R8:
3382 x86_push_reg (code, ins->sreg1);
3383 x86_fild_membase (code, X86_ESP, 0, FALSE);
3384 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3385 break;
3386 case OP_ICONV_TO_R_UN:
3387 x86_push_imm (code, 0);
3388 x86_push_reg (code, ins->sreg1);
3389 x86_fild_membase (code, X86_ESP, 0, TRUE);
3390 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3391 break;
3392 case OP_X86_FP_LOAD_I8:
3393 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3394 break;
3395 case OP_X86_FP_LOAD_I4:
3396 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3397 break;
3398 case OP_FCONV_TO_R4:
3399 /* Change precision */
3400 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3401 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3402 x86_fld_membase (code, X86_ESP, 0, FALSE);
3403 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3404 break;
3405 case OP_FCONV_TO_I1:
3406 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3407 break;
3408 case OP_FCONV_TO_U1:
3409 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3410 break;
3411 case OP_FCONV_TO_I2:
3412 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3413 break;
3414 case OP_FCONV_TO_U2:
3415 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3416 break;
3417 case OP_FCONV_TO_I4:
3418 case OP_FCONV_TO_I:
3419 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3420 break;
3421 case OP_FCONV_TO_I8:
3422 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3423 x86_fnstcw_membase(code, X86_ESP, 0);
3424 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3425 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3426 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3427 x86_fldcw_membase (code, X86_ESP, 2);
3428 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3429 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3430 x86_pop_reg (code, ins->dreg);
3431 x86_pop_reg (code, ins->backend.reg3);
3432 x86_fldcw_membase (code, X86_ESP, 0);
3433 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3434 break;
3435 case OP_LCONV_TO_R8_2:
3436 x86_push_reg (code, ins->sreg2);
3437 x86_push_reg (code, ins->sreg1);
3438 x86_fild_membase (code, X86_ESP, 0, TRUE);
3439 /* Change precision */
3440 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3441 x86_fld_membase (code, X86_ESP, 0, TRUE);
3442 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3443 break;
3444 case OP_LCONV_TO_R4_2:
3445 x86_push_reg (code, ins->sreg2);
3446 x86_push_reg (code, ins->sreg1);
3447 x86_fild_membase (code, X86_ESP, 0, TRUE);
3448 /* Change precision */
3449 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3450 x86_fld_membase (code, X86_ESP, 0, FALSE);
3451 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3452 break;
3453 case OP_LCONV_TO_R_UN_2: {
3454 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3455 guint8 *br;
3456
3457 /* load 64bit integer to FP stack */
3458 x86_push_reg (code, ins->sreg2);
3459 x86_push_reg (code, ins->sreg1);
3460 x86_fild_membase (code, X86_ESP, 0, TRUE);
3461
3462 /* test if lreg is negative */
3463 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3464 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3465
3466 /* add correction constant mn */
3467 if (cfg->compile_aot) {
3468 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3469 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3470 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3471 x86_fld80_membase (code, X86_ESP, 2);
3472 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3473 } else {
3474 x86_fld80_mem (code, mn);
3475 }
3476 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3477
3478 x86_patch (br, code);
3479
3480 /* Change precision */
3481 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3482 x86_fld_membase (code, X86_ESP, 0, TRUE);
3483
3484 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3485
3486 break;
3487 }
3488 case OP_LCONV_TO_OVF_I:
3489 case OP_LCONV_TO_OVF_I4_2: {
3490 guint8 *br [3], *label [1];
3491 MonoInst *tins;
3492
3493 /*
3494 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3495 */
3496 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3497
3498 /* If the low word top bit is set, see if we are negative */
3499 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3500 /* We are not negative (no top bit set, check for our top word to be zero */
3501 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3502 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3503 label [0] = code;
3504
3505 /* throw exception */
3506 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3507 if (tins) {
3508 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3509 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3510 x86_jump8 (code, 0);
3511 else
3512 x86_jump32 (code, 0);
3513 } else {
3514 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3515 x86_jump32 (code, 0);
3516 }
3517
3518
3519 x86_patch (br [0], code);
3520 /* our top bit is set, check that top word is 0xfffffff */
3521 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3522
3523 x86_patch (br [1], code);
3524 /* nope, emit exception */
3525 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3526 x86_patch (br [2], label [0]);
3527
3528 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
3529 break;
3530 }
3531 case OP_FMOVE:
3532 /* Not needed on the fp stack */
3533 break;
3534 case OP_MOVE_F_TO_I4:
3535 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3536 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3537 break;
3538 case OP_MOVE_I4_TO_F:
3539 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3540 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3541 break;
3542 case OP_FADD:
3543 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3544 break;
3545 case OP_FSUB:
3546 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3547 break;
3548 case OP_FMUL:
3549 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3550 break;
3551 case OP_FDIV:
3552 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3553 break;
3554 case OP_FNEG:
3555 x86_fchs (code);
3556 break;
3557 case OP_SIN:
3558 x86_fsin (code);
3559 x86_fldz (code);
3560 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3561 break;
3562 case OP_COS:
3563 x86_fcos (code);
3564 x86_fldz (code);
3565 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3566 break;
3567 case OP_ABS:
3568 x86_fabs (code);
3569 break;
3570 case OP_TAN: {
3571 /*
3572 * it really doesn't make sense to inline all this code,
3573 * it's here just to show that things may not be as simple
3574 * as they appear.
3575 */
3576 guchar *check_pos, *end_tan, *pop_jump;
3577 x86_push_reg (code, X86_EAX);
3578 x86_fptan (code);
3579 x86_fnstsw (code);
3580 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3581 check_pos = code;
3582 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3583 x86_fstp (code, 0); /* pop the 1.0 */
3584 end_tan = code;
3585 x86_jump8 (code, 0);
3586 x86_fldpi (code);
3587 x86_fp_op (code, X86_FADD, 0);
3588 x86_fxch (code, 1);
3589 x86_fprem1 (code);
3590 x86_fstsw (code);
3591 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3592 pop_jump = code;
3593 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3594 x86_fstp (code, 1);
3595 x86_fptan (code);
3596 x86_patch (pop_jump, code);
3597 x86_fstp (code, 0); /* pop the 1.0 */
3598 x86_patch (check_pos, code);
3599 x86_patch (end_tan, code);
3600 x86_fldz (code);
3601 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3602 x86_pop_reg (code, X86_EAX);
3603 break;
3604 }
3605 case OP_ATAN:
3606 x86_fld1 (code);
3607 x86_fpatan (code);
3608 x86_fldz (code);
3609 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3610 break;
3611 case OP_SQRT:
3612 x86_fsqrt (code);
3613 break;
3614 case OP_ROUND:
3615 x86_frndint (code);
3616 break;
3617 case OP_IMIN:
3618 g_assert (cfg->opt & MONO_OPT_CMOV);
3619 g_assert (ins->dreg == ins->sreg1);
3620 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3621 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3622 break;
3623 case OP_IMIN_UN:
3624 g_assert (cfg->opt & MONO_OPT_CMOV);
3625 g_assert (ins->dreg == ins->sreg1);
3626 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3627 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3628 break;
3629 case OP_IMAX:
3630 g_assert (cfg->opt & MONO_OPT_CMOV);
3631 g_assert (ins->dreg == ins->sreg1);
3632 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3633 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3634 break;
3635 case OP_IMAX_UN:
3636 g_assert (cfg->opt & MONO_OPT_CMOV);
3637 g_assert (ins->dreg == ins->sreg1);
3638 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3639 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3640 break;
3641 case OP_X86_FPOP:
3642 x86_fstp (code, 0);
3643 break;
3644 case OP_X86_FXCH:
3645 x86_fxch (code, ins->inst_imm);
3646 break;
3647 case OP_FREM: {
3648 guint8 *l1, *l2;
3649
3650 x86_push_reg (code, X86_EAX);
3651 /* we need to exchange ST(0) with ST(1) */
3652 x86_fxch (code, 1);
3653
3654 /* this requires a loop, because fprem somtimes
3655 * returns a partial remainder */
3656 l1 = code;
3657 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3658 /* x86_fprem1 (code); */
3659 x86_fprem (code);
3660 x86_fnstsw (code);
3661 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3662 l2 = code;
3663 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3664 x86_patch (l2, l1);
3665
3666 /* pop result */
3667 x86_fstp (code, 1);
3668
3669 x86_pop_reg (code, X86_EAX);
3670 break;
3671 }
3672 case OP_FCOMPARE:
3673 if (cfg->opt & MONO_OPT_FCMOV) {
3674 x86_fcomip (code, 1);
3675 x86_fstp (code, 0);
3676 break;
3677 }
3678 /* this overwrites EAX */
3679 EMIT_FPCOMPARE(code);
3680 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3681 break;
3682 case OP_FCEQ:
3683 case OP_FCNEQ:
3684 if (cfg->opt & MONO_OPT_FCMOV) {
3685 /* zeroing the register at the start results in
3686 * shorter and faster code (we can also remove the widening op)
3687 */
3688 guchar *unordered_check;
3689 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3690 x86_fcomip (code, 1);
3691 x86_fstp (code, 0);
3692 unordered_check = code;
3693 x86_branch8 (code, X86_CC_P, 0, FALSE);
3694 if (ins->opcode == OP_FCEQ) {
3695 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3696 x86_patch (unordered_check, code);
3697 } else {
3698 guchar *jump_to_end;
3699 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3700 jump_to_end = code;
3701 x86_jump8 (code, 0);
3702 x86_patch (unordered_check, code);
3703 x86_inc_reg (code, ins->dreg);
3704 x86_patch (jump_to_end, code);
3705 }
3706
3707 break;
3708 }
3709 if (ins->dreg != X86_EAX)
3710 x86_push_reg (code, X86_EAX);
3711
3712 EMIT_FPCOMPARE(code);
3713 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3714 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3715 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3716 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3717
3718 if (ins->dreg != X86_EAX)
3719 x86_pop_reg (code, X86_EAX);
3720 break;
3721 case OP_FCLT:
3722 case OP_FCLT_UN:
3723 if (cfg->opt & MONO_OPT_FCMOV) {
3724 /* zeroing the register at the start results in
3725 * shorter and faster code (we can also remove the widening op)
3726 */
3727 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3728 x86_fcomip (code, 1);
3729 x86_fstp (code, 0);
3730 if (ins->opcode == OP_FCLT_UN) {
3731 guchar *unordered_check = code;
3732 guchar *jump_to_end;
3733 x86_branch8 (code, X86_CC_P, 0, FALSE);
3734 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3735 jump_to_end = code;
3736 x86_jump8 (code, 0);
3737 x86_patch (unordered_check, code);
3738 x86_inc_reg (code, ins->dreg);
3739 x86_patch (jump_to_end, code);
3740 } else {
3741 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3742 }
3743 break;
3744 }
3745 if (ins->dreg != X86_EAX)
3746 x86_push_reg (code, X86_EAX);
3747
3748 EMIT_FPCOMPARE(code);
3749 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3750 if (ins->opcode == OP_FCLT_UN) {
3751 guchar *is_not_zero_check, *end_jump;
3752 is_not_zero_check = code;
3753 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3754 end_jump = code;
3755 x86_jump8 (code, 0);
3756 x86_patch (is_not_zero_check, code);
3757 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3758
3759 x86_patch (end_jump, code);
3760 }
3761 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3762 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3763
3764 if (ins->dreg != X86_EAX)
3765 x86_pop_reg (code, X86_EAX);
3766 break;
3767 case OP_FCLE: {
3768 guchar *unordered_check;
3769 guchar *jump_to_end;
3770 if (cfg->opt & MONO_OPT_FCMOV) {
3771 /* zeroing the register at the start results in
3772 * shorter and faster code (we can also remove the widening op)
3773 */
3774 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3775 x86_fcomip (code, 1);
3776 x86_fstp (code, 0);
3777 unordered_check = code;
3778 x86_branch8 (code, X86_CC_P, 0, FALSE);
3779 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3780 x86_patch (unordered_check, code);
3781 break;
3782 }
3783 if (ins->dreg != X86_EAX)
3784 x86_push_reg (code, X86_EAX);
3785
3786 EMIT_FPCOMPARE(code);
3787 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3788 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3789 unordered_check = code;
3790 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3791
3792 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3793 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3794 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3795 jump_to_end = code;
3796 x86_jump8 (code, 0);
3797 x86_patch (unordered_check, code);
3798 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3799 x86_patch (jump_to_end, code);
3800
3801 if (ins->dreg != X86_EAX)
3802 x86_pop_reg (code, X86_EAX);
3803 break;
3804 }
3805 case OP_FCGT:
3806 case OP_FCGT_UN:
3807 if (cfg->opt & MONO_OPT_FCMOV) {
3808 /* zeroing the register at the start results in
3809 * shorter and faster code (we can also remove the widening op)
3810 */
3811 guchar *unordered_check;
3812 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3813 x86_fcomip (code, 1);
3814 x86_fstp (code, 0);
3815 if (ins->opcode == OP_FCGT) {
3816 unordered_check = code;
3817 x86_branch8 (code, X86_CC_P, 0, FALSE);
3818 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3819 x86_patch (unordered_check, code);
3820 } else {
3821 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3822 }
3823 break;
3824 }
3825 if (ins->dreg != X86_EAX)
3826 x86_push_reg (code, X86_EAX);
3827
3828 EMIT_FPCOMPARE(code);
3829 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3830 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3831 if (ins->opcode == OP_FCGT_UN) {
3832 guchar *is_not_zero_check, *end_jump;
3833 is_not_zero_check = code;
3834 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3835 end_jump = code;
3836 x86_jump8 (code, 0);
3837 x86_patch (is_not_zero_check, code);
3838 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3839
3840 x86_patch (end_jump, code);
3841 }
3842 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3843 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3844
3845 if (ins->dreg != X86_EAX)
3846 x86_pop_reg (code, X86_EAX);
3847 break;
3848 case OP_FCGE: {
3849 guchar *unordered_check;
3850 guchar *jump_to_end;
3851 if (cfg->opt & MONO_OPT_FCMOV) {
3852 /* zeroing the register at the start results in
3853 * shorter and faster code (we can also remove the widening op)
3854 */
3855 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3856 x86_fcomip (code, 1);
3857 x86_fstp (code, 0);
3858 unordered_check = code;
3859 x86_branch8 (code, X86_CC_P, 0, FALSE);
3860 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3861 x86_patch (unordered_check, code);
3862 break;
3863 }
3864 if (ins->dreg != X86_EAX)
3865 x86_push_reg (code, X86_EAX);
3866
3867 EMIT_FPCOMPARE(code);
3868 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3869 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3870 unordered_check = code;
3871 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3872
3873 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3874 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3875 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3876 jump_to_end = code;
3877 x86_jump8 (code, 0);
3878 x86_patch (unordered_check, code);
3879 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3880 x86_patch (jump_to_end, code);
3881
3882 if (ins->dreg != X86_EAX)
3883 x86_pop_reg (code, X86_EAX);
3884 break;
3885 }
3886 case OP_FBEQ:
3887 if (cfg->opt & MONO_OPT_FCMOV) {
3888 guchar *jump = code;
3889 x86_branch8 (code, X86_CC_P, 0, TRUE);
3890 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3891 x86_patch (jump, code);
3892 break;
3893 }
3894 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3895 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3896 break;
3897 case OP_FBNE_UN:
3898 /* Branch if C013 != 100 */
3899 if (cfg->opt & MONO_OPT_FCMOV) {
3900 /* branch if !ZF or (PF|CF) */
3901 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3902 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3903 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3904 break;
3905 }
3906 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3907 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3908 break;
3909 case OP_FBLT:
3910 if (cfg->opt & MONO_OPT_FCMOV) {
3911 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3912 break;
3913 }
3914 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3915 break;
3916 case OP_FBLT_UN:
3917 if (cfg->opt & MONO_OPT_FCMOV) {
3918 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3919 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3920 break;
3921 }
3922 if (ins->opcode == OP_FBLT_UN) {
3923 guchar *is_not_zero_check, *end_jump;
3924 is_not_zero_check = code;
3925 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3926 end_jump = code;
3927 x86_jump8 (code, 0);
3928 x86_patch (is_not_zero_check, code);
3929 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3930
3931 x86_patch (end_jump, code);
3932 }
3933 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3934 break;
3935 case OP_FBGT:
3936 case OP_FBGT_UN:
3937 if (cfg->opt & MONO_OPT_FCMOV) {
3938 if (ins->opcode == OP_FBGT) {
3939 guchar *br1;
3940
3941 /* skip branch if C1=1 */
3942 br1 = code;
3943 x86_branch8 (code, X86_CC_P, 0, FALSE);
3944 /* branch if (C0 | C3) = 1 */
3945 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3946 x86_patch (br1, code);
3947 } else {
3948 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3949 }
3950 break;
3951 }
3952 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3953 if (ins->opcode == OP_FBGT_UN) {
3954 guchar *is_not_zero_check, *end_jump;
3955 is_not_zero_check = code;
3956 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3957 end_jump = code;
3958 x86_jump8 (code, 0);
3959 x86_patch (is_not_zero_check, code);
3960 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3961
3962 x86_patch (end_jump, code);
3963 }
3964 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3965 break;
3966 case OP_FBGE:
3967 /* Branch if C013 == 100 or 001 */
3968 if (cfg->opt & MONO_OPT_FCMOV) {
3969 guchar *br1;
3970
3971 /* skip branch if C1=1 */
3972 br1 = code;
3973 x86_branch8 (code, X86_CC_P, 0, FALSE);
3974 /* branch if (C0 | C3) = 1 */
3975 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3976 x86_patch (br1, code);
3977 break;
3978 }
3979 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3980 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3981 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3982 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3983 break;
3984 case OP_FBGE_UN:
3985 /* Branch if C013 == 000 */
3986 if (cfg->opt & MONO_OPT_FCMOV) {
3987 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3988 break;
3989 }
3990 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3991 break;
3992 case OP_FBLE:
3993 /* Branch if C013=000 or 100 */
3994 if (cfg->opt & MONO_OPT_FCMOV) {
3995 guchar *br1;
3996
3997 /* skip branch if C1=1 */
3998 br1 = code;
3999 x86_branch8 (code, X86_CC_P, 0, FALSE);
4000 /* branch if C0=0 */
4001 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4002 x86_patch (br1, code);
4003 break;
4004 }
4005 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4006 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4007 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4008 break;
4009 case OP_FBLE_UN:
4010 /* Branch if C013 != 001 */
4011 if (cfg->opt & MONO_OPT_FCMOV) {
4012 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4013 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4014 break;
4015 }
4016 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4017 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4018 break;
4019 case OP_CKFINITE: {
4020 guchar *br1;
4021 x86_push_reg (code, X86_EAX);
4022 x86_fxam (code);
4023 x86_fnstsw (code);
4024 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4025 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4026 x86_pop_reg (code, X86_EAX);
4027
4028 /* Have to clean up the fp stack before throwing the exception */
4029 br1 = code;
4030 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4031
4032 x86_fstp (code, 0);
4033 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4034
4035 x86_patch (br1, code);
4036 break;
4037 }
4038 case OP_TLS_GET: {
4039 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4040 break;
4041 }
4042 case OP_TLS_SET: {
4043 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4044 break;
4045 }
4046 case OP_MEMORY_BARRIER: {
4047 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4048 x86_prefix (code, X86_LOCK_PREFIX);
4049 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4050 }
4051 break;
4052 }
4053 case OP_ATOMIC_ADD_I4: {
4054 int dreg = ins->dreg;
4055
4056 g_assert (cfg->has_atomic_add_i4);
4057
4058 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4059 if (ins->sreg2 == dreg) {
4060 if (dreg == X86_EBX) {
4061 dreg = X86_EDI;
4062 if (ins->inst_basereg == X86_EDI)
4063 dreg = X86_ESI;
4064 } else {
4065 dreg = X86_EBX;
4066 if (ins->inst_basereg == X86_EBX)
4067 dreg = X86_EDI;
4068 }
4069 } else if (ins->inst_basereg == dreg) {
4070 if (dreg == X86_EBX) {
4071 dreg = X86_EDI;
4072 if (ins->sreg2 == X86_EDI)
4073 dreg = X86_ESI;
4074 } else {
4075 dreg = X86_EBX;
4076 if (ins->sreg2 == X86_EBX)
4077 dreg = X86_EDI;
4078 }
4079 }
4080
4081 if (dreg != ins->dreg) {
4082 x86_push_reg (code, dreg);
4083 }
4084
4085 x86_mov_reg_reg (code, dreg, ins->sreg2);
4086 x86_prefix (code, X86_LOCK_PREFIX);
4087 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4088 /* dreg contains the old value, add with sreg2 value */
4089 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4090
4091 if (ins->dreg != dreg) {
4092 x86_mov_reg_reg (code, ins->dreg, dreg);
4093 x86_pop_reg (code, dreg);
4094 }
4095
4096 break;
4097 }
4098 case OP_ATOMIC_EXCHANGE_I4: {
4099 guchar *br[2];
4100 int sreg2 = ins->sreg2;
4101 int breg = ins->inst_basereg;
4102
4103 g_assert (cfg->has_atomic_exchange_i4);
4104
4105 /* cmpxchg uses eax as comperand, need to make sure we can use it
4106 * hack to overcome limits in x86 reg allocator
4107 * (req: dreg == eax and sreg2 != eax and breg != eax)
4108 */
4109 g_assert (ins->dreg == X86_EAX);
4110
4111 /* We need the EAX reg for the cmpxchg */
4112 if (ins->sreg2 == X86_EAX) {
4113 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4114 x86_push_reg (code, sreg2);
4115 x86_mov_reg_reg (code, sreg2, X86_EAX);
4116 }
4117
4118 if (breg == X86_EAX) {
4119 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4120 x86_push_reg (code, breg);
4121 x86_mov_reg_reg (code, breg, X86_EAX);
4122 }
4123
4124 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4125
4126 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4127 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4128 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4129 x86_patch (br [1], br [0]);
4130
4131 if (breg != ins->inst_basereg)
4132 x86_pop_reg (code, breg);
4133
4134 if (ins->sreg2 != sreg2)
4135 x86_pop_reg (code, sreg2);
4136
4137 break;
4138 }
4139 case OP_ATOMIC_CAS_I4: {
4140 g_assert (ins->dreg == X86_EAX);
4141 g_assert (ins->sreg3 == X86_EAX);
4142 g_assert (ins->sreg1 != X86_EAX);
4143 g_assert (ins->sreg1 != ins->sreg2);
4144
4145 x86_prefix (code, X86_LOCK_PREFIX);
4146 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4147 break;
4148 }
4149 case OP_ATOMIC_LOAD_I1: {
4150 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4151 break;
4152 }
4153 case OP_ATOMIC_LOAD_U1: {
4154 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4155 break;
4156 }
4157 case OP_ATOMIC_LOAD_I2: {
4158 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4159 break;
4160 }
4161 case OP_ATOMIC_LOAD_U2: {
4162 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4163 break;
4164 }
4165 case OP_ATOMIC_LOAD_I4:
4166 case OP_ATOMIC_LOAD_U4: {
4167 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4168 break;
4169 }
4170 case OP_ATOMIC_LOAD_R4:
4171 case OP_ATOMIC_LOAD_R8: {
4172 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4173 break;
4174 }
4175 case OP_ATOMIC_STORE_I1:
4176 case OP_ATOMIC_STORE_U1:
4177 case OP_ATOMIC_STORE_I2:
4178 case OP_ATOMIC_STORE_U2:
4179 case OP_ATOMIC_STORE_I4:
4180 case OP_ATOMIC_STORE_U4: {
4181 int size;
4182
4183 switch (ins->opcode) {
4184 case OP_ATOMIC_STORE_I1:
4185 case OP_ATOMIC_STORE_U1:
4186 size = 1;
4187 break;
4188 case OP_ATOMIC_STORE_I2:
4189 case OP_ATOMIC_STORE_U2:
4190 size = 2;
4191 break;
4192 case OP_ATOMIC_STORE_I4:
4193 case OP_ATOMIC_STORE_U4:
4194 size = 4;
4195 break;
4196 }
4197
4198 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4199
4200 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4201 x86_mfence (code);
4202 break;
4203 }
4204 case OP_ATOMIC_STORE_R4:
4205 case OP_ATOMIC_STORE_R8: {
4206 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4207
4208 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4209 x86_mfence (code);
4210 break;
4211 }
4212 case OP_CARD_TABLE_WBARRIER: {
4213 int ptr = ins->sreg1;
4214 int value = ins->sreg2;
4215 guchar *br = NULL;
4216 int nursery_shift, card_table_shift;
4217 gpointer card_table_mask;
4218 size_t nursery_size;
4219 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4220 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4221 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4222
4223 /*
4224 * We need one register we can clobber, we choose EDX and make sreg1
4225 * fixed EAX to work around limitations in the local register allocator.
4226 * sreg2 might get allocated to EDX, but that is not a problem since
4227 * we use it before clobbering EDX.
4228 */
4229 g_assert (ins->sreg1 == X86_EAX);
4230
4231 /*
4232 * This is the code we produce:
4233 *
4234 * edx = value
4235 * edx >>= nursery_shift
4236 * cmp edx, (nursery_start >> nursery_shift)
4237 * jne done
4238 * edx = ptr
4239 * edx >>= card_table_shift
4240 * card_table[edx] = 1
4241 * done:
4242 */
4243
4244 if (card_table_nursery_check) {
4245 if (value != X86_EDX)
4246 x86_mov_reg_reg (code, X86_EDX, value);
4247 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4248 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4249 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4250 }
4251 x86_mov_reg_reg (code, X86_EDX, ptr);
4252 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4253 if (card_table_mask)
4254 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4255 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4256 if (card_table_nursery_check)
4257 x86_patch (br, code);
4258 break;
4259 }
4260 #ifdef MONO_ARCH_SIMD_INTRINSICS
4261 case OP_ADDPS:
4262 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4263 break;
4264 case OP_DIVPS:
4265 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4266 break;
4267 case OP_MULPS:
4268 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4269 break;
4270 case OP_SUBPS:
4271 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4272 break;
4273 case OP_MAXPS:
4274 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4275 break;
4276 case OP_MINPS:
4277 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4278 break;
4279 case OP_COMPPS:
4280 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4281 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4282 break;
4283 case OP_ANDPS:
4284 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4285 break;
4286 case OP_ANDNPS:
4287 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4288 break;
4289 case OP_ORPS:
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4291 break;
4292 case OP_XORPS:
4293 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4294 break;
4295 case OP_SQRTPS:
4296 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4297 break;
4298 case OP_RSQRTPS:
4299 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4300 break;
4301 case OP_RCPPS:
4302 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4303 break;
4304 case OP_ADDSUBPS:
4305 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4306 break;
4307 case OP_HADDPS:
4308 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4309 break;
4310 case OP_HSUBPS:
4311 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4312 break;
4313 case OP_DUPPS_HIGH:
4314 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4315 break;
4316 case OP_DUPPS_LOW:
4317 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4318 break;
4319
4320 case OP_PSHUFLEW_HIGH:
4321 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4322 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4323 break;
4324 case OP_PSHUFLEW_LOW:
4325 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4326 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4327 break;
4328 case OP_PSHUFLED:
4329 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4330 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4331 break;
4332 case OP_SHUFPS:
4333 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4334 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4335 break;
4336 case OP_SHUFPD:
4337 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4338 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4339 break;
4340
4341 case OP_ADDPD:
4342 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4343 break;
4344 case OP_DIVPD:
4345 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4346 break;
4347 case OP_MULPD:
4348 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4349 break;
4350 case OP_SUBPD:
4351 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4352 break;
4353 case OP_MAXPD:
4354 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4355 break;
4356 case OP_MINPD:
4357 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4358 break;
4359 case OP_COMPPD:
4360 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4361 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4362 break;
4363 case OP_ANDPD:
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4365 break;
4366 case OP_ANDNPD:
4367 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4368 break;
4369 case OP_ORPD:
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4371 break;
4372 case OP_XORPD:
4373 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4374 break;
4375 case OP_SQRTPD:
4376 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4377 break;
4378 case OP_ADDSUBPD:
4379 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4380 break;
4381 case OP_HADDPD:
4382 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4383 break;
4384 case OP_HSUBPD:
4385 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4386 break;
4387 case OP_DUPPD:
4388 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4389 break;
4390
4391 case OP_EXTRACT_MASK:
4392 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4393 break;
4394
4395 case OP_PAND:
4396 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4397 break;
4398 case OP_POR:
4399 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4400 break;
4401 case OP_PXOR:
4402 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4403 break;
4404
4405 case OP_PADDB:
4406 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4407 break;
4408 case OP_PADDW:
4409 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4410 break;
4411 case OP_PADDD:
4412 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4413 break;
4414 case OP_PADDQ:
4415 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4416 break;
4417
4418 case OP_PSUBB:
4419 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4420 break;
4421 case OP_PSUBW:
4422 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4423 break;
4424 case OP_PSUBD:
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4426 break;
4427 case OP_PSUBQ:
4428 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4429 break;
4430
4431 case OP_PMAXB_UN:
4432 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4433 break;
4434 case OP_PMAXW_UN:
4435 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4436 break;
4437 case OP_PMAXD_UN:
4438 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4439 break;
4440
4441 case OP_PMAXB:
4442 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4443 break;
4444 case OP_PMAXW:
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4446 break;
4447 case OP_PMAXD:
4448 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4449 break;
4450
4451 case OP_PAVGB_UN:
4452 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4453 break;
4454 case OP_PAVGW_UN:
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4456 break;
4457
4458 case OP_PMINB_UN:
4459 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4460 break;
4461 case OP_PMINW_UN:
4462 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4463 break;
4464 case OP_PMIND_UN:
4465 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4466 break;
4467
4468 case OP_PMINB:
4469 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4470 break;
4471 case OP_PMINW:
4472 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4473 break;
4474 case OP_PMIND:
4475 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4476 break;
4477
4478 case OP_PCMPEQB:
4479 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4480 break;
4481 case OP_PCMPEQW:
4482 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4483 break;
4484 case OP_PCMPEQD:
4485 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4486 break;
4487 case OP_PCMPEQQ:
4488 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4489 break;
4490
4491 case OP_PCMPGTB:
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4493 break;
4494 case OP_PCMPGTW:
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4496 break;
4497 case OP_PCMPGTD:
4498 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4499 break;
4500 case OP_PCMPGTQ:
4501 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4502 break;
4503
4504 case OP_PSUM_ABS_DIFF:
4505 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4506 break;
4507
4508 case OP_UNPACK_LOWB:
4509 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4510 break;
4511 case OP_UNPACK_LOWW:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4513 break;
4514 case OP_UNPACK_LOWD:
4515 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4516 break;
4517 case OP_UNPACK_LOWQ:
4518 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4519 break;
4520 case OP_UNPACK_LOWPS:
4521 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4522 break;
4523 case OP_UNPACK_LOWPD:
4524 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4525 break;
4526
4527 case OP_UNPACK_HIGHB:
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4529 break;
4530 case OP_UNPACK_HIGHW:
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4532 break;
4533 case OP_UNPACK_HIGHD:
4534 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4535 break;
4536 case OP_UNPACK_HIGHQ:
4537 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4538 break;
4539 case OP_UNPACK_HIGHPS:
4540 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4541 break;
4542 case OP_UNPACK_HIGHPD:
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4544 break;
4545
4546 case OP_PACKW:
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4548 break;
4549 case OP_PACKD:
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4551 break;
4552 case OP_PACKW_UN:
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4554 break;
4555 case OP_PACKD_UN:
4556 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4557 break;
4558
4559 case OP_PADDB_SAT_UN:
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4561 break;
4562 case OP_PSUBB_SAT_UN:
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4564 break;
4565 case OP_PADDW_SAT_UN:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4567 break;
4568 case OP_PSUBW_SAT_UN:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4570 break;
4571
4572 case OP_PADDB_SAT:
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4574 break;
4575 case OP_PSUBB_SAT:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4577 break;
4578 case OP_PADDW_SAT:
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4580 break;
4581 case OP_PSUBW_SAT:
4582 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4583 break;
4584
4585 case OP_PMULW:
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4587 break;
4588 case OP_PMULD:
4589 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4590 break;
4591 case OP_PMULQ:
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4593 break;
4594 case OP_PMULW_HIGH_UN:
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4596 break;
4597 case OP_PMULW_HIGH:
4598 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4599 break;
4600
4601 case OP_PSHRW:
4602 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4603 break;
4604 case OP_PSHRW_REG:
4605 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4606 break;
4607
4608 case OP_PSARW:
4609 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4610 break;
4611 case OP_PSARW_REG:
4612 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4613 break;
4614
4615 case OP_PSHLW:
4616 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4617 break;
4618 case OP_PSHLW_REG:
4619 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4620 break;
4621
4622 case OP_PSHRD:
4623 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4624 break;
4625 case OP_PSHRD_REG:
4626 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4627 break;
4628
4629 case OP_PSARD:
4630 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4631 break;
4632 case OP_PSARD_REG:
4633 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4634 break;
4635
4636 case OP_PSHLD:
4637 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4638 break;
4639 case OP_PSHLD_REG:
4640 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4641 break;
4642
4643 case OP_PSHRQ:
4644 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4645 break;
4646 case OP_PSHRQ_REG:
4647 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4648 break;
4649
4650 case OP_PSHLQ:
4651 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4652 break;
4653 case OP_PSHLQ_REG:
4654 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4655 break;
4656
4657 case OP_ICONV_TO_X:
4658 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4659 break;
4660 case OP_EXTRACT_I4:
4661 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4662 break;
4663 case OP_EXTRACT_I1:
4664 case OP_EXTRACT_U1:
4665 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4666 if (ins->inst_c0)
4667 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4668 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4669 break;
4670 case OP_EXTRACT_I2:
4671 case OP_EXTRACT_U2:
4672 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4673 if (ins->inst_c0)
4674 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4675 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4676 break;
4677 case OP_EXTRACT_R8:
4678 if (ins->inst_c0)
4679 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4680 else
4681 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4682 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4683 break;
4684
4685 case OP_INSERT_I2:
4686 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4687 break;
4688 case OP_EXTRACTX_U2:
4689 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4690 break;
4691 case OP_INSERTX_U1_SLOW:
4692 /*sreg1 is the extracted ireg (scratch)
4693 /sreg2 is the to be inserted ireg (scratch)
4694 /dreg is the xreg to receive the value*/
4695
4696 /*clear the bits from the extracted word*/
4697 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4698 /*shift the value to insert if needed*/
4699 if (ins->inst_c0 & 1)
4700 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4701 /*join them together*/
4702 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4704 break;
4705 case OP_INSERTX_I4_SLOW:
4706 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4707 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4708 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4709 break;
4710
4711 case OP_INSERTX_R4_SLOW:
4712 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4713 /*TODO if inst_c0 == 0 use movss*/
4714 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4715 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4716 break;
4717 case OP_INSERTX_R8_SLOW:
4718 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4719 if (cfg->verbose_level)
4720 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4721 if (ins->inst_c0)
4722 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4723 else
4724 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4725 break;
4726
4727 case OP_STOREX_MEMBASE_REG:
4728 case OP_STOREX_MEMBASE:
4729 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4730 break;
4731 case OP_LOADX_MEMBASE:
4732 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4733 break;
4734 case OP_LOADX_ALIGNED_MEMBASE:
4735 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4736 break;
4737 case OP_STOREX_ALIGNED_MEMBASE_REG:
4738 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4739 break;
4740 case OP_STOREX_NTA_MEMBASE_REG:
4741 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4742 break;
4743 case OP_PREFETCH_MEMBASE:
4744 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4745
4746 break;
4747 case OP_XMOVE:
4748 /*FIXME the peephole pass should have killed this*/
4749 if (ins->dreg != ins->sreg1)
4750 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4751 break;
4752 case OP_XZERO:
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4754 break;
4755 case OP_XONES:
4756 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4757 break;
4758
4759 case OP_FCONV_TO_R8_X:
4760 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4761 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4762 break;
4763
4764 case OP_XCONV_R8_TO_I4:
4765 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4766 switch (ins->backend.source_opcode) {
4767 case OP_FCONV_TO_I1:
4768 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4769 break;
4770 case OP_FCONV_TO_U1:
4771 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4772 break;
4773 case OP_FCONV_TO_I2:
4774 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4775 break;
4776 case OP_FCONV_TO_U2:
4777 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4778 break;
4779 }
4780 break;
4781
4782 case OP_EXPAND_I2:
4783 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4784 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4785 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4786 break;
4787 case OP_EXPAND_I4:
4788 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4789 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4790 break;
4791 case OP_EXPAND_R4:
4792 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4793 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4794 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4795 break;
4796 case OP_EXPAND_R8:
4797 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4798 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4799 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4800 break;
4801
4802 case OP_CVTDQ2PD:
4803 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4804 break;
4805 case OP_CVTDQ2PS:
4806 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4807 break;
4808 case OP_CVTPD2DQ:
4809 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4810 break;
4811 case OP_CVTPD2PS:
4812 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4813 break;
4814 case OP_CVTPS2DQ:
4815 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4816 break;
4817 case OP_CVTPS2PD:
4818 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4819 break;
4820 case OP_CVTTPD2DQ:
4821 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4822 break;
4823 case OP_CVTTPS2DQ:
4824 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4825 break;
4826
4827 #endif
4828 case OP_LIVERANGE_START: {
4829 if (cfg->verbose_level > 1)
4830 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4831 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4832 break;
4833 }
4834 case OP_LIVERANGE_END: {
4835 if (cfg->verbose_level > 1)
4836 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4837 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4838 break;
4839 }
4840 case OP_GC_SAFE_POINT: {
4841 guint8 *br [1];
4842
4843 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4844 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4845 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_threads_state_poll));
4846 x86_patch (br [0], code);
4847
4848 break;
4849 }
4850 case OP_GC_LIVENESS_DEF:
4851 case OP_GC_LIVENESS_USE:
4852 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4853 ins->backend.pc_offset = code - cfg->native_code;
4854 break;
4855 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4856 ins->backend.pc_offset = code - cfg->native_code;
4857 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4858 break;
4859 case OP_GET_SP:
4860 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
4861 break;
4862 case OP_SET_SP:
4863 x86_mov_reg_reg (code, X86_ESP, ins->sreg1);
4864 break;
4865 case OP_FILL_PROF_CALL_CTX:
4866 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (target_mgreg_t));
4867 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (target_mgreg_t));
4868 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (target_mgreg_t));
4869 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (target_mgreg_t));
4870 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (target_mgreg_t));
4871 break;
4872 case OP_GET_LAST_ERROR:
4873 code = emit_get_last_error (code, ins->dreg);
4874 break;
4875 default:
4876 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4877 g_assert_not_reached ();
4878 }
4879
4880 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4881 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4882 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4883 g_assert_not_reached ();
4884 }
4885
4886 cpos += max_len;
4887 }
4888
4889 set_code_cursor (cfg, code);
4890 }
4891
4892 #endif /* DISABLE_JIT */
4893
4894 void
4895 mono_arch_register_lowlevel_calls (void)
4896 {
4897 }
4898
4899 void
4900 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4901 {
4902 unsigned char *ip = ji->ip.i + code;
4903
4904 switch (ji->type) {
4905 case MONO_PATCH_INFO_IP:
4906 *((gconstpointer *)(ip)) = target;
4907 break;
4908 case MONO_PATCH_INFO_ABS:
4909 case MONO_PATCH_INFO_METHOD:
4910 case MONO_PATCH_INFO_METHOD_JUMP:
4911 case MONO_PATCH_INFO_JIT_ICALL_ID:
4912 case MONO_PATCH_INFO_BB:
4913 case MONO_PATCH_INFO_LABEL:
4914 case MONO_PATCH_INFO_RGCTX_FETCH:
4915 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4916 case MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR:
4917 x86_patch (ip, (unsigned char*)target);
4918 break;
4919 case MONO_PATCH_INFO_NONE:
4920 break;
4921 case MONO_PATCH_INFO_R4:
4922 case MONO_PATCH_INFO_R8: {
4923 guint32 offset = mono_arch_get_patch_offset (ip);
4924 *((gconstpointer *)(ip + offset)) = target;
4925 break;
4926 }
4927 default: {
4928 guint32 offset = mono_arch_get_patch_offset (ip);
4929 *((gconstpointer *)(ip + offset)) = target;
4930 break;
4931 }
4932 }
4933 }
4934
4935 static G_GNUC_UNUSED void
4936 stack_unaligned (MonoMethod *m, gpointer caller)
4937 {
4938 printf ("%s\n", mono_method_full_name (m, TRUE));
4939 g_assert_not_reached ();
4940 }
4941
4942 guint8 *
4943 mono_arch_emit_prolog (MonoCompile *cfg)
4944 {
4945 MonoMethod *method = cfg->method;
4946 MonoBasicBlock *bb;
4947 MonoMethodSignature *sig;
4948 MonoInst *inst;
4949 CallInfo *cinfo;
4950 ArgInfo *ainfo;
4951 int alloc_size, pos, max_offset, i, cfa_offset;
4952 guint8 *code;
4953 gboolean need_stack_frame;
4954
4955 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4956
4957 code = cfg->native_code = g_malloc (cfg->code_size);
4958
4959 #if 0
4960 {
4961 guint8 *br [16];
4962
4963 /* Check that the stack is aligned on osx */
4964 x86_mov_reg_reg (code, X86_EAX, X86_ESP);
4965 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
4966 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
4967 br [0] = code;
4968 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
4969 x86_push_membase (code, X86_ESP, 0);
4970 x86_push_imm (code, cfg->method);
4971 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
4972 x86_call_reg (code, X86_EAX);
4973 x86_patch (br [0], code);
4974 }
4975 #endif
4976
4977 /* Offset between RSP and the CFA */
4978 cfa_offset = 0;
4979
4980 // CFA = sp + 4
4981 cfa_offset = 4;
4982 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, cfa_offset);
4983 // IP saved at CFA - 4
4984 /* There is no IP reg on x86 */
4985 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4986 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4987
4988 need_stack_frame = needs_stack_frame (cfg);
4989
4990 if (need_stack_frame) {
4991 x86_push_reg (code, X86_EBP);
4992 cfa_offset += 4;
4993 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4994 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4995 x86_mov_reg_reg (code, X86_EBP, X86_ESP);
4996 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4997 /* These are handled automatically by the stack marking code */
4998 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4999 } else {
5000 cfg->frame_reg = X86_ESP;
5001 }
5002
5003 cfg->stack_offset += cfg->param_area;
5004 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5005
5006 alloc_size = cfg->stack_offset;
5007 pos = 0;
5008
5009 if (!method->save_lmf) {
5010 if (cfg->used_int_regs & (1 << X86_EBX)) {
5011 x86_push_reg (code, X86_EBX);
5012 pos += 4;
5013 cfa_offset += 4;
5014 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5015 /* These are handled automatically by the stack marking code */
5016 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5017 }
5018
5019 if (cfg->used_int_regs & (1 << X86_EDI)) {
5020 x86_push_reg (code, X86_EDI);
5021 pos += 4;
5022 cfa_offset += 4;
5023 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5024 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5025 }
5026
5027 if (cfg->used_int_regs & (1 << X86_ESI)) {
5028 x86_push_reg (code, X86_ESI);
5029 pos += 4;
5030 cfa_offset += 4;
5031 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5032 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5033 }
5034 }
5035
5036 alloc_size -= pos;
5037
5038 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5039 if (mono_do_x86_stack_align && need_stack_frame) {
5040 int tot = alloc_size + pos + 4; /* ret ip */
5041 if (need_stack_frame)
5042 tot += 4; /* ebp */
5043 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5044 if (tot) {
5045 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5046 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (target_mgreg_t))
5047 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5048 }
5049 }
5050
5051 cfg->arch.sp_fp_offset = alloc_size + pos;
5052
5053 if (alloc_size) {
5054 /* See mono_emit_stack_alloc */
5055 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5056 guint32 remaining_size = alloc_size;
5057 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5058 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5059 set_code_cursor (cfg, code);
5060 code = realloc_code (cfg, required_code_size);
5061 while (remaining_size >= 0x1000) {
5062 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5063 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5064 remaining_size -= 0x1000;
5065 }
5066 if (remaining_size)
5067 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5068 #else
5069 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5070 #endif
5071
5072 g_assert (need_stack_frame);
5073 }
5074
5075 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5076 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5077 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5078 }
5079
5080 #if DEBUG_STACK_ALIGNMENT
5081 /* check the stack is aligned */
5082 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5083 x86_mov_reg_reg (code, X86_ECX, X86_ESP);
5084 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5085 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5086 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5087 x86_breakpoint (code);
5088 }
5089 #endif
5090
5091 /* compute max_offset in order to use short forward jumps */
5092 max_offset = 0;
5093 if (cfg->opt & MONO_OPT_BRANCH) {
5094 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5095 MonoInst *ins;
5096 bb->max_offset = max_offset;
5097
5098 /* max alignment for loops */
5099 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5100 max_offset += LOOP_ALIGNMENT;
5101 MONO_BB_FOR_EACH_INS (bb, ins) {
5102 if (ins->opcode == OP_LABEL)
5103 ins->inst_c1 = max_offset;
5104 max_offset += ins_get_size (ins->opcode);
5105 }
5106 }
5107 }
5108
5109 /* store runtime generic context */
5110 if (cfg->rgctx_var) {
5111 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5112
5113 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5114 }
5115
5116 if (method->save_lmf)
5117 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5118
5119 {
5120 MonoInst *ins;
5121
5122 if (cfg->arch.ss_tramp_var) {
5123 /* Initialize ss_tramp_var */
5124 ins = cfg->arch.ss_tramp_var;
5125 g_assert (ins->opcode == OP_REGOFFSET);
5126
5127 g_assert (!cfg->compile_aot);
5128 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5129 }
5130
5131 if (cfg->arch.bp_tramp_var) {
5132 /* Initialize bp_tramp_var */
5133 ins = cfg->arch.bp_tramp_var;
5134 g_assert (ins->opcode == OP_REGOFFSET);
5135
5136 g_assert (!cfg->compile_aot);
5137 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5138 }
5139 }
5140
5141 /* load arguments allocated to register from the stack */
5142 sig = mono_method_signature_internal (method);
5143 pos = 0;
5144
5145 cinfo = cfg->arch.cinfo;
5146
5147 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5148 inst = cfg->args [pos];
5149 ainfo = &cinfo->args [pos];
5150 if (inst->opcode == OP_REGVAR) {
5151 if (storage_in_ireg (ainfo->storage)) {
5152 x86_mov_reg_reg (code, inst->dreg, ainfo->reg);
5153 } else {
5154 g_assert (need_stack_frame);
5155 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5156 }
5157 if (cfg->verbose_level > 2)
5158 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5159 } else {
5160 if (storage_in_ireg (ainfo->storage)) {
5161 x86_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, 4);
5162 }
5163 }
5164 pos++;
5165 }
5166
5167 set_code_cursor (cfg, code);
5168
5169 return code;
5170 }
5171
5172 void
5173 mono_arch_emit_epilog (MonoCompile *cfg)
5174 {
5175 MonoMethod *method = cfg->method;
5176 MonoMethodSignature *sig = mono_method_signature_internal (method);
5177 int i, quad, pos;
5178 guint32 stack_to_pop;
5179 guint8 *code;
5180 int max_epilog_size = 16;
5181 CallInfo *cinfo;
5182 gboolean need_stack_frame = needs_stack_frame (cfg);
5183
5184 if (cfg->method->save_lmf)
5185 max_epilog_size += 128;
5186
5187 code = realloc_code (cfg, max_epilog_size);
5188
5189 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5190 pos = 0;
5191
5192 if (method->save_lmf) {
5193 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5194
5195 /* restore caller saved regs */
5196 if (cfg->used_int_regs & (1 << X86_EBX)) {
5197 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5198 }
5199
5200 if (cfg->used_int_regs & (1 << X86_EDI)) {
5201 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5202 }
5203 if (cfg->used_int_regs & (1 << X86_ESI)) {
5204 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5205 }
5206
5207 /* EBP is restored by LEAVE */
5208 } else {
5209 for (i = 0; i < X86_NREG; ++i) {
5210 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5211 pos -= 4;
5212 }
5213 }
5214
5215 g_assert (!pos || need_stack_frame);
5216 if (pos) {
5217 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5218 }
5219
5220 if (cfg->used_int_regs & (1 << X86_ESI)) {
5221 x86_pop_reg (code, X86_ESI);
5222 }
5223 if (cfg->used_int_regs & (1 << X86_EDI)) {
5224 x86_pop_reg (code, X86_EDI);
5225 }
5226 if (cfg->used_int_regs & (1 << X86_EBX)) {
5227 x86_pop_reg (code, X86_EBX);
5228 }
5229 }
5230
5231 /* Load returned vtypes into registers if needed */
5232 cinfo = cfg->arch.cinfo;
5233 if (cinfo->ret.storage == ArgValuetypeInReg) {
5234 for (quad = 0; quad < 2; quad ++) {
5235 switch (cinfo->ret.pair_storage [quad]) {
5236 case ArgInIReg:
5237 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), 4);
5238 break;
5239 case ArgOnFloatFpStack:
5240 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), FALSE);
5241 break;
5242 case ArgOnDoubleFpStack:
5243 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), TRUE);
5244 break;
5245 case ArgNone:
5246 break;
5247 default:
5248 g_assert_not_reached ();
5249 }
5250 }
5251 }
5252
5253 if (need_stack_frame)
5254 x86_leave (code);
5255
5256 if (CALLCONV_IS_STDCALL (sig)) {
5257 MonoJitArgumentInfo *arg_info = g_newa (MonoJitArgumentInfo, sig->param_count + 1);
5258
5259 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5260 } else if (cinfo->callee_stack_pop)
5261 stack_to_pop = cinfo->callee_stack_pop;
5262 else
5263 stack_to_pop = 0;
5264
5265 if (stack_to_pop) {
5266 g_assert (need_stack_frame);
5267 x86_ret_imm (code, stack_to_pop);
5268 } else {
5269 x86_ret (code);
5270 }
5271
5272 set_code_cursor (cfg, code);
5273 }
5274
5275 void
5276 mono_arch_emit_exceptions (MonoCompile *cfg)
5277 {
5278 MonoJumpInfo *patch_info;
5279 int nthrows, i;
5280 guint8 *code;
5281 MonoClass *exc_classes [16];
5282 guint8 *exc_throw_start [16], *exc_throw_end [16];
5283 guint32 code_size;
5284 int exc_count = 0;
5285
5286 /* Compute needed space */
5287 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5288 if (patch_info->type == MONO_PATCH_INFO_EXC)
5289 exc_count++;
5290 }
5291
5292 /*
5293 * make sure we have enough space for exceptions
5294 * 16 is the size of two push_imm instructions and a call
5295 */
5296 if (cfg->compile_aot)
5297 code_size = exc_count * 32;
5298 else
5299 code_size = exc_count * 16;
5300
5301 code = realloc_code (cfg, code_size);
5302
5303 nthrows = 0;
5304 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5305 switch (patch_info->type) {
5306 case MONO_PATCH_INFO_EXC: {
5307 MonoClass *exc_class;
5308 guint8 *buf, *buf2;
5309 guint32 throw_ip;
5310
5311 x86_patch (patch_info->ip.i + cfg->native_code, code);
5312
5313 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5314 throw_ip = patch_info->ip.i;
5315
5316 /* Find a throw sequence for the same exception class */
5317 for (i = 0; i < nthrows; ++i)
5318 if (exc_classes [i] == exc_class)
5319 break;
5320 if (i < nthrows) {
5321 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5322 x86_jump_code (code, exc_throw_start [i]);
5323 patch_info->type = MONO_PATCH_INFO_NONE;
5324 }
5325 else {
5326 guint32 size;
5327
5328 /* Compute size of code following the push <OFFSET> */
5329 size = 5 + 5;
5330
5331 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5332
5333 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5334 /* Use the shorter form */
5335 buf = buf2 = code;
5336 x86_push_imm (code, 0);
5337 }
5338 else {
5339 buf = code;
5340 x86_push_imm (code, 0xf0f0f0f0);
5341 buf2 = code;
5342 }
5343
5344 if (nthrows < 16) {
5345 exc_classes [nthrows] = exc_class;
5346 exc_throw_start [nthrows] = code;
5347 }
5348
5349 x86_push_imm (code, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
5350 patch_info->data.jit_icall_id = MONO_JIT_ICALL_mono_arch_throw_corlib_exception;
5351 patch_info->type = MONO_PATCH_INFO_JIT_ICALL_ID;
5352 patch_info->ip.i = code - cfg->native_code;
5353 x86_call_code (code, 0);
5354 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5355 while (buf < buf2)
5356 x86_nop (buf);
5357
5358 if (nthrows < 16) {
5359 exc_throw_end [nthrows] = code;
5360 nthrows ++;
5361 }
5362 }
5363 break;
5364 }
5365 default:
5366 /* do nothing */
5367 break;
5368 }
5369 set_code_cursor (cfg, code);
5370 }
5371 set_code_cursor (cfg, code);
5372 }
5373
5374 MONO_NEVER_INLINE
5375 void
5376 mono_arch_flush_icache (guint8 *code, gint size)
5377 {
5378 /* call/ret required (or likely other control transfer) */
5379 }
5380
5381 void
5382 mono_arch_flush_register_windows (void)
5383 {
5384 }
5385
5386 gboolean
5387 mono_arch_is_inst_imm (int opcode, int imm_opcode, gint64 imm)
5388 {
5389 return TRUE;
5390 }
5391
5392 void
5393 mono_arch_finish_init (void)
5394 {
5395 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5396 if (!mono_no_tls) {
5397 #ifndef TARGET_WIN32
5398 #if MONO_XEN_OPT
5399 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5400 #endif
5401 #endif
5402 } else {
5403 g_free (mono_no_tls);
5404 }
5405 }
5406
5407 // Linear handler, the bsearch head compare is shorter
5408 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5409 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5410 // x86_patch(ins,target)
5411 //[1 + 5] x86_jump_mem(inst,mem)
5412
5413 #define CMP_SIZE 6
5414 #define BR_SMALL_SIZE 2
5415 #define BR_LARGE_SIZE 5
5416 #define JUMP_IMM_SIZE 6
5417 #define ENABLE_WRONG_METHOD_CHECK 0
5418 #define DEBUG_IMT 0
5419
5420 static int
5421 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5422 {
5423 int i, distance = 0;
5424 for (i = start; i < target; ++i)
5425 distance += imt_entries [i]->chunk_size;
5426 return distance;
5427 }
5428
5429 /*
5430 * LOCKING: called with the domain lock held
5431 */
5432 gpointer
5433 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5434 gpointer fail_tramp)
5435 {
5436 int i;
5437 int size = 0;
5438 guint8 *code, *start;
5439 GSList *unwind_ops;
5440
5441 for (i = 0; i < count; ++i) {
5442 MonoIMTCheckItem *item = imt_entries [i];
5443 if (item->is_equals) {
5444 if (item->check_target_idx) {
5445 if (!item->compare_done)
5446 item->chunk_size += CMP_SIZE;
5447 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5448 } else {
5449 if (fail_tramp) {
5450 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5451 } else {
5452 item->chunk_size += JUMP_IMM_SIZE;
5453 #if ENABLE_WRONG_METHOD_CHECK
5454 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5455 #endif
5456 }
5457 }
5458 } else {
5459 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5460 imt_entries [item->check_target_idx]->compare_done = TRUE;
5461 }
5462 size += item->chunk_size;
5463 }
5464 if (fail_tramp)
5465 code = (guint8*)mono_method_alloc_generic_virtual_trampoline (domain, size);
5466 else
5467 code = mono_domain_code_reserve (domain, size);
5468 start = code;
5469
5470 unwind_ops = mono_arch_get_cie_program ();
5471
5472 for (i = 0; i < count; ++i) {
5473 MonoIMTCheckItem *item = imt_entries [i];
5474 item->code_target = code;
5475 if (item->is_equals) {
5476 if (item->check_target_idx) {
5477 if (!item->compare_done)
5478 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5479 item->jmp_code = code;
5480 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5481 if (item->has_target_code)
5482 x86_jump_code (code, item->value.target_code);
5483 else
5484 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5485 } else {
5486 if (fail_tramp) {
5487 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5488 item->jmp_code = code;
5489 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5490 if (item->has_target_code)
5491 x86_jump_code (code, item->value.target_code);
5492 else
5493 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5494 x86_patch (item->jmp_code, code);
5495 x86_jump_code (code, fail_tramp);
5496 item->jmp_code = NULL;
5497 } else {
5498 /* enable the commented code to assert on wrong method */
5499 #if ENABLE_WRONG_METHOD_CHECK
5500 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5501 item->jmp_code = code;
5502 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5503 #endif
5504 if (item->has_target_code)
5505 x86_jump_code (code, item->value.target_code);
5506 else
5507 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5508 #if ENABLE_WRONG_METHOD_CHECK
5509 x86_patch (item->jmp_code, code);
5510 x86_breakpoint (code);
5511 item->jmp_code = NULL;
5512 #endif
5513 }
5514 }
5515 } else {
5516 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5517 item->jmp_code = code;
5518 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5519 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5520 else
5521 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5522 }
5523 }
5524 /* patch the branches to get to the target items */
5525 for (i = 0; i < count; ++i) {
5526 MonoIMTCheckItem *item = imt_entries [i];
5527 if (item->jmp_code) {
5528 if (item->check_target_idx) {
5529 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5530 }
5531 }
5532 }
5533
5534 if (!fail_tramp)
5535 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
5536 g_assert (code - start <= size);
5537
5538 #if DEBUG_IMT
5539 {
5540 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5541 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5542 g_free (buff);
5543 }
5544 #endif
5545 if (mono_jit_map_is_enabled ()) {
5546 char *buff;
5547 if (vtable)
5548 buff = g_strdup_printf ("imt_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5549 else
5550 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5551 mono_emit_jit_tramp (start, code - start, buff);
5552 g_free (buff);
5553 }
5554
5555 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5556
5557 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5558
5559 return start;
5560 }
5561
5562 MonoMethod*
5563 mono_arch_find_imt_method (host_mgreg_t *regs, guint8 *code)
5564 {
5565 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5566 }
5567
5568 MonoVTable*
5569 mono_arch_find_static_call_vtable (host_mgreg_t *regs, guint8 *code)
5570 {
5571 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5572 }
5573
5574 GSList*
5575 mono_arch_get_cie_program (void)
5576 {
5577 GSList *l = NULL;
5578
5579 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5580 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5581
5582 return l;
5583 }
5584
5585 MonoInst*
5586 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5587 {
5588 MonoInst *ins = NULL;
5589 int opcode = 0;
5590
5591 if (cmethod->klass == mono_class_try_get_math_class ()) {
5592 if (strcmp (cmethod->name, "Sin") == 0) {
5593 opcode = OP_SIN;
5594 } else if (strcmp (cmethod->name, "Cos") == 0) {
5595 opcode = OP_COS;
5596 } else if (strcmp (cmethod->name, "Tan") == 0) {
5597 opcode = OP_TAN;
5598 } else if (strcmp (cmethod->name, "Atan") == 0) {
5599 opcode = OP_ATAN;
5600 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5601 opcode = OP_SQRT;
5602 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5603 opcode = OP_ABS;
5604 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5605 opcode = OP_ROUND;
5606 }
5607
5608 if (opcode && fsig->param_count == 1) {
5609 MONO_INST_NEW (cfg, ins, opcode);
5610 ins->type = STACK_R8;
5611 ins->dreg = mono_alloc_freg (cfg);
5612 ins->sreg1 = args [0]->dreg;
5613 MONO_ADD_INS (cfg->cbb, ins);
5614 }
5615
5616 if (cfg->opt & MONO_OPT_CMOV) {
5617 opcode = 0;
5618
5619 if (strcmp (cmethod->name, "Min") == 0) {
5620 if (fsig->params [0]->type == MONO_TYPE_I4)
5621 opcode = OP_IMIN;
5622 } else if (strcmp (cmethod->name, "Max") == 0) {
5623 if (fsig->params [0]->type == MONO_TYPE_I4)
5624 opcode = OP_IMAX;
5625 }
5626
5627 if (opcode && fsig->param_count == 2) {
5628 MONO_INST_NEW (cfg, ins, opcode);
5629 ins->type = STACK_I4;
5630 ins->dreg = mono_alloc_ireg (cfg);
5631 ins->sreg1 = args [0]->dreg;
5632 ins->sreg2 = args [1]->dreg;
5633 MONO_ADD_INS (cfg->cbb, ins);
5634 }
5635 }
5636
5637 #if 0
5638 /* OP_FREM is not IEEE compatible */
5639 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5640 MONO_INST_NEW (cfg, ins, OP_FREM);
5641 ins->inst_i0 = args [0];
5642 ins->inst_i1 = args [1];
5643 }
5644 #endif
5645 }
5646
5647 return ins;
5648 }
5649
5650 guint32
5651 mono_arch_get_patch_offset (guint8 *code)
5652 {
5653 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5654 return 2;
5655 else if (code [0] == 0xba)
5656 return 1;
5657 else if (code [0] == 0x68)
5658 /* push IMM */
5659 return 1;
5660 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5661 /* push <OFFSET>(<REG>) */
5662 return 2;
5663 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5664 /* call *<OFFSET>(<REG>) */
5665 return 2;
5666 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5667 /* fldl <ADDR> */
5668 return 2;
5669 else if ((code [0] == 0x58) && (code [1] == 0x05))
5670 /* pop %eax; add <OFFSET>, %eax */
5671 return 2;
5672 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5673 /* pop <REG>; add <OFFSET>, <REG> */
5674 return 3;
5675 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5676 /* mov <REG>, imm */
5677 return 1;
5678 else if (code [0] == 0xE9)
5679 /* jmp eip+32b */
5680 return 1;
5681 g_assert_not_reached ();
5682 return -1;
5683 }
5684
5685 /**
5686 * \return TRUE if no sw breakpoint was present.
5687 *
5688 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5689 * breakpoints in the original code, they are removed in the copy.
5690 */
5691 gboolean
5692 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5693 {
5694 /*
5695 * If method_start is non-NULL we need to perform bound checks, since we access memory
5696 * at code - offset we could go before the start of the method and end up in a different
5697 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5698 * instead.
5699 */
5700 if (!method_start || code - offset >= method_start) {
5701 memcpy (buf, code - offset, size);
5702 } else {
5703 int diff = code - method_start;
5704 memset (buf, 0, size);
5705 memcpy (buf + offset - diff, method_start, diff + size - offset);
5706 }
5707 return TRUE;
5708 }
5709
5710 /*
5711 * mono_x86_get_this_arg_offset:
5712 *
5713 * Return the offset of the stack location where this is passed during a virtual
5714 * call.
5715 */
5716 guint32
5717 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5718 {
5719 return 0;
5720 }
5721
5722 gpointer
5723 mono_arch_get_this_arg_from_call (host_mgreg_t *regs, guint8 *code)
5724 {
5725 host_mgreg_t esp = regs [X86_ESP];
5726 gpointer res;
5727 int offset;
5728
5729 offset = 0;
5730
5731 /*
5732 * The stack looks like:
5733 * <other args>
5734 * <this=delegate>
5735 */
5736 res = ((MonoObject**)esp) [0];
5737 return res;
5738 }
5739
5740 #define MAX_ARCH_DELEGATE_PARAMS 10
5741
5742 static gpointer
5743 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5744 {
5745 guint8 *code, *start;
5746 int code_reserve = 64;
5747 GSList *unwind_ops;
5748
5749 unwind_ops = mono_arch_get_cie_program ();
5750
5751 /*
5752 * The stack contains:
5753 * <delegate>
5754 * <return addr>
5755 */
5756
5757 if (has_target) {
5758 start = code = mono_global_codeman_reserve (code_reserve);
5759
5760 /* Replace the this argument with the target */
5761 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5762 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5763 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5764 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5765
5766 g_assert ((code - start) < code_reserve);
5767 } else {
5768 int i = 0;
5769 /* 8 for mov_reg and jump, plus 8 for each parameter */
5770 code_reserve = 8 + (param_count * 8);
5771 /*
5772 * The stack contains:
5773 * <args in reverse order>
5774 * <delegate>
5775 * <return addr>
5776 *
5777 * and we need:
5778 * <args in reverse order>
5779 * <return addr>
5780 *
5781 * without unbalancing the stack.
5782 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5783 * and leaving original spot of first arg as placeholder in stack so
5784 * when callee pops stack everything works.
5785 */
5786
5787 start = code = mono_global_codeman_reserve (code_reserve);
5788
5789 /* store delegate for access to method_ptr */
5790 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5791
5792 /* move args up */
5793 for (i = 0; i < param_count; ++i) {
5794 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5795 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5796 }
5797
5798 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5799
5800 g_assert ((code - start) < code_reserve);
5801 }
5802
5803 if (has_target) {
5804 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5805 } else {
5806 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5807 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5808 g_free (name);
5809 }
5810
5811 if (mono_jit_map_is_enabled ()) {
5812 char *buff;
5813 if (has_target)
5814 buff = (char*)"delegate_invoke_has_target";
5815 else
5816 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5817 mono_emit_jit_tramp (start, code - start, buff);
5818 if (!has_target)
5819 g_free (buff);
5820 }
5821 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5822
5823 return start;
5824 }
5825
5826 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5827
5828 static gpointer
5829 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5830 {
5831 guint8 *code, *start;
5832 int size = 24;
5833 char *tramp_name;
5834 GSList *unwind_ops;
5835
5836 if (offset / (int)sizeof (target_mgreg_t) > MAX_VIRTUAL_DELEGATE_OFFSET)
5837 return NULL;
5838
5839 /*
5840 * The stack contains:
5841 * <delegate>
5842 * <return addr>
5843 */
5844 start = code = mono_global_codeman_reserve (size);
5845
5846 unwind_ops = mono_arch_get_cie_program ();
5847
5848 /* Replace the this argument with the target */
5849 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5850 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5851 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5852
5853 if (load_imt_reg) {
5854 /* Load the IMT reg */
5855 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5856 }
5857
5858 /* Load the vtable */
5859 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5860 x86_jump_membase (code, X86_EAX, offset);
5861 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5862
5863 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5864 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5865 g_free (tramp_name);
5866
5867
5868 return start;
5869 }
5870
5871 GSList*
5872 mono_arch_get_delegate_invoke_impls (void)
5873 {
5874 GSList *res = NULL;
5875 MonoTrampInfo *info;
5876 int i;
5877
5878 get_delegate_invoke_impl (&info, TRUE, 0);
5879 res = g_slist_prepend (res, info);
5880
5881 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5882 get_delegate_invoke_impl (&info, FALSE, i);
5883 res = g_slist_prepend (res, info);
5884 }
5885
5886 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5887 get_delegate_virtual_invoke_impl (&info, TRUE, - i * TARGET_SIZEOF_VOID_P);
5888 res = g_slist_prepend (res, info);
5889
5890 get_delegate_virtual_invoke_impl (&info, FALSE, i * TARGET_SIZEOF_VOID_P);
5891 res = g_slist_prepend (res, info);
5892 }
5893
5894 return res;
5895 }
5896
5897 gpointer
5898 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5899 {
5900 guint8 *code, *start;
5901
5902 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5903 return NULL;
5904
5905 /* FIXME: Support more cases */
5906 if (MONO_TYPE_ISSTRUCT (sig->ret))
5907 return NULL;
5908
5909 /*
5910 * The stack contains:
5911 * <delegate>
5912 * <return addr>
5913 */
5914
5915 if (has_target) {
5916 static guint8* cached = NULL;
5917 if (cached)
5918 return cached;
5919
5920 if (mono_ee_features.use_aot_trampolines) {
5921 start = (guint8*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
5922 } else {
5923 MonoTrampInfo *info;
5924 start = (guint8*)get_delegate_invoke_impl (&info, TRUE, 0);
5925 mono_tramp_info_register (info, NULL);
5926 }
5927
5928 mono_memory_barrier ();
5929
5930 cached = start;
5931 } else {
5932 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5933 int i = 0;
5934
5935 for (i = 0; i < sig->param_count; ++i)
5936 if (!mono_is_regsize_var (sig->params [i]))
5937 return NULL;
5938
5939 code = cache [sig->param_count];
5940 if (code)
5941 return code;
5942
5943 if (mono_ee_features.use_aot_trampolines) {
5944 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5945 start = (guint8*)mono_aot_get_trampoline (name);
5946 g_free (name);
5947 } else {
5948 MonoTrampInfo *info;
5949 start = (guint8*)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
5950 mono_tramp_info_register (info, NULL);
5951 }
5952
5953 mono_memory_barrier ();
5954
5955 cache [sig->param_count] = start;
5956 }
5957
5958 return start;
5959 }
5960
5961 gpointer
5962 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
5963 {
5964 MonoTrampInfo *info;
5965 gpointer code;
5966
5967 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
5968 if (code)
5969 mono_tramp_info_register (info, NULL);
5970 return code;
5971 }
5972
5973 host_mgreg_t
5974 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5975 {
5976 switch (reg) {
5977 case X86_EAX: return ctx->eax;
5978 case X86_EBX: return ctx->ebx;
5979 case X86_ECX: return ctx->ecx;
5980 case X86_EDX: return ctx->edx;
5981 case X86_ESP: return ctx->esp;
5982 case X86_EBP: return ctx->ebp;
5983 case X86_ESI: return ctx->esi;
5984 case X86_EDI: return ctx->edi;
5985 default:
5986 g_assert_not_reached ();
5987 return 0;
5988 }
5989 }
5990
5991 void
5992 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, host_mgreg_t val)
5993 {
5994 switch (reg) {
5995 case X86_EAX:
5996 ctx->eax = val;
5997 break;
5998 case X86_EBX:
5999 ctx->ebx = val;
6000 break;
6001 case X86_ECX:
6002 ctx->ecx = val;
6003 break;
6004 case X86_EDX:
6005 ctx->edx = val;
6006 break;
6007 case X86_ESP:
6008 ctx->esp = val;
6009 break;
6010 case X86_EBP:
6011 ctx->ebp = val;
6012 break;
6013 case X86_ESI:
6014 ctx->esi = val;
6015 break;
6016 case X86_EDI:
6017 ctx->edi = val;
6018 break;
6019 default:
6020 g_assert_not_reached ();
6021 }
6022 }
6023
6024 #ifdef MONO_ARCH_SIMD_INTRINSICS
6025
6026 static MonoInst*
6027 get_float_to_x_spill_area (MonoCompile *cfg)
6028 {
6029 if (!cfg->fconv_to_r8_x_var) {
6030 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
6031 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6032 }
6033 return cfg->fconv_to_r8_x_var;
6034 }
6035
6036 /*
6037 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6038 */
6039 void
6040 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6041 {
6042 MonoInst *fconv;
6043 int dreg, src_opcode;
6044
6045 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6046 return;
6047
6048 switch (src_opcode = ins->opcode) {
6049 case OP_FCONV_TO_I1:
6050 case OP_FCONV_TO_U1:
6051 case OP_FCONV_TO_I2:
6052 case OP_FCONV_TO_U2:
6053 case OP_FCONV_TO_I4:
6054 case OP_FCONV_TO_I:
6055 break;
6056 default:
6057 return;
6058 }
6059
6060 /* dreg is the IREG and sreg1 is the FREG */
6061 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6062 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6063 fconv->sreg1 = ins->sreg1;
6064 fconv->dreg = mono_alloc_ireg (cfg);
6065 fconv->type = STACK_VTYPE;
6066 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6067
6068 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6069
6070 dreg = ins->dreg;
6071 NULLIFY_INS (ins);
6072 ins->opcode = OP_XCONV_R8_TO_I4;
6073
6074 ins->klass = mono_defaults.int32_class;
6075 ins->sreg1 = fconv->dreg;
6076 ins->dreg = dreg;
6077 ins->type = STACK_I4;
6078 ins->backend.source_opcode = src_opcode;
6079 }
6080
6081 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6082
6083 void
6084 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6085 {
6086 MonoInst *ins;
6087 int vreg;
6088
6089 if (long_ins->opcode == OP_LNEG) {
6090 ins = long_ins;
6091 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6092 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6093 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6094 NULLIFY_INS (ins);
6095 return;
6096 }
6097
6098 #ifdef MONO_ARCH_SIMD_INTRINSICS
6099
6100 if (!(cfg->opt & MONO_OPT_SIMD))
6101 return;
6102
6103 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6104 switch (long_ins->opcode) {
6105 case OP_EXTRACT_I8:
6106 vreg = long_ins->sreg1;
6107
6108 if (long_ins->inst_c0) {
6109 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6110 ins->klass = long_ins->klass;
6111 ins->sreg1 = long_ins->sreg1;
6112 ins->inst_c0 = 2;
6113 ins->type = STACK_VTYPE;
6114 ins->dreg = vreg = alloc_ireg (cfg);
6115 MONO_ADD_INS (cfg->cbb, ins);
6116 }
6117
6118 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6119 ins->klass = mono_defaults.int32_class;
6120 ins->sreg1 = vreg;
6121 ins->type = STACK_I4;
6122 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6123 MONO_ADD_INS (cfg->cbb, ins);
6124
6125 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6126 ins->klass = long_ins->klass;
6127 ins->sreg1 = long_ins->sreg1;
6128 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6129 ins->type = STACK_VTYPE;
6130 ins->dreg = vreg = alloc_ireg (cfg);
6131 MONO_ADD_INS (cfg->cbb, ins);
6132
6133 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6134 ins->klass = mono_defaults.int32_class;
6135 ins->sreg1 = vreg;
6136 ins->type = STACK_I4;
6137 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6138 MONO_ADD_INS (cfg->cbb, ins);
6139
6140 long_ins->opcode = OP_NOP;
6141 break;
6142 case OP_INSERTX_I8_SLOW:
6143 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6144 ins->dreg = long_ins->dreg;
6145 ins->sreg1 = long_ins->dreg;
6146 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6147 ins->inst_c0 = long_ins->inst_c0 * 2;
6148 MONO_ADD_INS (cfg->cbb, ins);
6149
6150 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6151 ins->dreg = long_ins->dreg;
6152 ins->sreg1 = long_ins->dreg;
6153 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6154 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6155 MONO_ADD_INS (cfg->cbb, ins);
6156
6157 long_ins->opcode = OP_NOP;
6158 break;
6159 case OP_EXPAND_I8:
6160 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6161 ins->dreg = long_ins->dreg;
6162 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6163 ins->klass = long_ins->klass;
6164 ins->type = STACK_VTYPE;
6165 MONO_ADD_INS (cfg->cbb, ins);
6166
6167 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6168 ins->dreg = long_ins->dreg;
6169 ins->sreg1 = long_ins->dreg;
6170 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6171 ins->inst_c0 = 1;
6172 ins->klass = long_ins->klass;
6173 ins->type = STACK_VTYPE;
6174 MONO_ADD_INS (cfg->cbb, ins);
6175
6176 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6177 ins->dreg = long_ins->dreg;
6178 ins->sreg1 = long_ins->dreg;
6179 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6180 ins->klass = long_ins->klass;
6181 ins->type = STACK_VTYPE;
6182 MONO_ADD_INS (cfg->cbb, ins);
6183
6184 long_ins->opcode = OP_NOP;
6185 break;
6186 }
6187 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6188 }
6189
6190 /*
6191 * mono_aot_emit_load_got_addr:
6192 *
6193 * Emit code to load the got address.
6194 * On x86, the result is placed into EBX.
6195 */
6196 guint8*
6197 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6198 {
6199 x86_call_imm (code, 0);
6200 /*
6201 * The patch needs to point to the pop, since the GOT offset needs
6202 * to be added to that address.
6203 */
6204 if (cfg)
6205 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6206 else
6207 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6208 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6209 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6210
6211 set_code_cursor (cfg, code);
6212 return code;
6213 }
6214
6215 /*
6216 * mono_arch_emit_load_aotconst:
6217 *
6218 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6219 * TARGET from the mscorlib GOT in full-aot code.
6220 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6221 * EAX.
6222 */
6223 guint8*
6224 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6225 {
6226 /* Load the mscorlib got address */
6227 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (target_mgreg_t), 4);
6228 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6229 /* arch_emit_got_access () patches this */
6230 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6231
6232 return code;
6233 }
6234
6235 /* Can't put this into mini-x86.h */
6236 gpointer
6237 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6238
6239 GSList *
6240 mono_arch_get_trampolines (gboolean aot)
6241 {
6242 MonoTrampInfo *info;
6243 GSList *tramps = NULL;
6244
6245 mono_x86_get_signal_exception_trampoline (&info, aot);
6246
6247 tramps = g_slist_append (tramps, info);
6248
6249 return tramps;
6250 }
6251
6252 /* Soft Debug support */
6253 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6254
6255 /*
6256 * mono_arch_set_breakpoint:
6257 *
6258 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6259 * The location should contain code emitted by OP_SEQ_POINT.
6260 */
6261 void
6262 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6263 {
6264 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6265
6266 g_assert (code [0] == 0x90);
6267 x86_call_membase (code, X86_ECX, 0);
6268 }
6269
6270 /*
6271 * mono_arch_clear_breakpoint:
6272 *
6273 * Clear the breakpoint at IP.
6274 */
6275 void
6276 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6277 {
6278 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6279 int i;
6280
6281 for (i = 0; i < 2; ++i)
6282 x86_nop (code);
6283 }
6284
6285 /*
6286 * mono_arch_start_single_stepping:
6287 *
6288 * Start single stepping.
6289 */
6290 void
6291 mono_arch_start_single_stepping (void)
6292 {
6293 ss_trampoline = mini_get_single_step_trampoline ();
6294 }
6295
6296 /*
6297 * mono_arch_stop_single_stepping:
6298 *
6299 * Stop single stepping.
6300 */
6301 void
6302 mono_arch_stop_single_stepping (void)
6303 {
6304 ss_trampoline = NULL;
6305 }
6306
6307 /*
6308 * mono_arch_is_single_step_event:
6309 *
6310 * Return whenever the machine state in SIGCTX corresponds to a single
6311 * step event.
6312 */
6313 gboolean
6314 mono_arch_is_single_step_event (void *info, void *sigctx)
6315 {
6316 /* We use soft breakpoints */
6317 return FALSE;
6318 }
6319
6320 gboolean
6321 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6322 {
6323 /* We use soft breakpoints */
6324 return FALSE;
6325 }
6326
6327 #define BREAKPOINT_SIZE 2
6328
6329 /*
6330 * mono_arch_skip_breakpoint:
6331 *
6332 * See mini-amd64.c for docs.
6333 */
6334 void
6335 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6336 {
6337 g_assert_not_reached ();
6338 }
6339
6340 /*
6341 * mono_arch_skip_single_step:
6342 *
6343 * See mini-amd64.c for docs.
6344 */
6345 void
6346 mono_arch_skip_single_step (MonoContext *ctx)
6347 {
6348 g_assert_not_reached ();
6349 }
6350
6351 /*
6352 * mono_arch_get_seq_point_info:
6353 *
6354 * See mini-amd64.c for docs.
6355 */
6356 SeqPointInfo*
6357 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6358 {
6359 NOT_IMPLEMENTED;
6360 return NULL;
6361 }
6362
6363 #endif
6364
6365 gboolean
6366 mono_arch_opcode_supported (int opcode)
6367 {
6368 switch (opcode) {
6369 case OP_ATOMIC_ADD_I4:
6370 case OP_ATOMIC_EXCHANGE_I4:
6371 case OP_ATOMIC_CAS_I4:
6372 case OP_ATOMIC_LOAD_I1:
6373 case OP_ATOMIC_LOAD_I2:
6374 case OP_ATOMIC_LOAD_I4:
6375 case OP_ATOMIC_LOAD_U1:
6376 case OP_ATOMIC_LOAD_U2:
6377 case OP_ATOMIC_LOAD_U4:
6378 case OP_ATOMIC_LOAD_R4:
6379 case OP_ATOMIC_LOAD_R8:
6380 case OP_ATOMIC_STORE_I1:
6381 case OP_ATOMIC_STORE_I2:
6382 case OP_ATOMIC_STORE_I4:
6383 case OP_ATOMIC_STORE_U1:
6384 case OP_ATOMIC_STORE_U2:
6385 case OP_ATOMIC_STORE_U4:
6386 case OP_ATOMIC_STORE_R4:
6387 case OP_ATOMIC_STORE_R8:
6388 return TRUE;
6389 default:
6390 return FALSE;
6391 }
6392 }
6393
6394 CallInfo*
6395 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6396 {
6397 return get_call_info (mp, sig);
6398 }
6399
6400 gpointer
6401 mono_arch_load_function (MonoJitICallId jit_icall_id)
6402 {
6403 gpointer target = NULL;
6404 switch (jit_icall_id) {
6405 #undef MONO_AOT_ICALL
6406 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
6407 MONO_AOT_ICALL (mono_x86_start_gsharedvt_call)
6408 MONO_AOT_ICALL (mono_x86_throw_corlib_exception)
6409 MONO_AOT_ICALL (mono_x86_throw_exception)
6410 }
6411 return target;
6412 }
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