| blob | d37ad6818bfb9c856f29c738c29a8798ddd71fe7 |
1 /*
2 * mini-amd64.c: AMD64 backend for the Mono code generator
3 *
4 * Based on mini-x86.c.
5 *
6 * Authors:
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
9 * Patrik Torstensson
10 * Zoltan Varga (vargaz@gmail.com)
11 *
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 */
17 #include <string.h>
18 #include <math.h>
19 #ifdef HAVE_UNISTD_H
20 #include <unistd.h>
21 #endif
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internals.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
44 #ifdef MONO_XEN_OPT
46 #else
47 #define optimize_for_xen 0
48 #endif
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
56 #ifdef TARGET_WIN32
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #else
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
61 #endif
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
68 /* The single step trampoline */
71 /* The breakpoint trampoline */
74 /* Offset between fp and the first argument in the callee */
75 #define ARGS_OFFSET 16
76 #define GP_SCRATCH_REG AMD64_R11
78 /*
79 * AMD64 register usage:
80 * - callee saved registers are used for global register allocation
81 * - %r11 is used for materializing 64 bit constants in opcodes
82 * - the rest is used for local allocation
83 */
85 /*
86 * Floating point comparison results:
87 * ZF PF CF
88 * A > B 0 0 0
89 * A < B 0 0 1
90 * A = B 1 0 0
91 * A > B 0 0 0
92 * UNORDERED 1 1 1
93 */
97 {
115 }
117 }
122 };
127 };
131 {
134 else
136 }
140 {
143 else
145 }
147 static gboolean
149 {
150 #if 0
152 #else
154 #endif
155 }
159 {
160 /* Skip REX */
165 }
169 {
174 }
176 #ifdef __native_client_codegen__
178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
179 /* for any given instruction. For instance, amd64_call_reg resolves to */
180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
181 /* We only want to force bundle alignment for the top level instruction, */
182 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
188 void
190 {
192 }
194 void
196 {
199 }
201 void
203 {
205 }
207 guint8*
209 {
211 }
213 guint8*
215 {
217 }
219 /* Increment the instruction "depth" described above */
220 void
222 {
224 depth++;
226 }
228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
229 /* alignment if depth == 0 (top level instruction) */
230 /* IN: start, end pointers to instruction beginning and end */
231 /* OUT: start, end pointers to beginning and end after possible alignment */
232 /* GLOBALS: nacl_instruction_depth defined above */
233 void
235 {
237 depth--;
245 /* if legacy prefix is present, and if it was emitted before */
246 /* the start of the instruction sequence, adjust the start */
250 }
253 /* Only check for instructions which are less than */
254 /* kNaClAlignment. The only instructions that should ever */
255 /* be that long are call sequences, which are already */
256 /* padded out to align the return to the next bundle. */
267 }
270 }
271 }
273 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
274 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
275 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
276 /* make sure the upper 32-bits are cleared, and use that register in the */
277 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
278 /* IN: code */
279 /* pointer to current instruction stream (in the */
280 /* middle of an instruction, after opcode is emitted) */
281 /* basereg/offset/dreg */
282 /* operands of normal membase address */
283 /* OUT: code */
284 /* pointer to the end of the membase/memindex emit */
285 /* GLOBALS: nacl_rex_tag */
286 /* position in instruction stream that rex prefix was emitted */
287 /* nacl_legacy_prefix_tag */
288 /* (possibly NULL) position in instruction of legacy x86 prefix */
289 void
291 {
294 /* Cache these values, they might change */
295 /* as new instructions are emitted below. */
299 /* 'basereg' is given masked to 0x7 at this point, so check */
300 /* the rex prefix to see if this is an extended register. */
303 }
305 #define X86_LEA_OPCODE (0x8D)
310 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
311 /* 32-bits of the old base register (new index register) */
319 /* The old rex.B should be the new rex.X */
322 }
323 /* Since our new base is %r15 set rex.B */
326 /* Shift the instruction by one byte */
327 /* so we can insert a rex prefix */
330 /* New rex prefix only needs rex.B for %r15 base */
332 }
338 }
340 /* Clears the upper 32-bits of the previous base register */
344 /* Move the old instruction forward to make */
345 /* room for 'mov' stored in 'buf_ptr' */
346 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
350 /* Sandboxed replacement for the normal membase_emit */
354 /* Normal default behavior, emit membase memory location */
356 }
357 }
362 {
363 guint8 in_nop;
369 }
373 }
378 }
383 }
389 }
395 }
402 }
409 }
412 }
414 guint8*
416 {
418 }
422 static void
424 {
427 #ifdef __native_client_codegen__
429 #endif
430 #if defined(__native_client_codegen__) && defined(__native_client__)
432 /* For tail calls, code is patched after being installed */
433 /* but not through the normal "patch callsite" method. */
438 /* Patch a temp buffer of bundle size, */
439 /* then install to actual location. */
444 }
446 #endif
448 /* Skip REX */
452 }
455 /* amd64_set_reg_template */
457 }
458 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
459 /* mov 0(%rip), %dreg */
461 }
463 /* call *<OFFSET>(%rip) */
465 }
467 /* call <DISP> */
471 }
472 else
474 }
476 void
478 {
480 }
483 ArgInIReg,
484 ArgInFloatSSEReg,
485 ArgInDoubleSSEReg,
486 ArgOnStack,
487 ArgValuetypeInReg,
488 ArgValuetypeAddrInIReg,
489 /* gsharedvt argument passed by addr */
490 ArgGSharedVtInReg,
491 ArgGSharedVtOnStack,
492 ArgNone /* only in pair_storage */
496 gint16 offset;
497 gint8 reg;
501 /* Only if storage == ArgValuetypeInReg */
504 /* The size of each pair */
507 /* Only if storage == ArgOnStack */
513 guint32 stack_usage;
514 guint32 reg_usage;
515 guint32 freg_usage;
516 gboolean need_stack_align;
517 /* The index of the vret arg in the argument list */
519 ArgInfo ret;
520 ArgInfo sig_cookie;
524 #define DEBUG(a) if (cfg->verbose_level > 1) a
526 #ifdef TARGET_WIN32
530 #else
531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
534 #endif
538 {
544 /* Since the same stack slot size is used for all arg */
545 /* types, it needs to be big enough to hold them all */
547 }
552 }
553 }
555 #ifdef TARGET_WIN32
556 #define FLOAT_PARAM_REGS 4
557 #else
558 #define FLOAT_PARAM_REGS 8
559 #endif
563 {
569 /* Since the same stack slot size is used for both float */
570 /* types, it needs to be big enough to hold them both */
572 }
574 /* A double register */
577 else
581 }
582 }
585 ARG_CLASS_NO_CLASS,
586 ARG_CLASS_MEMORY,
587 ARG_CLASS_INTEGER,
588 ARG_CLASS_SSE
591 static ArgumentClass
593 {
620 #ifdef TARGET_WIN32
622 #else
624 #endif
634 }
635 /* fall through */
643 }
645 }
648 }
650 /* Merge */
652 ;
659 else
663 }
664 #ifdef __native_client_codegen__
666 /* Default alignment for Native Client is 32-byte. */
669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
670 /* Check that alignment doesn't cross an alignment boundary. */
671 guint8*
673 {
677 /* assertion: alignment cannot cross a block boundary */
683 }
686 }
687 #endif
689 static int
691 {
701 else
702 count ++;
703 }
705 }
707 static int
709 {
717 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
721 index ++;
722 }
723 }
725 }
727 #ifdef TARGET_WIN32
728 static void
730 gboolean is_return,
732 {
735 ArgumentClass arg_class;
746 /* If this struct can't be split up naturally into 8-byte */
747 /* chunks (registers), pass it on the stack. */
749 guint32 align;
750 guint32 field_size;
755 /*
756 * Collect field information recursively to be able to
757 * handle nested structures.
758 */
770 }
771 }
772 }
775 /* Allways pass in memory */
784 }
793 else
794 /* Always pass in 1 integer register */
803 }
813 }
821 }
827 }
828 }
832 }
835 guint32 align;
836 ArgumentClass class1;
840 else
846 /* How far into this quad this data extends.*/
847 /* (8 is size of quad) */
851 }
854 }
858 /* Allocate registers */
859 {
864 argsize ++;
879 else
882 }
890 else
894 }
900 }
903 /* Revert possible register assignments */
912 }
913 }
914 }
917 static void
919 gboolean is_return,
921 {
922 #ifdef TARGET_WIN32
924 #else
926 /* Keep track of the size used in each quad so we can */
927 /* use the right size when copying args/return vars. */
938 /* We pass and return vtypes of size 8 in a register */
941 }
943 /* If this struct can't be split up naturally into 8-byte */
944 /* chunks (registers), pass it on the stack. */
946 guint32 align;
947 guint32 field_size;
952 /*
953 * Collect field information recursively to be able to
954 * handle nested structures.
955 */
967 }
968 }
969 }
975 }
978 /* Allways pass in memory */
987 }
991 else
1000 /* Always pass in 1 or 2 integer registers */
1003 /* Only the simplest cases are supported */
1007 }
1009 /*
1010 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
1011 * The X87 and SSEUP stuff is left out since there are no such types in
1012 * the CLR.
1013 */
1020 }
1031 }
1037 guint32 align;
1038 ArgumentClass class1;
1042 else
1049 /* Unaligned field */
1050 NOT_IMPLEMENTED;
1051 }
1053 /* Skip fields in other quad */
1059 /* How far into this quad this data extends.*/
1060 /* (8 is size of quad) */
1064 }
1067 }
1068 }
1072 /* Post merger cleanup */
1076 /* Allocate registers */
1077 {
1083 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1102 else
1105 }
1116 }
1122 }
1123 }
1127 /* Revert possible register assignments */
1134 else
1140 }
1141 }
1143 }
1145 /*
1146 * get_call_info:
1147 *
1148 * Obtain information about a call according to the calling convention.
1149 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1150 * Draft Version 0.23" document for more information.
1151 */
1154 {
1164 else
1172 #ifdef TARGET_WIN32
1173 /* Reserve space where the callee can save the argument registers */
1175 #endif
1177 /* return value */
1216 }
1221 }
1222 /* fall through */
1230 }
1241 }
1244 /*
1245 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1246 * the first argument, allowing 'this' to be always passed in the first arg reg.
1247 * Also do this if the first argument is a reference type, since virtual calls
1248 * are sometimes made using calli without sig->hasthis set, like in the delegate
1249 * invoke wrappers.
1250 */
1251 if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1257 }
1262 /* this */
1269 }
1270 }
1276 /* Emit the signature cookie just before the implicit arguments */
1278 }
1284 #ifdef TARGET_WIN32
1285 /* The float param registers and other param registers must be the same index on Windows x64.*/
1290 #endif
1293 /* We allways pass the sig cookie on the stack for simplicity */
1294 /*
1295 * Prevent implicit arguments + the sig cookie from being passed
1296 * in registers.
1297 */
1301 /* Emit the signature cookie just before the implicit arguments */
1303 }
1334 }
1336 /* gsharedvt arguments are passed by ref */
1340 else
1343 }
1344 /* fall through */
1362 /* gsharedvt arguments are passed by ref */
1367 else
1372 }
1373 }
1375 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1379 /* Emit the signature cookie just before the implicit arguments */
1381 }
1387 }
1389 /*
1390 * mono_arch_get_argument_info:
1391 * @csig: a method signature
1392 * @param_count: the number of parameters to consider
1393 * @arg_info: an array to store the result infos
1394 *
1395 * Gathers information on parameters such as size, alignment and
1396 * padding. arg_info should be large enought to hold param_count + 1 entries.
1397 *
1398 * Returns the size of the argument area on the stack.
1399 */
1400 int
1401 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1402 {
1407 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1410 }
1414 /* FIXME: */
1416 }
1421 }
1423 gboolean
1424 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1425 {
1427 gboolean res;
1435 /* An address on the callee's stack is passed as the first argument */
1442 }
1444 /*
1445 * Initialize the cpu to execute managed code.
1446 */
1447 void
1449 {
1450 #ifndef _MSC_VER
1451 guint16 fpcw;
1453 /* spec compliance requires running with double precision */
1459 #else
1460 /* TODO: This is crashing on Win64 right now.
1461 * _control87 (_PC_53, MCW_PC);
1462 */
1463 #endif
1464 }
1466 /*
1467 * Initialize architecture specific code.
1468 */
1469 void
1471 {
1473 #if defined(__native_client_codegen__)
1478 #endif
1481 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1484 #if defined(ENABLE_GSHAREDVT)
1485 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1486 #endif
1490 }
1492 /*
1493 * Cleanup architecture specific code.
1494 */
1495 void
1497 {
1499 #if defined(__native_client_codegen__)
1503 #endif
1504 }
1506 /*
1507 * This function returns the optimizations supported on this cpu.
1508 */
1509 guint32
1511 {
1521 else
1525 }
1528 }
1530 /*
1531 * This function test for all SSE functions supported.
1532 *
1533 * Returns a bitmask corresponding to all supported versions.
1534 *
1535 */
1536 guint32
1538 {
1563 }
1565 #ifndef DISABLE_JIT
1567 GList *
1569 {
1577 /* unused vars */
1589 }
1590 }
1595 }
1597 /**
1598 * mono_arch_compute_omit_fp:
1599 *
1600 * Determine whenever the frame pointer can be eliminated.
1601 */
1602 static void
1604 {
1621 /*
1622 * FIXME: Remove some of the restrictions.
1623 */
1627 #ifdef __native_client_codegen__
1628 /* NaCl modules may not change the value of RBP, so it cannot be */
1629 /* used as a normal register, but it can be used as a frame pointer*/
1632 #endif
1639 /*
1640 if (cfg->method->save_lmf)
1641 cfg->arch.omit_fp = FALSE;
1642 */
1658 /*
1659 * The stack offset can only be determined when the frame
1660 * size is known.
1661 */
1663 }
1664 }
1672 }
1673 }
1675 GList *
1677 {
1685 /* We use the callee saved registers for global allocation */
1690 #ifndef __native_client_codegen__
1692 #endif
1693 #ifdef TARGET_WIN32
1696 #endif
1699 }
1701 GList*
1703 {
1707 /* All XMM registers */
1712 }
1714 GList*
1716 {
1727 #ifndef __native_client_codegen__
1729 #endif
1741 }
1744 }
1746 GList*
1748 {
1759 }
1762 }
1764 /*
1765 * mono_arch_regalloc_cost:
1766 *
1767 * Return the cost, in number of memory references, of the action of
1768 * allocating the variable VMV into a register during global register
1769 * allocation.
1770 */
1771 guint32
1773 {
1777 /* The register is already saved */
1778 /* substract 1 for the invisible store in the prolog */
1780 else
1781 /* push+pop */
1783 }
1785 /*
1786 * mono_arch_fill_argument_info:
1787 *
1788 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1789 * of the method.
1790 */
1791 void
1793 {
1805 /*
1806 * Contrary to mono_arch_allocate_vars (), the information should describe
1807 * where the arguments are at the beginning of the method, not where they can be
1808 * accessed during the execution of the method. The later makes no sense for the
1809 * global register allocator, since a variable can be in more than one location.
1810 */
1827 }
1847 /* Dummy */
1852 }
1853 }
1854 }
1856 void
1858 {
1874 /*
1875 * We use the ABI calling conventions for managed code as well.
1876 * Exception: valuetypes are only sometimes passed or returned in registers.
1877 */
1879 /*
1880 * The stack looks like this:
1881 * <incoming arguments passed on the stack>
1882 * <return value>
1883 * <lmf/caller saved registers>
1884 * <locals>
1885 * <spill area>
1886 * <localloc area> -> grows dynamically
1887 * <params area>
1888 */
1895 /* Locals are allocated backwards from %fp */
1898 }
1902 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1903 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1907 /* Reserve space for callee saved registers */
1911 }
1925 /* The register is volatile */
1934 }
1938 }
1941 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1950 }
1954 }
1955 }
1957 /* Allocate locals */
1958 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1961 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1964 }
1969 }
1976 }
1985 else
1987 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1988 }
1989 }
1996 }
2004 /* FIXME: Allocate volatile arguments to registers */
2008 /*
2009 * Under AMD64, all registers used to pass arguments to functions
2010 * are volatile across calls.
2011 * FIXME: Optimize this.
2012 */
2013 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
2026 }
2048 }
2052 }
2058 }
2060 NOT_IMPLEMENTED;
2061 }
2063 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2066 /* These arguments are saved to the stack in the prolog */
2070 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2071 // Arguments are yet supported by the stack map creation code
2072 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2074 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2076 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2077 }
2078 }
2079 }
2080 }
2083 }
2085 void
2087 {
2107 }
2108 }
2117 }
2125 }
2132 #if !defined(TARGET_WIN32)
2135 #endif
2136 }
2137 }
2139 static void
2140 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2141 {
2171 }
2172 }
2174 static int
2176 {
2179 #if defined(__mono_ilp32__)
2181 #else
2183 #endif
2190 }
2193 }
2195 static void
2197 {
2202 NOT_IMPLEMENTED;
2206 /*
2207 * mono_ArgIterator_Setup assumes the signature cookie is
2208 * passed first and all the arguments which were before it are
2209 * passed on the stack after the signature. So compensate by
2210 * passing a different signature.
2211 */
2215 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2220 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2221 }
2223 #ifdef ENABLE_LLVM
2226 {
2238 }
2239 }
2241 LLVMCallInfo*
2243 {
2256 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2258 /*
2259 * LLVM always uses the native ABI while we use our own ABI, the
2260 * only difference is the handling of vtypes:
2261 * - we only pass/receive them in registers in some cases, and only
2262 * in 1 or 2 integer registers.
2263 */
2277 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2278 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2282 }
2288 }
2290 /* Vtype returned using a hidden argument */
2297 }
2304 else
2320 else
2325 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2326 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2330 }
2334 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2344 }
2345 }
2348 }
2349 #endif
2351 void
2353 {
2369 /* We shouldn't be called in the llvm case */
2372 }
2374 /*
2375 * Emit all arguments which are passed on the stack to prevent register
2376 * allocation problems.
2377 */
2386 else
2390 //XXX what about ArgGSharedVtOnStack here?
2397 else
2401 }
2406 }
2407 }
2408 }
2410 /*
2411 * Emit all parameters passed in registers in non-reverse order for better readability
2412 * and to help the optimization in emit_prolog ().
2413 */
2421 }
2432 else
2438 /* Already done */
2450 /* Already emitted above */
2452 //FIXME what about ArgGSharedVtOnStack ?
2458 }
2460 guint32 align;
2461 guint32 size;
2466 /*
2467 * Other backends use mono_type_stack_size (), but that
2468 * aligns the size to 8, which is larger than the size of
2469 * the source, leading to reads of invalid memory if the
2470 * source is at the end of address space.
2471 */
2473 }
2476 /* Avoid asserts in emit_memcpy () */
2477 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2478 /* Continue normally */
2479 }
2491 }
2493 }
2496 }
2499 /* Emit the signature cookie just before the implicit arguments */
2501 }
2503 /* Handle the case where there are no implicit arguments */
2510 /*
2511 * Tell the JIT to use a more efficient calling convention: call using
2512 * OP_CALL, compute the result location after the call, and save the
2513 * result there.
2514 */
2516 /*
2517 * Nullify the instruction computing the vret addr to enable
2518 * future optimizations.
2519 */
2524 NOT_IMPLEMENTED;
2525 /*
2526 * The valuetype is in RAX:RDX after the call, need to be copied to
2527 * the stack. Push the address here, so the call instruction can
2528 * access it.
2529 */
2531 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2532 /* Prevent it from being register allocated or optimized away */
2534 }
2536 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2537 }
2548 }
2551 }
2556 }
2559 }
2561 void
2563 {
2592 }
2596 }
2598 }
2622 }
2624 }
2626 /* Pass by addr */
2641 // FIXME: Code growth
2643 }
2648 }
2649 }
2650 }
2652 void
2654 {
2660 else
2666 }
2669 }
2673 #define EMIT_COND_BRANCH(ins,cond,sign) \
2674 if (ins->inst_true_bb->native_offset) { \
2675 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2676 } else { \
2677 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2678 if ((cfg->opt & MONO_OPT_BRANCH) && \
2679 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2680 x86_branch8 (code, cond, 0, sign); \
2681 else \
2682 x86_branch32 (code, cond, 0, sign); \
2683 }
2690 static gboolean
2692 {
2695 #ifdef HOST_WIN32
2697 #endif
2711 }
2714 }
2729 }
2730 }
2733 }
2735 /*
2736 * mono_arch_dyn_call_prepare:
2737 *
2738 * Return a pointer to an arch-specific structure which contains information
2739 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2740 * supported for SIG.
2741 * This function is equivalent to ffi_prep_cif in libffi.
2742 */
2743 MonoDynCallInfo*
2745 {
2754 }
2757 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2762 }
2764 /*
2765 * mono_arch_dyn_call_free:
2766 *
2767 * Free a MonoDynCallInfo structure.
2768 */
2769 void
2771 {
2776 }
2778 #if !defined(__native_client__)
2779 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2780 #define GREG_TO_PTR(greg) (gpointer)(greg)
2781 #else
2782 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2783 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2784 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2785 #endif
2787 /*
2788 * mono_arch_get_start_dyn_call:
2789 *
2790 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2791 * store the result into BUF.
2792 * ARGS should be an array of pointers pointing to the arguments.
2793 * RET should point to a memory buffer large enought to hold the result of the
2794 * call.
2795 * This function should be as fast as possible, any work which does not depend
2796 * on the actual values of the arguments should be done in
2797 * mono_arch_dyn_call_prepare ().
2798 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2799 * libffi.
2800 */
2801 void
2802 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2803 {
2823 }
2835 }
2846 #if !defined(__mono_ilp32__)
2849 #endif
2853 #if defined(__mono_ilp32__)
2859 #endif
2882 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2892 /* The argument pointed to by arg is either a boxed vtype or null */
2896 /* Fall though */
2899 /* Fall through */
2900 }
2908 }
2912 }
2914 }
2917 }
2918 }
2921 }
2923 /*
2924 * mono_arch_finish_dyn_call:
2925 *
2926 * Store the result of a dyn call into the return value buffer passed to
2927 * start_dyn_call ().
2928 * This function should be as fast as possible, any work which does not depend
2929 * on the actual values of the arguments should be done in
2930 * mono_arch_dyn_call_prepare ().
2931 */
2932 void
2934 {
2984 /* Fall through */
2985 }
2988 /* Nothing to do */
2997 }
3000 }
3004 }
3005 }
3007 /* emit an exception if condition is fail */
3008 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
3009 do { \
3010 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3011 if (tins == NULL) { \
3012 mono_add_patch_info (cfg, code - cfg->native_code, \
3013 MONO_PATCH_INFO_EXC, exc_name); \
3014 x86_branch32 (code, cond, 0, signed); \
3015 } else { \
3016 EMIT_COND_BRANCH (tins, cond, signed); \
3017 } \
3018 } while (0);
3020 #define EMIT_FPCOMPARE(code) do { \
3021 amd64_fcompp (code); \
3022 amd64_fnstsw (code); \
3023 } while (0);
3025 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3026 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3027 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3028 amd64_ ##op (code); \
3029 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3030 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3031 } while (0);
3034 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3035 {
3038 /*
3039 * FIXME: Add support for thunks
3040 */
3041 {
3044 /*
3045 * Indirect calls are expensive so try to make a near call if possible.
3046 * The caller memory is allocated by the code manager so it is
3047 * guaranteed to be at a 32 bit offset.
3048 */
3051 /* The target is in memory allocated using the code manager */
3056 /* The callee might be an AOT method */
3059 /* The target is in malloc-ed memory */
3061 }
3064 /*
3065 * The call might go directly to a native function without
3066 * the wrapper.
3067 */
3073 }
3074 }
3075 }
3088 /*
3089 * This is not really an optimization, but required because the
3090 * generic class init trampolines use R11 to pass the vtable.
3091 */
3093 }
3098 /* No wrapper */
3101 }
3103 /* See the comment in mono_codegen () */
3104 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3106 }
3107 }
3111 }
3112 }
3113 }
3116 /* These methods are allocated using malloc */
3119 #ifdef MONO_ARCH_NOMAP32BIT
3121 #endif
3122 #if defined(__native_client__)
3123 /* Always use near_call == TRUE for Native Client */
3125 #endif
3126 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3133 }
3136 /*
3137 * Align the call displacement to an address divisible by 4 so it does
3138 * not span cache lines. This is required for code patching to work on SMP
3139 * systems.
3140 */
3144 }
3147 }
3152 }
3153 }
3156 }
3159 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3160 {
3161 #ifdef TARGET_WIN32
3164 #endif
3166 #ifdef TARGET_WIN32
3169 #endif
3172 }
3176 {
3184 }
3187 }
3189 #ifndef DISABLE_JIT
3191 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3193 /*
3194 * mono_arch_peephole_pass_1:
3195 *
3196 * Perform peephole opts which should/can be performed before local regalloc
3197 */
3198 void
3200 {
3211 /*
3212 * X86_LEA is like ADD, but doesn't have the
3213 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3214 * its operand to 64 bit.
3215 */
3218 }
3225 /*
3226 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3227 * the latter has length 2-3 instead of 6 (reverse constant
3228 * propagation). These instruction sequences are very common
3229 * in the initlocals bblock.
3230 */
3232 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3235 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3236 /* Continue */
3237 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3239 /* Continue */
3241 /* Continue */
3244 }
3245 }
3246 }
3250 /* OP_COMPARE_IMM (reg, 0)
3251 * -->
3252 * OP_AMD64_TEST_NULL (reg)
3253 */
3262 /*
3263 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3264 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3265 * -->
3266 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3267 * OP_COMPARE_IMM reg, imm
3268 *
3269 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3270 */
3277 /* check if we can remove cmp reg,0 with test null */
3280 }
3283 }
3286 }
3287 }
3289 void
3291 {
3299 /* reg = 0 -> XOR (reg, reg) */
3300 /* XOR sets cflags on x86, so we cant do it always */
3305 /* Fall through */
3308 }
3309 }
3311 /*
3312 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3313 * 0 result into 64 bits.
3314 */
3317 }
3318 /* Fall through */
3323 /*
3324 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3325 * the latter has length 2-3 instead of 6 (reverse constant
3326 * propagation). These instruction sequences are very common
3327 * in the initlocals bblock.
3328 */
3330 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3333 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3334 /* Continue */
3335 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3337 /* Continue */
3339 /* Continue */
3342 }
3343 }
3344 }
3354 }
3357 }
3358 }
3360 #define NEW_INS(cfg,ins,dest,op) do { \
3361 MONO_INST_NEW ((cfg), (dest), (op)); \
3362 (dest)->cil_code = (ins)->cil_code; \
3363 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3364 } while (0)
3366 /*
3367 * mono_arch_lowering_pass:
3368 *
3369 * Converts complex opcodes into simpler ones so that each IR instruction
3370 * corresponds to one machine instruction.
3371 */
3372 void
3374 {
3377 /*
3378 * FIXME: Need to add more instructions, but the current machine
3379 * description can't model some parts of the composite instructions like
3380 * cdq.
3381 */
3401 }
3403 #ifndef __mono_ilp32__
3405 #endif
3407 #ifndef __native_client_codegen__
3408 /* Don't generate memindex opcodes (to simplify */
3409 /* read sandboxing) */
3416 }
3417 #endif
3419 #ifndef __mono_ilp32__
3421 #endif
3429 }
3431 #ifdef MONO_ARCH_SIMD_INTRINSICS
3452 }
3454 #endif
3457 }
3458 }
3461 }
3463 static const int
3464 branch_cc_table [] = {
3468 };
3470 /* Maps CMP_... constants to X86_CC_... constants */
3471 static const int
3472 cc_table [] = {
3475 };
3477 static const int
3478 cc_signed_table [] = {
3481 };
3483 /*#include "cprop.c"*/
3486 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3487 {
3490 else
3498 }
3502 {
3506 #if defined(TARGET_WIN32)
3508 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3511 #endif
3516 /*
3517 * Under Windows:
3518 * If requested stack size is larger than one page,
3519 * perform stack-touch operation
3520 */
3521 /*
3522 * Generate stack probe code.
3523 * Under Windows, it is necessary to allocate one page at a time,
3524 * "touching" stack after each successful sub-allocation. This is
3525 * because of the way stack growth is implemented - there is a
3526 * guard page before the lowest stack page that is currently commited.
3527 * Stack normally grows sequentially so OS traps access to the
3528 * guard page and commits more pages when needed.
3529 */
3550 }
3551 else
3559 }
3563 }
3567 }
3578 #if defined(__default_codegen__)
3581 #elif defined(__native_client_codegen__)
3582 /* NaCl stos pseudo-instruction */
3584 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3586 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3599 }
3601 }
3605 {
3607 guint32 quad;
3609 /* Move return value to the target register */
3610 /* FIXME: do this in the local reg allocator */
3626 }
3630 }
3632 }
3649 /* Load the destination address */
3651 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3656 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3667 NOT_IMPLEMENTED;
3668 }
3669 }
3670 }
3672 }
3675 }
3679 #ifdef __APPLE__
3681 #endif
3683 gboolean
3685 {
3686 #ifdef TARGET_MACH
3693 #if MONO_HAVE_FAST_TLS
3696 /*
3697 * We're looking for these two instructions:
3698 *
3699 * mov %gs:[offset](,%rdi,8),%rax
3700 * retq
3701 */
3714 /*
3715 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3716 * For that version we're looking for these instructions:
3717 *
3718 * pushq %rbp
3719 * movq %rsp, %rbp
3720 * mov %gs:[offset](,%rdi,8),%rax
3721 * popq %rbp
3722 * retq
3723 */
3741 }
3742 #endif
3747 #elif defined(TARGET_ANDROID)
3749 #else
3751 #endif
3752 }
3754 int
3756 {
3757 #ifdef TARGET_OSX
3759 #else
3762 #endif
3763 }
3765 /*
3766 * mono_amd64_emit_tls_get:
3767 * @code: buffer to store code to
3768 * @dreg: hard register where to place the result
3769 * @tls_offset: offset info
3770 *
3771 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3772 * the dreg register the item in the thread local storage identified
3773 * by tls_offset.
3774 *
3775 * Returns: a pointer to the end of the stored code
3776 */
3777 guint8*
3779 {
3780 #ifdef TARGET_WIN32
3788 /* Load TEB->TlsExpansionSlots */
3796 }
3797 #elif defined(__APPLE__)
3800 #else
3808 }
3809 #endif
3811 }
3815 {
3816 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3817 #ifdef TARGET_OSX
3822 #elif defined(__linux__)
3826 /* Use a temporary reg by saving it to the redzone */
3831 }
3837 #else
3839 #endif
3841 }
3845 {
3846 #ifdef TARGET_WIN32
3848 #elif defined(__APPLE__)
3851 #else
3855 #endif
3857 }
3861 {
3862 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3863 #ifdef TARGET_WIN32
3865 #elif defined(__APPLE__)
3868 #else
3871 #endif
3873 }
3875 /*
3876 * mono_arch_translate_tls_offset:
3877 *
3878 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3879 */
3880 int
3882 {
3883 #ifdef __APPLE__
3885 #else
3887 #endif
3888 }
3890 /*
3891 * emit_setup_lmf:
3892 *
3893 * Emit code to initialize an LMF structure at LMF_OFFSET.
3894 */
3897 {
3898 /*
3899 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3900 */
3901 /*
3902 * sp is saved right before calls but we need to save it here too so
3903 * async stack walks would work.
3904 */
3905 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3906 /* Save rbp */
3907 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3909 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3911 /* These can't contain refs */
3912 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3913 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3914 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3915 /* These are handled automatically by the stack marking code */
3916 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3919 }
3921 #define REAL_PRINT_REG(text,reg) \
3922 mono_assert (reg >= 0); \
3923 amd64_push_reg (code, AMD64_RAX); \
3924 amd64_push_reg (code, AMD64_RDX); \
3925 amd64_push_reg (code, AMD64_RCX); \
3926 amd64_push_reg (code, reg); \
3927 amd64_push_imm (code, reg); \
3929 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3930 amd64_call_reg (code, AMD64_RAX); \
3931 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3932 amd64_pop_reg (code, AMD64_RCX); \
3933 amd64_pop_reg (code, AMD64_RDX); \
3934 amd64_pop_reg (code, AMD64_RAX);
3936 /* benchmark and set based on cpu */
3937 #define LOOP_ALIGNMENT 8
3938 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3940 #ifndef DISABLE_JIT
3941 void
3943 {
3946 guint offset;
3950 /* Fix max_offset estimate for each successor bb */
3957 }
3958 }
3962 /* set alignment depending on cpu */
3965 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3969 }
3970 }
3972 #if defined(__native_client_codegen__)
3973 /* For Native Client, all indirect call/jump targets must be */
3974 /* 32-byte aligned. Exception handler blocks are jumped to */
3975 /* indirectly as well. */
3984 }
3996 /* this is not thread save, but good enough */
3998 }
4004 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4012 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
4019 }
4049 /* In AMD64 NaCl, pointers are 4 bytes, */
4050 /* so STORE_* != STOREI8_*. Likewise below. */
4052 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4061 #ifndef __native_client_codegen__
4062 /* In NaCl, this could be a PCONST type, which could */
4063 /* mean a pointer type was copied directly into the */
4064 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4065 /* the value would be 0x00000000FFFFFFFF which is */
4066 /* not proper for an imm32 unless you cast it. */
4068 #endif
4069 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4076 #ifdef __mono_ilp32__
4077 /* In ILP32, pointers are 4 bytes, so separate these */
4078 /* cases, use literal 8 below where we really want 8 */
4082 #endif
4084 // FIXME: Decompose this earlier
4090 }
4097 // FIXME: Decompose this earlier
4103 }
4110 /* For NaCl, pointers are 4 bytes, so separate these */
4111 /* cases, use literal 8 below where we really want 8 */
4117 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4120 /* Use literal 8 instead of sizeof pointer or */
4121 /* register, we really want 8 for this opcode */
4132 /* The cpu zero extends the result into 64 bits */
4133 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4139 /* The cpu zero extends the result into 64 bits */
4140 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4167 /* Clean out the upper word */
4178 #if defined(__mono_ilp32__)
4179 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4183 #endif
4215 /* FIXME: Make a 64 version too */
4216 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4220 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4224 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4228 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4232 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4235 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4238 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4241 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4247 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4266 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4269 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4272 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4276 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4279 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4305 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4308 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4311 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4317 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4322 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4326 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4330 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4334 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4338 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4367 /* Load ss_tramp_var */
4368 /* This is equal to &ss_trampoline */
4370 /* Load the trampoline address */
4372 /* Call it if it is non-null */
4378 }
4380 /*
4381 * This is the address which is saved in seq points,
4382 */
4387 guint32 val;
4391 /* Load info var */
4394 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4399 /* Call the trampoline */
4406 /*
4407 * Emit a test+branch against a constant, the constant will be overwritten
4408 * by mono_arch_set_breakpoint () to cause the test to fail.
4409 */
4417 /* Load bp_tramp_var */
4418 /* This is equal to &bp_trampoline */
4420 /* Call the trampoline */
4423 }
4424 /*
4425 * Add an additional nop so skipping the bp doesn't cause the ip to point
4426 * to another IL offset.
4427 */
4430 }
4483 /* MOV r1, r2 */
4484 /* ADD r1, r1 */
4490 /* LEA r1, [r2 + r2*2] */
4494 /* LEA r1, [r2 + r2*4] */
4498 /* LEA r1, [r2 + r2*2] */
4499 /* ADD r1, r1 */
4504 /* LEA r1, [r2 + r2*8] */
4508 /* LEA r1, [r2 + r2*4] */
4509 /* ADD r1, r1 */
4514 /* LEA r1, [r2 + r2*2] */
4515 /* SHL r1, 2 */
4520 /* LEA r1, [r2 + r2*4] */
4521 /* LEA r1, [r1 + r1*4] */
4526 /* LEA r1, [r2 + r2*4] */
4527 /* SHL r1, 2 */
4528 /* LEA r1, [r1 + r1*4] */
4536 }
4538 }
4541 #if defined( __native_client_codegen__ )
4544 #endif
4545 /* Regalloc magic makes the div/rem cases the same */
4553 }
4557 #if defined( __native_client_codegen__ )
4560 #endif
4568 }
4572 #if defined( __native_client_codegen__ )
4575 #endif
4583 }
4587 #if defined( __native_client_codegen__ )
4590 #endif
4598 }
4731 /* the mul operation and the exception check should most likely be split */
4734 /*g_assert (ins->sreg2 == X86_EAX);
4735 g_assert (ins->dreg == X86_EAX);*/
4741 /* no need to save since we're going to store to it anyway */
4745 }
4748 }
4753 }
4757 }
4759 /* save before the check since pop and mov don't change the flags */
4768 }
4795 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4819 /* This needs to operate on 64 bit values */
4820 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4834 else
4855 }
4857 }
4862 }
4869 /* Restore callee saved registers */
4875 }
4880 // FIXME:
4882 NOT_IMPLEMENTED;
4884 /* Copy arguments on the stack to our argument area */
4888 }
4891 }
4897 else
4903 }
4905 /* ensure ins->sreg1 is not NULL */
4912 }
4921 /*
4922 * The AMD64 ABI forces callers to know about varargs.
4923 */
4926 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4927 /*
4928 * Since the unmanaged calling convention doesn't contain a
4929 * 'vararg' entry, we have to treat every pinvoke call as a
4930 * potential vararg call.
4931 */
4936 nregs ++;
4939 else
4941 }
4945 else
4963 }
4965 /*
4966 * The AMD64 ABI forces callers to know about varargs.
4967 */
4972 }
4974 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4975 /*
4976 * Since the unmanaged calling convention doesn't contain a
4977 * 'vararg' entry, we have to treat every pinvoke call as a
4978 * potential vararg call.
4979 */
4984 nregs ++;
4988 }
4991 else
4993 }
5020 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5022 /* r10 = ftn */
5025 /* Save args buffer */
5028 /* Set argument registers */
5032 /* Make the call */
5038 /* Save result */
5042 }
5045 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5047 }
5072 else
5083 }
5098 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5104 }
5107 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5116 /* keep alignment */
5144 }
5148 }
5152 }
5160 }
5168 }
5170 /* Align stack */
5175 /* Restore stack alignment */
5179 /* Even though we're saving RSP, use sizeof */
5180 /* gpointer because spvar is of type IntPtr */
5181 /* see: mono_create_spvar_for_region */
5183 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5188 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5189 }
5191 }
5194 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5197 }
5200 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5201 /* The local allocator will put the result into RAX */
5204 }
5213 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5214 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5215 //break;
5223 else
5225 }
5251 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5274 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5291 /* floating point opcodes */
5297 }
5301 }
5303 }
5310 else
5312 }
5318 }
5320 }
5331 /* This requires a double->single conversion */
5333 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5334 }
5342 }
5350 }
5361 }
5372 }
5433 /* Based on gcc code */
5437 /* Positive case */
5442 /* Negative case */
5443 /* Save to the red zone */
5453 /* Restore */
5458 }
5483 }
5516 }
5531 }
5557 }
5610 /*
5611 * The two arguments are swapped because the fbranch instructions
5612 * depend on this for the non-sse case to work.
5613 */
5617 /*
5618 * FIXME: Get rid of this.
5619 * The two arguments are swapped because the fbranch instructions
5620 * depend on this for the non-sse case to work.
5621 */
5626 /* zeroing the register at the start results in
5627 * shorter and faster code (we can also remove the widening op)
5628 */
5647 }
5649 }
5652 /* zeroing the register at the start results in
5653 * shorter and faster code (we can also remove the widening op)
5654 */
5669 }
5671 }
5681 }
5684 /* zeroing the register at the start results in
5685 * shorter and faster code (we can also remove the widening op)
5686 */
5698 }
5700 }
5710 }
5744 }
5760 }
5762 }
5788 }
5810 }
5812 }
5819 }
5821 /* Branch if C013 != 100 */
5822 /* branch if !ZF or (PF|CF) */
5839 /* skip branch if C1=1 */
5842 /* branch if (C0 | C3) = 1 */
5848 }
5851 /* Branch if C013 == 100 or 001 */
5854 /* skip branch if C1=1 */
5857 /* branch if (C0 | C3) = 1 */
5861 }
5863 /* Branch if C013 == 000 */
5867 /* Branch if C013=000 or 100 */
5870 /* skip branch if C1=1 */
5873 /* branch if C0=0 */
5877 }
5879 /* Branch if C013 != 001 */
5884 /* Transfer value to the fp stack */
5902 }
5909 }
5913 }
5918 }
5930 /* dreg contains the old value, add with sreg2 value */
5937 }
5942 /* LOCK prefix is implied. */
5947 }
5950 guint32 size;
5954 else
5957 /*
5958 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5959 * an explanation of how this works.
5960 */
5971 }
5975 }
5979 }
5983 }
5987 }
5991 }
5995 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5997 }
6002 }
6006 }
6034 }
6041 }
6044 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6049 }
6060 }
6066 gpointer card_table_mask;
6073 /*If either point to the stack we can simply avoid the WB. This happens due to
6074 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6075 */
6079 /*
6080 * We need one register we can clobber, we choose EDX and make sreg1
6081 * fixed EAX to work around limitations in the local register allocator.
6082 * sreg2 might get allocated to EDX, but that is not a problem since
6083 * we use it before clobbering EDX.
6084 */
6087 /*
6088 * This is the code we produce:
6089 *
6090 * edx = value
6091 * edx >>= nursery_shift
6092 * cmp edx, (nursery_start >> nursery_shift)
6093 * jne done
6094 * edx = ptr
6095 * edx >>= card_table_shift
6096 * edx += cardtable
6097 * [edx] = 1
6098 * done:
6099 */
6106 /*
6107 * The value we need to compare against is 64 bits, so we need
6108 * another spare register. We use RBX, which we save and
6109 * restore.
6110 */
6117 }
6119 }
6125 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6133 }
6134 #ifdef MONO_ARCH_SIMD_INTRINSICS
6135 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6525 /*TODO: This is appart of the sse spec but not added
6526 case OP_PSARQ:
6527 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6528 break;
6529 case OP_PSARQ_REG:
6530 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6531 break;
6532 */
6577 }
6588 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6589 if (ins->inst_c0)
6590 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6597 else
6607 /*sreg1 is the extracted ireg (scratch)
6608 /sreg2 is the to be inserted ireg (scratch)
6609 /dreg is the xreg to receive the value*/
6611 /*clear the bits from the extracted word*/
6613 /*shift the value to insert if needed*/
6616 /*join them together*/
6629 else
6638 else
6645 else
6653 else
6661 else
6665 }
6670 else
6694 /*FIXME the peephole pass should have killed this*/
6724 }
6746 }
6753 #endif
6756 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6759 }
6762 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6765 }
6771 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6774 #else
6778 #endif
6785 }
6799 }
6802 #if !defined(__native_client_codegen__)
6806 #endif
6807 }
6808 }
6811 }
6815 void
6817 {
6818 /* The signature doesn't matter */
6819 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6820 }
6822 void
6823 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6824 {
6827 /*
6828 * Debug code to help track down problems where the target of a near call is
6829 * is not valid.
6830 */
6846 }
6847 }
6848 }
6851 }
6853 #ifndef DISABLE_JIT
6855 static int
6857 {
6872 }
6874 /*
6875 * This macro is used for testing whenever the unwinder works correctly at every point
6876 * where an async exception can happen.
6877 */
6878 /* This will generate a SIGSEGV at the given point in the code */
6879 #define async_exc_point(code) do { \
6880 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6881 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6882 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6883 cfg->arch.async_point_count ++; \
6884 } \
6885 } while (0)
6887 guint8 *
6889 {
6900 #ifdef __native_client_codegen__
6901 guint alignment_check;
6902 #endif
6906 #if defined(__default_codegen__)
6908 #elif defined(__native_client_codegen__)
6909 /* native_code_alloc is not 32-byte aligned, native_code is. */
6912 /* Align native_code to next nearest kNaclAlignment byte. */
6920 #endif
6925 /* Amount of stack space allocated by register saving code */
6928 /* Offset between RSP and the CFA */
6931 /*
6932 * The prolog consists of the following parts:
6933 * FP present:
6934 * - push rbp, mov rbp, rsp
6935 * - save callee saved regs using pushes
6936 * - allocate frame
6937 * - save rgctx if needed
6938 * - save lmf if needed
6939 * FP not present:
6940 * - allocate frame
6941 * - save rgctx if needed
6942 * - save lmf if needed
6943 * - save callee saved regs using moves
6944 */
6946 // CFA = sp + 8
6949 // IP saved at CFA - 8
6960 #ifdef TARGET_WIN32
6961 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6962 #endif
6963 /* These are handled automatically by the stack marking code */
6969 #ifdef TARGET_WIN32
6971 #endif
6972 }
6974 /* The param area is always at offset 0 from sp */
6975 /* This needs to be allocated here, since it has to come after the spill area */
6978 // FIXME:
6981 }
6984 /*
6985 * On enter, the stack is misaligned by the pushing of the return
6986 * address. It is either made aligned by the pushing of %rbp, or by
6987 * this.
6988 */
6992 /* Mark the padding slot as NOREF */
6994 }
6998 /* Mark the padding slot as NOREF */
7000 }
7003 }
7007 /* Allocate stack frame */
7009 /* See mono_emit_stack_alloc */
7010 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7012 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
7013 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7021 }
7028 }
7030 #ifdef TARGET_WIN32
7033 #endif
7037 }
7044 }
7045 #ifdef TARGET_WIN32
7047 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7048 #endif
7049 }
7050 #else
7056 }
7057 #endif
7058 }
7060 /* Stack alignment check */
7061 #if 0
7062 {
7068 }
7069 #endif
7072 /* Fill the stack frame with a dummy value to force deterministic behavior */
7074 /* Save registers to the red zone */
7083 #if defined(__default_codegen__)
7086 #elif defined(__native_client_codegen__)
7087 /* NaCl stos pseudo-instruction */
7089 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
7091 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7100 }
7102 /* Save LMF */
7106 /* Save callee saved registers */
7109 /* Save caller saved registers after sp is adjusted */
7110 /* The registers are saved at the bottom of the frame */
7111 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7113 /* The registers are saved just below the saved rbp */
7115 }
7123 /* These are handled automatically by the stack marking code */
7127 // FIXME: GC
7128 }
7132 }
7133 }
7135 /* store runtime generic context */
7140 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7142 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7143 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7144 }
7146 /* compute max_length in order to use short forward jumps */
7155 /* max alignment for loops */
7158 #ifdef __native_client_codegen__
7159 /* max alignment for native client */
7161 #endif
7164 #ifdef __native_client_codegen__
7165 {
7171 }
7172 }
7175 }
7177 /* Take prolog and epilog instrumentation into account */
7182 }
7183 }
7191 /* Save volatile arguments to the stack */
7193 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7194 }
7196 /* Keep this in sync with emit_load_volatile_arguments */
7203 /* Unused arguments */
7206 /* Save volatile arguments to the stack */
7212 /* FIXME: I1 etc */
7213 /*
7214 if (stack_offset & 0x1)
7215 size = 1;
7216 else if (stack_offset & 0x2)
7217 size = 2;
7218 else if (stack_offset & 0x4)
7219 size = 4;
7220 else
7221 size = 8;
7222 */
7225 /*
7226 * Save the original location of 'this',
7227 * get_generic_info_from_stack_frame () needs this to properly look up
7228 * the argument value during the handling of async exceptions.
7229 */
7232 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7233 }
7235 }
7246 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7249 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7252 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7258 }
7259 }
7263 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7270 }
7272 /* Argument allocated to (non-volatile) register */
7282 }
7287 }
7288 }
7289 }
7297 }
7302 /*
7303 * Optimize the common case of the first bblock making a call with the same
7304 * arguments as the method. This works because the arguments are still in their
7305 * original argument registers.
7306 * FIXME: Generalize this
7307 */
7317 }
7330 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7337 /* Only continue if the instruction doesn't change argument regs */
7340 }
7341 }
7343 }
7346 }
7348 /* Argument allocated to (non-volatile) register */
7354 }
7358 }
7359 }
7363 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7366 }
7367 }
7368 }
7373 /* Initialize seq_point_info_var */
7375 /* Initialize the variable from a GOT slot */
7376 /* Same as OP_AOTCONST */
7377 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7381 }
7384 /* Initialize ss_tramp_var */
7389 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7392 /* Initialize ss_tramp_var */
7399 /* Initialize bp_tramp_var */
7405 }
7406 }
7413 }
7415 void
7417 {
7432 }
7437 /* Mark the start of the epilog */
7440 /* Save the uwind state which is needed by the out-of-line code */
7446 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7449 /* check if we need to restore protection of the stack after a stack overflow */
7453 /* we load the value in a separate instruction: this mechanism may be
7454 * used later as a safer way to do thread interruption
7455 */
7456 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7460 /* note that the call trampoline will preserve eax/edx */
7464 /* FIXME: maybe save the jit tls in the prolog */
7465 }
7467 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7468 }
7469 }
7471 /* Restore callee saved regs */
7474 /* Restore only used_int_regs, not arch.saved_iregs */
7479 }
7481 }
7482 }
7484 /* Load returned vtypes into registers if needed */
7493 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7496 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7499 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7505 }
7506 }
7507 }
7512 }
7516 }
7521 /* Restore the unwind state to be the same as before the epilog */
7527 }
7529 void
7531 {
7539 /* Compute needed space */
7549 }
7551 #ifdef __native_client_codegen__
7552 /* Give us extra room on Native Client. This could be */
7553 /* more carefully calculated, but bundle alignment makes */
7554 /* it much trickier, so *2 like other places is good. */
7556 #endif
7562 }
7566 /* add code to raise exceptions */
7573 guint32 throw_ip;
7581 //x86_breakpoint (code);
7582 /* Find a throw sequence for the same exception class */
7590 }
7599 }
7604 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7612 nthrows ++;
7613 }
7614 }
7616 }
7618 /* do nothing */
7620 }
7622 }
7624 /* Handle relocations with RIP relative addressing */
7633 guint32 target_pos;
7635 /* The SSE opcodes require a 16 byte alignment */
7636 #if defined(__default_codegen__)
7638 #elif defined(__native_client_codegen__)
7639 {
7640 /* Pad this out with HLT instructions */
7641 /* or we can get garbage bytes emitted */
7642 /* which will fail validation */
7644 /* extra align to make room for */
7645 /* mov/push below */
7648 /* The technique of hiding data in an */
7649 /* instruction has a problem here: we */
7650 /* need the data aligned to a 16-byte */
7651 /* boundary but the instruction cannot */
7652 /* cross the bundle boundary. so only */
7653 /* odd multiples of 16 can be used */
7656 }
7659 }
7660 }
7661 #endif
7667 }
7671 }
7674 #ifdef __native_client_codegen__
7675 /* Hide 64-bit data in a */
7676 /* "mov imm64, r11" instruction. */
7677 /* write it before the start of */
7678 /* the data*/
7681 #endif
7685 #ifdef __native_client_codegen__
7686 /* Hide 32-bit data in a */
7687 /* "push imm32" instruction. */
7689 #endif
7692 }
7698 }
7705 /*loading is faster against aligned addresses.*/
7711 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7714 else
7722 }
7725 }
7734 ;
7736 }
7737 }
7739 }
7745 }
7751 {
7757 /* Keep this in sync with mono_arch_get_argument_info */
7760 /* Allocate a new area on the stack and save arguments there */
7777 }
7778 }
7779 }
7790 }
7793 SAVE_NONE,
7794 SAVE_STRUCT,
7795 SAVE_EAX,
7796 SAVE_EAX_EDX,
7797 SAVE_XMM
7798 };
7801 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7802 {
7811 /* special case string .ctor icall */
7814 else
7829 }
7830 /* Fall through */
7837 }
7839 /* Save the result and copy it into the proper argument register */
7843 /* Align stack */
7849 /* FIXME: */
7856 /* Align stack */
7858 /*
7859 * The result is already in the proper argument register so no copying
7860 * needed.
7861 */
7867 }
7869 /* Set %al since this is a varargs call */
7872 else
7878 }
7887 }
7889 /* Restore result */
7896 /* FIXME: */
7907 }
7910 }
7912 void
7914 {
7915 /* Not needed */
7916 }
7918 void
7920 {
7921 }
7923 gboolean
7925 {
7927 }
7929 /*
7930 * Determine whenever the trap whose info is in SIGINFO is caused by
7931 * integer overflow.
7932 */
7933 gboolean
7935 {
7936 MonoContext ctx;
7939 gint64 value;
7947 rip ++;
7948 }
7949 else
7952 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7953 /* idiv REG */
7960 }
7963 }
7965 guint32
7967 {
7969 }
7971 /**
7972 * mono_breakpoint_clean_code:
7973 *
7974 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7975 * breakpoints in the original code, they are removed in the copy.
7976 *
7977 * Returns TRUE if no sw breakpoint was present.
7978 */
7979 gboolean
7980 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7981 {
7982 /*
7983 * If method_start is non-NULL we need to perform bound checks, since we access memory
7984 * at code - offset we could go before the start of the method and end up in a different
7985 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7986 * instead.
7987 */
7994 }
7996 }
7998 #if defined(__native_client_codegen__)
7999 /* For membase calls, we want the base register. for Native Client, */
8000 /* all indirect calls have the following sequence with the given sizes: */
8001 /* mov %eXX,%eXX [2-3] */
8002 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
8003 /* and $0xffffffffffffffe0,%r11d [4] */
8004 /* add %r15,%r11 [3] */
8005 /* callq *%r11 [3] */
8008 /* Determine if code points to a NaCl call-through-register sequence, */
8009 /* (i.e., the last 3 instructions listed above) */
8010 int
8012 {
8017 }
8019 /* Determine if code points to the first opcode of the mov membase component */
8020 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
8021 /* (there could be a REX prefix before the opcode but it is ignored) */
8022 static int
8024 {
8025 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8027 /* and that src reg = dest reg */
8029 /* Check that next inst is mov, uses SIB byte (rm = 4), */
8032 /* and has dst of r11 and base of r15 */
8035 }
8038 int
8040 {
8042 }
8044 gpointer
8046 {
8048 }
8050 #define MAX_ARCH_DELEGATE_PARAMS 10
8052 static gpointer
8054 {
8064 /* Replace the this argument with the target */
8066 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8076 /* We have to shift the arguments left */
8079 #ifdef TARGET_WIN32
8082 else
8084 #else
8086 #endif
8087 }
8090 }
8092 }
8098 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8103 }
8109 else
8114 }
8115 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8118 }
8120 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8122 static gpointer
8124 {
8137 /* Replace the this argument with the target */
8139 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8142 /* Load the IMT reg */
8143 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8144 }
8146 /* Load the vtable */
8147 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8149 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8153 else
8159 }
8161 /*
8162 * mono_arch_get_delegate_invoke_impls:
8163 *
8164 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8165 * trampolines.
8166 */
8167 GSList*
8169 {
8180 }
8188 }
8191 }
8193 gpointer
8195 {
8202 /* FIXME: Support more cases */
8218 }
8243 }
8248 }
8251 }
8253 gpointer
8254 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8255 {
8257 gpointer code;
8263 }
8265 void
8267 {
8268 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8270 #endif
8271 }
8273 void
8275 {
8276 }
8278 #if defined(__default_codegen__)
8279 #define CMP_SIZE (6 + 1)
8280 #define CMP_REG_REG_SIZE (4 + 1)
8281 #define BR_SMALL_SIZE 2
8282 #define BR_LARGE_SIZE 6
8283 #define MOV_REG_IMM_SIZE 10
8284 #define MOV_REG_IMM_32BIT_SIZE 6
8285 #define JUMP_REG_SIZE (2 + 1)
8286 #elif defined(__native_client_codegen__)
8287 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8288 #define CMP_SIZE ((6 + 1) * 2 - 1)
8289 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8290 #define BR_SMALL_SIZE (2 * 2 - 1)
8291 #define BR_LARGE_SIZE (6 * 2 - 1)
8292 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8293 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8294 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8295 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8296 /* Jump membase's size is large and unpredictable */
8297 /* in native client, just pad it out a whole bundle. */
8298 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8299 #endif
8301 static int
8303 {
8308 }
8310 /*
8311 * LOCKING: called with the domain lock held
8312 */
8313 gpointer
8314 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8315 gpointer fail_tramp)
8316 {
8330 else
8332 }
8338 else
8340 #ifdef __native_client_codegen__
8342 #endif
8343 }
8352 else
8355 /* with assert below:
8356 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8357 */
8358 #ifdef __native_client_codegen__
8360 #endif
8361 }
8362 }
8366 else
8370 }
8372 }
8373 #if defined(__native_client__) && defined(__native_client_codegen__)
8374 /* In Native Client, we don't re-use thunks, allocate from the */
8375 /* normal code manager paths. */
8377 #else
8380 else
8382 #endif
8396 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8400 }
8401 }
8408 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8410 }
8417 }
8419 /* enable the commented code to assert on wrong method */
8420 #if 0
8422 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8426 }
8429 /* See the comment below about R10 */
8430 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8435 #else
8436 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8437 needs to be preserved. R10 needs
8438 to be preserved for calls which
8439 require a runtime generic context,
8440 but interface calls don't. */
8441 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8443 #endif
8444 }
8447 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8451 }
8455 else
8457 }
8459 }
8460 /* patch the branches to get to the target items */
8466 }
8467 }
8468 }
8475 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8477 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8480 }
8482 MonoMethod*
8484 {
8486 }
8488 MonoVTable*
8490 {
8492 }
8494 GSList*
8496 {
8503 }
8505 #ifndef DISABLE_JIT
8507 MonoInst*
8508 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8509 {
8522 }
8530 }
8552 }
8553 }
8562 }
8564 #if 0
8565 /* OP_FREM is not IEEE compatible */
8570 }
8571 #endif
8572 }
8575 }
8576 #endif
8578 gboolean
8580 {
8582 }
8584 mgreg_t
8586 {
8588 }
8590 void
8592 {
8594 }
8596 gpointer
8597 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8598 {
8602 /*Load the spvar*/
8613 }
8615 /*
8616 * mono_arch_emit_load_aotconst:
8617 *
8618 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8619 * TARGET from the mscorlib GOT in full-aot code.
8620 * On AMD64, the result is placed into R11.
8621 */
8622 guint8*
8623 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8624 {
8629 }
8631 /*
8632 * mono_arch_get_trampolines:
8633 *
8634 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8635 * for AOT.
8636 */
8637 GSList *
8639 {
8641 }
8643 /* Soft Debug support */
8644 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8646 /*
8647 * mono_arch_set_breakpoint:
8648 *
8649 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8650 * The location should contain code emitted by OP_SEQ_POINT.
8651 */
8652 void
8654 {
8659 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8664 /* ip points to a mov r11, 0 */
8668 }
8669 }
8671 /*
8672 * mono_arch_clear_breakpoint:
8673 *
8674 * Clear the breakpoint at IP.
8675 */
8676 void
8678 {
8683 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8688 }
8689 }
8691 gboolean
8693 {
8694 /* We use soft breakpoints on amd64 */
8696 }
8698 /*
8699 * mono_arch_skip_breakpoint:
8700 *
8701 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8702 * we resume, the instruction is not executed again.
8703 */
8704 void
8706 {
8708 }
8710 /*
8711 * mono_arch_start_single_stepping:
8712 *
8713 * Start single stepping.
8714 */
8715 void
8717 {
8719 }
8721 /*
8722 * mono_arch_stop_single_stepping:
8723 *
8724 * Stop single stepping.
8725 */
8726 void
8728 {
8730 }
8732 /*
8733 * mono_arch_is_single_step_event:
8734 *
8735 * Return whenever the machine state in SIGCTX corresponds to a single
8736 * step event.
8737 */
8738 gboolean
8740 {
8741 /* We use soft breakpoints on amd64 */
8743 }
8745 /*
8746 * mono_arch_skip_single_step:
8747 *
8748 * Modify CTX so the ip is placed after the single step trigger instruction,
8749 * we resume, the instruction is not executed again.
8750 */
8751 void
8753 {
8755 }
8757 /*
8758 * mono_arch_create_seq_point_info:
8759 *
8760 * Return a pointer to a data structure which is used by the sequence
8761 * point implementation in AOTed code.
8762 */
8763 gpointer
8765 {
8769 // FIXME: Add a free function
8773 code);
8780 // FIXME: Optimize the size
8781 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8789 }
8792 }
8794 void
8796 {
8798 /* Mark that this is a MonoLMFExt */
8801 }
8803 #endif
8805 gboolean
8807 {
8838 }
8839 }
8841 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)