2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internals.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
39 #include "mini-amd64.h"
40 #include "cpu-amd64.h"
41 #include "debugger-agent.h"
45 static gboolean optimize_for_xen
= TRUE
;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
66 static mono_mutex_t mini_arch_mutex
;
68 /* The single step trampoline */
69 static gpointer ss_trampoline
;
71 /* The breakpoint trampoline */
72 static gpointer bp_trampoline
;
74 /* Offset between fp and the first argument in the callee */
75 #define ARGS_OFFSET 16
76 #define GP_SCRATCH_REG AMD64_R11
79 * AMD64 register usage:
80 * - callee saved registers are used for global register allocation
81 * - %r11 is used for materializing 64 bit constants in opcodes
82 * - the rest is used for local allocation
86 * Floating point comparison results:
96 mono_arch_regname (int reg
)
99 case AMD64_RAX
: return "%rax";
100 case AMD64_RBX
: return "%rbx";
101 case AMD64_RCX
: return "%rcx";
102 case AMD64_RDX
: return "%rdx";
103 case AMD64_RSP
: return "%rsp";
104 case AMD64_RBP
: return "%rbp";
105 case AMD64_RDI
: return "%rdi";
106 case AMD64_RSI
: return "%rsi";
107 case AMD64_R8
: return "%r8";
108 case AMD64_R9
: return "%r9";
109 case AMD64_R10
: return "%r10";
110 case AMD64_R11
: return "%r11";
111 case AMD64_R12
: return "%r12";
112 case AMD64_R13
: return "%r13";
113 case AMD64_R14
: return "%r14";
114 case AMD64_R15
: return "%r15";
119 static const char * packed_xmmregs
[] = {
120 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
121 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
124 static const char * single_xmmregs
[] = {
125 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
126 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
130 mono_arch_fregname (int reg
)
132 if (reg
< AMD64_XMM_NREG
)
133 return single_xmmregs
[reg
];
139 mono_arch_xregname (int reg
)
141 if (reg
< AMD64_XMM_NREG
)
142 return packed_xmmregs
[reg
];
151 return mono_debug_count ();
157 static inline gboolean
158 amd64_is_near_call (guint8
*code
)
161 if ((code
[0] >= 0x40) && (code
[0] <= 0x4f))
164 return code
[0] == 0xe8;
167 static inline gboolean
168 amd64_use_imm32 (gint64 val
)
170 if (mini_get_debug_options()->single_imm_size
)
173 return amd64_is_imm32 (val
);
176 #ifdef __native_client_codegen__
178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
179 /* for any given instruction. For instance, amd64_call_reg resolves to */
180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
181 /* We only want to force bundle alignment for the top level instruction, */
182 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
183 static MonoNativeTlsKey nacl_instruction_depth
;
185 static MonoNativeTlsKey nacl_rex_tag
;
186 static MonoNativeTlsKey nacl_legacy_prefix_tag
;
189 amd64_nacl_clear_legacy_prefix_tag ()
191 mono_native_tls_set_value (nacl_legacy_prefix_tag
, NULL
);
195 amd64_nacl_tag_legacy_prefix (guint8
* code
)
197 if (mono_native_tls_get_value (nacl_legacy_prefix_tag
) == NULL
)
198 mono_native_tls_set_value (nacl_legacy_prefix_tag
, code
);
202 amd64_nacl_tag_rex (guint8
* code
)
204 mono_native_tls_set_value (nacl_rex_tag
, code
);
208 amd64_nacl_get_legacy_prefix_tag ()
210 return (guint8
*)mono_native_tls_get_value (nacl_legacy_prefix_tag
);
214 amd64_nacl_get_rex_tag ()
216 return (guint8
*)mono_native_tls_get_value (nacl_rex_tag
);
219 /* Increment the instruction "depth" described above */
221 amd64_nacl_instruction_pre ()
223 intptr_t depth
= (intptr_t) mono_native_tls_get_value (nacl_instruction_depth
);
225 mono_native_tls_set_value (nacl_instruction_depth
, (gpointer
)depth
);
228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
229 /* alignment if depth == 0 (top level instruction) */
230 /* IN: start, end pointers to instruction beginning and end */
231 /* OUT: start, end pointers to beginning and end after possible alignment */
232 /* GLOBALS: nacl_instruction_depth defined above */
234 amd64_nacl_instruction_post (guint8
**start
, guint8
**end
)
236 intptr_t depth
= (intptr_t) mono_native_tls_get_value (nacl_instruction_depth
);
238 mono_native_tls_set_value (nacl_instruction_depth
, (void*)depth
);
240 g_assert ( depth
>= 0 );
242 uintptr_t space_in_block
;
244 guint8
*prefix
= amd64_nacl_get_legacy_prefix_tag ();
245 /* if legacy prefix is present, and if it was emitted before */
246 /* the start of the instruction sequence, adjust the start */
247 if (prefix
!= NULL
&& prefix
< *start
) {
248 g_assert (*start
- prefix
<= 3);/* only 3 are allowed */
251 space_in_block
= kNaClAlignment
- ((uintptr_t)(*start
) & kNaClAlignmentMask
);
252 instlen
= (uintptr_t)(*end
- *start
);
253 /* Only check for instructions which are less than */
254 /* kNaClAlignment. The only instructions that should ever */
255 /* be that long are call sequences, which are already */
256 /* padded out to align the return to the next bundle. */
257 if (instlen
> space_in_block
&& instlen
< kNaClAlignment
) {
258 const size_t MAX_NACL_INST_LENGTH
= kNaClAlignment
;
259 guint8 copy_of_instruction
[MAX_NACL_INST_LENGTH
];
260 const size_t length
= (size_t)((*end
)-(*start
));
261 g_assert (length
< MAX_NACL_INST_LENGTH
);
263 memcpy (copy_of_instruction
, *start
, length
);
264 *start
= mono_arch_nacl_pad (*start
, space_in_block
);
265 memcpy (*start
, copy_of_instruction
, length
);
266 *end
= *start
+ length
;
268 amd64_nacl_clear_legacy_prefix_tag ();
269 amd64_nacl_tag_rex (NULL
);
273 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
274 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
275 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
276 /* make sure the upper 32-bits are cleared, and use that register in the */
277 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
279 /* pointer to current instruction stream (in the */
280 /* middle of an instruction, after opcode is emitted) */
281 /* basereg/offset/dreg */
282 /* operands of normal membase address */
284 /* pointer to the end of the membase/memindex emit */
285 /* GLOBALS: nacl_rex_tag */
286 /* position in instruction stream that rex prefix was emitted */
287 /* nacl_legacy_prefix_tag */
288 /* (possibly NULL) position in instruction of legacy x86 prefix */
290 amd64_nacl_membase_handler (guint8
** code
, gint8 basereg
, gint32 offset
, gint8 dreg
)
292 gint8 true_basereg
= basereg
;
294 /* Cache these values, they might change */
295 /* as new instructions are emitted below. */
296 guint8
* rex_tag
= amd64_nacl_get_rex_tag ();
297 guint8
* legacy_prefix_tag
= amd64_nacl_get_legacy_prefix_tag ();
299 /* 'basereg' is given masked to 0x7 at this point, so check */
300 /* the rex prefix to see if this is an extended register. */
301 if ((rex_tag
!= NULL
) && IS_REX(*rex_tag
) && (*rex_tag
& AMD64_REX_B
)) {
305 #define X86_LEA_OPCODE (0x8D)
307 if (!amd64_is_valid_nacl_base (true_basereg
) && (*(*code
-1) != X86_LEA_OPCODE
)) {
308 guint8
* old_instruction_start
;
310 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
311 /* 32-bits of the old base register (new index register) */
313 guint8
* buf_ptr
= buf
;
316 g_assert (rex_tag
!= NULL
);
318 if (IS_REX(*rex_tag
)) {
319 /* The old rex.B should be the new rex.X */
320 if (*rex_tag
& AMD64_REX_B
) {
321 *rex_tag
|= AMD64_REX_X
;
323 /* Since our new base is %r15 set rex.B */
324 *rex_tag
|= AMD64_REX_B
;
326 /* Shift the instruction by one byte */
327 /* so we can insert a rex prefix */
328 memmove (rex_tag
+ 1, rex_tag
, (size_t)(*code
- rex_tag
));
330 /* New rex prefix only needs rex.B for %r15 base */
331 *rex_tag
= AMD64_REX(AMD64_REX_B
);
334 if (legacy_prefix_tag
) {
335 old_instruction_start
= legacy_prefix_tag
;
337 old_instruction_start
= rex_tag
;
340 /* Clears the upper 32-bits of the previous base register */
341 amd64_mov_reg_reg_size (buf_ptr
, true_basereg
, true_basereg
, 4);
342 insert_len
= buf_ptr
- buf
;
344 /* Move the old instruction forward to make */
345 /* room for 'mov' stored in 'buf_ptr' */
346 memmove (old_instruction_start
+ insert_len
, old_instruction_start
, (size_t)(*code
- old_instruction_start
));
348 memcpy (old_instruction_start
, buf
, insert_len
);
350 /* Sandboxed replacement for the normal membase_emit */
351 x86_memindex_emit (*code
, dreg
, AMD64_R15
, offset
, basereg
, 0);
354 /* Normal default behavior, emit membase memory location */
355 x86_membase_emit_body (*code
, dreg
, basereg
, offset
);
360 static inline unsigned char*
361 amd64_skip_nops (unsigned char* code
)
366 if ( code
[0] == 0x90) {
370 if ( code
[0] == 0x66 && code
[1] == 0x90) {
374 if (code
[0] == 0x0f && code
[1] == 0x1f
375 && code
[2] == 0x00) {
379 if (code
[0] == 0x0f && code
[1] == 0x1f
380 && code
[2] == 0x40 && code
[3] == 0x00) {
384 if (code
[0] == 0x0f && code
[1] == 0x1f
385 && code
[2] == 0x44 && code
[3] == 0x00
386 && code
[4] == 0x00) {
390 if (code
[0] == 0x66 && code
[1] == 0x0f
391 && code
[2] == 0x1f && code
[3] == 0x44
392 && code
[4] == 0x00 && code
[5] == 0x00) {
396 if (code
[0] == 0x0f && code
[1] == 0x1f
397 && code
[2] == 0x80 && code
[3] == 0x00
398 && code
[4] == 0x00 && code
[5] == 0x00
399 && code
[6] == 0x00) {
403 if (code
[0] == 0x0f && code
[1] == 0x1f
404 && code
[2] == 0x84 && code
[3] == 0x00
405 && code
[4] == 0x00 && code
[5] == 0x00
406 && code
[6] == 0x00 && code
[7] == 0x00) {
415 mono_arch_nacl_skip_nops (guint8
* code
)
417 return amd64_skip_nops(code
);
420 #endif /*__native_client_codegen__*/
423 amd64_patch (unsigned char* code
, gpointer target
)
427 #ifdef __native_client_codegen__
428 code
= amd64_skip_nops (code
);
430 #if defined(__native_client_codegen__) && defined(__native_client__)
431 if (nacl_is_code_address (code
)) {
432 /* For tail calls, code is patched after being installed */
433 /* but not through the normal "patch callsite" method. */
434 unsigned char buf
[kNaClAlignment
];
435 unsigned char *aligned_code
= (uintptr_t)code
& ~kNaClAlignmentMask
;
437 memcpy (buf
, aligned_code
, kNaClAlignment
);
438 /* Patch a temp buffer of bundle size, */
439 /* then install to actual location. */
440 amd64_patch (buf
+ ((uintptr_t)code
- (uintptr_t)aligned_code
), target
);
441 ret
= nacl_dyncode_modify (aligned_code
, buf
, kNaClAlignment
);
445 target
= nacl_modify_patch_target (target
);
449 if ((code
[0] >= 0x40) && (code
[0] <= 0x4f)) {
454 if ((code
[0] & 0xf8) == 0xb8) {
455 /* amd64_set_reg_template */
456 *(guint64
*)(code
+ 1) = (guint64
)target
;
458 else if ((code
[0] == 0x8b) && rex
&& x86_modrm_mod (code
[1]) == 0 && x86_modrm_rm (code
[1]) == 5) {
459 /* mov 0(%rip), %dreg */
460 *(guint32
*)(code
+ 2) = (guint32
)(guint64
)target
- 7;
462 else if ((code
[0] == 0xff) && (code
[1] == 0x15)) {
463 /* call *<OFFSET>(%rip) */
464 *(guint32
*)(code
+ 2) = ((guint32
)(guint64
)target
) - 7;
466 else if (code
[0] == 0xe8) {
468 gint64 disp
= (guint8
*)target
- (guint8
*)code
;
469 g_assert (amd64_is_imm32 (disp
));
470 x86_patch (code
, (unsigned char*)target
);
473 x86_patch (code
, (unsigned char*)target
);
477 mono_amd64_patch (unsigned char* code
, gpointer target
)
479 amd64_patch (code
, target
);
488 ArgValuetypeAddrInIReg
,
489 /* gsharedvt argument passed by addr */
492 ArgNone
/* only in pair_storage */
498 ArgStorage storage
: 8;
499 gboolean is_gsharedvt_return_value
: 1;
501 /* Only if storage == ArgValuetypeInReg */
502 ArgStorage pair_storage
[2];
504 /* The size of each pair */
507 /* Only if storage == ArgOnStack */
516 gboolean need_stack_align
;
517 /* The index of the vret arg in the argument list */
524 #define DEBUG(a) if (cfg->verbose_level > 1) a
527 static AMD64_Reg_No param_regs
[] = { AMD64_RCX
, AMD64_RDX
, AMD64_R8
, AMD64_R9
};
529 static AMD64_Reg_No return_regs
[] = { AMD64_RAX
, AMD64_RDX
};
531 static AMD64_Reg_No param_regs
[] = { AMD64_RDI
, AMD64_RSI
, AMD64_RDX
, AMD64_RCX
, AMD64_R8
, AMD64_R9
};
533 static AMD64_Reg_No return_regs
[] = { AMD64_RAX
, AMD64_RDX
};
537 add_general (guint32
*gr
, guint32
*stack_size
, ArgInfo
*ainfo
)
539 ainfo
->offset
= *stack_size
;
541 if (*gr
>= PARAM_REGS
) {
542 ainfo
->storage
= ArgOnStack
;
543 ainfo
->arg_size
= sizeof (mgreg_t
);
544 /* Since the same stack slot size is used for all arg */
545 /* types, it needs to be big enough to hold them all */
546 (*stack_size
) += sizeof(mgreg_t
);
549 ainfo
->storage
= ArgInIReg
;
550 ainfo
->reg
= param_regs
[*gr
];
556 #define FLOAT_PARAM_REGS 4
558 #define FLOAT_PARAM_REGS 8
562 add_float (guint32
*gr
, guint32
*stack_size
, ArgInfo
*ainfo
, gboolean is_double
)
564 ainfo
->offset
= *stack_size
;
566 if (*gr
>= FLOAT_PARAM_REGS
) {
567 ainfo
->storage
= ArgOnStack
;
568 ainfo
->arg_size
= sizeof (mgreg_t
);
569 /* Since the same stack slot size is used for both float */
570 /* types, it needs to be big enough to hold them both */
571 (*stack_size
) += sizeof(mgreg_t
);
574 /* A double register */
576 ainfo
->storage
= ArgInDoubleSSEReg
;
578 ainfo
->storage
= ArgInFloatSSEReg
;
584 typedef enum ArgumentClass
{
592 merge_argument_class_from_type (MonoType
*type
, ArgumentClass class1
)
594 ArgumentClass class2
= ARG_CLASS_NO_CLASS
;
597 ptype
= mini_get_underlying_type (type
);
598 switch (ptype
->type
) {
607 case MONO_TYPE_STRING
:
608 case MONO_TYPE_OBJECT
:
609 case MONO_TYPE_CLASS
:
610 case MONO_TYPE_SZARRAY
:
612 case MONO_TYPE_FNPTR
:
613 case MONO_TYPE_ARRAY
:
616 class2
= ARG_CLASS_INTEGER
;
621 class2
= ARG_CLASS_INTEGER
;
623 class2
= ARG_CLASS_SSE
;
627 case MONO_TYPE_TYPEDBYREF
:
628 g_assert_not_reached ();
630 case MONO_TYPE_GENERICINST
:
631 if (!mono_type_generic_inst_is_valuetype (ptype
)) {
632 class2
= ARG_CLASS_INTEGER
;
636 case MONO_TYPE_VALUETYPE
: {
637 MonoMarshalType
*info
= mono_marshal_load_type_info (ptype
->data
.klass
);
640 for (i
= 0; i
< info
->num_fields
; ++i
) {
642 class2
= merge_argument_class_from_type (info
->fields
[i
].field
->type
, class2
);
647 g_assert_not_reached ();
651 if (class1
== class2
)
653 else if (class1
== ARG_CLASS_NO_CLASS
)
655 else if ((class1
== ARG_CLASS_MEMORY
) || (class2
== ARG_CLASS_MEMORY
))
656 class1
= ARG_CLASS_MEMORY
;
657 else if ((class1
== ARG_CLASS_INTEGER
) || (class2
== ARG_CLASS_INTEGER
))
658 class1
= ARG_CLASS_INTEGER
;
660 class1
= ARG_CLASS_SSE
;
664 #ifdef __native_client_codegen__
666 /* Default alignment for Native Client is 32-byte. */
667 gint8 nacl_align_byte
= -32; /* signed version of 0xe0 */
669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
670 /* Check that alignment doesn't cross an alignment boundary. */
672 mono_arch_nacl_pad(guint8
*code
, int pad
)
674 const int kMaxPadding
= 8; /* see amd64-codegen.h:amd64_padding_size() */
676 if (pad
== 0) return code
;
677 /* assertion: alignment cannot cross a block boundary */
678 g_assert (((uintptr_t)code
& (~kNaClAlignmentMask
)) ==
679 (((uintptr_t)code
+ pad
- 1) & (~kNaClAlignmentMask
)));
680 while (pad
>= kMaxPadding
) {
681 amd64_padding (code
, kMaxPadding
);
684 if (pad
!= 0) amd64_padding (code
, pad
);
690 count_fields_nested (MonoClass
*klass
)
692 MonoMarshalType
*info
;
695 info
= mono_marshal_load_type_info (klass
);
698 for (i
= 0; i
< info
->num_fields
; ++i
) {
699 if (MONO_TYPE_ISSTRUCT (info
->fields
[i
].field
->type
))
700 count
+= count_fields_nested (mono_class_from_mono_type (info
->fields
[i
].field
->type
));
708 collect_field_info_nested (MonoClass
*klass
, MonoMarshalField
*fields
, int index
, int offset
)
710 MonoMarshalType
*info
;
713 info
= mono_marshal_load_type_info (klass
);
715 for (i
= 0; i
< info
->num_fields
; ++i
) {
716 if (MONO_TYPE_ISSTRUCT (info
->fields
[i
].field
->type
)) {
717 index
= collect_field_info_nested (mono_class_from_mono_type (info
->fields
[i
].field
->type
), fields
, index
, info
->fields
[i
].offset
);
719 memcpy (&fields
[index
], &info
->fields
[i
], sizeof (MonoMarshalField
));
720 fields
[index
].offset
+= offset
;
729 add_valuetype_win64 (MonoMethodSignature
*sig
, ArgInfo
*ainfo
, MonoType
*type
,
731 guint32
*gr
, guint32
*fr
, guint32
*stack_size
)
733 guint32 size
, i
, nfields
;
735 ArgumentClass arg_class
;
736 MonoMarshalType
*info
= NULL
;
737 MonoMarshalField
*fields
= NULL
;
739 gboolean pass_on_stack
= FALSE
;
741 klass
= mono_class_from_mono_type (type
);
742 size
= mini_type_stack_size_full (&klass
->byval_arg
, NULL
, sig
->pinvoke
);
744 pass_on_stack
= TRUE
;
746 /* If this struct can't be split up naturally into 8-byte */
747 /* chunks (registers), pass it on the stack. */
748 if (sig
->pinvoke
&& !pass_on_stack
) {
752 info
= mono_marshal_load_type_info (klass
);
756 * Collect field information recursively to be able to
757 * handle nested structures.
759 nfields
= count_fields_nested (klass
);
760 fields
= g_new0 (MonoMarshalField
, nfields
);
761 collect_field_info_nested (klass
, fields
, 0, 0);
763 for (i
= 0; i
< nfields
; ++i
) {
764 field_size
= mono_marshal_type_size (fields
[i
].field
->type
,
766 &align
, TRUE
, klass
->unicode
);
767 if ((fields
[i
].offset
< 8) && (fields
[i
].offset
+ field_size
) > 8) {
768 pass_on_stack
= TRUE
;
775 /* Allways pass in memory */
776 ainfo
->offset
= *stack_size
;
777 *stack_size
+= ALIGN_TO (size
, 8);
778 ainfo
->storage
= is_return
? ArgValuetypeAddrInIReg
: ArgOnStack
;
780 ainfo
->arg_size
= ALIGN_TO (size
, 8);
787 int n
= mono_class_value_size (klass
, NULL
);
792 arg_class
= ARG_CLASS_MEMORY
;
794 /* Always pass in 1 integer register */
795 arg_class
= ARG_CLASS_INTEGER
;
800 ainfo
->storage
= ArgValuetypeInReg
;
801 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
805 switch (info
->native_size
) {
806 case 1: case 2: case 4: case 8:
810 ainfo
->storage
= ArgValuetypeAddrInIReg
;
811 ainfo
->offset
= *stack_size
;
812 *stack_size
+= ALIGN_TO (info
->native_size
, 8);
815 ainfo
->storage
= ArgValuetypeAddrInIReg
;
817 if (*gr
< PARAM_REGS
) {
818 ainfo
->pair_storage
[0] = ArgInIReg
;
819 ainfo
->pair_regs
[0] = param_regs
[*gr
];
823 ainfo
->pair_storage
[0] = ArgOnStack
;
824 ainfo
->offset
= *stack_size
;
825 ainfo
->arg_size
= sizeof (mgreg_t
);
836 ArgumentClass class1
;
839 class1
= ARG_CLASS_MEMORY
;
841 class1
= ARG_CLASS_NO_CLASS
;
842 for (i
= 0; i
< nfields
; ++i
) {
843 size
= mono_marshal_type_size (fields
[i
].field
->type
,
845 &align
, TRUE
, klass
->unicode
);
846 /* How far into this quad this data extends.*/
847 /* (8 is size of quad) */
848 argsize
= fields
[i
].offset
+ size
;
850 class1
= merge_argument_class_from_type (fields
[i
].field
->type
, class1
);
852 g_assert (class1
!= ARG_CLASS_NO_CLASS
);
858 /* Allocate registers */
863 while (argsize
!= 1 && argsize
!= 2 && argsize
!= 4 && argsize
!= 8)
866 ainfo
->storage
= ArgValuetypeInReg
;
867 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
868 ainfo
->pair_size
[0] = argsize
;
869 ainfo
->pair_size
[1] = 0;
872 case ARG_CLASS_INTEGER
:
873 if (*gr
>= PARAM_REGS
)
874 arg_class
= ARG_CLASS_MEMORY
;
876 ainfo
->pair_storage
[0] = ArgInIReg
;
878 ainfo
->pair_regs
[0] = return_regs
[*gr
];
880 ainfo
->pair_regs
[0] = param_regs
[*gr
];
885 if (*fr
>= FLOAT_PARAM_REGS
)
886 arg_class
= ARG_CLASS_MEMORY
;
889 ainfo
->pair_storage
[0] = ArgInFloatSSEReg
;
891 ainfo
->pair_storage
[0] = ArgInDoubleSSEReg
;
892 ainfo
->pair_regs
[0] = *fr
;
896 case ARG_CLASS_MEMORY
:
899 g_assert_not_reached ();
902 if (arg_class
== ARG_CLASS_MEMORY
) {
903 /* Revert possible register assignments */
907 ainfo
->offset
= *stack_size
;
908 *stack_size
+= sizeof (mgreg_t
);
909 ainfo
->storage
= is_return
? ArgValuetypeAddrInIReg
: ArgOnStack
;
911 ainfo
->arg_size
= sizeof (mgreg_t
);
915 #endif /* TARGET_WIN32 */
918 add_valuetype (MonoMethodSignature
*sig
, ArgInfo
*ainfo
, MonoType
*type
,
920 guint32
*gr
, guint32
*fr
, guint32
*stack_size
)
923 add_valuetype_win64 (sig
, ainfo
, type
, is_return
, gr
, fr
, stack_size
);
925 guint32 size
, quad
, nquads
, i
, nfields
;
926 /* Keep track of the size used in each quad so we can */
927 /* use the right size when copying args/return vars. */
928 guint32 quadsize
[2] = {8, 8};
929 ArgumentClass args
[2];
930 MonoMarshalType
*info
= NULL
;
931 MonoMarshalField
*fields
= NULL
;
933 gboolean pass_on_stack
= FALSE
;
935 klass
= mono_class_from_mono_type (type
);
936 size
= mini_type_stack_size_full (&klass
->byval_arg
, NULL
, sig
->pinvoke
);
937 if (!sig
->pinvoke
&& ((is_return
&& (size
== 8)) || (!is_return
&& (size
<= 16)))) {
938 /* We pass and return vtypes of size 8 in a register */
939 } else if (!sig
->pinvoke
|| (size
== 0) || (size
> 16)) {
940 pass_on_stack
= TRUE
;
943 /* If this struct can't be split up naturally into 8-byte */
944 /* chunks (registers), pass it on the stack. */
945 if (sig
->pinvoke
&& !pass_on_stack
) {
949 info
= mono_marshal_load_type_info (klass
);
953 * Collect field information recursively to be able to
954 * handle nested structures.
956 nfields
= count_fields_nested (klass
);
957 fields
= g_new0 (MonoMarshalField
, nfields
);
958 collect_field_info_nested (klass
, fields
, 0, 0);
960 for (i
= 0; i
< nfields
; ++i
) {
961 field_size
= mono_marshal_type_size (fields
[i
].field
->type
,
963 &align
, TRUE
, klass
->unicode
);
964 if ((fields
[i
].offset
< 8) && (fields
[i
].offset
+ field_size
) > 8) {
965 pass_on_stack
= TRUE
;
972 ainfo
->storage
= ArgValuetypeInReg
;
973 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
978 /* Allways pass in memory */
979 ainfo
->offset
= *stack_size
;
980 *stack_size
+= ALIGN_TO (size
, 8);
981 ainfo
->storage
= is_return
? ArgValuetypeAddrInIReg
: ArgOnStack
;
983 ainfo
->arg_size
= ALIGN_TO (size
, 8);
995 int n
= mono_class_value_size (klass
, NULL
);
997 quadsize
[0] = n
>= 8 ? 8 : n
;
998 quadsize
[1] = n
>= 8 ? MAX (n
- 8, 8) : 0;
1000 /* Always pass in 1 or 2 integer registers */
1001 args
[0] = ARG_CLASS_INTEGER
;
1002 args
[1] = ARG_CLASS_INTEGER
;
1003 /* Only the simplest cases are supported */
1004 if (is_return
&& nquads
!= 1) {
1005 args
[0] = ARG_CLASS_MEMORY
;
1006 args
[1] = ARG_CLASS_MEMORY
;
1010 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
1011 * The X87 and SSEUP stuff is left out since there are no such types in
1017 ainfo
->storage
= ArgValuetypeInReg
;
1018 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
1022 if (info
->native_size
> 16) {
1023 ainfo
->offset
= *stack_size
;
1024 *stack_size
+= ALIGN_TO (info
->native_size
, 8);
1025 ainfo
->storage
= is_return
? ArgValuetypeAddrInIReg
: ArgOnStack
;
1027 ainfo
->arg_size
= ALIGN_TO (info
->native_size
, 8);
1033 args
[0] = ARG_CLASS_NO_CLASS
;
1034 args
[1] = ARG_CLASS_NO_CLASS
;
1035 for (quad
= 0; quad
< nquads
; ++quad
) {
1038 ArgumentClass class1
;
1041 class1
= ARG_CLASS_MEMORY
;
1043 class1
= ARG_CLASS_NO_CLASS
;
1044 for (i
= 0; i
< nfields
; ++i
) {
1045 size
= mono_marshal_type_size (fields
[i
].field
->type
,
1047 &align
, TRUE
, klass
->unicode
);
1048 if ((fields
[i
].offset
< 8) && (fields
[i
].offset
+ size
) > 8) {
1049 /* Unaligned field */
1053 /* Skip fields in other quad */
1054 if ((quad
== 0) && (fields
[i
].offset
>= 8))
1056 if ((quad
== 1) && (fields
[i
].offset
< 8))
1059 /* How far into this quad this data extends.*/
1060 /* (8 is size of quad) */
1061 quadsize
[quad
] = fields
[i
].offset
+ size
- (quad
* 8);
1063 class1
= merge_argument_class_from_type (fields
[i
].field
->type
, class1
);
1065 g_assert (class1
!= ARG_CLASS_NO_CLASS
);
1066 args
[quad
] = class1
;
1072 /* Post merger cleanup */
1073 if ((args
[0] == ARG_CLASS_MEMORY
) || (args
[1] == ARG_CLASS_MEMORY
))
1074 args
[0] = args
[1] = ARG_CLASS_MEMORY
;
1076 /* Allocate registers */
1081 while (quadsize
[0] != 1 && quadsize
[0] != 2 && quadsize
[0] != 4 && quadsize
[0] != 8)
1083 while (quadsize
[1] != 0 && quadsize
[1] != 1 && quadsize
[1] != 2 && quadsize
[1] != 4 && quadsize
[1] != 8)
1086 ainfo
->storage
= ArgValuetypeInReg
;
1087 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
1088 g_assert (quadsize
[0] <= 8);
1089 g_assert (quadsize
[1] <= 8);
1090 ainfo
->pair_size
[0] = quadsize
[0];
1091 ainfo
->pair_size
[1] = quadsize
[1];
1092 ainfo
->nregs
= nquads
;
1093 for (quad
= 0; quad
< nquads
; ++quad
) {
1094 switch (args
[quad
]) {
1095 case ARG_CLASS_INTEGER
:
1096 if (*gr
>= PARAM_REGS
)
1097 args
[quad
] = ARG_CLASS_MEMORY
;
1099 ainfo
->pair_storage
[quad
] = ArgInIReg
;
1101 ainfo
->pair_regs
[quad
] = return_regs
[*gr
];
1103 ainfo
->pair_regs
[quad
] = param_regs
[*gr
];
1108 if (*fr
>= FLOAT_PARAM_REGS
)
1109 args
[quad
] = ARG_CLASS_MEMORY
;
1111 if (quadsize
[quad
] <= 4)
1112 ainfo
->pair_storage
[quad
] = ArgInFloatSSEReg
;
1113 else ainfo
->pair_storage
[quad
] = ArgInDoubleSSEReg
;
1114 ainfo
->pair_regs
[quad
] = *fr
;
1118 case ARG_CLASS_MEMORY
:
1121 g_assert_not_reached ();
1125 if ((args
[0] == ARG_CLASS_MEMORY
) || (args
[1] == ARG_CLASS_MEMORY
)) {
1127 /* Revert possible register assignments */
1131 ainfo
->offset
= *stack_size
;
1133 arg_size
= ALIGN_TO (info
->native_size
, 8);
1135 arg_size
= nquads
* sizeof(mgreg_t
);
1136 *stack_size
+= arg_size
;
1137 ainfo
->storage
= is_return
? ArgValuetypeAddrInIReg
: ArgOnStack
;
1139 ainfo
->arg_size
= arg_size
;
1142 #endif /* !TARGET_WIN32 */
1148 * Obtain information about a call according to the calling convention.
1149 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1150 * Draft Version 0.23" document for more information.
1153 get_call_info (MonoMemPool
*mp
, MonoMethodSignature
*sig
)
1155 guint32 i
, gr
, fr
, pstart
;
1157 int n
= sig
->hasthis
+ sig
->param_count
;
1158 guint32 stack_size
= 0;
1160 gboolean is_pinvoke
= sig
->pinvoke
;
1163 cinfo
= (CallInfo
*)mono_mempool_alloc0 (mp
, sizeof (CallInfo
) + (sizeof (ArgInfo
) * n
));
1165 cinfo
= (CallInfo
*)g_malloc0 (sizeof (CallInfo
) + (sizeof (ArgInfo
) * n
));
1173 /* Reserve space where the callee can save the argument registers */
1174 stack_size
= 4 * sizeof (mgreg_t
);
1178 ret_type
= mini_get_underlying_type (sig
->ret
);
1179 switch (ret_type
->type
) {
1189 case MONO_TYPE_FNPTR
:
1190 case MONO_TYPE_CLASS
:
1191 case MONO_TYPE_OBJECT
:
1192 case MONO_TYPE_SZARRAY
:
1193 case MONO_TYPE_ARRAY
:
1194 case MONO_TYPE_STRING
:
1195 cinfo
->ret
.storage
= ArgInIReg
;
1196 cinfo
->ret
.reg
= AMD64_RAX
;
1200 cinfo
->ret
.storage
= ArgInIReg
;
1201 cinfo
->ret
.reg
= AMD64_RAX
;
1204 cinfo
->ret
.storage
= ArgInFloatSSEReg
;
1205 cinfo
->ret
.reg
= AMD64_XMM0
;
1208 cinfo
->ret
.storage
= ArgInDoubleSSEReg
;
1209 cinfo
->ret
.reg
= AMD64_XMM0
;
1211 case MONO_TYPE_GENERICINST
:
1212 if (!mono_type_generic_inst_is_valuetype (ret_type
)) {
1213 cinfo
->ret
.storage
= ArgInIReg
;
1214 cinfo
->ret
.reg
= AMD64_RAX
;
1217 if (mini_is_gsharedvt_type (ret_type
)) {
1218 cinfo
->ret
.storage
= ArgValuetypeAddrInIReg
;
1219 cinfo
->ret
.is_gsharedvt_return_value
= 1;
1223 case MONO_TYPE_VALUETYPE
:
1224 case MONO_TYPE_TYPEDBYREF
: {
1225 guint32 tmp_gr
= 0, tmp_fr
= 0, tmp_stacksize
= 0;
1227 add_valuetype (sig
, &cinfo
->ret
, ret_type
, TRUE
, &tmp_gr
, &tmp_fr
, &tmp_stacksize
);
1228 g_assert (cinfo
->ret
.storage
!= ArgInIReg
);
1232 case MONO_TYPE_MVAR
:
1233 g_assert (mini_is_gsharedvt_type (ret_type
));
1234 cinfo
->ret
.storage
= ArgValuetypeAddrInIReg
;
1235 cinfo
->ret
.is_gsharedvt_return_value
= 1;
1237 case MONO_TYPE_VOID
:
1240 g_error ("Can't handle as return value 0x%x", ret_type
->type
);
1245 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1246 * the first argument, allowing 'this' to be always passed in the first arg reg.
1247 * Also do this if the first argument is a reference type, since virtual calls
1248 * are sometimes made using calli without sig->hasthis set, like in the delegate
1251 if (cinfo
->ret
.storage
== ArgValuetypeAddrInIReg
&& !is_pinvoke
&& (sig
->hasthis
|| (sig
->param_count
> 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig
->params
[0]))))) {
1253 add_general (&gr
, &stack_size
, cinfo
->args
+ 0);
1255 add_general (&gr
, &stack_size
, &cinfo
->args
[sig
->hasthis
+ 0]);
1258 add_general (&gr
, &stack_size
, &cinfo
->ret
);
1259 cinfo
->ret
.storage
= ArgValuetypeAddrInIReg
;
1260 cinfo
->vret_arg_index
= 1;
1264 add_general (&gr
, &stack_size
, cinfo
->args
+ 0);
1266 if (cinfo
->ret
.storage
== ArgValuetypeAddrInIReg
) {
1267 add_general (&gr
, &stack_size
, &cinfo
->ret
);
1268 cinfo
->ret
.storage
= ArgValuetypeAddrInIReg
;
1272 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
== 0)) {
1274 fr
= FLOAT_PARAM_REGS
;
1276 /* Emit the signature cookie just before the implicit arguments */
1277 add_general (&gr
, &stack_size
, &cinfo
->sig_cookie
);
1280 for (i
= pstart
; i
< sig
->param_count
; ++i
) {
1281 ArgInfo
*ainfo
= &cinfo
->args
[sig
->hasthis
+ i
];
1285 /* The float param registers and other param registers must be the same index on Windows x64.*/
1292 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (i
== sig
->sentinelpos
)) {
1293 /* We allways pass the sig cookie on the stack for simplicity */
1295 * Prevent implicit arguments + the sig cookie from being passed
1299 fr
= FLOAT_PARAM_REGS
;
1301 /* Emit the signature cookie just before the implicit arguments */
1302 add_general (&gr
, &stack_size
, &cinfo
->sig_cookie
);
1305 ptype
= mini_get_underlying_type (sig
->params
[i
]);
1306 switch (ptype
->type
) {
1309 add_general (&gr
, &stack_size
, ainfo
);
1313 add_general (&gr
, &stack_size
, ainfo
);
1317 add_general (&gr
, &stack_size
, ainfo
);
1322 case MONO_TYPE_FNPTR
:
1323 case MONO_TYPE_CLASS
:
1324 case MONO_TYPE_OBJECT
:
1325 case MONO_TYPE_STRING
:
1326 case MONO_TYPE_SZARRAY
:
1327 case MONO_TYPE_ARRAY
:
1328 add_general (&gr
, &stack_size
, ainfo
);
1330 case MONO_TYPE_GENERICINST
:
1331 if (!mono_type_generic_inst_is_valuetype (ptype
)) {
1332 add_general (&gr
, &stack_size
, ainfo
);
1335 if (mini_is_gsharedvt_variable_type (ptype
)) {
1336 /* gsharedvt arguments are passed by ref */
1337 add_general (&gr
, &stack_size
, ainfo
);
1338 if (ainfo
->storage
== ArgInIReg
)
1339 ainfo
->storage
= ArgGSharedVtInReg
;
1341 ainfo
->storage
= ArgGSharedVtOnStack
;
1345 case MONO_TYPE_VALUETYPE
:
1346 case MONO_TYPE_TYPEDBYREF
:
1347 add_valuetype (sig
, ainfo
, sig
->params
[i
], FALSE
, &gr
, &fr
, &stack_size
);
1352 add_general (&gr
, &stack_size
, ainfo
);
1355 add_float (&fr
, &stack_size
, ainfo
, FALSE
);
1358 add_float (&fr
, &stack_size
, ainfo
, TRUE
);
1361 case MONO_TYPE_MVAR
:
1362 /* gsharedvt arguments are passed by ref */
1363 g_assert (mini_is_gsharedvt_type (ptype
));
1364 add_general (&gr
, &stack_size
, ainfo
);
1365 if (ainfo
->storage
== ArgInIReg
)
1366 ainfo
->storage
= ArgGSharedVtInReg
;
1368 ainfo
->storage
= ArgGSharedVtOnStack
;
1371 g_assert_not_reached ();
1375 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
> 0) && (sig
->sentinelpos
== sig
->param_count
)) {
1377 fr
= FLOAT_PARAM_REGS
;
1379 /* Emit the signature cookie just before the implicit arguments */
1380 add_general (&gr
, &stack_size
, &cinfo
->sig_cookie
);
1383 cinfo
->stack_usage
= stack_size
;
1384 cinfo
->reg_usage
= gr
;
1385 cinfo
->freg_usage
= fr
;
1390 * mono_arch_get_argument_info:
1391 * @csig: a method signature
1392 * @param_count: the number of parameters to consider
1393 * @arg_info: an array to store the result infos
1395 * Gathers information on parameters such as size, alignment and
1396 * padding. arg_info should be large enought to hold param_count + 1 entries.
1398 * Returns the size of the argument area on the stack.
1401 mono_arch_get_argument_info (MonoMethodSignature
*csig
, int param_count
, MonoJitArgumentInfo
*arg_info
)
1404 CallInfo
*cinfo
= get_call_info (NULL
, csig
);
1405 guint32 args_size
= cinfo
->stack_usage
;
1407 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1408 if (csig
->hasthis
) {
1409 arg_info
[0].offset
= 0;
1412 for (k
= 0; k
< param_count
; k
++) {
1413 arg_info
[k
+ 1].offset
= ((k
+ csig
->hasthis
) * 8);
1415 arg_info
[k
+ 1].size
= 0;
1424 mono_arch_tail_call_supported (MonoCompile
*cfg
, MonoMethodSignature
*caller_sig
, MonoMethodSignature
*callee_sig
)
1428 MonoType
*callee_ret
;
1430 c1
= get_call_info (NULL
, caller_sig
);
1431 c2
= get_call_info (NULL
, callee_sig
);
1432 res
= c1
->stack_usage
>= c2
->stack_usage
;
1433 callee_ret
= mini_get_underlying_type (callee_sig
->ret
);
1434 if (callee_ret
&& MONO_TYPE_ISSTRUCT (callee_ret
) && c2
->ret
.storage
!= ArgValuetypeInReg
)
1435 /* An address on the callee's stack is passed as the first argument */
1445 * Initialize the cpu to execute managed code.
1448 mono_arch_cpu_init (void)
1453 /* spec compliance requires running with double precision */
1454 __asm__
__volatile__ ("fnstcw %0\n": "=m" (fpcw
));
1455 fpcw
&= ~X86_FPCW_PRECC_MASK
;
1456 fpcw
|= X86_FPCW_PREC_DOUBLE
;
1457 __asm__
__volatile__ ("fldcw %0\n": : "m" (fpcw
));
1458 __asm__
__volatile__ ("fnstcw %0\n": "=m" (fpcw
));
1460 /* TODO: This is crashing on Win64 right now.
1461 * _control87 (_PC_53, MCW_PC);
1467 * Initialize architecture specific code.
1470 mono_arch_init (void)
1472 mono_os_mutex_init_recursive (&mini_arch_mutex
);
1473 #if defined(__native_client_codegen__)
1474 mono_native_tls_alloc (&nacl_instruction_depth
, NULL
);
1475 mono_native_tls_set_value (nacl_instruction_depth
, (gpointer
)0);
1476 mono_native_tls_alloc (&nacl_rex_tag
, NULL
);
1477 mono_native_tls_alloc (&nacl_legacy_prefix_tag
, NULL
);
1480 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception
);
1481 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception
);
1482 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind
);
1483 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip
);
1484 #if defined(ENABLE_GSHAREDVT)
1485 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call
);
1489 bp_trampoline
= mini_get_breakpoint_trampoline ();
1493 * Cleanup architecture specific code.
1496 mono_arch_cleanup (void)
1498 mono_os_mutex_destroy (&mini_arch_mutex
);
1499 #if defined(__native_client_codegen__)
1500 mono_native_tls_free (nacl_instruction_depth
);
1501 mono_native_tls_free (nacl_rex_tag
);
1502 mono_native_tls_free (nacl_legacy_prefix_tag
);
1507 * This function returns the optimizations supported on this cpu.
1510 mono_arch_cpu_optimizations (guint32
*exclude_mask
)
1516 if (mono_hwcap_x86_has_cmov
) {
1517 opts
|= MONO_OPT_CMOV
;
1519 if (mono_hwcap_x86_has_fcmov
)
1520 opts
|= MONO_OPT_FCMOV
;
1522 *exclude_mask
|= MONO_OPT_FCMOV
;
1524 *exclude_mask
|= MONO_OPT_CMOV
;
1531 * This function test for all SSE functions supported.
1533 * Returns a bitmask corresponding to all supported versions.
1537 mono_arch_cpu_enumerate_simd_versions (void)
1539 guint32 sse_opts
= 0;
1541 if (mono_hwcap_x86_has_sse1
)
1542 sse_opts
|= SIMD_VERSION_SSE1
;
1544 if (mono_hwcap_x86_has_sse2
)
1545 sse_opts
|= SIMD_VERSION_SSE2
;
1547 if (mono_hwcap_x86_has_sse3
)
1548 sse_opts
|= SIMD_VERSION_SSE3
;
1550 if (mono_hwcap_x86_has_ssse3
)
1551 sse_opts
|= SIMD_VERSION_SSSE3
;
1553 if (mono_hwcap_x86_has_sse41
)
1554 sse_opts
|= SIMD_VERSION_SSE41
;
1556 if (mono_hwcap_x86_has_sse42
)
1557 sse_opts
|= SIMD_VERSION_SSE42
;
1559 if (mono_hwcap_x86_has_sse4a
)
1560 sse_opts
|= SIMD_VERSION_SSE4a
;
1568 mono_arch_get_allocatable_int_vars (MonoCompile
*cfg
)
1573 for (i
= 0; i
< cfg
->num_varinfo
; i
++) {
1574 MonoInst
*ins
= cfg
->varinfo
[i
];
1575 MonoMethodVar
*vmv
= MONO_VARINFO (cfg
, i
);
1578 if (vmv
->range
.first_use
.abs_pos
>= vmv
->range
.last_use
.abs_pos
)
1581 if ((ins
->flags
& (MONO_INST_IS_DEAD
|MONO_INST_VOLATILE
|MONO_INST_INDIRECT
)) ||
1582 (ins
->opcode
!= OP_LOCAL
&& ins
->opcode
!= OP_ARG
))
1585 if (mono_is_regsize_var (ins
->inst_vtype
)) {
1586 g_assert (MONO_VARINFO (cfg
, i
)->reg
== -1);
1587 g_assert (i
== vmv
->idx
);
1588 vars
= g_list_prepend (vars
, vmv
);
1592 vars
= mono_varlist_sort (cfg
, vars
, 0);
1598 * mono_arch_compute_omit_fp:
1600 * Determine whenever the frame pointer can be eliminated.
1603 mono_arch_compute_omit_fp (MonoCompile
*cfg
)
1605 MonoMethodSignature
*sig
;
1606 MonoMethodHeader
*header
;
1610 if (cfg
->arch
.omit_fp_computed
)
1613 header
= cfg
->header
;
1615 sig
= mono_method_signature (cfg
->method
);
1617 if (!cfg
->arch
.cinfo
)
1618 cfg
->arch
.cinfo
= get_call_info (cfg
->mempool
, sig
);
1619 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
1622 * FIXME: Remove some of the restrictions.
1624 cfg
->arch
.omit_fp
= TRUE
;
1625 cfg
->arch
.omit_fp_computed
= TRUE
;
1627 #ifdef __native_client_codegen__
1628 /* NaCl modules may not change the value of RBP, so it cannot be */
1629 /* used as a normal register, but it can be used as a frame pointer*/
1630 cfg
->disable_omit_fp
= TRUE
;
1631 cfg
->arch
.omit_fp
= FALSE
;
1634 if (cfg
->disable_omit_fp
)
1635 cfg
->arch
.omit_fp
= FALSE
;
1637 if (!debug_omit_fp ())
1638 cfg
->arch
.omit_fp
= FALSE
;
1640 if (cfg->method->save_lmf)
1641 cfg->arch.omit_fp = FALSE;
1643 if (cfg
->flags
& MONO_CFG_HAS_ALLOCA
)
1644 cfg
->arch
.omit_fp
= FALSE
;
1645 if (header
->num_clauses
)
1646 cfg
->arch
.omit_fp
= FALSE
;
1647 if (cfg
->param_area
)
1648 cfg
->arch
.omit_fp
= FALSE
;
1649 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
))
1650 cfg
->arch
.omit_fp
= FALSE
;
1651 if ((mono_jit_trace_calls
!= NULL
&& mono_trace_eval (cfg
->method
)) ||
1652 (cfg
->prof_options
& MONO_PROFILE_ENTER_LEAVE
))
1653 cfg
->arch
.omit_fp
= FALSE
;
1654 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
1655 ArgInfo
*ainfo
= &cinfo
->args
[i
];
1657 if (ainfo
->storage
== ArgOnStack
) {
1659 * The stack offset can only be determined when the frame
1662 cfg
->arch
.omit_fp
= FALSE
;
1667 for (i
= cfg
->locals_start
; i
< cfg
->num_varinfo
; i
++) {
1668 MonoInst
*ins
= cfg
->varinfo
[i
];
1671 locals_size
+= mono_type_size (ins
->inst_vtype
, &ialign
);
1676 mono_arch_get_global_int_regs (MonoCompile
*cfg
)
1680 mono_arch_compute_omit_fp (cfg
);
1682 if (cfg
->arch
.omit_fp
)
1683 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RBP
);
1685 /* We use the callee saved registers for global allocation */
1686 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RBX
);
1687 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R12
);
1688 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R13
);
1689 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R14
);
1690 #ifndef __native_client_codegen__
1691 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R15
);
1694 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RDI
);
1695 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RSI
);
1702 mono_arch_get_global_fp_regs (MonoCompile
*cfg
)
1707 /* All XMM registers */
1708 for (i
= 0; i
< 16; ++i
)
1709 regs
= g_list_prepend (regs
, GINT_TO_POINTER (i
));
1715 mono_arch_get_iregs_clobbered_by_call (MonoCallInst
*call
)
1717 static GList
*r
= NULL
;
1722 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RBP
);
1723 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RBX
);
1724 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R12
);
1725 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R13
);
1726 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R14
);
1727 #ifndef __native_client_codegen__
1728 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R15
);
1731 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R10
);
1732 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R9
);
1733 regs
= g_list_prepend (regs
, (gpointer
)AMD64_R8
);
1734 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RDI
);
1735 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RSI
);
1736 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RDX
);
1737 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RCX
);
1738 regs
= g_list_prepend (regs
, (gpointer
)AMD64_RAX
);
1740 InterlockedCompareExchangePointer ((gpointer
*)&r
, regs
, NULL
);
1747 mono_arch_get_fregs_clobbered_by_call (MonoCallInst
*call
)
1750 static GList
*r
= NULL
;
1755 for (i
= 0; i
< AMD64_XMM_NREG
; ++i
)
1756 regs
= g_list_prepend (regs
, GINT_TO_POINTER (MONO_MAX_IREGS
+ i
));
1758 InterlockedCompareExchangePointer ((gpointer
*)&r
, regs
, NULL
);
1765 * mono_arch_regalloc_cost:
1767 * Return the cost, in number of memory references, of the action of
1768 * allocating the variable VMV into a register during global register
1772 mono_arch_regalloc_cost (MonoCompile
*cfg
, MonoMethodVar
*vmv
)
1774 MonoInst
*ins
= cfg
->varinfo
[vmv
->idx
];
1776 if (cfg
->method
->save_lmf
)
1777 /* The register is already saved */
1778 /* substract 1 for the invisible store in the prolog */
1779 return (ins
->opcode
== OP_ARG
) ? 0 : 1;
1782 return (ins
->opcode
== OP_ARG
) ? 1 : 2;
1786 * mono_arch_fill_argument_info:
1788 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1792 mono_arch_fill_argument_info (MonoCompile
*cfg
)
1795 MonoMethodSignature
*sig
;
1800 sig
= mono_method_signature (cfg
->method
);
1802 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
1803 sig_ret
= mini_get_underlying_type (sig
->ret
);
1806 * Contrary to mono_arch_allocate_vars (), the information should describe
1807 * where the arguments are at the beginning of the method, not where they can be
1808 * accessed during the execution of the method. The later makes no sense for the
1809 * global register allocator, since a variable can be in more than one location.
1811 switch (cinfo
->ret
.storage
) {
1813 case ArgInFloatSSEReg
:
1814 case ArgInDoubleSSEReg
:
1815 cfg
->ret
->opcode
= OP_REGVAR
;
1816 cfg
->ret
->inst_c0
= cinfo
->ret
.reg
;
1818 case ArgValuetypeInReg
:
1819 cfg
->ret
->opcode
= OP_REGOFFSET
;
1820 cfg
->ret
->inst_basereg
= -1;
1821 cfg
->ret
->inst_offset
= -1;
1826 g_assert_not_reached ();
1829 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
1830 ArgInfo
*ainfo
= &cinfo
->args
[i
];
1832 ins
= cfg
->args
[i
];
1834 switch (ainfo
->storage
) {
1836 case ArgInFloatSSEReg
:
1837 case ArgInDoubleSSEReg
:
1838 ins
->opcode
= OP_REGVAR
;
1839 ins
->inst_c0
= ainfo
->reg
;
1842 ins
->opcode
= OP_REGOFFSET
;
1843 ins
->inst_basereg
= -1;
1844 ins
->inst_offset
= -1;
1846 case ArgValuetypeInReg
:
1848 ins
->opcode
= OP_NOP
;
1851 g_assert_not_reached ();
1857 mono_arch_allocate_vars (MonoCompile
*cfg
)
1860 MonoMethodSignature
*sig
;
1863 guint32 locals_stack_size
, locals_stack_align
;
1867 sig
= mono_method_signature (cfg
->method
);
1869 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
1870 sig_ret
= mini_get_underlying_type (sig
->ret
);
1872 mono_arch_compute_omit_fp (cfg
);
1875 * We use the ABI calling conventions for managed code as well.
1876 * Exception: valuetypes are only sometimes passed or returned in registers.
1880 * The stack looks like this:
1881 * <incoming arguments passed on the stack>
1883 * <lmf/caller saved registers>
1886 * <localloc area> -> grows dynamically
1890 if (cfg
->arch
.omit_fp
) {
1891 cfg
->flags
|= MONO_CFG_HAS_SPILLUP
;
1892 cfg
->frame_reg
= AMD64_RSP
;
1895 /* Locals are allocated backwards from %fp */
1896 cfg
->frame_reg
= AMD64_RBP
;
1900 cfg
->arch
.saved_iregs
= cfg
->used_int_regs
;
1901 if (cfg
->method
->save_lmf
)
1902 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1903 cfg
->arch
.saved_iregs
|= (1 << AMD64_RBX
) | (1 << AMD64_R12
) | (1 << AMD64_R13
) | (1 << AMD64_R14
) | (1 << AMD64_R15
);
1905 if (cfg
->arch
.omit_fp
)
1906 cfg
->arch
.reg_save_area_offset
= offset
;
1907 /* Reserve space for callee saved registers */
1908 for (i
= 0; i
< AMD64_NREG
; ++i
)
1909 if (AMD64_IS_CALLEE_SAVED_REG (i
) && (cfg
->arch
.saved_iregs
& (1 << i
))) {
1910 offset
+= sizeof(mgreg_t
);
1912 if (!cfg
->arch
.omit_fp
)
1913 cfg
->arch
.reg_save_area_offset
= -offset
;
1915 if (sig_ret
->type
!= MONO_TYPE_VOID
) {
1916 switch (cinfo
->ret
.storage
) {
1918 case ArgInFloatSSEReg
:
1919 case ArgInDoubleSSEReg
:
1920 cfg
->ret
->opcode
= OP_REGVAR
;
1921 cfg
->ret
->inst_c0
= cinfo
->ret
.reg
;
1922 cfg
->ret
->dreg
= cinfo
->ret
.reg
;
1924 case ArgValuetypeAddrInIReg
:
1925 /* The register is volatile */
1926 cfg
->vret_addr
->opcode
= OP_REGOFFSET
;
1927 cfg
->vret_addr
->inst_basereg
= cfg
->frame_reg
;
1928 if (cfg
->arch
.omit_fp
) {
1929 cfg
->vret_addr
->inst_offset
= offset
;
1933 cfg
->vret_addr
->inst_offset
= -offset
;
1935 if (G_UNLIKELY (cfg
->verbose_level
> 1)) {
1936 printf ("vret_addr =");
1937 mono_print_ins (cfg
->vret_addr
);
1940 case ArgValuetypeInReg
:
1941 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1942 cfg
->ret
->opcode
= OP_REGOFFSET
;
1943 cfg
->ret
->inst_basereg
= cfg
->frame_reg
;
1944 if (cfg
->arch
.omit_fp
) {
1945 cfg
->ret
->inst_offset
= offset
;
1946 offset
+= cinfo
->ret
.pair_storage
[1] == ArgNone
? 8 : 16;
1948 offset
+= cinfo
->ret
.pair_storage
[1] == ArgNone
? 8 : 16;
1949 cfg
->ret
->inst_offset
= - offset
;
1953 g_assert_not_reached ();
1957 /* Allocate locals */
1958 offsets
= mono_allocate_stack_slots (cfg
, cfg
->arch
.omit_fp
? FALSE
: TRUE
, &locals_stack_size
, &locals_stack_align
);
1959 if (locals_stack_size
> MONO_ARCH_MAX_FRAME_SIZE
) {
1960 char *mname
= mono_method_full_name (cfg
->method
, TRUE
);
1961 mono_cfg_set_exception_invalid_program (cfg
, g_strdup_printf ("Method %s stack is too big.", mname
));
1966 if (locals_stack_align
) {
1967 offset
+= (locals_stack_align
- 1);
1968 offset
&= ~(locals_stack_align
- 1);
1970 if (cfg
->arch
.omit_fp
) {
1971 cfg
->locals_min_stack_offset
= offset
;
1972 cfg
->locals_max_stack_offset
= offset
+ locals_stack_size
;
1974 cfg
->locals_min_stack_offset
= - (offset
+ locals_stack_size
);
1975 cfg
->locals_max_stack_offset
= - offset
;
1978 for (i
= cfg
->locals_start
; i
< cfg
->num_varinfo
; i
++) {
1979 if (offsets
[i
] != -1) {
1980 MonoInst
*ins
= cfg
->varinfo
[i
];
1981 ins
->opcode
= OP_REGOFFSET
;
1982 ins
->inst_basereg
= cfg
->frame_reg
;
1983 if (cfg
->arch
.omit_fp
)
1984 ins
->inst_offset
= (offset
+ offsets
[i
]);
1986 ins
->inst_offset
= - (offset
+ offsets
[i
]);
1987 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1990 offset
+= locals_stack_size
;
1992 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
)) {
1993 g_assert (!cfg
->arch
.omit_fp
);
1994 g_assert (cinfo
->sig_cookie
.storage
== ArgOnStack
);
1995 cfg
->sig_cookie
= cinfo
->sig_cookie
.offset
+ ARGS_OFFSET
;
1998 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
1999 ins
= cfg
->args
[i
];
2000 if (ins
->opcode
!= OP_REGVAR
) {
2001 ArgInfo
*ainfo
= &cinfo
->args
[i
];
2002 gboolean inreg
= TRUE
;
2004 /* FIXME: Allocate volatile arguments to registers */
2005 if (ins
->flags
& (MONO_INST_VOLATILE
|MONO_INST_INDIRECT
))
2009 * Under AMD64, all registers used to pass arguments to functions
2010 * are volatile across calls.
2011 * FIXME: Optimize this.
2013 if ((ainfo
->storage
== ArgInIReg
) || (ainfo
->storage
== ArgInFloatSSEReg
) || (ainfo
->storage
== ArgInDoubleSSEReg
) || (ainfo
->storage
== ArgValuetypeInReg
) || (ainfo
->storage
== ArgGSharedVtInReg
))
2016 ins
->opcode
= OP_REGOFFSET
;
2018 switch (ainfo
->storage
) {
2020 case ArgInFloatSSEReg
:
2021 case ArgInDoubleSSEReg
:
2022 case ArgGSharedVtInReg
:
2024 ins
->opcode
= OP_REGVAR
;
2025 ins
->dreg
= ainfo
->reg
;
2029 case ArgGSharedVtOnStack
:
2030 g_assert (!cfg
->arch
.omit_fp
);
2031 ins
->opcode
= OP_REGOFFSET
;
2032 ins
->inst_basereg
= cfg
->frame_reg
;
2033 ins
->inst_offset
= ainfo
->offset
+ ARGS_OFFSET
;
2035 case ArgValuetypeInReg
:
2037 case ArgValuetypeAddrInIReg
: {
2039 g_assert (!cfg
->arch
.omit_fp
);
2041 MONO_INST_NEW (cfg
, indir
, 0);
2042 indir
->opcode
= OP_REGOFFSET
;
2043 if (ainfo
->pair_storage
[0] == ArgInIReg
) {
2044 indir
->inst_basereg
= cfg
->frame_reg
;
2045 offset
= ALIGN_TO (offset
, sizeof (gpointer
));
2046 offset
+= (sizeof (gpointer
));
2047 indir
->inst_offset
= - offset
;
2050 indir
->inst_basereg
= cfg
->frame_reg
;
2051 indir
->inst_offset
= ainfo
->offset
+ ARGS_OFFSET
;
2054 ins
->opcode
= OP_VTARG_ADDR
;
2055 ins
->inst_left
= indir
;
2063 if (!inreg
&& (ainfo
->storage
!= ArgOnStack
) && (ainfo
->storage
!= ArgValuetypeAddrInIReg
) && (ainfo
->storage
!= ArgGSharedVtOnStack
)) {
2064 ins
->opcode
= OP_REGOFFSET
;
2065 ins
->inst_basereg
= cfg
->frame_reg
;
2066 /* These arguments are saved to the stack in the prolog */
2067 offset
= ALIGN_TO (offset
, sizeof(mgreg_t
));
2068 if (cfg
->arch
.omit_fp
) {
2069 ins
->inst_offset
= offset
;
2070 offset
+= (ainfo
->storage
== ArgValuetypeInReg
) ? ainfo
->nregs
* sizeof (mgreg_t
) : sizeof (mgreg_t
);
2071 // Arguments are yet supported by the stack map creation code
2072 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2074 offset
+= (ainfo
->storage
== ArgValuetypeInReg
) ? ainfo
->nregs
* sizeof (mgreg_t
) : sizeof (mgreg_t
);
2075 ins
->inst_offset
= - offset
;
2076 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2082 cfg
->stack_offset
= offset
;
2086 mono_arch_create_vars (MonoCompile
*cfg
)
2088 MonoMethodSignature
*sig
;
2092 sig
= mono_method_signature (cfg
->method
);
2094 if (!cfg
->arch
.cinfo
)
2095 cfg
->arch
.cinfo
= get_call_info (cfg
->mempool
, sig
);
2096 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
2098 if (cinfo
->ret
.storage
== ArgValuetypeInReg
)
2099 cfg
->ret_var_is_local
= TRUE
;
2101 sig_ret
= mini_get_underlying_type (sig
->ret
);
2102 if (cinfo
->ret
.storage
== ArgValuetypeAddrInIReg
) {
2103 cfg
->vret_addr
= mono_compile_create_var (cfg
, &mono_defaults
.int_class
->byval_arg
, OP_ARG
);
2104 if (G_UNLIKELY (cfg
->verbose_level
> 1)) {
2105 printf ("vret_addr = ");
2106 mono_print_ins (cfg
->vret_addr
);
2110 if (cfg
->gen_sdb_seq_points
) {
2113 if (cfg
->compile_aot
) {
2114 MonoInst
*ins
= mono_compile_create_var (cfg
, &mono_defaults
.int_class
->byval_arg
, OP_LOCAL
);
2115 ins
->flags
|= MONO_INST_VOLATILE
;
2116 cfg
->arch
.seq_point_info_var
= ins
;
2118 ins
= mono_compile_create_var (cfg
, &mono_defaults
.int_class
->byval_arg
, OP_LOCAL
);
2119 ins
->flags
|= MONO_INST_VOLATILE
;
2120 cfg
->arch
.ss_tramp_var
= ins
;
2122 ins
= mono_compile_create_var (cfg
, &mono_defaults
.int_class
->byval_arg
, OP_LOCAL
);
2123 ins
->flags
|= MONO_INST_VOLATILE
;
2124 cfg
->arch
.bp_tramp_var
= ins
;
2127 if (cfg
->method
->save_lmf
)
2128 cfg
->create_lmf_var
= TRUE
;
2130 if (cfg
->method
->save_lmf
) {
2132 #if !defined(TARGET_WIN32)
2133 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen
)
2134 cfg
->lmf_ir_mono_lmf
= TRUE
;
2140 add_outarg_reg (MonoCompile
*cfg
, MonoCallInst
*call
, ArgStorage storage
, int reg
, MonoInst
*tree
)
2146 MONO_INST_NEW (cfg
, ins
, OP_MOVE
);
2147 ins
->dreg
= mono_alloc_ireg_copy (cfg
, tree
->dreg
);
2148 ins
->sreg1
= tree
->dreg
;
2149 MONO_ADD_INS (cfg
->cbb
, ins
);
2150 mono_call_inst_add_outarg_reg (cfg
, call
, ins
->dreg
, reg
, FALSE
);
2152 case ArgInFloatSSEReg
:
2153 MONO_INST_NEW (cfg
, ins
, OP_AMD64_SET_XMMREG_R4
);
2154 ins
->dreg
= mono_alloc_freg (cfg
);
2155 ins
->sreg1
= tree
->dreg
;
2156 MONO_ADD_INS (cfg
->cbb
, ins
);
2158 mono_call_inst_add_outarg_reg (cfg
, call
, ins
->dreg
, reg
, TRUE
);
2160 case ArgInDoubleSSEReg
:
2161 MONO_INST_NEW (cfg
, ins
, OP_FMOVE
);
2162 ins
->dreg
= mono_alloc_freg (cfg
);
2163 ins
->sreg1
= tree
->dreg
;
2164 MONO_ADD_INS (cfg
->cbb
, ins
);
2166 mono_call_inst_add_outarg_reg (cfg
, call
, ins
->dreg
, reg
, TRUE
);
2170 g_assert_not_reached ();
2175 arg_storage_to_load_membase (ArgStorage storage
)
2179 #if defined(__mono_ilp32__)
2180 return OP_LOADI8_MEMBASE
;
2182 return OP_LOAD_MEMBASE
;
2184 case ArgInDoubleSSEReg
:
2185 return OP_LOADR8_MEMBASE
;
2186 case ArgInFloatSSEReg
:
2187 return OP_LOADR4_MEMBASE
;
2189 g_assert_not_reached ();
2196 emit_sig_cookie (MonoCompile
*cfg
, MonoCallInst
*call
, CallInfo
*cinfo
)
2198 MonoMethodSignature
*tmp_sig
;
2201 if (call
->tail_call
)
2204 g_assert (cinfo
->sig_cookie
.storage
== ArgOnStack
);
2207 * mono_ArgIterator_Setup assumes the signature cookie is
2208 * passed first and all the arguments which were before it are
2209 * passed on the stack after the signature. So compensate by
2210 * passing a different signature.
2212 tmp_sig
= mono_metadata_signature_dup_full (cfg
->method
->klass
->image
, call
->signature
);
2213 tmp_sig
->param_count
-= call
->signature
->sentinelpos
;
2214 tmp_sig
->sentinelpos
= 0;
2215 memcpy (tmp_sig
->params
, call
->signature
->params
+ call
->signature
->sentinelpos
, tmp_sig
->param_count
* sizeof (MonoType
*));
2217 sig_reg
= mono_alloc_ireg (cfg
);
2218 MONO_EMIT_NEW_SIGNATURECONST (cfg
, sig_reg
, tmp_sig
);
2220 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, cinfo
->sig_cookie
.offset
, sig_reg
);
2224 static inline LLVMArgStorage
2225 arg_storage_to_llvm_arg_storage (MonoCompile
*cfg
, ArgStorage storage
)
2229 return LLVMArgInIReg
;
2232 case ArgGSharedVtInReg
:
2233 case ArgGSharedVtOnStack
:
2234 return LLVMArgGSharedVt
;
2236 g_assert_not_reached ();
2242 mono_arch_get_llvm_call_info (MonoCompile
*cfg
, MonoMethodSignature
*sig
)
2248 LLVMCallInfo
*linfo
;
2249 MonoType
*t
, *sig_ret
;
2251 n
= sig
->param_count
+ sig
->hasthis
;
2252 sig_ret
= mini_get_underlying_type (sig
->ret
);
2254 cinfo
= get_call_info (cfg
->mempool
, sig
);
2256 linfo
= mono_mempool_alloc0 (cfg
->mempool
, sizeof (LLVMCallInfo
) + (sizeof (LLVMArgInfo
) * n
));
2259 * LLVM always uses the native ABI while we use our own ABI, the
2260 * only difference is the handling of vtypes:
2261 * - we only pass/receive them in registers in some cases, and only
2262 * in 1 or 2 integer registers.
2264 switch (cinfo
->ret
.storage
) {
2266 linfo
->ret
.storage
= LLVMArgNone
;
2269 case ArgInFloatSSEReg
:
2270 case ArgInDoubleSSEReg
:
2271 linfo
->ret
.storage
= LLVMArgNormal
;
2273 case ArgValuetypeInReg
: {
2274 ainfo
= &cinfo
->ret
;
2277 (ainfo
->pair_storage
[0] == ArgInFloatSSEReg
|| ainfo
->pair_storage
[0] == ArgInDoubleSSEReg
||
2278 ainfo
->pair_storage
[1] == ArgInFloatSSEReg
|| ainfo
->pair_storage
[1] == ArgInDoubleSSEReg
)) {
2279 cfg
->exception_message
= g_strdup ("pinvoke + vtype ret");
2280 cfg
->disable_llvm
= TRUE
;
2284 linfo
->ret
.storage
= LLVMArgVtypeInReg
;
2285 for (j
= 0; j
< 2; ++j
)
2286 linfo
->ret
.pair_storage
[j
] = arg_storage_to_llvm_arg_storage (cfg
, ainfo
->pair_storage
[j
]);
2289 case ArgValuetypeAddrInIReg
:
2290 /* Vtype returned using a hidden argument */
2291 linfo
->ret
.storage
= LLVMArgVtypeRetAddr
;
2292 linfo
->vret_arg_index
= cinfo
->vret_arg_index
;
2295 g_assert_not_reached ();
2299 for (i
= 0; i
< n
; ++i
) {
2300 ainfo
= cinfo
->args
+ i
;
2302 if (i
>= sig
->hasthis
)
2303 t
= sig
->params
[i
- sig
->hasthis
];
2305 t
= &mono_defaults
.int_class
->byval_arg
;
2307 linfo
->args
[i
].storage
= LLVMArgNone
;
2309 switch (ainfo
->storage
) {
2311 linfo
->args
[i
].storage
= LLVMArgNormal
;
2313 case ArgInDoubleSSEReg
:
2314 case ArgInFloatSSEReg
:
2315 linfo
->args
[i
].storage
= LLVMArgNormal
;
2318 if (MONO_TYPE_ISSTRUCT (t
))
2319 linfo
->args
[i
].storage
= LLVMArgVtypeByVal
;
2321 linfo
->args
[i
].storage
= LLVMArgNormal
;
2323 case ArgValuetypeInReg
:
2325 (ainfo
->pair_storage
[0] == ArgInFloatSSEReg
|| ainfo
->pair_storage
[0] == ArgInDoubleSSEReg
||
2326 ainfo
->pair_storage
[1] == ArgInFloatSSEReg
|| ainfo
->pair_storage
[1] == ArgInDoubleSSEReg
)) {
2327 cfg
->exception_message
= g_strdup ("pinvoke + vtypes");
2328 cfg
->disable_llvm
= TRUE
;
2332 linfo
->args
[i
].storage
= LLVMArgVtypeInReg
;
2333 for (j
= 0; j
< 2; ++j
)
2334 linfo
->args
[i
].pair_storage
[j
] = arg_storage_to_llvm_arg_storage (cfg
, ainfo
->pair_storage
[j
]);
2336 case ArgGSharedVtInReg
:
2337 case ArgGSharedVtOnStack
:
2338 linfo
->args
[i
].storage
= LLVMArgGSharedVt
;
2341 cfg
->exception_message
= g_strdup ("ainfo->storage");
2342 cfg
->disable_llvm
= TRUE
;
2352 mono_arch_emit_call (MonoCompile
*cfg
, MonoCallInst
*call
)
2355 MonoMethodSignature
*sig
;
2361 sig
= call
->signature
;
2362 n
= sig
->param_count
+ sig
->hasthis
;
2364 cinfo
= get_call_info (cfg
->mempool
, sig
);
2368 if (COMPILE_LLVM (cfg
)) {
2369 /* We shouldn't be called in the llvm case */
2370 cfg
->disable_llvm
= TRUE
;
2375 * Emit all arguments which are passed on the stack to prevent register
2376 * allocation problems.
2378 for (i
= 0; i
< n
; ++i
) {
2380 ainfo
= cinfo
->args
+ i
;
2382 in
= call
->args
[i
];
2384 if (sig
->hasthis
&& i
== 0)
2385 t
= &mono_defaults
.object_class
->byval_arg
;
2387 t
= sig
->params
[i
- sig
->hasthis
];
2389 t
= mini_get_underlying_type (t
);
2390 //XXX what about ArgGSharedVtOnStack here?
2391 if (ainfo
->storage
== ArgOnStack
&& !MONO_TYPE_ISSTRUCT (t
) && !call
->tail_call
) {
2393 if (t
->type
== MONO_TYPE_R4
)
2394 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORER4_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, in
->dreg
);
2395 else if (t
->type
== MONO_TYPE_R8
)
2396 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORER8_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, in
->dreg
);
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, in
->dreg
);
2400 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, in
->dreg
);
2402 if (cfg
->compute_gc_maps
) {
2405 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg
, def
, ainfo
->offset
, t
);
2411 * Emit all parameters passed in registers in non-reverse order for better readability
2412 * and to help the optimization in emit_prolog ().
2414 for (i
= 0; i
< n
; ++i
) {
2415 ainfo
= cinfo
->args
+ i
;
2417 in
= call
->args
[i
];
2419 if (ainfo
->storage
== ArgInIReg
)
2420 add_outarg_reg (cfg
, call
, ainfo
->storage
, ainfo
->reg
, in
);
2423 for (i
= n
- 1; i
>= 0; --i
) {
2426 ainfo
= cinfo
->args
+ i
;
2428 in
= call
->args
[i
];
2430 if (sig
->hasthis
&& i
== 0)
2431 t
= &mono_defaults
.object_class
->byval_arg
;
2433 t
= sig
->params
[i
- sig
->hasthis
];
2434 t
= mini_get_underlying_type (t
);
2436 switch (ainfo
->storage
) {
2440 case ArgInFloatSSEReg
:
2441 case ArgInDoubleSSEReg
:
2442 add_outarg_reg (cfg
, call
, ainfo
->storage
, ainfo
->reg
, in
);
2445 case ArgValuetypeInReg
:
2446 case ArgValuetypeAddrInIReg
:
2447 case ArgGSharedVtInReg
:
2448 case ArgGSharedVtOnStack
: {
2449 if (ainfo
->storage
== ArgOnStack
&& !MONO_TYPE_ISSTRUCT (t
) && !call
->tail_call
)
2450 /* Already emitted above */
2452 //FIXME what about ArgGSharedVtOnStack ?
2453 if (ainfo
->storage
== ArgOnStack
&& call
->tail_call
) {
2454 MonoInst
*call_inst
= (MonoInst
*)call
;
2455 cfg
->args
[i
]->flags
|= MONO_INST_VOLATILE
;
2456 EMIT_NEW_ARGSTORE (cfg
, call_inst
, i
, in
);
2464 size
= mono_type_native_stack_size (t
, &align
);
2467 * Other backends use mono_type_stack_size (), but that
2468 * aligns the size to 8, which is larger than the size of
2469 * the source, leading to reads of invalid memory if the
2470 * source is at the end of address space.
2472 size
= mono_class_value_size (mono_class_from_mono_type (t
), &align
);
2475 if (size
>= 10000) {
2476 /* Avoid asserts in emit_memcpy () */
2477 mono_cfg_set_exception_invalid_program (cfg
, g_strdup_printf ("Passing an argument of size '%d'.", size
));
2478 /* Continue normally */
2482 MONO_INST_NEW (cfg
, arg
, OP_OUTARG_VT
);
2483 arg
->sreg1
= in
->dreg
;
2484 arg
->klass
= mono_class_from_mono_type (t
);
2485 arg
->backend
.size
= size
;
2486 arg
->inst_p0
= call
;
2487 arg
->inst_p1
= mono_mempool_alloc (cfg
->mempool
, sizeof (ArgInfo
));
2488 memcpy (arg
->inst_p1
, ainfo
, sizeof (ArgInfo
));
2490 MONO_ADD_INS (cfg
->cbb
, arg
);
2495 g_assert_not_reached ();
2498 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (i
== sig
->sentinelpos
))
2499 /* Emit the signature cookie just before the implicit arguments */
2500 emit_sig_cookie (cfg
, call
, cinfo
);
2503 /* Handle the case where there are no implicit arguments */
2504 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
== sig
->sentinelpos
))
2505 emit_sig_cookie (cfg
, call
, cinfo
);
2507 switch (cinfo
->ret
.storage
) {
2508 case ArgValuetypeInReg
:
2509 if (cinfo
->ret
.pair_storage
[0] == ArgInIReg
&& cinfo
->ret
.pair_storage
[1] == ArgNone
) {
2511 * Tell the JIT to use a more efficient calling convention: call using
2512 * OP_CALL, compute the result location after the call, and save the
2515 call
->vret_in_reg
= TRUE
;
2517 * Nullify the instruction computing the vret addr to enable
2518 * future optimizations.
2521 NULLIFY_INS (call
->vret_var
);
2523 if (call
->tail_call
)
2526 * The valuetype is in RAX:RDX after the call, need to be copied to
2527 * the stack. Push the address here, so the call instruction can
2530 if (!cfg
->arch
.vret_addr_loc
) {
2531 cfg
->arch
.vret_addr_loc
= mono_compile_create_var (cfg
, &mono_defaults
.int_class
->byval_arg
, OP_LOCAL
);
2532 /* Prevent it from being register allocated or optimized away */
2533 ((MonoInst
*)cfg
->arch
.vret_addr_loc
)->flags
|= MONO_INST_VOLATILE
;
2536 MONO_EMIT_NEW_UNALU (cfg
, OP_MOVE
, ((MonoInst
*)cfg
->arch
.vret_addr_loc
)->dreg
, call
->vret_var
->dreg
);
2539 case ArgValuetypeAddrInIReg
: {
2541 MONO_INST_NEW (cfg
, vtarg
, OP_MOVE
);
2542 vtarg
->sreg1
= call
->vret_var
->dreg
;
2543 vtarg
->dreg
= mono_alloc_preg (cfg
);
2544 MONO_ADD_INS (cfg
->cbb
, vtarg
);
2546 mono_call_inst_add_outarg_reg (cfg
, call
, vtarg
->dreg
, cinfo
->ret
.reg
, FALSE
);
2553 if (cfg
->method
->save_lmf
) {
2554 MONO_INST_NEW (cfg
, arg
, OP_AMD64_SAVE_SP_TO_LMF
);
2555 MONO_ADD_INS (cfg
->cbb
, arg
);
2558 call
->stack_usage
= cinfo
->stack_usage
;
2562 mono_arch_emit_outarg_vt (MonoCompile
*cfg
, MonoInst
*ins
, MonoInst
*src
)
2565 MonoCallInst
*call
= (MonoCallInst
*)ins
->inst_p0
;
2566 ArgInfo
*ainfo
= (ArgInfo
*)ins
->inst_p1
;
2567 int size
= ins
->backend
.size
;
2569 switch (ainfo
->storage
) {
2570 case ArgValuetypeInReg
: {
2574 for (part
= 0; part
< 2; ++part
) {
2575 if (ainfo
->pair_storage
[part
] == ArgNone
)
2578 MONO_INST_NEW (cfg
, load
, arg_storage_to_load_membase (ainfo
->pair_storage
[part
]));
2579 load
->inst_basereg
= src
->dreg
;
2580 load
->inst_offset
= part
* sizeof(mgreg_t
);
2582 switch (ainfo
->pair_storage
[part
]) {
2584 load
->dreg
= mono_alloc_ireg (cfg
);
2586 case ArgInDoubleSSEReg
:
2587 case ArgInFloatSSEReg
:
2588 load
->dreg
= mono_alloc_freg (cfg
);
2591 g_assert_not_reached ();
2593 MONO_ADD_INS (cfg
->cbb
, load
);
2595 add_outarg_reg (cfg
, call
, ainfo
->pair_storage
[part
], ainfo
->pair_regs
[part
], load
);
2599 case ArgValuetypeAddrInIReg
: {
2600 MonoInst
*vtaddr
, *load
;
2601 vtaddr
= mono_compile_create_var (cfg
, &ins
->klass
->byval_arg
, OP_LOCAL
);
2603 MONO_INST_NEW (cfg
, load
, OP_LDADDR
);
2604 cfg
->has_indirection
= TRUE
;
2605 load
->inst_p0
= vtaddr
;
2606 vtaddr
->flags
|= MONO_INST_INDIRECT
;
2607 load
->type
= STACK_MP
;
2608 load
->klass
= vtaddr
->klass
;
2609 load
->dreg
= mono_alloc_ireg (cfg
);
2610 MONO_ADD_INS (cfg
->cbb
, load
);
2611 mini_emit_memcpy (cfg
, load
->dreg
, 0, src
->dreg
, 0, size
, 4);
2613 if (ainfo
->pair_storage
[0] == ArgInIReg
) {
2614 MONO_INST_NEW (cfg
, arg
, OP_X86_LEA_MEMBASE
);
2615 arg
->dreg
= mono_alloc_ireg (cfg
);
2616 arg
->sreg1
= load
->dreg
;
2618 MONO_ADD_INS (cfg
->cbb
, arg
);
2619 mono_call_inst_add_outarg_reg (cfg
, call
, arg
->dreg
, ainfo
->pair_regs
[0], FALSE
);
2621 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, load
->dreg
);
2625 case ArgGSharedVtInReg
:
2627 mono_call_inst_add_outarg_reg (cfg
, call
, src
->dreg
, ainfo
->reg
, FALSE
);
2629 case ArgGSharedVtOnStack
:
2630 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, src
->dreg
);
2634 int dreg
= mono_alloc_ireg (cfg
);
2636 MONO_EMIT_NEW_LOAD_MEMBASE (cfg
, dreg
, src
->dreg
, 0);
2637 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, AMD64_RSP
, ainfo
->offset
, dreg
);
2638 } else if (size
<= 40) {
2639 mini_emit_memcpy (cfg
, AMD64_RSP
, ainfo
->offset
, src
->dreg
, 0, size
, 4);
2641 // FIXME: Code growth
2642 mini_emit_memcpy (cfg
, AMD64_RSP
, ainfo
->offset
, src
->dreg
, 0, size
, 4);
2645 if (cfg
->compute_gc_maps
) {
2647 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg
, def
, ainfo
->offset
, &ins
->klass
->byval_arg
);
2653 mono_arch_emit_setret (MonoCompile
*cfg
, MonoMethod
*method
, MonoInst
*val
)
2655 MonoType
*ret
= mini_get_underlying_type (mono_method_signature (method
)->ret
);
2657 if (ret
->type
== MONO_TYPE_R4
) {
2658 if (COMPILE_LLVM (cfg
))
2659 MONO_EMIT_NEW_UNALU (cfg
, OP_FMOVE
, cfg
->ret
->dreg
, val
->dreg
);
2661 MONO_EMIT_NEW_UNALU (cfg
, OP_AMD64_SET_XMMREG_R4
, cfg
->ret
->dreg
, val
->dreg
);
2663 } else if (ret
->type
== MONO_TYPE_R8
) {
2664 MONO_EMIT_NEW_UNALU (cfg
, OP_FMOVE
, cfg
->ret
->dreg
, val
->dreg
);
2668 MONO_EMIT_NEW_UNALU (cfg
, OP_MOVE
, cfg
->ret
->dreg
, val
->dreg
);
2671 #endif /* DISABLE_JIT */
2673 #define EMIT_COND_BRANCH(ins,cond,sign) \
2674 if (ins->inst_true_bb->native_offset) { \
2675 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2677 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2678 if ((cfg->opt & MONO_OPT_BRANCH) && \
2679 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2680 x86_branch8 (code, cond, 0, sign); \
2682 x86_branch32 (code, cond, 0, sign); \
2686 MonoMethodSignature
*sig
;
2691 dyn_call_supported (MonoMethodSignature
*sig
, CallInfo
*cinfo
)
2699 switch (cinfo
->ret
.storage
) {
2703 case ArgValuetypeInReg
: {
2704 ArgInfo
*ainfo
= &cinfo
->ret
;
2706 if (ainfo
->pair_storage
[0] != ArgNone
&& ainfo
->pair_storage
[0] != ArgInIReg
)
2708 if (ainfo
->pair_storage
[1] != ArgNone
&& ainfo
->pair_storage
[1] != ArgInIReg
)
2716 for (i
= 0; i
< cinfo
->nargs
; ++i
) {
2717 ArgInfo
*ainfo
= &cinfo
->args
[i
];
2718 switch (ainfo
->storage
) {
2721 case ArgValuetypeInReg
:
2722 if (ainfo
->pair_storage
[0] != ArgNone
&& ainfo
->pair_storage
[0] != ArgInIReg
)
2724 if (ainfo
->pair_storage
[1] != ArgNone
&& ainfo
->pair_storage
[1] != ArgInIReg
)
2736 * mono_arch_dyn_call_prepare:
2738 * Return a pointer to an arch-specific structure which contains information
2739 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2740 * supported for SIG.
2741 * This function is equivalent to ffi_prep_cif in libffi.
2744 mono_arch_dyn_call_prepare (MonoMethodSignature
*sig
)
2746 ArchDynCallInfo
*info
;
2749 cinfo
= get_call_info (NULL
, sig
);
2751 if (!dyn_call_supported (sig
, cinfo
)) {
2756 info
= g_new0 (ArchDynCallInfo
, 1);
2757 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2759 info
->cinfo
= cinfo
;
2761 return (MonoDynCallInfo
*)info
;
2765 * mono_arch_dyn_call_free:
2767 * Free a MonoDynCallInfo structure.
2770 mono_arch_dyn_call_free (MonoDynCallInfo
*info
)
2772 ArchDynCallInfo
*ainfo
= (ArchDynCallInfo
*)info
;
2774 g_free (ainfo
->cinfo
);
2778 #if !defined(__native_client__)
2779 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2780 #define GREG_TO_PTR(greg) (gpointer)(greg)
2782 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2783 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2784 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2788 * mono_arch_get_start_dyn_call:
2790 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2791 * store the result into BUF.
2792 * ARGS should be an array of pointers pointing to the arguments.
2793 * RET should point to a memory buffer large enought to hold the result of the
2795 * This function should be as fast as possible, any work which does not depend
2796 * on the actual values of the arguments should be done in
2797 * mono_arch_dyn_call_prepare ().
2798 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2802 mono_arch_start_dyn_call (MonoDynCallInfo
*info
, gpointer
**args
, guint8
*ret
, guint8
*buf
, int buf_len
)
2804 ArchDynCallInfo
*dinfo
= (ArchDynCallInfo
*)info
;
2805 DynCallArgs
*p
= (DynCallArgs
*)buf
;
2806 int arg_index
, greg
, i
, pindex
;
2807 MonoMethodSignature
*sig
= dinfo
->sig
;
2808 int buffer_offset
= 0;
2810 g_assert (buf_len
>= sizeof (DynCallArgs
));
2819 if (sig
->hasthis
|| dinfo
->cinfo
->vret_arg_index
== 1) {
2820 p
->regs
[greg
++] = PTR_TO_GREG(*(args
[arg_index
++]));
2825 if (dinfo
->cinfo
->ret
.storage
== ArgValuetypeAddrInIReg
)
2826 p
->regs
[greg
++] = PTR_TO_GREG(ret
);
2828 for (i
= pindex
; i
< sig
->param_count
; i
++) {
2829 MonoType
*t
= mini_get_underlying_type (sig
->params
[i
]);
2830 gpointer
*arg
= args
[arg_index
++];
2833 p
->regs
[greg
++] = PTR_TO_GREG(*(arg
));
2838 case MONO_TYPE_STRING
:
2839 case MONO_TYPE_CLASS
:
2840 case MONO_TYPE_ARRAY
:
2841 case MONO_TYPE_SZARRAY
:
2842 case MONO_TYPE_OBJECT
:
2846 #if !defined(__mono_ilp32__)
2850 g_assert (dinfo
->cinfo
->args
[i
+ sig
->hasthis
].reg
== param_regs
[greg
]);
2851 p
->regs
[greg
++] = PTR_TO_GREG(*(arg
));
2853 #if defined(__mono_ilp32__)
2856 g_assert (dinfo
->cinfo
->args
[i
+ sig
->hasthis
].reg
== param_regs
[greg
]);
2857 p
->regs
[greg
++] = *(guint64
*)(arg
);
2861 p
->regs
[greg
++] = *(guint8
*)(arg
);
2864 p
->regs
[greg
++] = *(gint8
*)(arg
);
2867 p
->regs
[greg
++] = *(gint16
*)(arg
);
2870 p
->regs
[greg
++] = *(guint16
*)(arg
);
2873 p
->regs
[greg
++] = *(gint32
*)(arg
);
2876 p
->regs
[greg
++] = *(guint32
*)(arg
);
2878 case MONO_TYPE_GENERICINST
:
2879 if (MONO_TYPE_IS_REFERENCE (t
)) {
2880 p
->regs
[greg
++] = PTR_TO_GREG(*(arg
));
2882 } else if (t
->type
== MONO_TYPE_GENERICINST
&& mono_class_is_nullable (mono_class_from_mono_type (t
))) {
2883 MonoClass
*klass
= mono_class_from_mono_type (t
);
2884 guint8
*nullable_buf
;
2887 size
= mono_class_value_size (klass
, NULL
);
2888 nullable_buf
= p
->buffer
+ buffer_offset
;
2889 buffer_offset
+= size
;
2890 g_assert (buffer_offset
<= 256);
2892 /* The argument pointed to by arg is either a boxed vtype or null */
2893 mono_nullable_init (nullable_buf
, (MonoObject
*)arg
, klass
);
2895 arg
= (gpointer
*)nullable_buf
;
2901 case MONO_TYPE_VALUETYPE
: {
2902 ArgInfo
*ainfo
= &dinfo
->cinfo
->args
[i
+ sig
->hasthis
];
2904 g_assert (ainfo
->storage
== ArgValuetypeInReg
);
2905 if (ainfo
->pair_storage
[0] != ArgNone
) {
2906 g_assert (ainfo
->pair_storage
[0] == ArgInIReg
);
2907 p
->regs
[greg
++] = ((mgreg_t
*)(arg
))[0];
2909 if (ainfo
->pair_storage
[1] != ArgNone
) {
2910 g_assert (ainfo
->pair_storage
[1] == ArgInIReg
);
2911 p
->regs
[greg
++] = ((mgreg_t
*)(arg
))[1];
2916 g_assert_not_reached ();
2920 g_assert (greg
<= PARAM_REGS
);
2924 * mono_arch_finish_dyn_call:
2926 * Store the result of a dyn call into the return value buffer passed to
2927 * start_dyn_call ().
2928 * This function should be as fast as possible, any work which does not depend
2929 * on the actual values of the arguments should be done in
2930 * mono_arch_dyn_call_prepare ().
2933 mono_arch_finish_dyn_call (MonoDynCallInfo
*info
, guint8
*buf
)
2935 ArchDynCallInfo
*dinfo
= (ArchDynCallInfo
*)info
;
2936 MonoMethodSignature
*sig
= dinfo
->sig
;
2937 guint8
*ret
= ((DynCallArgs
*)buf
)->ret
;
2938 mgreg_t res
= ((DynCallArgs
*)buf
)->res
;
2939 MonoType
*sig_ret
= mini_get_underlying_type (sig
->ret
);
2941 switch (sig_ret
->type
) {
2942 case MONO_TYPE_VOID
:
2943 *(gpointer
*)ret
= NULL
;
2945 case MONO_TYPE_STRING
:
2946 case MONO_TYPE_CLASS
:
2947 case MONO_TYPE_ARRAY
:
2948 case MONO_TYPE_SZARRAY
:
2949 case MONO_TYPE_OBJECT
:
2953 *(gpointer
*)ret
= GREG_TO_PTR(res
);
2959 *(guint8
*)ret
= res
;
2962 *(gint16
*)ret
= res
;
2965 *(guint16
*)ret
= res
;
2968 *(gint32
*)ret
= res
;
2971 *(guint32
*)ret
= res
;
2974 *(gint64
*)ret
= res
;
2977 *(guint64
*)ret
= res
;
2979 case MONO_TYPE_GENERICINST
:
2980 if (MONO_TYPE_IS_REFERENCE (sig_ret
)) {
2981 *(gpointer
*)ret
= GREG_TO_PTR(res
);
2986 case MONO_TYPE_VALUETYPE
:
2987 if (dinfo
->cinfo
->ret
.storage
== ArgValuetypeAddrInIReg
) {
2990 ArgInfo
*ainfo
= &dinfo
->cinfo
->ret
;
2992 g_assert (ainfo
->storage
== ArgValuetypeInReg
);
2994 if (ainfo
->pair_storage
[0] != ArgNone
) {
2995 g_assert (ainfo
->pair_storage
[0] == ArgInIReg
);
2996 ((mgreg_t
*)ret
)[0] = res
;
2999 g_assert (ainfo
->pair_storage
[1] == ArgNone
);
3003 g_assert_not_reached ();
3007 /* emit an exception if condition is fail */
3008 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
3010 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3011 if (tins == NULL) { \
3012 mono_add_patch_info (cfg, code - cfg->native_code, \
3013 MONO_PATCH_INFO_EXC, exc_name); \
3014 x86_branch32 (code, cond, 0, signed); \
3016 EMIT_COND_BRANCH (tins, cond, signed); \
3020 #define EMIT_FPCOMPARE(code) do { \
3021 amd64_fcompp (code); \
3022 amd64_fnstsw (code); \
3025 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3026 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3027 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3028 amd64_ ##op (code); \
3029 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3030 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3034 emit_call_body (MonoCompile
*cfg
, guint8
*code
, MonoJumpInfoType patch_type
, gconstpointer data
)
3036 gboolean no_patch
= FALSE
;
3039 * FIXME: Add support for thunks
3042 gboolean near_call
= FALSE
;
3045 * Indirect calls are expensive so try to make a near call if possible.
3046 * The caller memory is allocated by the code manager so it is
3047 * guaranteed to be at a 32 bit offset.
3050 if (patch_type
!= MONO_PATCH_INFO_ABS
) {
3051 /* The target is in memory allocated using the code manager */
3054 if ((patch_type
== MONO_PATCH_INFO_METHOD
) || (patch_type
== MONO_PATCH_INFO_METHOD_JUMP
)) {
3055 if (((MonoMethod
*)data
)->klass
->image
->aot_module
)
3056 /* The callee might be an AOT method */
3058 if (((MonoMethod
*)data
)->dynamic
)
3059 /* The target is in malloc-ed memory */
3063 if (patch_type
== MONO_PATCH_INFO_INTERNAL_METHOD
) {
3065 * The call might go directly to a native function without
3068 MonoJitICallInfo
*mi
= mono_find_jit_icall_by_name ((const char *)data
);
3070 gconstpointer target
= mono_icall_get_wrapper (mi
);
3071 if ((((guint64
)target
) >> 32) != 0)
3077 MonoJumpInfo
*jinfo
= NULL
;
3079 if (cfg
->abs_patches
)
3080 jinfo
= (MonoJumpInfo
*)g_hash_table_lookup (cfg
->abs_patches
, data
);
3082 if (jinfo
->type
== MONO_PATCH_INFO_JIT_ICALL_ADDR
) {
3083 MonoJitICallInfo
*mi
= mono_find_jit_icall_by_name (jinfo
->data
.name
);
3084 if (mi
&& (((guint64
)mi
->func
) >> 32) == 0)
3089 * This is not really an optimization, but required because the
3090 * generic class init trampolines use R11 to pass the vtable.
3095 MonoJitICallInfo
*info
= mono_find_jit_icall_by_addr (data
);
3097 if (info
->func
== info
->wrapper
) {
3099 if ((((guint64
)info
->func
) >> 32) == 0)
3103 /* See the comment in mono_codegen () */
3104 if ((info
->name
[0] != 'v') || (strstr (info
->name
, "ves_array_new_va_") == NULL
&& strstr (info
->name
, "ves_array_element_address_") == NULL
))
3108 else if ((((guint64
)data
) >> 32) == 0) {
3115 if (cfg
->method
->dynamic
)
3116 /* These methods are allocated using malloc */
3119 #ifdef MONO_ARCH_NOMAP32BIT
3122 #if defined(__native_client__)
3123 /* Always use near_call == TRUE for Native Client */
3126 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3127 if (optimize_for_xen
)
3130 if (cfg
->compile_aot
) {
3137 * Align the call displacement to an address divisible by 4 so it does
3138 * not span cache lines. This is required for code patching to work on SMP
3141 if (!no_patch
&& ((guint32
)(code
+ 1 - cfg
->native_code
) % 4) != 0) {
3142 guint32 pad_size
= 4 - ((guint32
)(code
+ 1 - cfg
->native_code
) % 4);
3143 amd64_padding (code
, pad_size
);
3145 mono_add_patch_info (cfg
, code
- cfg
->native_code
, patch_type
, data
);
3146 amd64_call_code (code
, 0);
3149 mono_add_patch_info (cfg
, code
- cfg
->native_code
, patch_type
, data
);
3150 amd64_set_reg_template (code
, GP_SCRATCH_REG
);
3151 amd64_call_reg (code
, GP_SCRATCH_REG
);
3158 static inline guint8
*
3159 emit_call (MonoCompile
*cfg
, guint8
*code
, MonoJumpInfoType patch_type
, gconstpointer data
, gboolean win64_adjust_stack
)
3162 if (win64_adjust_stack
)
3163 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 32);
3165 code
= emit_call_body (cfg
, code
, patch_type
, data
);
3167 if (win64_adjust_stack
)
3168 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 32);
3175 store_membase_imm_to_store_membase_reg (int opcode
)
3178 case OP_STORE_MEMBASE_IMM
:
3179 return OP_STORE_MEMBASE_REG
;
3180 case OP_STOREI4_MEMBASE_IMM
:
3181 return OP_STOREI4_MEMBASE_REG
;
3182 case OP_STOREI8_MEMBASE_IMM
:
3183 return OP_STOREI8_MEMBASE_REG
;
3191 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3194 * mono_arch_peephole_pass_1:
3196 * Perform peephole opts which should/can be performed before local regalloc
3199 mono_arch_peephole_pass_1 (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
3203 MONO_BB_FOR_EACH_INS_SAFE (bb
, n
, ins
) {
3204 MonoInst
*last_ins
= mono_inst_prev (ins
, FILTER_IL_SEQ_POINT
);
3206 switch (ins
->opcode
) {
3210 if ((ins
->sreg1
< MONO_MAX_IREGS
) && (ins
->dreg
>= MONO_MAX_IREGS
) && (ins
->inst_imm
> 0)) {
3212 * X86_LEA is like ADD, but doesn't have the
3213 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3214 * its operand to 64 bit.
3216 ins
->opcode
= OP_X86_LEA_MEMBASE
;
3217 ins
->inst_basereg
= ins
->sreg1
;
3222 if ((ins
->sreg1
== ins
->sreg2
) && (ins
->sreg1
== ins
->dreg
)) {
3226 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3227 * the latter has length 2-3 instead of 6 (reverse constant
3228 * propagation). These instruction sequences are very common
3229 * in the initlocals bblock.
3231 for (ins2
= ins
->next
; ins2
; ins2
= ins2
->next
) {
3232 if (((ins2
->opcode
== OP_STORE_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI4_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI8_MEMBASE_IMM
) || (ins2
->opcode
== OP_STORE_MEMBASE_IMM
)) && (ins2
->inst_imm
== 0)) {
3233 ins2
->opcode
= store_membase_imm_to_store_membase_reg (ins2
->opcode
);
3234 ins2
->sreg1
= ins
->dreg
;
3235 } else if ((ins2
->opcode
== OP_STOREI1_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI2_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI8_MEMBASE_REG
) || (ins2
->opcode
== OP_STORE_MEMBASE_REG
)) {
3237 } else if (((ins2
->opcode
== OP_ICONST
) || (ins2
->opcode
== OP_I8CONST
)) && (ins2
->dreg
== ins
->dreg
) && (ins2
->inst_c0
== 0)) {
3240 } else if (ins2
->opcode
== OP_IL_SEQ_POINT
) {
3248 case OP_COMPARE_IMM
:
3249 case OP_LCOMPARE_IMM
:
3250 /* OP_COMPARE_IMM (reg, 0)
3252 * OP_AMD64_TEST_NULL (reg)
3255 ins
->opcode
= OP_AMD64_TEST_NULL
;
3257 case OP_ICOMPARE_IMM
:
3259 ins
->opcode
= OP_X86_TEST_NULL
;
3261 case OP_AMD64_ICOMPARE_MEMBASE_IMM
:
3263 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3264 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3266 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3267 * OP_COMPARE_IMM reg, imm
3269 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3271 if (last_ins
&& (last_ins
->opcode
== OP_STOREI4_MEMBASE_REG
) &&
3272 ins
->inst_basereg
== last_ins
->inst_destbasereg
&&
3273 ins
->inst_offset
== last_ins
->inst_offset
) {
3274 ins
->opcode
= OP_ICOMPARE_IMM
;
3275 ins
->sreg1
= last_ins
->sreg1
;
3277 /* check if we can remove cmp reg,0 with test null */
3279 ins
->opcode
= OP_X86_TEST_NULL
;
3285 mono_peephole_ins (bb
, ins
);
3290 mono_arch_peephole_pass_2 (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
3294 MONO_BB_FOR_EACH_INS_SAFE (bb
, n
, ins
) {
3295 switch (ins
->opcode
) {
3298 MonoInst
*next
= mono_inst_next (ins
, FILTER_IL_SEQ_POINT
);
3299 /* reg = 0 -> XOR (reg, reg) */
3300 /* XOR sets cflags on x86, so we cant do it always */
3301 if (ins
->inst_c0
== 0 && (!next
|| (next
&& INST_IGNORES_CFLAGS (next
->opcode
)))) {
3302 ins
->opcode
= OP_LXOR
;
3303 ins
->sreg1
= ins
->dreg
;
3304 ins
->sreg2
= ins
->dreg
;
3312 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3313 * 0 result into 64 bits.
3315 if ((ins
->sreg1
== ins
->sreg2
) && (ins
->sreg1
== ins
->dreg
)) {
3316 ins
->opcode
= OP_IXOR
;
3320 if ((ins
->sreg1
== ins
->sreg2
) && (ins
->sreg1
== ins
->dreg
)) {
3324 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3325 * the latter has length 2-3 instead of 6 (reverse constant
3326 * propagation). These instruction sequences are very common
3327 * in the initlocals bblock.
3329 for (ins2
= ins
->next
; ins2
; ins2
= ins2
->next
) {
3330 if (((ins2
->opcode
== OP_STORE_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI4_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI8_MEMBASE_IMM
) || (ins2
->opcode
== OP_STORE_MEMBASE_IMM
)) && (ins2
->inst_imm
== 0)) {
3331 ins2
->opcode
= store_membase_imm_to_store_membase_reg (ins2
->opcode
);
3332 ins2
->sreg1
= ins
->dreg
;
3333 } else if ((ins2
->opcode
== OP_STOREI1_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI2_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI4_MEMBASE_REG
) || (ins2
->opcode
== OP_STOREI8_MEMBASE_REG
) || (ins2
->opcode
== OP_STORE_MEMBASE_REG
) || (ins2
->opcode
== OP_LIVERANGE_START
) || (ins2
->opcode
== OP_GC_LIVENESS_DEF
) || (ins2
->opcode
== OP_GC_LIVENESS_USE
)) {
3335 } else if (((ins2
->opcode
== OP_ICONST
) || (ins2
->opcode
== OP_I8CONST
)) && (ins2
->dreg
== ins
->dreg
) && (ins2
->inst_c0
== 0)) {
3338 } else if (ins2
->opcode
== OP_IL_SEQ_POINT
) {
3347 if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
3348 ins
->opcode
= OP_X86_INC_REG
;
3351 if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
3352 ins
->opcode
= OP_X86_DEC_REG
;
3356 mono_peephole_ins (bb
, ins
);
3360 #define NEW_INS(cfg,ins,dest,op) do { \
3361 MONO_INST_NEW ((cfg), (dest), (op)); \
3362 (dest)->cil_code = (ins)->cil_code; \
3363 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3367 * mono_arch_lowering_pass:
3369 * Converts complex opcodes into simpler ones so that each IR instruction
3370 * corresponds to one machine instruction.
3373 mono_arch_lowering_pass (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
3375 MonoInst
*ins
, *n
, *temp
;
3378 * FIXME: Need to add more instructions, but the current machine
3379 * description can't model some parts of the composite instructions like
3382 MONO_BB_FOR_EACH_INS_SAFE (bb
, n
, ins
) {
3383 switch (ins
->opcode
) {
3387 case OP_IDIV_UN_IMM
:
3388 case OP_IREM_UN_IMM
:
3391 mono_decompose_op_imm (cfg
, bb
, ins
);
3393 case OP_COMPARE_IMM
:
3394 case OP_LCOMPARE_IMM
:
3395 if (!amd64_use_imm32 (ins
->inst_imm
)) {
3396 NEW_INS (cfg
, ins
, temp
, OP_I8CONST
);
3397 temp
->inst_c0
= ins
->inst_imm
;
3398 temp
->dreg
= mono_alloc_ireg (cfg
);
3399 ins
->opcode
= OP_COMPARE
;
3400 ins
->sreg2
= temp
->dreg
;
3403 #ifndef __mono_ilp32__
3404 case OP_LOAD_MEMBASE
:
3406 case OP_LOADI8_MEMBASE
:
3407 #ifndef __native_client_codegen__
3408 /* Don't generate memindex opcodes (to simplify */
3409 /* read sandboxing) */
3410 if (!amd64_use_imm32 (ins
->inst_offset
)) {
3411 NEW_INS (cfg
, ins
, temp
, OP_I8CONST
);
3412 temp
->inst_c0
= ins
->inst_offset
;
3413 temp
->dreg
= mono_alloc_ireg (cfg
);
3414 ins
->opcode
= OP_AMD64_LOADI8_MEMINDEX
;
3415 ins
->inst_indexreg
= temp
->dreg
;
3419 #ifndef __mono_ilp32__
3420 case OP_STORE_MEMBASE_IMM
:
3422 case OP_STOREI8_MEMBASE_IMM
:
3423 if (!amd64_use_imm32 (ins
->inst_imm
)) {
3424 NEW_INS (cfg
, ins
, temp
, OP_I8CONST
);
3425 temp
->inst_c0
= ins
->inst_imm
;
3426 temp
->dreg
= mono_alloc_ireg (cfg
);
3427 ins
->opcode
= OP_STOREI8_MEMBASE_REG
;
3428 ins
->sreg1
= temp
->dreg
;
3431 #ifdef MONO_ARCH_SIMD_INTRINSICS
3432 case OP_EXPAND_I1
: {
3433 int temp_reg1
= mono_alloc_ireg (cfg
);
3434 int temp_reg2
= mono_alloc_ireg (cfg
);
3435 int original_reg
= ins
->sreg1
;
3437 NEW_INS (cfg
, ins
, temp
, OP_ICONV_TO_U1
);
3438 temp
->sreg1
= original_reg
;
3439 temp
->dreg
= temp_reg1
;
3441 NEW_INS (cfg
, ins
, temp
, OP_SHL_IMM
);
3442 temp
->sreg1
= temp_reg1
;
3443 temp
->dreg
= temp_reg2
;
3446 NEW_INS (cfg
, ins
, temp
, OP_LOR
);
3447 temp
->sreg1
= temp
->dreg
= temp_reg2
;
3448 temp
->sreg2
= temp_reg1
;
3450 ins
->opcode
= OP_EXPAND_I2
;
3451 ins
->sreg1
= temp_reg2
;
3460 bb
->max_vreg
= cfg
->next_vreg
;
3464 branch_cc_table
[] = {
3465 X86_CC_EQ
, X86_CC_GE
, X86_CC_GT
, X86_CC_LE
, X86_CC_LT
,
3466 X86_CC_NE
, X86_CC_GE
, X86_CC_GT
, X86_CC_LE
, X86_CC_LT
,
3467 X86_CC_O
, X86_CC_NO
, X86_CC_C
, X86_CC_NC
3470 /* Maps CMP_... constants to X86_CC_... constants */
3473 X86_CC_EQ
, X86_CC_NE
, X86_CC_LE
, X86_CC_GE
, X86_CC_LT
, X86_CC_GT
,
3474 X86_CC_LE
, X86_CC_GE
, X86_CC_LT
, X86_CC_GT
3478 cc_signed_table
[] = {
3479 TRUE
, TRUE
, TRUE
, TRUE
, TRUE
, TRUE
,
3480 FALSE
, FALSE
, FALSE
, FALSE
3483 /*#include "cprop.c"*/
3485 static unsigned char*
3486 emit_float_to_int (MonoCompile
*cfg
, guchar
*code
, int dreg
, int sreg
, int size
, gboolean is_signed
)
3489 amd64_sse_cvttsd2si_reg_reg (code
, dreg
, sreg
);
3491 amd64_sse_cvttsd2si_reg_reg_size (code
, dreg
, sreg
, 4);
3494 amd64_widen_reg (code
, dreg
, dreg
, is_signed
, FALSE
);
3496 amd64_widen_reg (code
, dreg
, dreg
, is_signed
, TRUE
);
3500 static unsigned char*
3501 mono_emit_stack_alloc (MonoCompile
*cfg
, guchar
*code
, MonoInst
* tree
)
3503 int sreg
= tree
->sreg1
;
3504 int need_touch
= FALSE
;
3506 #if defined(TARGET_WIN32)
3508 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3509 if (!tree
->flags
& MONO_INST_INIT
)
3518 * If requested stack size is larger than one page,
3519 * perform stack-touch operation
3522 * Generate stack probe code.
3523 * Under Windows, it is necessary to allocate one page at a time,
3524 * "touching" stack after each successful sub-allocation. This is
3525 * because of the way stack growth is implemented - there is a
3526 * guard page before the lowest stack page that is currently commited.
3527 * Stack normally grows sequentially so OS traps access to the
3528 * guard page and commits more pages when needed.
3530 amd64_test_reg_imm (code
, sreg
, ~0xFFF);
3531 br
[0] = code
; x86_branch8 (code
, X86_CC_Z
, 0, FALSE
);
3533 br
[2] = code
; /* loop */
3534 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 0x1000);
3535 amd64_test_membase_reg (code
, AMD64_RSP
, 0, AMD64_RSP
);
3536 amd64_alu_reg_imm (code
, X86_SUB
, sreg
, 0x1000);
3537 amd64_alu_reg_imm (code
, X86_CMP
, sreg
, 0x1000);
3538 br
[3] = code
; x86_branch8 (code
, X86_CC_AE
, 0, FALSE
);
3539 amd64_patch (br
[3], br
[2]);
3540 amd64_test_reg_reg (code
, sreg
, sreg
);
3541 br
[4] = code
; x86_branch8 (code
, X86_CC_Z
, 0, FALSE
);
3542 amd64_alu_reg_reg (code
, X86_SUB
, AMD64_RSP
, sreg
);
3544 br
[1] = code
; x86_jump8 (code
, 0);
3546 amd64_patch (br
[0], code
);
3547 amd64_alu_reg_reg (code
, X86_SUB
, AMD64_RSP
, sreg
);
3548 amd64_patch (br
[1], code
);
3549 amd64_patch (br
[4], code
);
3552 amd64_alu_reg_reg (code
, X86_SUB
, AMD64_RSP
, tree
->sreg1
);
3554 if (tree
->flags
& MONO_INST_INIT
) {
3556 if (tree
->dreg
!= AMD64_RAX
&& sreg
!= AMD64_RAX
) {
3557 amd64_push_reg (code
, AMD64_RAX
);
3560 if (tree
->dreg
!= AMD64_RCX
&& sreg
!= AMD64_RCX
) {
3561 amd64_push_reg (code
, AMD64_RCX
);
3564 if (tree
->dreg
!= AMD64_RDI
&& sreg
!= AMD64_RDI
) {
3565 amd64_push_reg (code
, AMD64_RDI
);
3569 amd64_shift_reg_imm (code
, X86_SHR
, sreg
, 3);
3570 if (sreg
!= AMD64_RCX
)
3571 amd64_mov_reg_reg (code
, AMD64_RCX
, sreg
, 8);
3572 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RAX
, AMD64_RAX
);
3574 amd64_lea_membase (code
, AMD64_RDI
, AMD64_RSP
, offset
);
3575 if (cfg
->param_area
)
3576 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RDI
, cfg
->param_area
);
3578 #if defined(__default_codegen__)
3579 amd64_prefix (code
, X86_REP_PREFIX
);
3581 #elif defined(__native_client_codegen__)
3582 /* NaCl stos pseudo-instruction */
3583 amd64_codegen_pre(code
);
3584 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3585 amd64_mov_reg_reg (code
, AMD64_RDI
, AMD64_RDI
, 4);
3586 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3587 amd64_lea_memindex_size (code
, AMD64_RDI
, AMD64_R15
, 0, AMD64_RDI
, 0, 8);
3588 amd64_prefix (code
, X86_REP_PREFIX
);
3590 amd64_codegen_post(code
);
3591 #endif /* __native_client_codegen__ */
3593 if (tree
->dreg
!= AMD64_RDI
&& sreg
!= AMD64_RDI
)
3594 amd64_pop_reg (code
, AMD64_RDI
);
3595 if (tree
->dreg
!= AMD64_RCX
&& sreg
!= AMD64_RCX
)
3596 amd64_pop_reg (code
, AMD64_RCX
);
3597 if (tree
->dreg
!= AMD64_RAX
&& sreg
!= AMD64_RAX
)
3598 amd64_pop_reg (code
, AMD64_RAX
);
3604 emit_move_return_value (MonoCompile
*cfg
, MonoInst
*ins
, guint8
*code
)
3609 /* Move return value to the target register */
3610 /* FIXME: do this in the local reg allocator */
3611 switch (ins
->opcode
) {
3614 case OP_CALL_MEMBASE
:
3617 case OP_LCALL_MEMBASE
:
3618 g_assert (ins
->dreg
== AMD64_RAX
);
3622 case OP_FCALL_MEMBASE
: {
3623 MonoType
*rtype
= mini_get_underlying_type (((MonoCallInst
*)ins
)->signature
->ret
);
3624 if (rtype
->type
== MONO_TYPE_R4
) {
3625 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, AMD64_XMM0
);
3628 if (ins
->dreg
!= AMD64_XMM0
)
3629 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, AMD64_XMM0
);
3635 case OP_RCALL_MEMBASE
:
3636 if (ins
->dreg
!= AMD64_XMM0
)
3637 amd64_sse_movss_reg_reg (code
, ins
->dreg
, AMD64_XMM0
);
3641 case OP_VCALL_MEMBASE
:
3644 case OP_VCALL2_MEMBASE
:
3645 cinfo
= get_call_info (cfg
->mempool
, ((MonoCallInst
*)ins
)->signature
);
3646 if (cinfo
->ret
.storage
== ArgValuetypeInReg
) {
3647 MonoInst
*loc
= (MonoInst
*)cfg
->arch
.vret_addr_loc
;
3649 /* Load the destination address */
3650 g_assert (loc
->opcode
== OP_REGOFFSET
);
3651 amd64_mov_reg_membase (code
, AMD64_RCX
, loc
->inst_basereg
, loc
->inst_offset
, sizeof(gpointer
));
3653 for (quad
= 0; quad
< 2; quad
++) {
3654 switch (cinfo
->ret
.pair_storage
[quad
]) {
3656 amd64_mov_membase_reg (code
, AMD64_RCX
, (quad
* sizeof(mgreg_t
)), cinfo
->ret
.pair_regs
[quad
], sizeof(mgreg_t
));
3658 case ArgInFloatSSEReg
:
3659 amd64_movss_membase_reg (code
, AMD64_RCX
, (quad
* 8), cinfo
->ret
.pair_regs
[quad
]);
3661 case ArgInDoubleSSEReg
:
3662 amd64_movsd_membase_reg (code
, AMD64_RCX
, (quad
* 8), cinfo
->ret
.pair_regs
[quad
]);
3677 #endif /* DISABLE_JIT */
3680 static int tls_gs_offset
;
3684 mono_amd64_have_tls_get (void)
3687 static gboolean have_tls_get
= FALSE
;
3688 static gboolean inited
= FALSE
;
3691 return have_tls_get
;
3693 #if MONO_HAVE_FAST_TLS
3694 guint8
*ins
= (guint8
*)pthread_getspecific
;
3697 * We're looking for these two instructions:
3699 * mov %gs:[offset](,%rdi,8),%rax
3702 have_tls_get
= ins
[0] == 0x65 &&
3712 tls_gs_offset
= ins
[5];
3715 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3716 * For that version we're looking for these instructions:
3720 * mov %gs:[offset](,%rdi,8),%rax
3724 if (!have_tls_get
) {
3725 have_tls_get
= ins
[0] == 0x55 &&
3740 tls_gs_offset
= ins
[9];
3746 return have_tls_get
;
3747 #elif defined(TARGET_ANDROID)
3755 mono_amd64_get_tls_gs_offset (void)
3758 return tls_gs_offset
;
3760 g_assert_not_reached ();
3766 * mono_amd64_emit_tls_get:
3767 * @code: buffer to store code to
3768 * @dreg: hard register where to place the result
3769 * @tls_offset: offset info
3771 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3772 * the dreg register the item in the thread local storage identified
3775 * Returns: a pointer to the end of the stored code
3778 mono_amd64_emit_tls_get (guint8
* code
, int dreg
, int tls_offset
)
3781 if (tls_offset
< 64) {
3782 x86_prefix (code
, X86_GS_PREFIX
);
3783 amd64_mov_reg_mem (code
, dreg
, (tls_offset
* 8) + 0x1480, 8);
3787 g_assert (tls_offset
< 0x440);
3788 /* Load TEB->TlsExpansionSlots */
3789 x86_prefix (code
, X86_GS_PREFIX
);
3790 amd64_mov_reg_mem (code
, dreg
, 0x1780, 8);
3791 amd64_test_reg_reg (code
, dreg
, dreg
);
3793 amd64_branch (code
, X86_CC_EQ
, code
, TRUE
);
3794 amd64_mov_reg_membase (code
, dreg
, dreg
, (tls_offset
* 8) - 0x200, 8);
3795 amd64_patch (buf
[0], code
);
3797 #elif defined(__APPLE__)
3798 x86_prefix (code
, X86_GS_PREFIX
);
3799 amd64_mov_reg_mem (code
, dreg
, tls_gs_offset
+ (tls_offset
* 8), 8);
3801 if (optimize_for_xen
) {
3802 x86_prefix (code
, X86_FS_PREFIX
);
3803 amd64_mov_reg_mem (code
, dreg
, 0, 8);
3804 amd64_mov_reg_membase (code
, dreg
, dreg
, tls_offset
, 8);
3806 x86_prefix (code
, X86_FS_PREFIX
);
3807 amd64_mov_reg_mem (code
, dreg
, tls_offset
, 8);
3814 emit_tls_get_reg (guint8
* code
, int dreg
, int offset_reg
)
3816 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3818 if (dreg
!= offset_reg
)
3819 amd64_mov_reg_reg (code
, dreg
, offset_reg
, sizeof (mgreg_t
));
3820 amd64_prefix (code
, X86_GS_PREFIX
);
3821 amd64_mov_reg_membase (code
, dreg
, dreg
, 0, sizeof (mgreg_t
));
3822 #elif defined(__linux__)
3825 if (dreg
== offset_reg
) {
3826 /* Use a temporary reg by saving it to the redzone */
3827 tmpreg
= dreg
== AMD64_RAX
? AMD64_RCX
: AMD64_RAX
;
3828 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, tmpreg
, 8);
3829 amd64_mov_reg_reg (code
, tmpreg
, offset_reg
, sizeof (gpointer
));
3830 offset_reg
= tmpreg
;
3832 x86_prefix (code
, X86_FS_PREFIX
);
3833 amd64_mov_reg_mem (code
, dreg
, 0, 8);
3834 amd64_mov_reg_memindex (code
, dreg
, dreg
, 0, offset_reg
, 0, 8);
3836 amd64_mov_reg_membase (code
, tmpreg
, AMD64_RSP
, -8, 8);
3838 g_assert_not_reached ();
3844 amd64_emit_tls_set (guint8
*code
, int sreg
, int tls_offset
)
3847 g_assert_not_reached ();
3848 #elif defined(__APPLE__)
3849 x86_prefix (code
, X86_GS_PREFIX
);
3850 amd64_mov_mem_reg (code
, tls_gs_offset
+ (tls_offset
* 8), sreg
, 8);
3852 g_assert (!optimize_for_xen
);
3853 x86_prefix (code
, X86_FS_PREFIX
);
3854 amd64_mov_mem_reg (code
, tls_offset
, sreg
, 8);
3860 amd64_emit_tls_set_reg (guint8
*code
, int sreg
, int offset_reg
)
3862 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3864 g_assert_not_reached ();
3865 #elif defined(__APPLE__)
3866 x86_prefix (code
, X86_GS_PREFIX
);
3867 amd64_mov_membase_reg (code
, offset_reg
, 0, sreg
, 8);
3869 x86_prefix (code
, X86_FS_PREFIX
);
3870 amd64_mov_membase_reg (code
, offset_reg
, 0, sreg
, 8);
3876 * mono_arch_translate_tls_offset:
3878 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3881 mono_arch_translate_tls_offset (int offset
)
3884 return tls_gs_offset
+ (offset
* 8);
3893 * Emit code to initialize an LMF structure at LMF_OFFSET.
3896 emit_setup_lmf (MonoCompile
*cfg
, guint8
*code
, gint32 lmf_offset
, int cfa_offset
)
3899 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3902 * sp is saved right before calls but we need to save it here too so
3903 * async stack walks would work.
3905 amd64_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rsp
), AMD64_RSP
, 8);
3907 amd64_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rbp
), AMD64_RBP
, 8);
3908 if (cfg
->arch
.omit_fp
&& cfa_offset
!= -1)
3909 mono_emit_unwind_op_offset (cfg
, code
, AMD64_RBP
, - (cfa_offset
- (lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rbp
))));
3911 /* These can't contain refs */
3912 mini_gc_set_slot_type_from_fp (cfg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, previous_lmf
), SLOT_NOREF
);
3913 mini_gc_set_slot_type_from_fp (cfg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rip
), SLOT_NOREF
);
3914 mini_gc_set_slot_type_from_fp (cfg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rsp
), SLOT_NOREF
);
3915 /* These are handled automatically by the stack marking code */
3916 mini_gc_set_slot_type_from_fp (cfg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rbp
), SLOT_NOREF
);
3921 #define REAL_PRINT_REG(text,reg) \
3922 mono_assert (reg >= 0); \
3923 amd64_push_reg (code, AMD64_RAX); \
3924 amd64_push_reg (code, AMD64_RDX); \
3925 amd64_push_reg (code, AMD64_RCX); \
3926 amd64_push_reg (code, reg); \
3927 amd64_push_imm (code, reg); \
3928 amd64_push_imm (code, text " %d %p\n"); \
3929 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3930 amd64_call_reg (code, AMD64_RAX); \
3931 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3932 amd64_pop_reg (code, AMD64_RCX); \
3933 amd64_pop_reg (code, AMD64_RDX); \
3934 amd64_pop_reg (code, AMD64_RAX);
3936 /* benchmark and set based on cpu */
3937 #define LOOP_ALIGNMENT 8
3938 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3942 mono_arch_output_basic_block (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
3947 guint8
*code
= cfg
->native_code
+ cfg
->code_len
;
3950 /* Fix max_offset estimate for each successor bb */
3951 if (cfg
->opt
& MONO_OPT_BRANCH
) {
3952 int current_offset
= cfg
->code_len
;
3953 MonoBasicBlock
*current_bb
;
3954 for (current_bb
= bb
; current_bb
!= NULL
; current_bb
= current_bb
->next_bb
) {
3955 current_bb
->max_offset
= current_offset
;
3956 current_offset
+= current_bb
->max_length
;
3960 if (cfg
->opt
& MONO_OPT_LOOP
) {
3961 int pad
, align
= LOOP_ALIGNMENT
;
3962 /* set alignment depending on cpu */
3963 if (bb_is_loop_start (bb
) && (pad
= (cfg
->code_len
& (align
- 1)))) {
3965 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3966 amd64_padding (code
, pad
);
3967 cfg
->code_len
+= pad
;
3968 bb
->native_offset
= cfg
->code_len
;
3972 #if defined(__native_client_codegen__)
3973 /* For Native Client, all indirect call/jump targets must be */
3974 /* 32-byte aligned. Exception handler blocks are jumped to */
3975 /* indirectly as well. */
3976 gboolean bb_needs_alignment
= (bb
->flags
& BB_INDIRECT_JUMP_TARGET
) ||
3977 (bb
->flags
& BB_EXCEPTION_HANDLER
);
3979 if ( bb_needs_alignment
&& ((cfg
->code_len
& kNaClAlignmentMask
) != 0)) {
3980 int pad
= kNaClAlignment
- (cfg
->code_len
& kNaClAlignmentMask
);
3981 if (pad
!= kNaClAlignment
) code
= mono_arch_nacl_pad(code
, pad
);
3982 cfg
->code_len
+= pad
;
3983 bb
->native_offset
= cfg
->code_len
;
3985 #endif /*__native_client_codegen__*/
3987 if (cfg
->verbose_level
> 2)
3988 g_print ("Basic block %d starting at offset 0x%x\n", bb
->block_num
, bb
->native_offset
);
3990 if ((cfg
->prof_options
& MONO_PROFILE_COVERAGE
) && cfg
->coverage_info
) {
3991 MonoProfileCoverageInfo
*cov
= cfg
->coverage_info
;
3992 g_assert (!cfg
->compile_aot
);
3994 cov
->data
[bb
->dfn
].cil_code
= bb
->cil_code
;
3995 amd64_mov_reg_imm (code
, AMD64_R11
, (guint64
)&cov
->data
[bb
->dfn
].count
);
3996 /* this is not thread save, but good enough */
3997 amd64_inc_membase (code
, AMD64_R11
, 0);
4000 offset
= code
- cfg
->native_code
;
4002 mono_debug_open_block (cfg
, bb
, offset
);
4004 if (mono_break_at_bb_method
&& mono_method_desc_full_match (mono_break_at_bb_method
, cfg
->method
) && bb
->block_num
== mono_break_at_bb_bb_num
)
4005 x86_breakpoint (code
);
4007 MONO_BB_FOR_EACH_INS (bb
, ins
) {
4008 offset
= code
- cfg
->native_code
;
4010 max_len
= ((guint8
*)ins_get_spec (ins
->opcode
))[MONO_INST_LEN
];
4012 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
4014 if (G_UNLIKELY (offset
> (cfg
->code_size
- max_len
- EXTRA_CODE_SPACE
))) {
4015 cfg
->code_size
*= 2;
4016 cfg
->native_code
= (unsigned char *)mono_realloc_native_code(cfg
);
4017 code
= cfg
->native_code
+ offset
;
4018 cfg
->stat_code_reallocs
++;
4021 if (cfg
->debug_info
)
4022 mono_debug_record_line_number (cfg
, ins
, offset
);
4024 switch (ins
->opcode
) {
4026 amd64_mul_reg (code
, ins
->sreg2
, TRUE
);
4029 amd64_mul_reg (code
, ins
->sreg2
, FALSE
);
4031 case OP_X86_SETEQ_MEMBASE
:
4032 amd64_set_membase (code
, X86_CC_EQ
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
);
4034 case OP_STOREI1_MEMBASE_IMM
:
4035 amd64_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 1);
4037 case OP_STOREI2_MEMBASE_IMM
:
4038 amd64_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 2);
4040 case OP_STOREI4_MEMBASE_IMM
:
4041 amd64_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4043 case OP_STOREI1_MEMBASE_REG
:
4044 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 1);
4046 case OP_STOREI2_MEMBASE_REG
:
4047 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 2);
4049 /* In AMD64 NaCl, pointers are 4 bytes, */
4050 /* so STORE_* != STOREI8_*. Likewise below. */
4051 case OP_STORE_MEMBASE_REG
:
4052 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, sizeof(gpointer
));
4054 case OP_STOREI8_MEMBASE_REG
:
4055 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 8);
4057 case OP_STOREI4_MEMBASE_REG
:
4058 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 4);
4060 case OP_STORE_MEMBASE_IMM
:
4061 #ifndef __native_client_codegen__
4062 /* In NaCl, this could be a PCONST type, which could */
4063 /* mean a pointer type was copied directly into the */
4064 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4065 /* the value would be 0x00000000FFFFFFFF which is */
4066 /* not proper for an imm32 unless you cast it. */
4067 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4069 amd64_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, (gint32
)ins
->inst_imm
, sizeof(gpointer
));
4071 case OP_STOREI8_MEMBASE_IMM
:
4072 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4073 amd64_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4076 #ifdef __mono_ilp32__
4077 /* In ILP32, pointers are 4 bytes, so separate these */
4078 /* cases, use literal 8 below where we really want 8 */
4079 amd64_mov_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
4080 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->dreg
, 0, sizeof(gpointer
));
4084 // FIXME: Decompose this earlier
4085 if (amd64_use_imm32 (ins
->inst_imm
))
4086 amd64_mov_reg_mem (code
, ins
->dreg
, ins
->inst_imm
, 8);
4088 amd64_mov_reg_imm_size (code
, ins
->dreg
, ins
->inst_imm
, sizeof(gpointer
));
4089 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->dreg
, 0, 8);
4093 amd64_mov_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
4094 amd64_movsxd_reg_membase (code
, ins
->dreg
, ins
->dreg
, 0);
4097 // FIXME: Decompose this earlier
4098 if (amd64_use_imm32 (ins
->inst_imm
))
4099 amd64_mov_reg_mem (code
, ins
->dreg
, ins
->inst_imm
, 4);
4101 amd64_mov_reg_imm_size (code
, ins
->dreg
, ins
->inst_imm
, sizeof(gpointer
));
4102 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->dreg
, 0, 4);
4106 amd64_mov_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
4107 amd64_widen_membase (code
, ins
->dreg
, ins
->dreg
, 0, FALSE
, FALSE
);
4110 /* For NaCl, pointers are 4 bytes, so separate these */
4111 /* cases, use literal 8 below where we really want 8 */
4112 amd64_mov_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
4113 amd64_widen_membase (code
, ins
->dreg
, ins
->dreg
, 0, FALSE
, TRUE
);
4115 case OP_LOAD_MEMBASE
:
4116 g_assert (amd64_is_imm32 (ins
->inst_offset
));
4117 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, sizeof(gpointer
));
4119 case OP_LOADI8_MEMBASE
:
4120 /* Use literal 8 instead of sizeof pointer or */
4121 /* register, we really want 8 for this opcode */
4122 g_assert (amd64_is_imm32 (ins
->inst_offset
));
4123 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, 8);
4125 case OP_LOADI4_MEMBASE
:
4126 amd64_movsxd_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
4128 case OP_LOADU4_MEMBASE
:
4129 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, 4);
4131 case OP_LOADU1_MEMBASE
:
4132 /* The cpu zero extends the result into 64 bits */
4133 amd64_widen_membase_size (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, FALSE
, 4);
4135 case OP_LOADI1_MEMBASE
:
4136 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, FALSE
);
4138 case OP_LOADU2_MEMBASE
:
4139 /* The cpu zero extends the result into 64 bits */
4140 amd64_widen_membase_size (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, TRUE
, 4);
4142 case OP_LOADI2_MEMBASE
:
4143 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, TRUE
);
4145 case OP_AMD64_LOADI8_MEMINDEX
:
4146 amd64_mov_reg_memindex_size (code
, ins
->dreg
, ins
->inst_basereg
, 0, ins
->inst_indexreg
, 0, 8);
4148 case OP_LCONV_TO_I1
:
4149 case OP_ICONV_TO_I1
:
4151 amd64_widen_reg (code
, ins
->dreg
, ins
->sreg1
, TRUE
, FALSE
);
4153 case OP_LCONV_TO_I2
:
4154 case OP_ICONV_TO_I2
:
4156 amd64_widen_reg (code
, ins
->dreg
, ins
->sreg1
, TRUE
, TRUE
);
4158 case OP_LCONV_TO_U1
:
4159 case OP_ICONV_TO_U1
:
4160 amd64_widen_reg (code
, ins
->dreg
, ins
->sreg1
, FALSE
, FALSE
);
4162 case OP_LCONV_TO_U2
:
4163 case OP_ICONV_TO_U2
:
4164 amd64_widen_reg (code
, ins
->dreg
, ins
->sreg1
, FALSE
, TRUE
);
4167 /* Clean out the upper word */
4168 amd64_mov_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
4171 amd64_movsxd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
4175 amd64_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
4177 case OP_COMPARE_IMM
:
4178 #if defined(__mono_ilp32__)
4179 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4180 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4181 amd64_alu_reg_imm_size (code
, X86_CMP
, ins
->sreg1
, ins
->inst_imm
, 4);
4184 case OP_LCOMPARE_IMM
:
4185 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4186 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg1
, ins
->inst_imm
);
4188 case OP_X86_COMPARE_REG_MEMBASE
:
4189 amd64_alu_reg_membase (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
4191 case OP_X86_TEST_NULL
:
4192 amd64_test_reg_reg_size (code
, ins
->sreg1
, ins
->sreg1
, 4);
4194 case OP_AMD64_TEST_NULL
:
4195 amd64_test_reg_reg (code
, ins
->sreg1
, ins
->sreg1
);
4198 case OP_X86_ADD_REG_MEMBASE
:
4199 amd64_alu_reg_membase_size (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4201 case OP_X86_SUB_REG_MEMBASE
:
4202 amd64_alu_reg_membase_size (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4204 case OP_X86_AND_REG_MEMBASE
:
4205 amd64_alu_reg_membase_size (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4207 case OP_X86_OR_REG_MEMBASE
:
4208 amd64_alu_reg_membase_size (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4210 case OP_X86_XOR_REG_MEMBASE
:
4211 amd64_alu_reg_membase_size (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4214 case OP_X86_ADD_MEMBASE_IMM
:
4215 /* FIXME: Make a 64 version too */
4216 amd64_alu_membase_imm_size (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4218 case OP_X86_SUB_MEMBASE_IMM
:
4219 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4220 amd64_alu_membase_imm_size (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4222 case OP_X86_AND_MEMBASE_IMM
:
4223 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4224 amd64_alu_membase_imm_size (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4226 case OP_X86_OR_MEMBASE_IMM
:
4227 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4228 amd64_alu_membase_imm_size (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4230 case OP_X86_XOR_MEMBASE_IMM
:
4231 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4232 amd64_alu_membase_imm_size (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4234 case OP_X86_ADD_MEMBASE_REG
:
4235 amd64_alu_membase_reg_size (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4237 case OP_X86_SUB_MEMBASE_REG
:
4238 amd64_alu_membase_reg_size (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4240 case OP_X86_AND_MEMBASE_REG
:
4241 amd64_alu_membase_reg_size (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4243 case OP_X86_OR_MEMBASE_REG
:
4244 amd64_alu_membase_reg_size (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4246 case OP_X86_XOR_MEMBASE_REG
:
4247 amd64_alu_membase_reg_size (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4249 case OP_X86_INC_MEMBASE
:
4250 amd64_inc_membase_size (code
, ins
->inst_basereg
, ins
->inst_offset
, 4);
4252 case OP_X86_INC_REG
:
4253 amd64_inc_reg_size (code
, ins
->dreg
, 4);
4255 case OP_X86_DEC_MEMBASE
:
4256 amd64_dec_membase_size (code
, ins
->inst_basereg
, ins
->inst_offset
, 4);
4258 case OP_X86_DEC_REG
:
4259 amd64_dec_reg_size (code
, ins
->dreg
, 4);
4261 case OP_X86_MUL_REG_MEMBASE
:
4262 case OP_X86_MUL_MEMBASE_REG
:
4263 amd64_imul_reg_membase_size (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4265 case OP_AMD64_ICOMPARE_MEMBASE_REG
:
4266 amd64_alu_membase_reg_size (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 4);
4268 case OP_AMD64_ICOMPARE_MEMBASE_IMM
:
4269 amd64_alu_membase_imm_size (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4271 case OP_AMD64_COMPARE_MEMBASE_REG
:
4272 amd64_alu_membase_reg_size (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4274 case OP_AMD64_COMPARE_MEMBASE_IMM
:
4275 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4276 amd64_alu_membase_imm_size (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4278 case OP_X86_COMPARE_MEMBASE8_IMM
:
4279 amd64_alu_membase8_imm_size (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
4281 case OP_AMD64_ICOMPARE_REG_MEMBASE
:
4282 amd64_alu_reg_membase_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 4);
4284 case OP_AMD64_COMPARE_REG_MEMBASE
:
4285 amd64_alu_reg_membase_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4288 case OP_AMD64_ADD_REG_MEMBASE
:
4289 amd64_alu_reg_membase_size (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4291 case OP_AMD64_SUB_REG_MEMBASE
:
4292 amd64_alu_reg_membase_size (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4294 case OP_AMD64_AND_REG_MEMBASE
:
4295 amd64_alu_reg_membase_size (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4297 case OP_AMD64_OR_REG_MEMBASE
:
4298 amd64_alu_reg_membase_size (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4300 case OP_AMD64_XOR_REG_MEMBASE
:
4301 amd64_alu_reg_membase_size (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
, 8);
4304 case OP_AMD64_ADD_MEMBASE_REG
:
4305 amd64_alu_membase_reg_size (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4307 case OP_AMD64_SUB_MEMBASE_REG
:
4308 amd64_alu_membase_reg_size (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4310 case OP_AMD64_AND_MEMBASE_REG
:
4311 amd64_alu_membase_reg_size (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4313 case OP_AMD64_OR_MEMBASE_REG
:
4314 amd64_alu_membase_reg_size (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4316 case OP_AMD64_XOR_MEMBASE_REG
:
4317 amd64_alu_membase_reg_size (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
, 8);
4320 case OP_AMD64_ADD_MEMBASE_IMM
:
4321 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4322 amd64_alu_membase_imm_size (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4324 case OP_AMD64_SUB_MEMBASE_IMM
:
4325 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4326 amd64_alu_membase_imm_size (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4328 case OP_AMD64_AND_MEMBASE_IMM
:
4329 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4330 amd64_alu_membase_imm_size (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4332 case OP_AMD64_OR_MEMBASE_IMM
:
4333 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4334 amd64_alu_membase_imm_size (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4336 case OP_AMD64_XOR_MEMBASE_IMM
:
4337 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4338 amd64_alu_membase_imm_size (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
, 8);
4342 amd64_breakpoint (code
);
4344 case OP_RELAXED_NOP
:
4345 x86_prefix (code
, X86_REP_PREFIX
);
4353 case OP_DUMMY_STORE
:
4354 case OP_DUMMY_ICONST
:
4355 case OP_DUMMY_R8CONST
:
4356 case OP_NOT_REACHED
:
4359 case OP_IL_SEQ_POINT
:
4360 mono_add_seq_point (cfg
, bb
, ins
, code
- cfg
->native_code
);
4362 case OP_SEQ_POINT
: {
4363 if (ins
->flags
& MONO_INST_SINGLE_STEP_LOC
) {
4364 MonoInst
*var
= (MonoInst
*)cfg
->arch
.ss_tramp_var
;
4367 /* Load ss_tramp_var */
4368 /* This is equal to &ss_trampoline */
4369 amd64_mov_reg_membase (code
, AMD64_R11
, var
->inst_basereg
, var
->inst_offset
, 8);
4370 /* Load the trampoline address */
4371 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_R11
, 0, 8);
4372 /* Call it if it is non-null */
4373 amd64_test_reg_reg (code
, AMD64_R11
, AMD64_R11
);
4375 amd64_branch8 (code
, X86_CC_Z
, 0, FALSE
);
4376 amd64_call_reg (code
, AMD64_R11
);
4377 amd64_patch (label
, code
);
4381 * This is the address which is saved in seq points,
4383 mono_add_seq_point (cfg
, bb
, ins
, code
- cfg
->native_code
);
4385 if (cfg
->compile_aot
) {
4386 guint32 offset
= code
- cfg
->native_code
;
4388 MonoInst
*info_var
= (MonoInst
*)cfg
->arch
.seq_point_info_var
;
4392 amd64_mov_reg_membase (code
, AMD64_R11
, info_var
->inst_basereg
, info_var
->inst_offset
, 8);
4393 val
= ((offset
) * sizeof (guint8
*)) + MONO_STRUCT_OFFSET (SeqPointInfo
, bp_addrs
);
4394 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4395 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_R11
, val
, 8);
4396 amd64_test_reg_reg (code
, AMD64_R11
, AMD64_R11
);
4398 amd64_branch8 (code
, X86_CC_Z
, 0, FALSE
);
4399 /* Call the trampoline */
4400 amd64_call_reg (code
, AMD64_R11
);
4401 amd64_patch (label
, code
);
4403 MonoInst
*var
= (MonoInst
*)cfg
->arch
.bp_tramp_var
;
4407 * Emit a test+branch against a constant, the constant will be overwritten
4408 * by mono_arch_set_breakpoint () to cause the test to fail.
4410 amd64_mov_reg_imm (code
, AMD64_R11
, 0);
4411 amd64_test_reg_reg (code
, AMD64_R11
, AMD64_R11
);
4413 amd64_branch8 (code
, X86_CC_Z
, 0, FALSE
);
4416 g_assert (var
->opcode
== OP_REGOFFSET
);
4417 /* Load bp_tramp_var */
4418 /* This is equal to &bp_trampoline */
4419 amd64_mov_reg_membase (code
, AMD64_R11
, var
->inst_basereg
, var
->inst_offset
, 8);
4420 /* Call the trampoline */
4421 amd64_call_membase (code
, AMD64_R11
, 0);
4422 amd64_patch (label
, code
);
4425 * Add an additional nop so skipping the bp doesn't cause the ip to point
4426 * to another IL offset.
4434 amd64_alu_reg_reg (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
);
4437 amd64_alu_reg_reg (code
, X86_ADC
, ins
->sreg1
, ins
->sreg2
);
4441 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4442 amd64_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, ins
->inst_imm
);
4445 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4446 amd64_alu_reg_imm (code
, X86_ADC
, ins
->dreg
, ins
->inst_imm
);
4451 amd64_alu_reg_reg (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
);
4454 amd64_alu_reg_reg (code
, X86_SBB
, ins
->sreg1
, ins
->sreg2
);
4458 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4459 amd64_alu_reg_imm (code
, X86_SUB
, ins
->dreg
, ins
->inst_imm
);
4462 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4463 amd64_alu_reg_imm (code
, X86_SBB
, ins
->dreg
, ins
->inst_imm
);
4466 amd64_alu_reg_reg (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
);
4470 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4471 amd64_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ins
->inst_imm
);
4474 amd64_imul_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
4479 guint32 size
= (ins
->opcode
== OP_IMUL_IMM
) ? 4 : 8;
4481 switch (ins
->inst_imm
) {
4485 if (ins
->dreg
!= ins
->sreg1
)
4486 amd64_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
, size
);
4487 amd64_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
4490 /* LEA r1, [r2 + r2*2] */
4491 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
4494 /* LEA r1, [r2 + r2*4] */
4495 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
4498 /* LEA r1, [r2 + r2*2] */
4500 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
4501 amd64_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
4504 /* LEA r1, [r2 + r2*8] */
4505 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 3);
4508 /* LEA r1, [r2 + r2*4] */
4510 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
4511 amd64_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
4514 /* LEA r1, [r2 + r2*2] */
4516 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
4517 amd64_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, 2);
4520 /* LEA r1, [r2 + r2*4] */
4521 /* LEA r1, [r1 + r1*4] */
4522 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
4523 amd64_lea_memindex (code
, ins
->dreg
, ins
->dreg
, 0, ins
->dreg
, 2);
4526 /* LEA r1, [r2 + r2*4] */
4528 /* LEA r1, [r1 + r1*4] */
4529 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
4530 amd64_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, 2);
4531 amd64_lea_memindex (code
, ins
->dreg
, ins
->dreg
, 0, ins
->dreg
, 2);
4534 amd64_imul_reg_reg_imm_size (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
, size
);
4541 #if defined( __native_client_codegen__ )
4542 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg2
, 0);
4543 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, TRUE
, "DivideByZeroException");
4545 /* Regalloc magic makes the div/rem cases the same */
4546 if (ins
->sreg2
== AMD64_RDX
) {
4547 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RDX
, 8);
4549 amd64_div_membase (code
, AMD64_RSP
, -8, TRUE
);
4552 amd64_div_reg (code
, ins
->sreg2
, TRUE
);
4557 #if defined( __native_client_codegen__ )
4558 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg2
, 0);
4559 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, TRUE
, "DivideByZeroException");
4561 if (ins
->sreg2
== AMD64_RDX
) {
4562 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RDX
, 8);
4563 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RDX
, AMD64_RDX
);
4564 amd64_div_membase (code
, AMD64_RSP
, -8, FALSE
);
4566 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RDX
, AMD64_RDX
);
4567 amd64_div_reg (code
, ins
->sreg2
, FALSE
);
4572 #if defined( __native_client_codegen__ )
4573 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg2
, 0);
4574 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, TRUE
, "DivideByZeroException");
4576 if (ins
->sreg2
== AMD64_RDX
) {
4577 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RDX
, 8);
4578 amd64_cdq_size (code
, 4);
4579 amd64_div_membase_size (code
, AMD64_RSP
, -8, TRUE
, 4);
4581 amd64_cdq_size (code
, 4);
4582 amd64_div_reg_size (code
, ins
->sreg2
, TRUE
, 4);
4587 #if defined( __native_client_codegen__ )
4588 amd64_alu_reg_imm_size (code
, X86_CMP
, ins
->sreg2
, 0, 4);
4589 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, TRUE
, "DivideByZeroException");
4591 if (ins
->sreg2
== AMD64_RDX
) {
4592 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RDX
, 8);
4593 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RDX
, AMD64_RDX
);
4594 amd64_div_membase_size (code
, AMD64_RSP
, -8, FALSE
, 4);
4596 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RDX
, AMD64_RDX
);
4597 amd64_div_reg_size (code
, ins
->sreg2
, FALSE
, 4);
4601 amd64_imul_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
4602 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O
, FALSE
, "OverflowException");
4605 amd64_alu_reg_reg (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
);
4609 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4610 amd64_alu_reg_imm (code
, X86_OR
, ins
->sreg1
, ins
->inst_imm
);
4613 amd64_alu_reg_reg (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
);
4617 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4618 amd64_alu_reg_imm (code
, X86_XOR
, ins
->sreg1
, ins
->inst_imm
);
4621 g_assert (ins
->sreg2
== AMD64_RCX
);
4622 amd64_shift_reg (code
, X86_SHL
, ins
->dreg
);
4625 g_assert (ins
->sreg2
== AMD64_RCX
);
4626 amd64_shift_reg (code
, X86_SAR
, ins
->dreg
);
4630 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4631 amd64_shift_reg_imm (code
, X86_SAR
, ins
->dreg
, ins
->inst_imm
);
4634 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4635 amd64_shift_reg_imm_size (code
, X86_SHR
, ins
->dreg
, ins
->inst_imm
, 4);
4637 case OP_LSHR_UN_IMM
:
4638 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4639 amd64_shift_reg_imm (code
, X86_SHR
, ins
->dreg
, ins
->inst_imm
);
4642 g_assert (ins
->sreg2
== AMD64_RCX
);
4643 amd64_shift_reg (code
, X86_SHR
, ins
->dreg
);
4647 g_assert (amd64_is_imm32 (ins
->inst_imm
));
4648 amd64_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, ins
->inst_imm
);
4653 amd64_alu_reg_reg_size (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
, 4);
4656 amd64_alu_reg_reg_size (code
, X86_ADC
, ins
->sreg1
, ins
->sreg2
, 4);
4659 amd64_alu_reg_imm_size (code
, X86_ADD
, ins
->dreg
, ins
->inst_imm
, 4);
4662 amd64_alu_reg_imm_size (code
, X86_ADC
, ins
->dreg
, ins
->inst_imm
, 4);
4666 amd64_alu_reg_reg_size (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
, 4);
4669 amd64_alu_reg_reg_size (code
, X86_SBB
, ins
->sreg1
, ins
->sreg2
, 4);
4672 amd64_alu_reg_imm_size (code
, X86_SUB
, ins
->dreg
, ins
->inst_imm
, 4);
4675 amd64_alu_reg_imm_size (code
, X86_SBB
, ins
->dreg
, ins
->inst_imm
, 4);
4678 amd64_alu_reg_reg_size (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
, 4);
4681 amd64_alu_reg_imm_size (code
, X86_AND
, ins
->sreg1
, ins
->inst_imm
, 4);
4684 amd64_alu_reg_reg_size (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
, 4);
4687 amd64_alu_reg_imm_size (code
, X86_OR
, ins
->sreg1
, ins
->inst_imm
, 4);
4690 amd64_alu_reg_reg_size (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
, 4);
4693 amd64_alu_reg_imm_size (code
, X86_XOR
, ins
->sreg1
, ins
->inst_imm
, 4);
4696 amd64_neg_reg_size (code
, ins
->sreg1
, 4);
4699 amd64_not_reg_size (code
, ins
->sreg1
, 4);
4702 g_assert (ins
->sreg2
== AMD64_RCX
);
4703 amd64_shift_reg_size (code
, X86_SHL
, ins
->dreg
, 4);
4706 g_assert (ins
->sreg2
== AMD64_RCX
);
4707 amd64_shift_reg_size (code
, X86_SAR
, ins
->dreg
, 4);
4710 amd64_shift_reg_imm_size (code
, X86_SAR
, ins
->dreg
, ins
->inst_imm
, 4);
4712 case OP_ISHR_UN_IMM
:
4713 amd64_shift_reg_imm_size (code
, X86_SHR
, ins
->dreg
, ins
->inst_imm
, 4);
4716 g_assert (ins
->sreg2
== AMD64_RCX
);
4717 amd64_shift_reg_size (code
, X86_SHR
, ins
->dreg
, 4);
4720 amd64_shift_reg_imm_size (code
, X86_SHL
, ins
->dreg
, ins
->inst_imm
, 4);
4723 amd64_imul_reg_reg_size (code
, ins
->sreg1
, ins
->sreg2
, 4);
4726 amd64_imul_reg_reg_size (code
, ins
->sreg1
, ins
->sreg2
, 4);
4727 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O
, FALSE
, "OverflowException");
4729 case OP_IMUL_OVF_UN
:
4730 case OP_LMUL_OVF_UN
: {
4731 /* the mul operation and the exception check should most likely be split */
4732 int non_eax_reg
, saved_eax
= FALSE
, saved_edx
= FALSE
;
4733 int size
= (ins
->opcode
== OP_IMUL_OVF_UN
) ? 4 : 8;
4734 /*g_assert (ins->sreg2 == X86_EAX);
4735 g_assert (ins->dreg == X86_EAX);*/
4736 if (ins
->sreg2
== X86_EAX
) {
4737 non_eax_reg
= ins
->sreg1
;
4738 } else if (ins
->sreg1
== X86_EAX
) {
4739 non_eax_reg
= ins
->sreg2
;
4741 /* no need to save since we're going to store to it anyway */
4742 if (ins
->dreg
!= X86_EAX
) {
4744 amd64_push_reg (code
, X86_EAX
);
4746 amd64_mov_reg_reg (code
, X86_EAX
, ins
->sreg1
, size
);
4747 non_eax_reg
= ins
->sreg2
;
4749 if (ins
->dreg
== X86_EDX
) {
4752 amd64_push_reg (code
, X86_EAX
);
4756 amd64_push_reg (code
, X86_EDX
);
4758 amd64_mul_reg_size (code
, non_eax_reg
, FALSE
, size
);
4759 /* save before the check since pop and mov don't change the flags */
4760 if (ins
->dreg
!= X86_EAX
)
4761 amd64_mov_reg_reg (code
, ins
->dreg
, X86_EAX
, size
);
4763 amd64_pop_reg (code
, X86_EDX
);
4765 amd64_pop_reg (code
, X86_EAX
);
4766 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O
, FALSE
, "OverflowException");
4770 amd64_alu_reg_reg_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, 4);
4772 case OP_ICOMPARE_IMM
:
4773 amd64_alu_reg_imm_size (code
, X86_CMP
, ins
->sreg1
, ins
->inst_imm
, 4);
4795 EMIT_COND_BRANCH (ins
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)]);
4803 case OP_CMOV_INE_UN
:
4804 case OP_CMOV_IGE_UN
:
4805 case OP_CMOV_IGT_UN
:
4806 case OP_CMOV_ILE_UN
:
4807 case OP_CMOV_ILT_UN
:
4813 case OP_CMOV_LNE_UN
:
4814 case OP_CMOV_LGE_UN
:
4815 case OP_CMOV_LGT_UN
:
4816 case OP_CMOV_LLE_UN
:
4817 case OP_CMOV_LLT_UN
:
4818 g_assert (ins
->dreg
== ins
->sreg1
);
4819 /* This needs to operate on 64 bit values */
4820 amd64_cmov_reg (code
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)], ins
->dreg
, ins
->sreg2
);
4824 amd64_not_reg (code
, ins
->sreg1
);
4827 amd64_neg_reg (code
, ins
->sreg1
);
4832 if ((((guint64
)ins
->inst_c0
) >> 32) == 0 && !mini_get_debug_options()->single_imm_size
)
4833 amd64_mov_reg_imm_size (code
, ins
->dreg
, ins
->inst_c0
, 4);
4835 amd64_mov_reg_imm_size (code
, ins
->dreg
, ins
->inst_c0
, 8);
4838 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)ins
->inst_i1
, ins
->inst_p0
);
4839 amd64_mov_reg_membase (code
, ins
->dreg
, AMD64_RIP
, 0, sizeof(gpointer
));
4842 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)ins
->inst_i1
, ins
->inst_p0
);
4843 amd64_mov_reg_imm_size (code
, ins
->dreg
, 0, 8);
4846 if (ins
->dreg
!= ins
->sreg1
)
4847 amd64_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
, sizeof(mgreg_t
));
4849 case OP_AMD64_SET_XMMREG_R4
: {
4851 if (ins
->dreg
!= ins
->sreg1
)
4852 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
4854 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
4858 case OP_AMD64_SET_XMMREG_R8
: {
4859 if (ins
->dreg
!= ins
->sreg1
)
4860 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
4864 MonoCallInst
*call
= (MonoCallInst
*)ins
;
4865 int i
, save_area_offset
;
4867 g_assert (!cfg
->method
->save_lmf
);
4869 /* Restore callee saved registers */
4870 save_area_offset
= cfg
->arch
.reg_save_area_offset
;
4871 for (i
= 0; i
< AMD64_NREG
; ++i
)
4872 if (AMD64_IS_CALLEE_SAVED_REG (i
) && (cfg
->used_int_regs
& (1 << i
))) {
4873 amd64_mov_reg_membase (code
, i
, cfg
->frame_reg
, save_area_offset
, 8);
4874 save_area_offset
+= 8;
4877 if (cfg
->arch
.omit_fp
) {
4878 if (cfg
->arch
.stack_alloc_size
)
4879 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, cfg
->arch
.stack_alloc_size
);
4881 if (call
->stack_usage
)
4884 /* Copy arguments on the stack to our argument area */
4885 for (i
= 0; i
< call
->stack_usage
; i
+= sizeof(mgreg_t
)) {
4886 amd64_mov_reg_membase (code
, AMD64_RAX
, AMD64_RSP
, i
, sizeof(mgreg_t
));
4887 amd64_mov_membase_reg (code
, AMD64_RBP
, 16 + i
, AMD64_RAX
, sizeof(mgreg_t
));
4893 offset
= code
- cfg
->native_code
;
4894 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_METHOD_JUMP
, call
->method
);
4895 if (cfg
->compile_aot
)
4896 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_RIP
, 0, 8);
4898 amd64_set_reg_template (code
, AMD64_R11
);
4899 amd64_jump_reg (code
, AMD64_R11
);
4900 ins
->flags
|= MONO_INST_GC_CALLSITE
;
4901 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
4905 /* ensure ins->sreg1 is not NULL */
4906 amd64_alu_membase_imm_size (code
, X86_CMP
, ins
->sreg1
, 0, 0, 4);
4909 amd64_lea_membase (code
, AMD64_R11
, cfg
->frame_reg
, cfg
->sig_cookie
);
4910 amd64_mov_membase_reg (code
, ins
->sreg1
, 0, AMD64_R11
, sizeof(gpointer
));
4920 call
= (MonoCallInst
*)ins
;
4922 * The AMD64 ABI forces callers to know about varargs.
4924 if ((call
->signature
->call_convention
== MONO_CALL_VARARG
) && (call
->signature
->pinvoke
))
4925 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RAX
, AMD64_RAX
);
4926 else if ((cfg
->method
->wrapper_type
== MONO_WRAPPER_MANAGED_TO_NATIVE
) && (cfg
->method
->klass
->image
!= mono_defaults
.corlib
)) {
4928 * Since the unmanaged calling convention doesn't contain a
4929 * 'vararg' entry, we have to treat every pinvoke call as a
4930 * potential vararg call.
4934 for (i
= 0; i
< AMD64_XMM_NREG
; ++i
)
4935 if (call
->used_fregs
& (1 << i
))
4938 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RAX
, AMD64_RAX
);
4940 amd64_mov_reg_imm (code
, AMD64_RAX
, nregs
);
4943 if (ins
->flags
& MONO_INST_HAS_METHOD
)
4944 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_METHOD
, call
->method
, FALSE
);
4946 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_ABS
, call
->fptr
, FALSE
);
4947 ins
->flags
|= MONO_INST_GC_CALLSITE
;
4948 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
4949 code
= emit_move_return_value (cfg
, ins
, code
);
4956 case OP_VOIDCALL_REG
:
4958 call
= (MonoCallInst
*)ins
;
4960 if (AMD64_IS_ARGUMENT_REG (ins
->sreg1
)) {
4961 amd64_mov_reg_reg (code
, AMD64_R11
, ins
->sreg1
, 8);
4962 ins
->sreg1
= AMD64_R11
;
4966 * The AMD64 ABI forces callers to know about varargs.
4968 if ((call
->signature
->call_convention
== MONO_CALL_VARARG
) && (call
->signature
->pinvoke
)) {
4969 if (ins
->sreg1
== AMD64_RAX
) {
4970 amd64_mov_reg_reg (code
, AMD64_R11
, AMD64_RAX
, 8);
4971 ins
->sreg1
= AMD64_R11
;
4973 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RAX
, AMD64_RAX
);
4974 } else if ((cfg
->method
->wrapper_type
== MONO_WRAPPER_MANAGED_TO_NATIVE
) && (cfg
->method
->klass
->image
!= mono_defaults
.corlib
)) {
4976 * Since the unmanaged calling convention doesn't contain a
4977 * 'vararg' entry, we have to treat every pinvoke call as a
4978 * potential vararg call.
4982 for (i
= 0; i
< AMD64_XMM_NREG
; ++i
)
4983 if (call
->used_fregs
& (1 << i
))
4985 if (ins
->sreg1
== AMD64_RAX
) {
4986 amd64_mov_reg_reg (code
, AMD64_R11
, AMD64_RAX
, 8);
4987 ins
->sreg1
= AMD64_R11
;
4990 amd64_alu_reg_reg (code
, X86_XOR
, AMD64_RAX
, AMD64_RAX
);
4992 amd64_mov_reg_imm (code
, AMD64_RAX
, nregs
);
4995 amd64_call_reg (code
, ins
->sreg1
);
4996 ins
->flags
|= MONO_INST_GC_CALLSITE
;
4997 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
4998 code
= emit_move_return_value (cfg
, ins
, code
);
5000 case OP_FCALL_MEMBASE
:
5001 case OP_RCALL_MEMBASE
:
5002 case OP_LCALL_MEMBASE
:
5003 case OP_VCALL_MEMBASE
:
5004 case OP_VCALL2_MEMBASE
:
5005 case OP_VOIDCALL_MEMBASE
:
5006 case OP_CALL_MEMBASE
:
5007 call
= (MonoCallInst
*)ins
;
5009 amd64_call_membase (code
, ins
->sreg1
, ins
->inst_offset
);
5010 ins
->flags
|= MONO_INST_GC_CALLSITE
;
5011 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
5012 code
= emit_move_return_value (cfg
, ins
, code
);
5016 MonoInst
*var
= cfg
->dyn_call_var
;
5018 g_assert (var
->opcode
== OP_REGOFFSET
);
5020 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5021 amd64_mov_reg_reg (code
, AMD64_R11
, ins
->sreg1
, 8);
5023 amd64_mov_reg_reg (code
, AMD64_R10
, ins
->sreg2
, 8);
5025 /* Save args buffer */
5026 amd64_mov_membase_reg (code
, var
->inst_basereg
, var
->inst_offset
, AMD64_R11
, 8);
5028 /* Set argument registers */
5029 for (i
= 0; i
< PARAM_REGS
; ++i
)
5030 amd64_mov_reg_membase (code
, param_regs
[i
], AMD64_R11
, i
* sizeof(mgreg_t
), sizeof(mgreg_t
));
5033 amd64_call_reg (code
, AMD64_R10
);
5035 ins
->flags
|= MONO_INST_GC_CALLSITE
;
5036 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
5039 amd64_mov_reg_membase (code
, AMD64_R11
, var
->inst_basereg
, var
->inst_offset
, 8);
5040 amd64_mov_membase_reg (code
, AMD64_R11
, MONO_STRUCT_OFFSET (DynCallArgs
, res
), AMD64_RAX
, 8);
5043 case OP_AMD64_SAVE_SP_TO_LMF
: {
5044 MonoInst
*lmf_var
= cfg
->lmf_var
;
5045 amd64_mov_membase_reg (code
, lmf_var
->inst_basereg
, lmf_var
->inst_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rsp
), AMD64_RSP
, 8);
5049 g_assert_not_reached ();
5050 amd64_push_reg (code
, ins
->sreg1
);
5052 case OP_X86_PUSH_IMM
:
5053 g_assert_not_reached ();
5054 g_assert (amd64_is_imm32 (ins
->inst_imm
));
5055 amd64_push_imm (code
, ins
->inst_imm
);
5057 case OP_X86_PUSH_MEMBASE
:
5058 g_assert_not_reached ();
5059 amd64_push_membase (code
, ins
->inst_basereg
, ins
->inst_offset
);
5061 case OP_X86_PUSH_OBJ
: {
5062 int size
= ALIGN_TO (ins
->inst_imm
, 8);
5064 g_assert_not_reached ();
5066 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, size
);
5067 amd64_push_reg (code
, AMD64_RDI
);
5068 amd64_push_reg (code
, AMD64_RSI
);
5069 amd64_push_reg (code
, AMD64_RCX
);
5070 if (ins
->inst_offset
)
5071 amd64_lea_membase (code
, AMD64_RSI
, ins
->inst_basereg
, ins
->inst_offset
);
5073 amd64_mov_reg_reg (code
, AMD64_RSI
, ins
->inst_basereg
, 8);
5074 amd64_lea_membase (code
, AMD64_RDI
, AMD64_RSP
, (3 * 8));
5075 amd64_mov_reg_imm (code
, AMD64_RCX
, (size
>> 3));
5077 amd64_prefix (code
, X86_REP_PREFIX
);
5079 amd64_pop_reg (code
, AMD64_RCX
);
5080 amd64_pop_reg (code
, AMD64_RSI
);
5081 amd64_pop_reg (code
, AMD64_RDI
);
5084 case OP_GENERIC_CLASS_INIT
: {
5085 static int byte_offset
= -1;
5086 static guint8 bitmask
;
5089 g_assert (ins
->sreg1
== MONO_AMD64_ARG_REG1
);
5091 if (byte_offset
< 0)
5092 mono_marshal_find_bitfield_offset (MonoVTable
, initialized
, &byte_offset
, &bitmask
);
5094 amd64_test_membase_imm_size (code
, ins
->sreg1
, byte_offset
, bitmask
, 1);
5096 amd64_branch8 (code
, X86_CC_NZ
, -1, 1);
5098 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_INTERNAL_METHOD
, "mono_generic_class_init", FALSE
);
5099 ins
->flags
|= MONO_INST_GC_CALLSITE
;
5100 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
5102 x86_patch (jump
, code
);
5107 amd64_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
, ins
->sreg2
, ins
->backend
.shift_amount
);
5109 case OP_X86_LEA_MEMBASE
:
5110 amd64_lea_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
);
5113 amd64_xchg_reg_reg (code
, ins
->sreg1
, ins
->sreg2
, 4);
5116 /* keep alignment */
5117 amd64_alu_reg_imm (code
, X86_ADD
, ins
->sreg1
, MONO_ARCH_FRAME_ALIGNMENT
- 1);
5118 amd64_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ~(MONO_ARCH_FRAME_ALIGNMENT
- 1));
5119 code
= mono_emit_stack_alloc (cfg
, code
, ins
);
5120 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RSP
, 8);
5121 if (cfg
->param_area
)
5122 amd64_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, cfg
->param_area
);
5124 case OP_LOCALLOC_IMM
: {
5125 guint32 size
= ins
->inst_imm
;
5126 size
= (size
+ (MONO_ARCH_FRAME_ALIGNMENT
- 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT
- 1);
5128 if (ins
->flags
& MONO_INST_INIT
) {
5132 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, size
);
5133 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5135 for (i
= 0; i
< size
; i
+= 8)
5136 amd64_mov_membase_reg (code
, AMD64_RSP
, i
, ins
->dreg
, 8);
5137 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RSP
, 8);
5139 amd64_mov_reg_imm (code
, ins
->dreg
, size
);
5140 ins
->sreg1
= ins
->dreg
;
5142 code
= mono_emit_stack_alloc (cfg
, code
, ins
);
5143 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RSP
, 8);
5146 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, size
);
5147 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RSP
, 8);
5149 if (cfg
->param_area
)
5150 amd64_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, cfg
->param_area
);
5154 amd64_mov_reg_reg (code
, AMD64_ARG_REG1
, ins
->sreg1
, 8);
5155 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_INTERNAL_METHOD
,
5156 (gpointer
)"mono_arch_throw_exception", FALSE
);
5157 ins
->flags
|= MONO_INST_GC_CALLSITE
;
5158 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
5162 amd64_mov_reg_reg (code
, AMD64_ARG_REG1
, ins
->sreg1
, 8);
5163 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_INTERNAL_METHOD
,
5164 (gpointer
)"mono_arch_rethrow_exception", FALSE
);
5165 ins
->flags
|= MONO_INST_GC_CALLSITE
;
5166 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
5169 case OP_CALL_HANDLER
:
5171 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 8);
5172 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_BB
, ins
->inst_target_bb
);
5173 amd64_call_imm (code
, 0);
5174 mono_cfg_add_try_hole (cfg
, ins
->inst_eh_block
, code
, bb
);
5175 /* Restore stack alignment */
5176 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 8);
5178 case OP_START_HANDLER
: {
5179 /* Even though we're saving RSP, use sizeof */
5180 /* gpointer because spvar is of type IntPtr */
5181 /* see: mono_create_spvar_for_region */
5182 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
5183 amd64_mov_membase_reg (code
, spvar
->inst_basereg
, spvar
->inst_offset
, AMD64_RSP
, sizeof(gpointer
));
5185 if ((MONO_BBLOCK_IS_IN_REGION (bb
, MONO_REGION_FINALLY
) ||
5186 MONO_BBLOCK_IS_IN_REGION (bb
, MONO_REGION_FINALLY
)) &&
5188 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
5192 case OP_ENDFINALLY
: {
5193 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
5194 amd64_mov_reg_membase (code
, AMD64_RSP
, spvar
->inst_basereg
, spvar
->inst_offset
, sizeof(gpointer
));
5198 case OP_ENDFILTER
: {
5199 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
5200 amd64_mov_reg_membase (code
, AMD64_RSP
, spvar
->inst_basereg
, spvar
->inst_offset
, sizeof(gpointer
));
5201 /* The local allocator will put the result into RAX */
5206 if (ins
->dreg
!= AMD64_RAX
)
5207 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RAX
, sizeof (gpointer
));
5210 ins
->inst_c0
= code
- cfg
->native_code
;
5213 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5214 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5216 if (ins
->inst_target_bb
->native_offset
) {
5217 amd64_jump_code (code
, cfg
->native_code
+ ins
->inst_target_bb
->native_offset
);
5219 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_BB
, ins
->inst_target_bb
);
5220 if ((cfg
->opt
& MONO_OPT_BRANCH
) &&
5221 x86_is_imm8 (ins
->inst_target_bb
->max_offset
- offset
))
5222 x86_jump8 (code
, 0);
5224 x86_jump32 (code
, 0);
5228 amd64_jump_reg (code
, ins
->sreg1
);
5251 amd64_set_reg (code
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], ins
->dreg
, cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)]);
5252 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
5254 case OP_COND_EXC_EQ
:
5255 case OP_COND_EXC_NE_UN
:
5256 case OP_COND_EXC_LT
:
5257 case OP_COND_EXC_LT_UN
:
5258 case OP_COND_EXC_GT
:
5259 case OP_COND_EXC_GT_UN
:
5260 case OP_COND_EXC_GE
:
5261 case OP_COND_EXC_GE_UN
:
5262 case OP_COND_EXC_LE
:
5263 case OP_COND_EXC_LE_UN
:
5264 case OP_COND_EXC_IEQ
:
5265 case OP_COND_EXC_INE_UN
:
5266 case OP_COND_EXC_ILT
:
5267 case OP_COND_EXC_ILT_UN
:
5268 case OP_COND_EXC_IGT
:
5269 case OP_COND_EXC_IGT_UN
:
5270 case OP_COND_EXC_IGE
:
5271 case OP_COND_EXC_IGE_UN
:
5272 case OP_COND_EXC_ILE
:
5273 case OP_COND_EXC_ILE_UN
:
5274 EMIT_COND_SYSTEM_EXCEPTION (cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)], (const char *)ins
->inst_p1
);
5276 case OP_COND_EXC_OV
:
5277 case OP_COND_EXC_NO
:
5279 case OP_COND_EXC_NC
:
5280 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins
->opcode
- OP_COND_EXC_EQ
],
5281 (ins
->opcode
< OP_COND_EXC_NE_UN
), (const char *)ins
->inst_p1
);
5283 case OP_COND_EXC_IOV
:
5284 case OP_COND_EXC_INO
:
5285 case OP_COND_EXC_IC
:
5286 case OP_COND_EXC_INC
:
5287 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins
->opcode
- OP_COND_EXC_IEQ
],
5288 (ins
->opcode
< OP_COND_EXC_INE_UN
), (const char *)ins
->inst_p1
);
5291 /* floating point opcodes */
5293 double d
= *(double *)ins
->inst_p0
;
5295 if ((d
== 0.0) && (mono_signbit (d
) == 0)) {
5296 amd64_sse_xorpd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5299 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_R8
, ins
->inst_p0
);
5300 amd64_sse_movsd_reg_membase (code
, ins
->dreg
, AMD64_RIP
, 0);
5305 float f
= *(float *)ins
->inst_p0
;
5307 if ((f
== 0.0) && (mono_signbit (f
) == 0)) {
5309 amd64_sse_xorps_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5311 amd64_sse_xorpd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5314 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_R4
, ins
->inst_p0
);
5315 amd64_sse_movss_reg_membase (code
, ins
->dreg
, AMD64_RIP
, 0);
5317 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5321 case OP_STORER8_MEMBASE_REG
:
5322 amd64_sse_movsd_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
);
5324 case OP_LOADR8_MEMBASE
:
5325 amd64_sse_movsd_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
5327 case OP_STORER4_MEMBASE_REG
:
5329 amd64_sse_movss_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
);
5331 /* This requires a double->single conversion */
5332 amd64_sse_cvtsd2ss_reg_reg (code
, MONO_ARCH_FP_SCRATCH_REG
, ins
->sreg1
);
5333 amd64_sse_movss_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, MONO_ARCH_FP_SCRATCH_REG
);
5336 case OP_LOADR4_MEMBASE
:
5338 amd64_sse_movss_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
5340 amd64_sse_movss_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
5341 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5344 case OP_ICONV_TO_R4
:
5346 amd64_sse_cvtsi2ss_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5348 amd64_sse_cvtsi2ss_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5349 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5352 case OP_ICONV_TO_R8
:
5353 amd64_sse_cvtsi2sd_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5355 case OP_LCONV_TO_R4
:
5357 amd64_sse_cvtsi2ss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5359 amd64_sse_cvtsi2ss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5360 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5363 case OP_LCONV_TO_R8
:
5364 amd64_sse_cvtsi2sd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5366 case OP_FCONV_TO_R4
:
5368 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5370 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5371 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5374 case OP_FCONV_TO_I1
:
5375 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 1, TRUE
);
5377 case OP_FCONV_TO_U1
:
5378 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 1, FALSE
);
5380 case OP_FCONV_TO_I2
:
5381 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 2, TRUE
);
5383 case OP_FCONV_TO_U2
:
5384 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 2, FALSE
);
5386 case OP_FCONV_TO_U4
:
5387 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 4, FALSE
);
5389 case OP_FCONV_TO_I4
:
5391 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 4, TRUE
);
5393 case OP_FCONV_TO_I8
:
5394 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, ins
->sreg1
, 8, TRUE
);
5397 case OP_RCONV_TO_I1
:
5398 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5399 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, FALSE
);
5401 case OP_RCONV_TO_U1
:
5402 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5403 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
5405 case OP_RCONV_TO_I2
:
5406 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5407 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, TRUE
);
5409 case OP_RCONV_TO_U2
:
5410 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5411 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, TRUE
);
5413 case OP_RCONV_TO_I4
:
5414 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5416 case OP_RCONV_TO_U4
:
5417 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
5419 case OP_RCONV_TO_I8
:
5420 amd64_sse_cvtss2si_reg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
5422 case OP_RCONV_TO_R8
:
5423 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5425 case OP_RCONV_TO_R4
:
5426 if (ins
->dreg
!= ins
->sreg1
)
5427 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5430 case OP_LCONV_TO_R_UN
: {
5433 /* Based on gcc code */
5434 amd64_test_reg_reg (code
, ins
->sreg1
, ins
->sreg1
);
5435 br
[0] = code
; x86_branch8 (code
, X86_CC_S
, 0, TRUE
);
5438 amd64_sse_cvtsi2sd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5439 br
[1] = code
; x86_jump8 (code
, 0);
5440 amd64_patch (br
[0], code
);
5443 /* Save to the red zone */
5444 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RAX
, 8);
5445 amd64_mov_membase_reg (code
, AMD64_RSP
, -16, AMD64_RCX
, 8);
5446 amd64_mov_reg_reg (code
, AMD64_RCX
, ins
->sreg1
, 8);
5447 amd64_mov_reg_reg (code
, AMD64_RAX
, ins
->sreg1
, 8);
5448 amd64_alu_reg_imm (code
, X86_AND
, AMD64_RCX
, 1);
5449 amd64_shift_reg_imm (code
, X86_SHR
, AMD64_RAX
, 1);
5450 amd64_alu_reg_imm (code
, X86_OR
, AMD64_RAX
, AMD64_RCX
);
5451 amd64_sse_cvtsi2sd_reg_reg (code
, ins
->dreg
, AMD64_RAX
);
5452 amd64_sse_addsd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5454 amd64_mov_reg_membase (code
, AMD64_RCX
, AMD64_RSP
, -16, 8);
5455 amd64_mov_reg_membase (code
, AMD64_RAX
, AMD64_RSP
, -8, 8);
5456 amd64_patch (br
[1], code
);
5459 case OP_LCONV_TO_OVF_U4
:
5460 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg1
, 0);
5461 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT
, TRUE
, "OverflowException");
5462 amd64_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
, 8);
5464 case OP_LCONV_TO_OVF_I4_UN
:
5465 amd64_alu_reg_imm (code
, X86_CMP
, ins
->sreg1
, 0x7fffffff);
5466 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT
, FALSE
, "OverflowException");
5467 amd64_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
, 8);
5470 if (ins
->dreg
!= ins
->sreg1
)
5471 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5474 if (ins
->dreg
!= ins
->sreg1
)
5475 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
5477 case OP_MOVE_F_TO_I4
:
5479 amd64_movd_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
5481 amd64_sse_cvtsd2ss_reg_reg (code
, MONO_ARCH_FP_SCRATCH_REG
, ins
->sreg1
);
5482 amd64_movd_reg_xreg_size (code
, ins
->dreg
, MONO_ARCH_FP_SCRATCH_REG
, 8);
5485 case OP_MOVE_I4_TO_F
:
5486 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
5488 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
5490 case OP_MOVE_F_TO_I8
:
5491 amd64_movd_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
5493 case OP_MOVE_I8_TO_F
:
5494 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
5497 amd64_sse_addsd_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5500 amd64_sse_subsd_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5503 amd64_sse_mulsd_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5506 amd64_sse_divsd_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5509 static double r8_0
= -0.0;
5511 g_assert (ins
->sreg1
== ins
->dreg
);
5513 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_R8
, &r8_0
);
5514 amd64_sse_xorpd_reg_membase (code
, ins
->dreg
, AMD64_RIP
, 0);
5518 EMIT_SSE2_FPFUNC (code
, fsin
, ins
->dreg
, ins
->sreg1
);
5521 EMIT_SSE2_FPFUNC (code
, fcos
, ins
->dreg
, ins
->sreg1
);
5524 static guint64 d
= 0x7fffffffffffffffUL
;
5526 g_assert (ins
->sreg1
== ins
->dreg
);
5528 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_R8
, &d
);
5529 amd64_sse_andpd_reg_membase (code
, ins
->dreg
, AMD64_RIP
, 0);
5533 EMIT_SSE2_FPFUNC (code
, fsqrt
, ins
->dreg
, ins
->sreg1
);
5537 amd64_sse_addss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5540 amd64_sse_subss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5543 amd64_sse_mulss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5546 amd64_sse_divss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
5549 static float r4_0
= -0.0;
5551 g_assert (ins
->sreg1
== ins
->dreg
);
5553 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_R4
, &r4_0
);
5554 amd64_sse_movss_reg_membase (code
, MONO_ARCH_FP_SCRATCH_REG
, AMD64_RIP
, 0);
5555 amd64_sse_xorps_reg_reg (code
, ins
->dreg
, MONO_ARCH_FP_SCRATCH_REG
);
5560 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5561 g_assert (ins
->dreg
== ins
->sreg1
);
5562 amd64_alu_reg_reg_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, 4);
5563 amd64_cmov_reg_size (code
, X86_CC_GT
, TRUE
, ins
->dreg
, ins
->sreg2
, 4);
5566 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5567 g_assert (ins
->dreg
== ins
->sreg1
);
5568 amd64_alu_reg_reg_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, 4);
5569 amd64_cmov_reg_size (code
, X86_CC_GT
, FALSE
, ins
->dreg
, ins
->sreg2
, 4);
5572 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5573 g_assert (ins
->dreg
== ins
->sreg1
);
5574 amd64_alu_reg_reg_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, 4);
5575 amd64_cmov_reg_size (code
, X86_CC_LT
, TRUE
, ins
->dreg
, ins
->sreg2
, 4);
5578 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5579 g_assert (ins
->dreg
== ins
->sreg1
);
5580 amd64_alu_reg_reg_size (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, 4);
5581 amd64_cmov_reg_size (code
, X86_CC_LT
, FALSE
, ins
->dreg
, ins
->sreg2
, 4);
5584 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5585 g_assert (ins
->dreg
== ins
->sreg1
);
5586 amd64_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
5587 amd64_cmov_reg (code
, X86_CC_GT
, TRUE
, ins
->dreg
, ins
->sreg2
);
5590 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5591 g_assert (ins
->dreg
== ins
->sreg1
);
5592 amd64_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
5593 amd64_cmov_reg (code
, X86_CC_GT
, FALSE
, ins
->dreg
, ins
->sreg2
);
5596 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5597 g_assert (ins
->dreg
== ins
->sreg1
);
5598 amd64_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
5599 amd64_cmov_reg (code
, X86_CC_LT
, TRUE
, ins
->dreg
, ins
->sreg2
);
5602 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
5603 g_assert (ins
->dreg
== ins
->sreg1
);
5604 amd64_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
5605 amd64_cmov_reg (code
, X86_CC_LT
, FALSE
, ins
->dreg
, ins
->sreg2
);
5611 * The two arguments are swapped because the fbranch instructions
5612 * depend on this for the non-sse case to work.
5614 amd64_sse_comisd_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5618 * FIXME: Get rid of this.
5619 * The two arguments are swapped because the fbranch instructions
5620 * depend on this for the non-sse case to work.
5622 amd64_sse_comiss_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5626 /* zeroing the register at the start results in
5627 * shorter and faster code (we can also remove the widening op)
5629 guchar
*unordered_check
;
5631 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5632 amd64_sse_comisd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
5633 unordered_check
= code
;
5634 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5636 if (ins
->opcode
== OP_FCEQ
) {
5637 amd64_set_reg (code
, X86_CC_EQ
, ins
->dreg
, FALSE
);
5638 amd64_patch (unordered_check
, code
);
5640 guchar
*jump_to_end
;
5641 amd64_set_reg (code
, X86_CC_NE
, ins
->dreg
, FALSE
);
5643 x86_jump8 (code
, 0);
5644 amd64_patch (unordered_check
, code
);
5645 amd64_inc_reg (code
, ins
->dreg
);
5646 amd64_patch (jump_to_end
, code
);
5652 /* zeroing the register at the start results in
5653 * shorter and faster code (we can also remove the widening op)
5655 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5656 amd64_sse_comisd_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5657 if (ins
->opcode
== OP_FCLT_UN
) {
5658 guchar
*unordered_check
= code
;
5659 guchar
*jump_to_end
;
5660 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5661 amd64_set_reg (code
, X86_CC_GT
, ins
->dreg
, FALSE
);
5663 x86_jump8 (code
, 0);
5664 amd64_patch (unordered_check
, code
);
5665 amd64_inc_reg (code
, ins
->dreg
);
5666 amd64_patch (jump_to_end
, code
);
5668 amd64_set_reg (code
, X86_CC_GT
, ins
->dreg
, FALSE
);
5673 guchar
*unordered_check
;
5674 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5675 amd64_sse_comisd_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5676 unordered_check
= code
;
5677 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5678 amd64_set_reg (code
, X86_CC_NB
, ins
->dreg
, FALSE
);
5679 amd64_patch (unordered_check
, code
);
5684 /* zeroing the register at the start results in
5685 * shorter and faster code (we can also remove the widening op)
5687 guchar
*unordered_check
;
5689 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5690 amd64_sse_comisd_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5691 if (ins
->opcode
== OP_FCGT
) {
5692 unordered_check
= code
;
5693 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5694 amd64_set_reg (code
, X86_CC_LT
, ins
->dreg
, FALSE
);
5695 amd64_patch (unordered_check
, code
);
5697 amd64_set_reg (code
, X86_CC_LT
, ins
->dreg
, FALSE
);
5702 guchar
*unordered_check
;
5703 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5704 amd64_sse_comisd_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5705 unordered_check
= code
;
5706 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5707 amd64_set_reg (code
, X86_CC_NA
, ins
->dreg
, FALSE
);
5708 amd64_patch (unordered_check
, code
);
5718 gboolean unordered
= FALSE
;
5720 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5721 amd64_sse_comiss_reg_reg (code
, ins
->sreg2
, ins
->sreg1
);
5723 switch (ins
->opcode
) {
5725 x86_cond
= X86_CC_EQ
;
5728 x86_cond
= X86_CC_LT
;
5731 x86_cond
= X86_CC_GT
;
5734 x86_cond
= X86_CC_GT
;
5738 x86_cond
= X86_CC_LT
;
5742 g_assert_not_reached ();
5747 guchar
*unordered_check
;
5748 guchar
*jump_to_end
;
5750 unordered_check
= code
;
5751 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5752 amd64_set_reg (code
, x86_cond
, ins
->dreg
, FALSE
);
5754 x86_jump8 (code
, 0);
5755 amd64_patch (unordered_check
, code
);
5756 amd64_inc_reg (code
, ins
->dreg
);
5757 amd64_patch (jump_to_end
, code
);
5759 amd64_set_reg (code
, x86_cond
, ins
->dreg
, FALSE
);
5763 case OP_FCLT_MEMBASE
:
5764 case OP_FCGT_MEMBASE
:
5765 case OP_FCLT_UN_MEMBASE
:
5766 case OP_FCGT_UN_MEMBASE
:
5767 case OP_FCEQ_MEMBASE
: {
5768 guchar
*unordered_check
, *jump_to_end
;
5771 amd64_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
5772 amd64_sse_comisd_reg_membase (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
5774 switch (ins
->opcode
) {
5775 case OP_FCEQ_MEMBASE
:
5776 x86_cond
= X86_CC_EQ
;
5778 case OP_FCLT_MEMBASE
:
5779 case OP_FCLT_UN_MEMBASE
:
5780 x86_cond
= X86_CC_LT
;
5782 case OP_FCGT_MEMBASE
:
5783 case OP_FCGT_UN_MEMBASE
:
5784 x86_cond
= X86_CC_GT
;
5787 g_assert_not_reached ();
5790 unordered_check
= code
;
5791 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5792 amd64_set_reg (code
, x86_cond
, ins
->dreg
, FALSE
);
5794 switch (ins
->opcode
) {
5795 case OP_FCEQ_MEMBASE
:
5796 case OP_FCLT_MEMBASE
:
5797 case OP_FCGT_MEMBASE
:
5798 amd64_patch (unordered_check
, code
);
5800 case OP_FCLT_UN_MEMBASE
:
5801 case OP_FCGT_UN_MEMBASE
:
5803 x86_jump8 (code
, 0);
5804 amd64_patch (unordered_check
, code
);
5805 amd64_inc_reg (code
, ins
->dreg
);
5806 amd64_patch (jump_to_end
, code
);
5814 guchar
*jump
= code
;
5815 x86_branch8 (code
, X86_CC_P
, 0, TRUE
);
5816 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
5817 amd64_patch (jump
, code
);
5821 /* Branch if C013 != 100 */
5822 /* branch if !ZF or (PF|CF) */
5823 EMIT_COND_BRANCH (ins
, X86_CC_NE
, FALSE
);
5824 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
5825 EMIT_COND_BRANCH (ins
, X86_CC_B
, FALSE
);
5828 EMIT_COND_BRANCH (ins
, X86_CC_GT
, FALSE
);
5831 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
5832 EMIT_COND_BRANCH (ins
, X86_CC_GT
, FALSE
);
5836 if (ins
->opcode
== OP_FBGT
) {
5839 /* skip branch if C1=1 */
5841 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5842 /* branch if (C0 | C3) = 1 */
5843 EMIT_COND_BRANCH (ins
, X86_CC_LT
, FALSE
);
5844 amd64_patch (br1
, code
);
5847 EMIT_COND_BRANCH (ins
, X86_CC_LT
, FALSE
);
5851 /* Branch if C013 == 100 or 001 */
5854 /* skip branch if C1=1 */
5856 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5857 /* branch if (C0 | C3) = 1 */
5858 EMIT_COND_BRANCH (ins
, X86_CC_BE
, FALSE
);
5859 amd64_patch (br1
, code
);
5863 /* Branch if C013 == 000 */
5864 EMIT_COND_BRANCH (ins
, X86_CC_LE
, FALSE
);
5867 /* Branch if C013=000 or 100 */
5870 /* skip branch if C1=1 */
5872 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
5873 /* branch if C0=0 */
5874 EMIT_COND_BRANCH (ins
, X86_CC_NB
, FALSE
);
5875 amd64_patch (br1
, code
);
5879 /* Branch if C013 != 001 */
5880 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
5881 EMIT_COND_BRANCH (ins
, X86_CC_GE
, FALSE
);
5884 /* Transfer value to the fp stack */
5885 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 16);
5886 amd64_movsd_membase_reg (code
, AMD64_RSP
, 0, ins
->sreg1
);
5887 amd64_fld_membase (code
, AMD64_RSP
, 0, TRUE
);
5889 amd64_push_reg (code
, AMD64_RAX
);
5891 amd64_fnstsw (code
);
5892 amd64_alu_reg_imm (code
, X86_AND
, AMD64_RAX
, 0x4100);
5893 amd64_alu_reg_imm (code
, X86_CMP
, AMD64_RAX
, X86_FP_C0
);
5894 amd64_pop_reg (code
, AMD64_RAX
);
5895 amd64_fstp (code
, 0);
5896 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, FALSE
, "ArithmeticException");
5897 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 16);
5900 code
= mono_amd64_emit_tls_get (code
, ins
->dreg
, ins
->inst_offset
);
5903 case OP_TLS_GET_REG
:
5904 code
= emit_tls_get_reg (code
, ins
->dreg
, ins
->sreg1
);
5907 code
= amd64_emit_tls_set (code
, ins
->sreg1
, ins
->inst_offset
);
5910 case OP_TLS_SET_REG
: {
5911 code
= amd64_emit_tls_set_reg (code
, ins
->sreg1
, ins
->sreg2
);
5914 case OP_MEMORY_BARRIER
: {
5915 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
5919 case OP_ATOMIC_ADD_I4
:
5920 case OP_ATOMIC_ADD_I8
: {
5921 int dreg
= ins
->dreg
;
5922 guint32 size
= (ins
->opcode
== OP_ATOMIC_ADD_I4
) ? 4 : 8;
5924 if ((dreg
== ins
->sreg2
) || (dreg
== ins
->inst_basereg
))
5927 amd64_mov_reg_reg (code
, dreg
, ins
->sreg2
, size
);
5928 amd64_prefix (code
, X86_LOCK_PREFIX
);
5929 amd64_xadd_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, dreg
, size
);
5930 /* dreg contains the old value, add with sreg2 value */
5931 amd64_alu_reg_reg_size (code
, X86_ADD
, dreg
, ins
->sreg2
, size
);
5933 if (ins
->dreg
!= dreg
)
5934 amd64_mov_reg_reg (code
, ins
->dreg
, dreg
, size
);
5938 case OP_ATOMIC_EXCHANGE_I4
:
5939 case OP_ATOMIC_EXCHANGE_I8
: {
5940 guint32 size
= ins
->opcode
== OP_ATOMIC_EXCHANGE_I4
? 4 : 8;
5942 /* LOCK prefix is implied. */
5943 amd64_mov_reg_reg (code
, GP_SCRATCH_REG
, ins
->sreg2
, size
);
5944 amd64_xchg_membase_reg_size (code
, ins
->sreg1
, ins
->inst_offset
, GP_SCRATCH_REG
, size
);
5945 amd64_mov_reg_reg (code
, ins
->dreg
, GP_SCRATCH_REG
, size
);
5948 case OP_ATOMIC_CAS_I4
:
5949 case OP_ATOMIC_CAS_I8
: {
5952 if (ins
->opcode
== OP_ATOMIC_CAS_I8
)
5958 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5959 * an explanation of how this works.
5961 g_assert (ins
->sreg3
== AMD64_RAX
);
5962 g_assert (ins
->sreg1
!= AMD64_RAX
);
5963 g_assert (ins
->sreg1
!= ins
->sreg2
);
5965 amd64_prefix (code
, X86_LOCK_PREFIX
);
5966 amd64_cmpxchg_membase_reg_size (code
, ins
->sreg1
, ins
->inst_offset
, ins
->sreg2
, size
);
5968 if (ins
->dreg
!= AMD64_RAX
)
5969 amd64_mov_reg_reg (code
, ins
->dreg
, AMD64_RAX
, size
);
5972 case OP_ATOMIC_LOAD_I1
: {
5973 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, FALSE
);
5976 case OP_ATOMIC_LOAD_U1
: {
5977 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, FALSE
);
5980 case OP_ATOMIC_LOAD_I2
: {
5981 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, TRUE
);
5984 case OP_ATOMIC_LOAD_U2
: {
5985 amd64_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, TRUE
);
5988 case OP_ATOMIC_LOAD_I4
: {
5989 amd64_movsxd_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
5992 case OP_ATOMIC_LOAD_U4
:
5993 case OP_ATOMIC_LOAD_I8
:
5994 case OP_ATOMIC_LOAD_U8
: {
5995 amd64_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, ins
->opcode
== OP_ATOMIC_LOAD_U4
? 4 : 8);
5998 case OP_ATOMIC_LOAD_R4
: {
5999 amd64_sse_movss_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
6000 amd64_sse_cvtss2sd_reg_reg (code
, ins
->dreg
, ins
->dreg
);
6003 case OP_ATOMIC_LOAD_R8
: {
6004 amd64_sse_movsd_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
);
6007 case OP_ATOMIC_STORE_I1
:
6008 case OP_ATOMIC_STORE_U1
:
6009 case OP_ATOMIC_STORE_I2
:
6010 case OP_ATOMIC_STORE_U2
:
6011 case OP_ATOMIC_STORE_I4
:
6012 case OP_ATOMIC_STORE_U4
:
6013 case OP_ATOMIC_STORE_I8
:
6014 case OP_ATOMIC_STORE_U8
: {
6017 switch (ins
->opcode
) {
6018 case OP_ATOMIC_STORE_I1
:
6019 case OP_ATOMIC_STORE_U1
:
6022 case OP_ATOMIC_STORE_I2
:
6023 case OP_ATOMIC_STORE_U2
:
6026 case OP_ATOMIC_STORE_I4
:
6027 case OP_ATOMIC_STORE_U4
:
6030 case OP_ATOMIC_STORE_I8
:
6031 case OP_ATOMIC_STORE_U8
:
6036 amd64_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, size
);
6038 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
6042 case OP_ATOMIC_STORE_R4
: {
6043 amd64_sse_cvtsd2ss_reg_reg (code
, MONO_ARCH_FP_SCRATCH_REG
, ins
->sreg1
);
6044 amd64_sse_movss_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, MONO_ARCH_FP_SCRATCH_REG
);
6046 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
6050 case OP_ATOMIC_STORE_R8
: {
6053 amd64_sse_movsd_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
);
6057 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
6061 case OP_CARD_TABLE_WBARRIER
: {
6062 int ptr
= ins
->sreg1
;
6063 int value
= ins
->sreg2
;
6065 int nursery_shift
, card_table_shift
;
6066 gpointer card_table_mask
;
6067 size_t nursery_size
;
6069 gpointer card_table
= mono_gc_get_card_table (&card_table_shift
, &card_table_mask
);
6070 guint64 nursery_start
= (guint64
)mono_gc_get_nursery (&nursery_shift
, &nursery_size
);
6071 guint64 shifted_nursery_start
= nursery_start
>> nursery_shift
;
6073 /*If either point to the stack we can simply avoid the WB. This happens due to
6074 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6076 if (ins
->sreg1
== AMD64_RSP
|| ins
->sreg2
== AMD64_RSP
)
6080 * We need one register we can clobber, we choose EDX and make sreg1
6081 * fixed EAX to work around limitations in the local register allocator.
6082 * sreg2 might get allocated to EDX, but that is not a problem since
6083 * we use it before clobbering EDX.
6085 g_assert (ins
->sreg1
== AMD64_RAX
);
6088 * This is the code we produce:
6091 * edx >>= nursery_shift
6092 * cmp edx, (nursery_start >> nursery_shift)
6095 * edx >>= card_table_shift
6101 if (mono_gc_card_table_nursery_check ()) {
6102 if (value
!= AMD64_RDX
)
6103 amd64_mov_reg_reg (code
, AMD64_RDX
, value
, 8);
6104 amd64_shift_reg_imm (code
, X86_SHR
, AMD64_RDX
, nursery_shift
);
6105 if (shifted_nursery_start
>> 31) {
6107 * The value we need to compare against is 64 bits, so we need
6108 * another spare register. We use RBX, which we save and
6111 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RBX
, 8);
6112 amd64_mov_reg_imm (code
, AMD64_RBX
, shifted_nursery_start
);
6113 amd64_alu_reg_reg (code
, X86_CMP
, AMD64_RDX
, AMD64_RBX
);
6114 amd64_mov_reg_membase (code
, AMD64_RBX
, AMD64_RSP
, -8, 8);
6116 amd64_alu_reg_imm (code
, X86_CMP
, AMD64_RDX
, shifted_nursery_start
);
6118 br
= code
; x86_branch8 (code
, X86_CC_NE
, -1, FALSE
);
6120 amd64_mov_reg_reg (code
, AMD64_RDX
, ptr
, 8);
6121 amd64_shift_reg_imm (code
, X86_SHR
, AMD64_RDX
, card_table_shift
);
6122 if (card_table_mask
)
6123 amd64_alu_reg_imm (code
, X86_AND
, AMD64_RDX
, (guint32
)(guint64
)card_table_mask
);
6125 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR
, card_table
);
6126 amd64_alu_reg_membase (code
, X86_ADD
, AMD64_RDX
, AMD64_RIP
, 0);
6128 amd64_mov_membase_imm (code
, AMD64_RDX
, 0, 1, 1);
6130 if (mono_gc_card_table_nursery_check ())
6131 x86_patch (br
, code
);
6134 #ifdef MONO_ARCH_SIMD_INTRINSICS
6135 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6137 amd64_sse_addps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6140 amd64_sse_divps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6143 amd64_sse_mulps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6146 amd64_sse_subps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6149 amd64_sse_maxps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6152 amd64_sse_minps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6155 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 7);
6156 amd64_sse_cmpps_reg_reg_imm (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
6159 amd64_sse_andps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6162 amd64_sse_andnps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6165 amd64_sse_orps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6168 amd64_sse_xorps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6171 amd64_sse_sqrtps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6174 amd64_sse_rsqrtps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6177 amd64_sse_rcpps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6180 amd64_sse_addsubps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6183 amd64_sse_haddps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6186 amd64_sse_hsubps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6189 amd64_sse_movshdup_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6192 amd64_sse_movsldup_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6195 case OP_PSHUFLEW_HIGH
:
6196 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
6197 amd64_sse_pshufhw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
6199 case OP_PSHUFLEW_LOW
:
6200 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
6201 amd64_sse_pshuflw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
6204 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
6205 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
6208 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
6209 amd64_sse_shufps_reg_reg_imm (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
6212 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0x3);
6213 amd64_sse_shufpd_reg_reg_imm (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
6217 amd64_sse_addpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6220 amd64_sse_divpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6223 amd64_sse_mulpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6226 amd64_sse_subpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6229 amd64_sse_maxpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6232 amd64_sse_minpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6235 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 7);
6236 amd64_sse_cmppd_reg_reg_imm (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
6239 amd64_sse_andpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6242 amd64_sse_andnpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6245 amd64_sse_orpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6248 amd64_sse_xorpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6251 amd64_sse_sqrtpd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6254 amd64_sse_addsubpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6257 amd64_sse_haddpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6260 amd64_sse_hsubpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6263 amd64_sse_movddup_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6266 case OP_EXTRACT_MASK
:
6267 amd64_sse_pmovmskb_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6271 amd64_sse_pand_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6274 amd64_sse_por_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6277 amd64_sse_pxor_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6281 amd64_sse_paddb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6284 amd64_sse_paddw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6287 amd64_sse_paddd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6290 amd64_sse_paddq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6294 amd64_sse_psubb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6297 amd64_sse_psubw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6300 amd64_sse_psubd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6303 amd64_sse_psubq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6307 amd64_sse_pmaxub_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6310 amd64_sse_pmaxuw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6313 amd64_sse_pmaxud_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6317 amd64_sse_pmaxsb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6320 amd64_sse_pmaxsw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6323 amd64_sse_pmaxsd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6327 amd64_sse_pavgb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6330 amd64_sse_pavgw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6334 amd64_sse_pminub_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6337 amd64_sse_pminuw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6340 amd64_sse_pminud_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6344 amd64_sse_pminsb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6347 amd64_sse_pminsw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6350 amd64_sse_pminsd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6354 amd64_sse_pcmpeqb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6357 amd64_sse_pcmpeqw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6360 amd64_sse_pcmpeqd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6363 amd64_sse_pcmpeqq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6367 amd64_sse_pcmpgtb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6370 amd64_sse_pcmpgtw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6373 amd64_sse_pcmpgtd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6376 amd64_sse_pcmpgtq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6379 case OP_PSUM_ABS_DIFF
:
6380 amd64_sse_psadbw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6383 case OP_UNPACK_LOWB
:
6384 amd64_sse_punpcklbw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6386 case OP_UNPACK_LOWW
:
6387 amd64_sse_punpcklwd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6389 case OP_UNPACK_LOWD
:
6390 amd64_sse_punpckldq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6392 case OP_UNPACK_LOWQ
:
6393 amd64_sse_punpcklqdq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6395 case OP_UNPACK_LOWPS
:
6396 amd64_sse_unpcklps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6398 case OP_UNPACK_LOWPD
:
6399 amd64_sse_unpcklpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6402 case OP_UNPACK_HIGHB
:
6403 amd64_sse_punpckhbw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6405 case OP_UNPACK_HIGHW
:
6406 amd64_sse_punpckhwd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6408 case OP_UNPACK_HIGHD
:
6409 amd64_sse_punpckhdq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6411 case OP_UNPACK_HIGHQ
:
6412 amd64_sse_punpckhqdq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6414 case OP_UNPACK_HIGHPS
:
6415 amd64_sse_unpckhps_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6417 case OP_UNPACK_HIGHPD
:
6418 amd64_sse_unpckhpd_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6422 amd64_sse_packsswb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6425 amd64_sse_packssdw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6428 amd64_sse_packuswb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6431 amd64_sse_packusdw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6434 case OP_PADDB_SAT_UN
:
6435 amd64_sse_paddusb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6437 case OP_PSUBB_SAT_UN
:
6438 amd64_sse_psubusb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6440 case OP_PADDW_SAT_UN
:
6441 amd64_sse_paddusw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6443 case OP_PSUBW_SAT_UN
:
6444 amd64_sse_psubusw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6448 amd64_sse_paddsb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6451 amd64_sse_psubsb_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6454 amd64_sse_paddsw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6457 amd64_sse_psubsw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6461 amd64_sse_pmullw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6464 amd64_sse_pmulld_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6467 amd64_sse_pmuludq_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6469 case OP_PMULW_HIGH_UN
:
6470 amd64_sse_pmulhuw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6473 amd64_sse_pmulhw_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
6477 amd64_sse_psrlw_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6480 amd64_sse_psrlw_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6484 amd64_sse_psraw_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6487 amd64_sse_psraw_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6491 amd64_sse_psllw_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6494 amd64_sse_psllw_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6498 amd64_sse_psrld_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6501 amd64_sse_psrld_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6505 amd64_sse_psrad_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6508 amd64_sse_psrad_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6512 amd64_sse_pslld_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6515 amd64_sse_pslld_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6519 amd64_sse_psrlq_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6522 amd64_sse_psrlq_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6525 /*TODO: This is appart of the sse spec but not added
6527 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6530 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6535 amd64_sse_psllq_reg_imm (code
, ins
->dreg
, ins
->inst_imm
);
6538 amd64_sse_psllq_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6541 amd64_sse_cvtdq2pd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6544 amd64_sse_cvtdq2ps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6547 amd64_sse_cvtpd2dq_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6550 amd64_sse_cvtpd2ps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6553 amd64_sse_cvtps2dq_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6556 amd64_sse_cvtps2pd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6559 amd64_sse_cvttpd2dq_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6562 amd64_sse_cvttps2dq_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6566 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6569 amd64_movd_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6573 amd64_movhlps_reg_reg (code
, MONO_ARCH_FP_SCRATCH_REG
, ins
->sreg1
);
6574 amd64_movd_reg_xreg_size (code
, ins
->dreg
, MONO_ARCH_FP_SCRATCH_REG
, 8);
6576 amd64_movd_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
6581 amd64_movd_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6583 amd64_shift_reg_imm (code
, X86_SHR
, ins
->dreg
, ins
->inst_c0
* 8);
6584 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, ins
->opcode
== OP_EXTRACT_I1
, FALSE
);
6588 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6590 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6591 amd64_sse_pextrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
6592 amd64_widen_reg_size (code
, ins
->dreg
, ins
->dreg
, ins
->opcode
== OP_EXTRACT_I2
, TRUE
, 4);
6596 amd64_movhlps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6598 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6601 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
6603 case OP_EXTRACTX_U2
:
6604 amd64_sse_pextrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
6606 case OP_INSERTX_U1_SLOW
:
6607 /*sreg1 is the extracted ireg (scratch)
6608 /sreg2 is the to be inserted ireg (scratch)
6609 /dreg is the xreg to receive the value*/
6611 /*clear the bits from the extracted word*/
6612 amd64_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ins
->inst_c0
& 1 ? 0x00FF : 0xFF00);
6613 /*shift the value to insert if needed*/
6614 if (ins
->inst_c0
& 1)
6615 amd64_shift_reg_imm_size (code
, X86_SHL
, ins
->sreg2
, 8, 4);
6616 /*join them together*/
6617 amd64_alu_reg_reg (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
);
6618 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
/ 2);
6620 case OP_INSERTX_I4_SLOW
:
6621 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg2
, ins
->inst_c0
* 2);
6622 amd64_shift_reg_imm (code
, X86_SHR
, ins
->sreg2
, 16);
6623 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg2
, ins
->inst_c0
* 2 + 1);
6625 case OP_INSERTX_I8_SLOW
:
6626 amd64_movd_xreg_reg_size(code
, MONO_ARCH_FP_SCRATCH_REG
, ins
->sreg2
, 8);
6628 amd64_movlhps_reg_reg (code
, ins
->dreg
, MONO_ARCH_FP_SCRATCH_REG
);
6630 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, MONO_ARCH_FP_SCRATCH_REG
);
6633 case OP_INSERTX_R4_SLOW
:
6634 switch (ins
->inst_c0
) {
6637 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6639 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6642 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(1, 0, 2, 3));
6644 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6646 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6647 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(1, 0, 2, 3));
6650 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(2, 1, 0, 3));
6652 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6654 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6655 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(2, 1, 0, 3));
6658 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(3, 1, 2, 0));
6660 amd64_sse_movss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6662 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6663 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, mono_simd_shuffle_mask(3, 1, 2, 0));
6667 case OP_INSERTX_R8_SLOW
:
6669 amd64_movlhps_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6671 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg2
);
6673 case OP_STOREX_MEMBASE_REG
:
6674 case OP_STOREX_MEMBASE
:
6675 amd64_sse_movups_membase_reg (code
, ins
->dreg
, ins
->inst_offset
, ins
->sreg1
);
6677 case OP_LOADX_MEMBASE
:
6678 amd64_sse_movups_reg_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
6680 case OP_LOADX_ALIGNED_MEMBASE
:
6681 amd64_sse_movaps_reg_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
6683 case OP_STOREX_ALIGNED_MEMBASE_REG
:
6684 amd64_sse_movaps_membase_reg (code
, ins
->dreg
, ins
->inst_offset
, ins
->sreg1
);
6686 case OP_STOREX_NTA_MEMBASE_REG
:
6687 amd64_sse_movntps_reg_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
6689 case OP_PREFETCH_MEMBASE
:
6690 amd64_sse_prefetch_reg_membase (code
, ins
->backend
.arg_info
, ins
->sreg1
, ins
->inst_offset
);
6694 /*FIXME the peephole pass should have killed this*/
6695 if (ins
->dreg
!= ins
->sreg1
)
6696 amd64_sse_movaps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6699 amd64_sse_pxor_reg_reg (code
, ins
->dreg
, ins
->dreg
);
6701 case OP_ICONV_TO_R4_RAW
:
6702 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6705 case OP_FCONV_TO_R8_X
:
6706 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6709 case OP_XCONV_R8_TO_I4
:
6710 amd64_sse_cvttsd2si_reg_xreg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6711 switch (ins
->backend
.source_opcode
) {
6712 case OP_FCONV_TO_I1
:
6713 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, FALSE
);
6715 case OP_FCONV_TO_U1
:
6716 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
6718 case OP_FCONV_TO_I2
:
6719 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, TRUE
);
6721 case OP_FCONV_TO_U2
:
6722 amd64_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, TRUE
);
6728 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, 0);
6729 amd64_sse_pinsrw_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, 1);
6730 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, 0);
6733 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 4);
6734 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, 0);
6737 amd64_movd_xreg_reg_size (code
, ins
->dreg
, ins
->sreg1
, 8);
6738 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, 0x44);
6742 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6744 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6745 amd64_sse_cvtsd2ss_reg_reg (code
, ins
->dreg
, ins
->dreg
);
6747 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, 0);
6750 amd64_sse_movsd_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
6751 amd64_sse_pshufd_reg_reg_imm (code
, ins
->dreg
, ins
->dreg
, 0x44);
6754 case OP_LIVERANGE_START
: {
6755 if (cfg
->verbose_level
> 1)
6756 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg
, ins
->inst_c0
)->vreg
, (int)(code
- cfg
->native_code
));
6757 MONO_VARINFO (cfg
, ins
->inst_c0
)->live_range_start
= code
- cfg
->native_code
;
6760 case OP_LIVERANGE_END
: {
6761 if (cfg
->verbose_level
> 1)
6762 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg
, ins
->inst_c0
)->vreg
, (int)(code
- cfg
->native_code
));
6763 MONO_VARINFO (cfg
, ins
->inst_c0
)->live_range_end
= code
- cfg
->native_code
;
6766 case OP_GC_SAFE_POINT
: {
6767 const char *polling_func
= NULL
;
6768 int compare_val
= 0;
6771 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6772 polling_func
= "mono_nacl_gc";
6773 compare_val
= 0xFFFFFFFF;
6775 g_assert (mono_threads_is_coop_enabled ());
6776 polling_func
= "mono_threads_state_poll";
6780 amd64_test_membase_imm_size (code
, ins
->sreg1
, 0, compare_val
, 4);
6781 br
[0] = code
; x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
6782 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_INTERNAL_METHOD
, polling_func
, FALSE
);
6783 amd64_patch (br
[0], code
);
6787 case OP_GC_LIVENESS_DEF
:
6788 case OP_GC_LIVENESS_USE
:
6789 case OP_GC_PARAM_SLOT_LIVENESS_DEF
:
6790 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
6792 case OP_GC_SPILL_SLOT_LIVENESS_DEF
:
6793 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
6794 bb
->spill_slot_defs
= g_slist_prepend_mempool (cfg
->mempool
, bb
->spill_slot_defs
, ins
);
6797 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins
->opcode
), __FUNCTION__
);
6798 g_assert_not_reached ();
6801 if ((code
- cfg
->native_code
- offset
) > max_len
) {
6802 #if !defined(__native_client_codegen__)
6803 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6804 mono_inst_name (ins
->opcode
), max_len
, code
- cfg
->native_code
- offset
);
6805 g_assert_not_reached ();
6810 cfg
->code_len
= code
- cfg
->native_code
;
6813 #endif /* DISABLE_JIT */
6816 mono_arch_register_lowlevel_calls (void)
6818 /* The signature doesn't matter */
6819 mono_register_jit_icall (mono_amd64_throw_exception
, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE
);
6823 mono_arch_patch_code_new (MonoCompile
*cfg
, MonoDomain
*domain
, guint8
*code
, MonoJumpInfo
*ji
, gpointer target
)
6825 unsigned char *ip
= ji
->ip
.i
+ code
;
6828 * Debug code to help track down problems where the target of a near call is
6831 if (amd64_is_near_call (ip
)) {
6832 gint64 disp
= (guint8
*)target
- (guint8
*)ip
;
6834 if (!amd64_is_imm32 (disp
)) {
6835 printf ("TYPE: %d\n", ji
->type
);
6837 case MONO_PATCH_INFO_INTERNAL_METHOD
:
6838 printf ("V: %s\n", ji
->data
.name
);
6840 case MONO_PATCH_INFO_METHOD_JUMP
:
6841 case MONO_PATCH_INFO_METHOD
:
6842 printf ("V: %s\n", ji
->data
.method
->name
);
6850 amd64_patch (ip
, (gpointer
)target
);
6856 get_max_epilog_size (MonoCompile
*cfg
)
6858 int max_epilog_size
= 16;
6860 if (cfg
->method
->save_lmf
)
6861 max_epilog_size
+= 256;
6863 if (mono_jit_trace_calls
!= NULL
)
6864 max_epilog_size
+= 50;
6866 if (cfg
->prof_options
& MONO_PROFILE_ENTER_LEAVE
)
6867 max_epilog_size
+= 50;
6869 max_epilog_size
+= (AMD64_NREG
* 2);
6871 return max_epilog_size
;
6875 * This macro is used for testing whenever the unwinder works correctly at every point
6876 * where an async exception can happen.
6878 /* This will generate a SIGSEGV at the given point in the code */
6879 #define async_exc_point(code) do { \
6880 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6881 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6882 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6883 cfg->arch.async_point_count ++; \
6888 mono_arch_emit_prolog (MonoCompile
*cfg
)
6890 MonoMethod
*method
= cfg
->method
;
6892 MonoMethodSignature
*sig
;
6894 int alloc_size
, pos
, i
, cfa_offset
, quad
, max_epilog_size
, save_area_offset
;
6897 MonoInst
*lmf_var
= cfg
->lmf_var
;
6898 gboolean args_clobbered
= FALSE
;
6899 gboolean trace
= FALSE
;
6900 #ifdef __native_client_codegen__
6901 guint alignment_check
;
6904 cfg
->code_size
= MAX (cfg
->header
->code_size
* 4, 1024);
6906 #if defined(__default_codegen__)
6907 code
= cfg
->native_code
= (unsigned char *)g_malloc (cfg
->code_size
);
6908 #elif defined(__native_client_codegen__)
6909 /* native_code_alloc is not 32-byte aligned, native_code is. */
6910 cfg
->native_code_alloc
= g_malloc (cfg
->code_size
+ kNaClAlignment
);
6912 /* Align native_code to next nearest kNaclAlignment byte. */
6913 cfg
->native_code
= (uintptr_t)cfg
->native_code_alloc
+ kNaClAlignment
;
6914 cfg
->native_code
= (uintptr_t)cfg
->native_code
& ~kNaClAlignmentMask
;
6916 code
= cfg
->native_code
;
6918 alignment_check
= (guint
)cfg
->native_code
& kNaClAlignmentMask
;
6919 g_assert (alignment_check
== 0);
6922 if (mono_jit_trace_calls
!= NULL
&& mono_trace_eval (method
))
6925 /* Amount of stack space allocated by register saving code */
6928 /* Offset between RSP and the CFA */
6932 * The prolog consists of the following parts:
6934 * - push rbp, mov rbp, rsp
6935 * - save callee saved regs using pushes
6937 * - save rgctx if needed
6938 * - save lmf if needed
6941 * - save rgctx if needed
6942 * - save lmf if needed
6943 * - save callee saved regs using moves
6948 mono_emit_unwind_op_def_cfa (cfg
, code
, AMD64_RSP
, 8);
6949 // IP saved at CFA - 8
6950 mono_emit_unwind_op_offset (cfg
, code
, AMD64_RIP
, -cfa_offset
);
6951 async_exc_point (code
);
6952 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
, SLOT_NOREF
);
6954 if (!cfg
->arch
.omit_fp
) {
6955 amd64_push_reg (code
, AMD64_RBP
);
6957 mono_emit_unwind_op_def_cfa_offset (cfg
, code
, cfa_offset
);
6958 mono_emit_unwind_op_offset (cfg
, code
, AMD64_RBP
, - cfa_offset
);
6959 async_exc_point (code
);
6961 mono_arch_unwindinfo_add_push_nonvol (&cfg
->arch
.unwindinfo
, cfg
->native_code
, code
, AMD64_RBP
);
6963 /* These are handled automatically by the stack marking code */
6964 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
, SLOT_NOREF
);
6966 amd64_mov_reg_reg (code
, AMD64_RBP
, AMD64_RSP
, sizeof(mgreg_t
));
6967 mono_emit_unwind_op_def_cfa_reg (cfg
, code
, AMD64_RBP
);
6968 async_exc_point (code
);
6970 mono_arch_unwindinfo_add_set_fpreg (&cfg
->arch
.unwindinfo
, cfg
->native_code
, code
, AMD64_RBP
);
6974 /* The param area is always at offset 0 from sp */
6975 /* This needs to be allocated here, since it has to come after the spill area */
6976 if (cfg
->param_area
) {
6977 if (cfg
->arch
.omit_fp
)
6979 g_assert_not_reached ();
6980 cfg
->stack_offset
+= ALIGN_TO (cfg
->param_area
, sizeof(mgreg_t
));
6983 if (cfg
->arch
.omit_fp
) {
6985 * On enter, the stack is misaligned by the pushing of the return
6986 * address. It is either made aligned by the pushing of %rbp, or by
6989 alloc_size
= ALIGN_TO (cfg
->stack_offset
, 8);
6990 if ((alloc_size
% 16) == 0) {
6992 /* Mark the padding slot as NOREF */
6993 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
- sizeof (mgreg_t
), SLOT_NOREF
);
6996 alloc_size
= ALIGN_TO (cfg
->stack_offset
, MONO_ARCH_FRAME_ALIGNMENT
);
6997 if (cfg
->stack_offset
!= alloc_size
) {
6998 /* Mark the padding slot as NOREF */
6999 mini_gc_set_slot_type_from_fp (cfg
, -alloc_size
+ cfg
->param_area
, SLOT_NOREF
);
7001 cfg
->arch
.sp_fp_offset
= alloc_size
;
7005 cfg
->arch
.stack_alloc_size
= alloc_size
;
7007 /* Allocate stack frame */
7009 /* See mono_emit_stack_alloc */
7010 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7011 guint32 remaining_size
= alloc_size
;
7012 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
7013 guint32 required_code_size
= ((remaining_size
/ 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7014 guint32 offset
= code
- cfg
->native_code
;
7015 if (G_UNLIKELY (required_code_size
>= (cfg
->code_size
- offset
))) {
7016 while (required_code_size
>= (cfg
->code_size
- offset
))
7017 cfg
->code_size
*= 2;
7018 cfg
->native_code
= (unsigned char *)mono_realloc_native_code (cfg
);
7019 code
= cfg
->native_code
+ offset
;
7020 cfg
->stat_code_reallocs
++;
7023 while (remaining_size
>= 0x1000) {
7024 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 0x1000);
7025 if (cfg
->arch
.omit_fp
) {
7026 cfa_offset
+= 0x1000;
7027 mono_emit_unwind_op_def_cfa_offset (cfg
, code
, cfa_offset
);
7029 async_exc_point (code
);
7031 if (cfg
->arch
.omit_fp
)
7032 mono_arch_unwindinfo_add_alloc_stack (&cfg
->arch
.unwindinfo
, cfg
->native_code
, code
, 0x1000);
7035 amd64_test_membase_reg (code
, AMD64_RSP
, 0, AMD64_RSP
);
7036 remaining_size
-= 0x1000;
7038 if (remaining_size
) {
7039 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, remaining_size
);
7040 if (cfg
->arch
.omit_fp
) {
7041 cfa_offset
+= remaining_size
;
7042 mono_emit_unwind_op_def_cfa_offset (cfg
, code
, cfa_offset
);
7043 async_exc_point (code
);
7046 if (cfg
->arch
.omit_fp
)
7047 mono_arch_unwindinfo_add_alloc_stack (&cfg
->arch
.unwindinfo
, cfg
->native_code
, code
, remaining_size
);
7051 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, alloc_size
);
7052 if (cfg
->arch
.omit_fp
) {
7053 cfa_offset
+= alloc_size
;
7054 mono_emit_unwind_op_def_cfa_offset (cfg
, code
, cfa_offset
);
7055 async_exc_point (code
);
7060 /* Stack alignment check */
7063 amd64_mov_reg_reg (code
, AMD64_RAX
, AMD64_RSP
, 8);
7064 amd64_alu_reg_imm (code
, X86_AND
, AMD64_RAX
, 0xf);
7065 amd64_alu_reg_imm (code
, X86_CMP
, AMD64_RAX
, 0);
7066 x86_branch8 (code
, X86_CC_EQ
, 2, FALSE
);
7067 amd64_breakpoint (code
);
7071 if (mini_get_debug_options ()->init_stacks
) {
7072 /* Fill the stack frame with a dummy value to force deterministic behavior */
7074 /* Save registers to the red zone */
7075 amd64_mov_membase_reg (code
, AMD64_RSP
, -8, AMD64_RDI
, 8);
7076 amd64_mov_membase_reg (code
, AMD64_RSP
, -16, AMD64_RCX
, 8);
7078 amd64_mov_reg_imm (code
, AMD64_RAX
, 0x2a2a2a2a2a2a2a2a);
7079 amd64_mov_reg_imm (code
, AMD64_RCX
, alloc_size
/ 8);
7080 amd64_mov_reg_reg (code
, AMD64_RDI
, AMD64_RSP
, 8);
7083 #if defined(__default_codegen__)
7084 amd64_prefix (code
, X86_REP_PREFIX
);
7086 #elif defined(__native_client_codegen__)
7087 /* NaCl stos pseudo-instruction */
7088 amd64_codegen_pre (code
);
7089 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
7090 amd64_mov_reg_reg (code
, AMD64_RDI
, AMD64_RDI
, 4);
7091 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7092 amd64_lea_memindex_size (code
, AMD64_RDI
, AMD64_R15
, 0, AMD64_RDI
, 0, 8);
7093 amd64_prefix (code
, X86_REP_PREFIX
);
7095 amd64_codegen_post (code
);
7096 #endif /* __native_client_codegen__ */
7098 amd64_mov_reg_membase (code
, AMD64_RDI
, AMD64_RSP
, -8, 8);
7099 amd64_mov_reg_membase (code
, AMD64_RCX
, AMD64_RSP
, -16, 8);
7103 if (method
->save_lmf
)
7104 code
= emit_setup_lmf (cfg
, code
, lmf_var
->inst_offset
, cfa_offset
);
7106 /* Save callee saved registers */
7107 if (cfg
->arch
.omit_fp
) {
7108 save_area_offset
= cfg
->arch
.reg_save_area_offset
;
7109 /* Save caller saved registers after sp is adjusted */
7110 /* The registers are saved at the bottom of the frame */
7111 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7113 /* The registers are saved just below the saved rbp */
7114 save_area_offset
= cfg
->arch
.reg_save_area_offset
;
7117 for (i
= 0; i
< AMD64_NREG
; ++i
) {
7118 if (AMD64_IS_CALLEE_SAVED_REG (i
) && (cfg
->arch
.saved_iregs
& (1 << i
))) {
7119 amd64_mov_membase_reg (code
, cfg
->frame_reg
, save_area_offset
, i
, 8);
7121 if (cfg
->arch
.omit_fp
) {
7122 mono_emit_unwind_op_offset (cfg
, code
, i
, - (cfa_offset
- save_area_offset
));
7123 /* These are handled automatically by the stack marking code */
7124 mini_gc_set_slot_type_from_cfa (cfg
, - (cfa_offset
- save_area_offset
), SLOT_NOREF
);
7126 mono_emit_unwind_op_offset (cfg
, code
, i
, - (-save_area_offset
+ (2 * 8)));
7130 save_area_offset
+= 8;
7131 async_exc_point (code
);
7135 /* store runtime generic context */
7136 if (cfg
->rgctx_var
) {
7137 g_assert (cfg
->rgctx_var
->opcode
== OP_REGOFFSET
&&
7138 (cfg
->rgctx_var
->inst_basereg
== AMD64_RBP
|| cfg
->rgctx_var
->inst_basereg
== AMD64_RSP
));
7140 amd64_mov_membase_reg (code
, cfg
->rgctx_var
->inst_basereg
, cfg
->rgctx_var
->inst_offset
, MONO_ARCH_RGCTX_REG
, sizeof(gpointer
));
7142 mono_add_var_location (cfg
, cfg
->rgctx_var
, TRUE
, MONO_ARCH_RGCTX_REG
, 0, 0, code
- cfg
->native_code
);
7143 mono_add_var_location (cfg
, cfg
->rgctx_var
, FALSE
, cfg
->rgctx_var
->inst_basereg
, cfg
->rgctx_var
->inst_offset
, code
- cfg
->native_code
, 0);
7146 /* compute max_length in order to use short forward jumps */
7147 max_epilog_size
= get_max_epilog_size (cfg
);
7148 if (cfg
->opt
& MONO_OPT_BRANCH
) {
7149 for (bb
= cfg
->bb_entry
; bb
; bb
= bb
->next_bb
) {
7153 if (cfg
->prof_options
& MONO_PROFILE_COVERAGE
)
7155 /* max alignment for loops */
7156 if ((cfg
->opt
& MONO_OPT_LOOP
) && bb_is_loop_start (bb
))
7157 max_length
+= LOOP_ALIGNMENT
;
7158 #ifdef __native_client_codegen__
7159 /* max alignment for native client */
7160 max_length
+= kNaClAlignment
;
7163 MONO_BB_FOR_EACH_INS (bb
, ins
) {
7164 #ifdef __native_client_codegen__
7166 int space_in_block
= kNaClAlignment
-
7167 ((max_length
+ cfg
->code_len
) & kNaClAlignmentMask
);
7168 int max_len
= ((guint8
*)ins_get_spec (ins
->opcode
))[MONO_INST_LEN
];
7169 if (space_in_block
< max_len
&& max_len
< kNaClAlignment
) {
7170 max_length
+= space_in_block
;
7173 #endif /*__native_client_codegen__*/
7174 max_length
+= ((guint8
*)ins_get_spec (ins
->opcode
))[MONO_INST_LEN
];
7177 /* Take prolog and epilog instrumentation into account */
7178 if (bb
== cfg
->bb_entry
|| bb
== cfg
->bb_exit
)
7179 max_length
+= max_epilog_size
;
7181 bb
->max_length
= max_length
;
7185 sig
= mono_method_signature (method
);
7188 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
7190 if (sig
->ret
->type
!= MONO_TYPE_VOID
) {
7191 /* Save volatile arguments to the stack */
7192 if (cfg
->vret_addr
&& (cfg
->vret_addr
->opcode
!= OP_REGVAR
))
7193 amd64_mov_membase_reg (code
, cfg
->vret_addr
->inst_basereg
, cfg
->vret_addr
->inst_offset
, cinfo
->ret
.reg
, 8);
7196 /* Keep this in sync with emit_load_volatile_arguments */
7197 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
7198 ArgInfo
*ainfo
= cinfo
->args
+ i
;
7200 ins
= cfg
->args
[i
];
7202 if ((ins
->flags
& MONO_INST_IS_DEAD
) && !trace
)
7203 /* Unused arguments */
7206 /* Save volatile arguments to the stack */
7207 if (ins
->opcode
!= OP_REGVAR
) {
7208 switch (ainfo
->storage
) {
7214 if (stack_offset & 0x1)
7216 else if (stack_offset & 0x2)
7218 else if (stack_offset & 0x4)
7223 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, ainfo
->reg
, size
);
7226 * Save the original location of 'this',
7227 * get_generic_info_from_stack_frame () needs this to properly look up
7228 * the argument value during the handling of async exceptions.
7230 if (ins
== cfg
->args
[0]) {
7231 mono_add_var_location (cfg
, ins
, TRUE
, ainfo
->reg
, 0, 0, code
- cfg
->native_code
);
7232 mono_add_var_location (cfg
, ins
, FALSE
, ins
->inst_basereg
, ins
->inst_offset
, code
- cfg
->native_code
, 0);
7236 case ArgInFloatSSEReg
:
7237 amd64_movss_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, ainfo
->reg
);
7239 case ArgInDoubleSSEReg
:
7240 amd64_movsd_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, ainfo
->reg
);
7242 case ArgValuetypeInReg
:
7243 for (quad
= 0; quad
< 2; quad
++) {
7244 switch (ainfo
->pair_storage
[quad
]) {
7246 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
+ (quad
* sizeof(mgreg_t
)), ainfo
->pair_regs
[quad
], sizeof(mgreg_t
));
7248 case ArgInFloatSSEReg
:
7249 amd64_movss_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
+ (quad
* sizeof(mgreg_t
)), ainfo
->pair_regs
[quad
]);
7251 case ArgInDoubleSSEReg
:
7252 amd64_movsd_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
+ (quad
* sizeof(mgreg_t
)), ainfo
->pair_regs
[quad
]);
7257 g_assert_not_reached ();
7261 case ArgValuetypeAddrInIReg
:
7262 if (ainfo
->pair_storage
[0] == ArgInIReg
)
7263 amd64_mov_membase_reg (code
, ins
->inst_left
->inst_basereg
, ins
->inst_left
->inst_offset
, ainfo
->pair_regs
[0], sizeof (gpointer
));
7265 case ArgGSharedVtInReg
:
7266 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, ainfo
->reg
, 8);
7272 /* Argument allocated to (non-volatile) register */
7273 switch (ainfo
->storage
) {
7275 amd64_mov_reg_reg (code
, ins
->dreg
, ainfo
->reg
, 8);
7278 amd64_mov_reg_membase (code
, ins
->dreg
, AMD64_RBP
, ARGS_OFFSET
+ ainfo
->offset
, 8);
7281 g_assert_not_reached ();
7284 if (ins
== cfg
->args
[0]) {
7285 mono_add_var_location (cfg
, ins
, TRUE
, ainfo
->reg
, 0, 0, code
- cfg
->native_code
);
7286 mono_add_var_location (cfg
, ins
, TRUE
, ins
->dreg
, 0, code
- cfg
->native_code
, 0);
7291 if (cfg
->method
->save_lmf
)
7292 args_clobbered
= TRUE
;
7295 args_clobbered
= TRUE
;
7296 code
= (guint8
*)mono_arch_instrument_prolog (cfg
, mono_trace_enter_method
, code
, TRUE
);
7299 if (cfg
->prof_options
& MONO_PROFILE_ENTER_LEAVE
)
7300 args_clobbered
= TRUE
;
7303 * Optimize the common case of the first bblock making a call with the same
7304 * arguments as the method. This works because the arguments are still in their
7305 * original argument registers.
7306 * FIXME: Generalize this
7308 if (!args_clobbered
) {
7309 MonoBasicBlock
*first_bb
= cfg
->bb_entry
;
7311 int filter
= FILTER_IL_SEQ_POINT
;
7313 next
= mono_bb_first_inst (first_bb
, filter
);
7314 if (!next
&& first_bb
->next_bb
) {
7315 first_bb
= first_bb
->next_bb
;
7316 next
= mono_bb_first_inst (first_bb
, filter
);
7319 if (first_bb
->in_count
> 1)
7322 for (i
= 0; next
&& i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
7323 ArgInfo
*ainfo
= cinfo
->args
+ i
;
7324 gboolean match
= FALSE
;
7326 ins
= cfg
->args
[i
];
7327 if (ins
->opcode
!= OP_REGVAR
) {
7328 switch (ainfo
->storage
) {
7330 if (((next
->opcode
== OP_LOAD_MEMBASE
) || (next
->opcode
== OP_LOADI4_MEMBASE
)) && next
->inst_basereg
== ins
->inst_basereg
&& next
->inst_offset
== ins
->inst_offset
) {
7331 if (next
->dreg
== ainfo
->reg
) {
7335 next
->opcode
= OP_MOVE
;
7336 next
->sreg1
= ainfo
->reg
;
7337 /* Only continue if the instruction doesn't change argument regs */
7338 if (next
->dreg
== ainfo
->reg
|| next
->dreg
== AMD64_RAX
)
7348 /* Argument allocated to (non-volatile) register */
7349 switch (ainfo
->storage
) {
7351 if (next
->opcode
== OP_MOVE
&& next
->sreg1
== ins
->dreg
&& next
->dreg
== ainfo
->reg
) {
7362 next
= mono_inst_next (next
, filter
);
7363 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7370 if (cfg
->gen_sdb_seq_points
) {
7371 MonoInst
*info_var
= (MonoInst
*)cfg
->arch
.seq_point_info_var
;
7373 /* Initialize seq_point_info_var */
7374 if (cfg
->compile_aot
) {
7375 /* Initialize the variable from a GOT slot */
7376 /* Same as OP_AOTCONST */
7377 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_SEQ_POINT_INFO
, cfg
->method
);
7378 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_RIP
, 0, sizeof(gpointer
));
7379 g_assert (info_var
->opcode
== OP_REGOFFSET
);
7380 amd64_mov_membase_reg (code
, info_var
->inst_basereg
, info_var
->inst_offset
, AMD64_R11
, 8);
7383 if (cfg
->compile_aot
) {
7384 /* Initialize ss_tramp_var */
7385 ins
= (MonoInst
*)cfg
->arch
.ss_tramp_var
;
7386 g_assert (ins
->opcode
== OP_REGOFFSET
);
7388 amd64_mov_reg_membase (code
, AMD64_R11
, info_var
->inst_basereg
, info_var
->inst_offset
, 8);
7389 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_R11
, MONO_STRUCT_OFFSET (SeqPointInfo
, ss_tramp_addr
), 8);
7390 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, AMD64_R11
, 8);
7392 /* Initialize ss_tramp_var */
7393 ins
= (MonoInst
*)cfg
->arch
.ss_tramp_var
;
7394 g_assert (ins
->opcode
== OP_REGOFFSET
);
7396 amd64_mov_reg_imm (code
, AMD64_R11
, (guint64
)&ss_trampoline
);
7397 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, AMD64_R11
, 8);
7399 /* Initialize bp_tramp_var */
7400 ins
= (MonoInst
*)cfg
->arch
.bp_tramp_var
;
7401 g_assert (ins
->opcode
== OP_REGOFFSET
);
7403 amd64_mov_reg_imm (code
, AMD64_R11
, (guint64
)&bp_trampoline
);
7404 amd64_mov_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, AMD64_R11
, 8);
7408 cfg
->code_len
= code
- cfg
->native_code
;
7410 g_assert (cfg
->code_len
< cfg
->code_size
);
7416 mono_arch_emit_epilog (MonoCompile
*cfg
)
7418 MonoMethod
*method
= cfg
->method
;
7421 int max_epilog_size
;
7423 gint32 lmf_offset
= cfg
->lmf_var
? ((MonoInst
*)cfg
->lmf_var
)->inst_offset
: -1;
7424 gint32 save_area_offset
= cfg
->arch
.reg_save_area_offset
;
7426 max_epilog_size
= get_max_epilog_size (cfg
);
7428 while (cfg
->code_len
+ max_epilog_size
> (cfg
->code_size
- 16)) {
7429 cfg
->code_size
*= 2;
7430 cfg
->native_code
= (unsigned char *)mono_realloc_native_code (cfg
);
7431 cfg
->stat_code_reallocs
++;
7433 code
= cfg
->native_code
+ cfg
->code_len
;
7435 cfg
->has_unwind_info_for_epilog
= TRUE
;
7437 /* Mark the start of the epilog */
7438 mono_emit_unwind_op_mark_loc (cfg
, code
, 0);
7440 /* Save the uwind state which is needed by the out-of-line code */
7441 mono_emit_unwind_op_remember_state (cfg
, code
);
7443 if (mono_jit_trace_calls
!= NULL
&& mono_trace_eval (method
))
7444 code
= (guint8
*)mono_arch_instrument_epilog (cfg
, mono_trace_leave_method
, code
, TRUE
);
7446 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7448 if (method
->save_lmf
) {
7449 /* check if we need to restore protection of the stack after a stack overflow */
7450 if (!cfg
->compile_aot
&& mono_get_jit_tls_offset () != -1) {
7452 code
= mono_amd64_emit_tls_get (code
, AMD64_RCX
, mono_get_jit_tls_offset ());
7453 /* we load the value in a separate instruction: this mechanism may be
7454 * used later as a safer way to do thread interruption
7456 amd64_mov_reg_membase (code
, AMD64_RCX
, AMD64_RCX
, MONO_STRUCT_OFFSET (MonoJitTlsData
, restore_stack_prot
), 8);
7457 x86_alu_reg_imm (code
, X86_CMP
, X86_ECX
, 0);
7459 x86_branch8 (code
, X86_CC_Z
, 0, FALSE
);
7460 /* note that the call trampoline will preserve eax/edx */
7461 x86_call_reg (code
, X86_ECX
);
7462 x86_patch (patch
, code
);
7464 /* FIXME: maybe save the jit tls in the prolog */
7466 if (cfg
->used_int_regs
& (1 << AMD64_RBP
)) {
7467 amd64_mov_reg_membase (code
, AMD64_RBP
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, rbp
), 8);
7471 /* Restore callee saved regs */
7472 for (i
= 0; i
< AMD64_NREG
; ++i
) {
7473 if (AMD64_IS_CALLEE_SAVED_REG (i
) && (cfg
->arch
.saved_iregs
& (1 << i
))) {
7474 /* Restore only used_int_regs, not arch.saved_iregs */
7475 if (cfg
->used_int_regs
& (1 << i
)) {
7476 amd64_mov_reg_membase (code
, i
, cfg
->frame_reg
, save_area_offset
, 8);
7477 mono_emit_unwind_op_same_value (cfg
, code
, i
);
7478 async_exc_point (code
);
7480 save_area_offset
+= 8;
7484 /* Load returned vtypes into registers if needed */
7485 cinfo
= (CallInfo
*)cfg
->arch
.cinfo
;
7486 if (cinfo
->ret
.storage
== ArgValuetypeInReg
) {
7487 ArgInfo
*ainfo
= &cinfo
->ret
;
7488 MonoInst
*inst
= cfg
->ret
;
7490 for (quad
= 0; quad
< 2; quad
++) {
7491 switch (ainfo
->pair_storage
[quad
]) {
7493 amd64_mov_reg_membase (code
, ainfo
->pair_regs
[quad
], inst
->inst_basereg
, inst
->inst_offset
+ (quad
* sizeof(mgreg_t
)), ainfo
->pair_size
[quad
]);
7495 case ArgInFloatSSEReg
:
7496 amd64_movss_reg_membase (code
, ainfo
->pair_regs
[quad
], inst
->inst_basereg
, inst
->inst_offset
+ (quad
* sizeof(mgreg_t
)));
7498 case ArgInDoubleSSEReg
:
7499 amd64_movsd_reg_membase (code
, ainfo
->pair_regs
[quad
], inst
->inst_basereg
, inst
->inst_offset
+ (quad
* sizeof(mgreg_t
)));
7504 g_assert_not_reached ();
7509 if (cfg
->arch
.omit_fp
) {
7510 if (cfg
->arch
.stack_alloc_size
) {
7511 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, cfg
->arch
.stack_alloc_size
);
7515 mono_emit_unwind_op_same_value (cfg
, code
, AMD64_RBP
);
7517 mono_emit_unwind_op_def_cfa (cfg
, code
, AMD64_RSP
, 8);
7518 async_exc_point (code
);
7521 /* Restore the unwind state to be the same as before the epilog */
7522 mono_emit_unwind_op_restore_state (cfg
, code
);
7524 cfg
->code_len
= code
- cfg
->native_code
;
7526 g_assert (cfg
->code_len
< cfg
->code_size
);
7530 mono_arch_emit_exceptions (MonoCompile
*cfg
)
7532 MonoJumpInfo
*patch_info
;
7535 MonoClass
*exc_classes
[16];
7536 guint8
*exc_throw_start
[16], *exc_throw_end
[16];
7537 guint32 code_size
= 0;
7539 /* Compute needed space */
7540 for (patch_info
= cfg
->patch_info
; patch_info
; patch_info
= patch_info
->next
) {
7541 if (patch_info
->type
== MONO_PATCH_INFO_EXC
)
7543 if (patch_info
->type
== MONO_PATCH_INFO_R8
)
7544 code_size
+= 8 + 15; /* sizeof (double) + alignment */
7545 if (patch_info
->type
== MONO_PATCH_INFO_R4
)
7546 code_size
+= 4 + 15; /* sizeof (float) + alignment */
7547 if (patch_info
->type
== MONO_PATCH_INFO_GC_CARD_TABLE_ADDR
)
7548 code_size
+= 8 + 7; /*sizeof (void*) + alignment */
7551 #ifdef __native_client_codegen__
7552 /* Give us extra room on Native Client. This could be */
7553 /* more carefully calculated, but bundle alignment makes */
7554 /* it much trickier, so *2 like other places is good. */
7558 while (cfg
->code_len
+ code_size
> (cfg
->code_size
- 16)) {
7559 cfg
->code_size
*= 2;
7560 cfg
->native_code
= (unsigned char *)mono_realloc_native_code (cfg
);
7561 cfg
->stat_code_reallocs
++;
7564 code
= cfg
->native_code
+ cfg
->code_len
;
7566 /* add code to raise exceptions */
7568 for (patch_info
= cfg
->patch_info
; patch_info
; patch_info
= patch_info
->next
) {
7569 switch (patch_info
->type
) {
7570 case MONO_PATCH_INFO_EXC
: {
7571 MonoClass
*exc_class
;
7575 amd64_patch (patch_info
->ip
.i
+ cfg
->native_code
, code
);
7577 exc_class
= mono_class_from_name (mono_defaults
.corlib
, "System", patch_info
->data
.name
);
7578 g_assert (exc_class
);
7579 throw_ip
= patch_info
->ip
.i
;
7581 //x86_breakpoint (code);
7582 /* Find a throw sequence for the same exception class */
7583 for (i
= 0; i
< nthrows
; ++i
)
7584 if (exc_classes
[i
] == exc_class
)
7587 amd64_mov_reg_imm (code
, AMD64_ARG_REG2
, (exc_throw_end
[i
] - cfg
->native_code
) - throw_ip
);
7588 x86_jump_code (code
, exc_throw_start
[i
]);
7589 patch_info
->type
= MONO_PATCH_INFO_NONE
;
7593 amd64_mov_reg_imm_size (code
, AMD64_ARG_REG2
, 0xf0f0f0f0, 4);
7597 exc_classes
[nthrows
] = exc_class
;
7598 exc_throw_start
[nthrows
] = code
;
7600 amd64_mov_reg_imm (code
, AMD64_ARG_REG1
, exc_class
->type_token
- MONO_TOKEN_TYPE_DEF
);
7602 patch_info
->type
= MONO_PATCH_INFO_NONE
;
7604 code
= emit_call_body (cfg
, code
, MONO_PATCH_INFO_INTERNAL_METHOD
, "mono_arch_throw_corlib_exception");
7606 amd64_mov_reg_imm (buf
, AMD64_ARG_REG2
, (code
- cfg
->native_code
) - throw_ip
);
7611 exc_throw_end
[nthrows
] = code
;
7621 g_assert(code
< cfg
->native_code
+ cfg
->code_size
);
7624 /* Handle relocations with RIP relative addressing */
7625 for (patch_info
= cfg
->patch_info
; patch_info
; patch_info
= patch_info
->next
) {
7626 gboolean remove
= FALSE
;
7627 guint8
*orig_code
= code
;
7629 switch (patch_info
->type
) {
7630 case MONO_PATCH_INFO_R8
:
7631 case MONO_PATCH_INFO_R4
: {
7632 guint8
*pos
, *patch_pos
;
7635 /* The SSE opcodes require a 16 byte alignment */
7636 #if defined(__default_codegen__)
7637 code
= (guint8
*)ALIGN_TO (code
, 16);
7638 #elif defined(__native_client_codegen__)
7640 /* Pad this out with HLT instructions */
7641 /* or we can get garbage bytes emitted */
7642 /* which will fail validation */
7643 guint8
*aligned_code
;
7644 /* extra align to make room for */
7645 /* mov/push below */
7646 int extra_align
= patch_info
->type
== MONO_PATCH_INFO_R8
? 2 : 1;
7647 aligned_code
= (guint8
*)ALIGN_TO (code
+ extra_align
, 16);
7648 /* The technique of hiding data in an */
7649 /* instruction has a problem here: we */
7650 /* need the data aligned to a 16-byte */
7651 /* boundary but the instruction cannot */
7652 /* cross the bundle boundary. so only */
7653 /* odd multiples of 16 can be used */
7654 if ((intptr_t)aligned_code
% kNaClAlignment
== 0) {
7657 while (code
< aligned_code
) {
7658 *(code
++) = 0xf4; /* hlt */
7663 pos
= cfg
->native_code
+ patch_info
->ip
.i
;
7664 if (IS_REX (pos
[1])) {
7665 patch_pos
= pos
+ 5;
7666 target_pos
= code
- pos
- 9;
7669 patch_pos
= pos
+ 4;
7670 target_pos
= code
- pos
- 8;
7673 if (patch_info
->type
== MONO_PATCH_INFO_R8
) {
7674 #ifdef __native_client_codegen__
7675 /* Hide 64-bit data in a */
7676 /* "mov imm64, r11" instruction. */
7677 /* write it before the start of */
7679 *(code
-2) = 0x49; /* prefix */
7680 *(code
-1) = 0xbb; /* mov X, %r11 */
7682 *(double*)code
= *(double*)patch_info
->data
.target
;
7683 code
+= sizeof (double);
7685 #ifdef __native_client_codegen__
7686 /* Hide 32-bit data in a */
7687 /* "push imm32" instruction. */
7688 *(code
-1) = 0x68; /* push */
7690 *(float*)code
= *(float*)patch_info
->data
.target
;
7691 code
+= sizeof (float);
7694 *(guint32
*)(patch_pos
) = target_pos
;
7699 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR
: {
7702 if (cfg
->compile_aot
)
7705 /*loading is faster against aligned addresses.*/
7706 code
= (guint8
*)ALIGN_TO (code
, 8);
7707 memset (orig_code
, 0, code
- orig_code
);
7709 pos
= cfg
->native_code
+ patch_info
->ip
.i
;
7711 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7712 if (IS_REX (pos
[1]))
7713 *(guint32
*)(pos
+ 4) = (guint8
*)code
- pos
- 8;
7715 *(guint32
*)(pos
+ 3) = (guint8
*)code
- pos
- 7;
7717 *(gpointer
*)code
= (gpointer
)patch_info
->data
.target
;
7718 code
+= sizeof (gpointer
);
7728 if (patch_info
== cfg
->patch_info
)
7729 cfg
->patch_info
= patch_info
->next
;
7733 for (tmp
= cfg
->patch_info
; tmp
->next
!= patch_info
; tmp
= tmp
->next
)
7735 tmp
->next
= patch_info
->next
;
7738 g_assert (code
< cfg
->native_code
+ cfg
->code_size
);
7741 cfg
->code_len
= code
- cfg
->native_code
;
7743 g_assert (cfg
->code_len
< cfg
->code_size
);
7747 #endif /* DISABLE_JIT */
7750 mono_arch_instrument_prolog (MonoCompile
*cfg
, void *func
, void *p
, gboolean enable_arguments
)
7752 guchar
*code
= (guchar
*)p
;
7753 MonoMethodSignature
*sig
;
7755 int i
, n
, stack_area
= 0;
7757 /* Keep this in sync with mono_arch_get_argument_info */
7759 if (enable_arguments
) {
7760 /* Allocate a new area on the stack and save arguments there */
7761 sig
= mono_method_signature (cfg
->method
);
7763 n
= sig
->param_count
+ sig
->hasthis
;
7765 stack_area
= ALIGN_TO (n
* 8, 16);
7767 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, stack_area
);
7769 for (i
= 0; i
< n
; ++i
) {
7770 inst
= cfg
->args
[i
];
7772 if (inst
->opcode
== OP_REGVAR
)
7773 amd64_mov_membase_reg (code
, AMD64_RSP
, (i
* 8), inst
->dreg
, 8);
7775 amd64_mov_reg_membase (code
, AMD64_R11
, inst
->inst_basereg
, inst
->inst_offset
, 8);
7776 amd64_mov_membase_reg (code
, AMD64_RSP
, (i
* 8), AMD64_R11
, 8);
7781 mono_add_patch_info (cfg
, code
-cfg
->native_code
, MONO_PATCH_INFO_METHODCONST
, cfg
->method
);
7782 amd64_set_reg_template (code
, AMD64_ARG_REG1
);
7783 amd64_mov_reg_reg (code
, AMD64_ARG_REG2
, AMD64_RSP
, 8);
7784 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_ABS
, (gpointer
)func
, TRUE
);
7786 if (enable_arguments
)
7787 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, stack_area
);
7801 mono_arch_instrument_epilog_full (MonoCompile
*cfg
, void *func
, void *p
, gboolean enable_arguments
, gboolean preserve_argument_registers
)
7803 guchar
*code
= (guchar
*)p
;
7804 int save_mode
= SAVE_NONE
;
7805 MonoMethod
*method
= cfg
->method
;
7806 MonoType
*ret_type
= mini_get_underlying_type (mono_method_signature (method
)->ret
);
7809 switch (ret_type
->type
) {
7810 case MONO_TYPE_VOID
:
7811 /* special case string .ctor icall */
7812 if (strcmp (".ctor", method
->name
) && method
->klass
== mono_defaults
.string_class
)
7813 save_mode
= SAVE_EAX
;
7815 save_mode
= SAVE_NONE
;
7819 save_mode
= SAVE_EAX
;
7823 save_mode
= SAVE_XMM
;
7825 case MONO_TYPE_GENERICINST
:
7826 if (!mono_type_generic_inst_is_valuetype (ret_type
)) {
7827 save_mode
= SAVE_EAX
;
7831 case MONO_TYPE_VALUETYPE
:
7832 save_mode
= SAVE_STRUCT
;
7835 save_mode
= SAVE_EAX
;
7839 /* Save the result and copy it into the proper argument register */
7840 switch (save_mode
) {
7842 amd64_push_reg (code
, AMD64_RAX
);
7844 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 8);
7845 if (enable_arguments
)
7846 amd64_mov_reg_reg (code
, AMD64_ARG_REG2
, AMD64_RAX
, 8);
7850 if (enable_arguments
)
7851 amd64_mov_reg_imm (code
, AMD64_ARG_REG2
, 0);
7854 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 8);
7855 amd64_movsd_membase_reg (code
, AMD64_RSP
, 0, AMD64_XMM0
);
7857 amd64_alu_reg_imm (code
, X86_SUB
, AMD64_RSP
, 8);
7859 * The result is already in the proper argument register so no copying
7866 g_assert_not_reached ();
7869 /* Set %al since this is a varargs call */
7870 if (save_mode
== SAVE_XMM
)
7871 amd64_mov_reg_imm (code
, AMD64_RAX
, 1);
7873 amd64_mov_reg_imm (code
, AMD64_RAX
, 0);
7875 if (preserve_argument_registers
) {
7876 for (i
= 0; i
< PARAM_REGS
; ++i
)
7877 amd64_push_reg (code
, param_regs
[i
]);
7880 mono_add_patch_info (cfg
, code
-cfg
->native_code
, MONO_PATCH_INFO_METHODCONST
, method
);
7881 amd64_set_reg_template (code
, AMD64_ARG_REG1
);
7882 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_ABS
, (gpointer
)func
, TRUE
);
7884 if (preserve_argument_registers
) {
7885 for (i
= PARAM_REGS
- 1; i
>= 0; --i
)
7886 amd64_pop_reg (code
, param_regs
[i
]);
7889 /* Restore result */
7890 switch (save_mode
) {
7892 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 8);
7893 amd64_pop_reg (code
, AMD64_RAX
);
7899 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 8);
7900 amd64_movsd_reg_membase (code
, AMD64_XMM0
, AMD64_RSP
, 0);
7901 amd64_alu_reg_imm (code
, X86_ADD
, AMD64_RSP
, 8);
7906 g_assert_not_reached ();
7913 mono_arch_flush_icache (guint8
*code
, gint size
)
7919 mono_arch_flush_register_windows (void)
7924 mono_arch_is_inst_imm (gint64 imm
)
7926 return amd64_use_imm32 (imm
);
7930 * Determine whenever the trap whose info is in SIGINFO is caused by
7934 mono_arch_is_int_overflow (void *sigctx
, void *info
)
7941 mono_sigctx_to_monoctx (sigctx
, &ctx
);
7943 rip
= (guint8
*)ctx
.gregs
[AMD64_RIP
];
7945 if (IS_REX (rip
[0])) {
7946 reg
= amd64_rex_b (rip
[0]);
7952 if ((rip
[0] == 0xf7) && (x86_modrm_mod (rip
[1]) == 0x3) && (x86_modrm_reg (rip
[1]) == 0x7)) {
7954 reg
+= x86_modrm_rm (rip
[1]);
7956 value
= ctx
.gregs
[reg
];
7966 mono_arch_get_patch_offset (guint8
*code
)
7972 * mono_breakpoint_clean_code:
7974 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7975 * breakpoints in the original code, they are removed in the copy.
7977 * Returns TRUE if no sw breakpoint was present.
7980 mono_breakpoint_clean_code (guint8
*method_start
, guint8
*code
, int offset
, guint8
*buf
, int size
)
7983 * If method_start is non-NULL we need to perform bound checks, since we access memory
7984 * at code - offset we could go before the start of the method and end up in a different
7985 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7988 if (!method_start
|| code
- offset
>= method_start
) {
7989 memcpy (buf
, code
- offset
, size
);
7991 int diff
= code
- method_start
;
7992 memset (buf
, 0, size
);
7993 memcpy (buf
+ offset
- diff
, method_start
, diff
+ size
- offset
);
7998 #if defined(__native_client_codegen__)
7999 /* For membase calls, we want the base register. for Native Client, */
8000 /* all indirect calls have the following sequence with the given sizes: */
8001 /* mov %eXX,%eXX [2-3] */
8002 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
8003 /* and $0xffffffffffffffe0,%r11d [4] */
8004 /* add %r15,%r11 [3] */
8005 /* callq *%r11 [3] */
8008 /* Determine if code points to a NaCl call-through-register sequence, */
8009 /* (i.e., the last 3 instructions listed above) */
8011 is_nacl_call_reg_sequence(guint8
* code
)
8013 const char *sequence
= "\x41\x83\xe3\xe0" /* and */
8014 "\x4d\x03\xdf" /* add */
8015 "\x41\xff\xd3"; /* call */
8016 return memcmp(code
, sequence
, 10) == 0;
8019 /* Determine if code points to the first opcode of the mov membase component */
8020 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
8021 /* (there could be a REX prefix before the opcode but it is ignored) */
8023 is_nacl_indirect_call_membase_sequence(guint8
* code
)
8025 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8026 return code
[0] == 0x8b && amd64_modrm_mod(code
[1]) == 3 &&
8027 /* and that src reg = dest reg */
8028 amd64_modrm_reg(code
[1]) == amd64_modrm_rm(code
[1]) &&
8029 /* Check that next inst is mov, uses SIB byte (rm = 4), */
8031 code
[3] == 0x8b && amd64_modrm_rm(code
[4]) == 4 &&
8032 /* and has dst of r11 and base of r15 */
8033 (amd64_modrm_reg(code
[4]) + amd64_rex_r(code
[2])) == AMD64_R11
&&
8034 (amd64_sib_base(code
[5]) + amd64_rex_b(code
[2])) == AMD64_R15
;
8036 #endif /* __native_client_codegen__ */
8039 mono_arch_get_this_arg_reg (guint8
*code
)
8041 return AMD64_ARG_REG1
;
8045 mono_arch_get_this_arg_from_call (mgreg_t
*regs
, guint8
*code
)
8047 return (gpointer
)regs
[mono_arch_get_this_arg_reg (code
)];
8050 #define MAX_ARCH_DELEGATE_PARAMS 10
8053 get_delegate_invoke_impl (MonoTrampInfo
**info
, gboolean has_target
, guint32 param_count
)
8055 guint8
*code
, *start
;
8056 GSList
*unwind_ops
= NULL
;
8059 unwind_ops
= mono_arch_get_cie_program ();
8062 start
= code
= (guint8
*)mono_global_codeman_reserve (64);
8064 /* Replace the this argument with the target */
8065 amd64_mov_reg_reg (code
, AMD64_RAX
, AMD64_ARG_REG1
, 8);
8066 amd64_mov_reg_membase (code
, AMD64_ARG_REG1
, AMD64_RAX
, MONO_STRUCT_OFFSET (MonoDelegate
, target
), 8);
8067 amd64_jump_membase (code
, AMD64_RAX
, MONO_STRUCT_OFFSET (MonoDelegate
, method_ptr
));
8069 g_assert ((code
- start
) < 64);
8071 start
= code
= (guint8
*)mono_global_codeman_reserve (64);
8073 if (param_count
== 0) {
8074 amd64_jump_membase (code
, AMD64_ARG_REG1
, MONO_STRUCT_OFFSET (MonoDelegate
, method_ptr
));
8076 /* We have to shift the arguments left */
8077 amd64_mov_reg_reg (code
, AMD64_RAX
, AMD64_ARG_REG1
, 8);
8078 for (i
= 0; i
< param_count
; ++i
) {
8081 amd64_mov_reg_reg (code
, param_regs
[i
], param_regs
[i
+ 1], 8);
8083 amd64_mov_reg_membase (code
, param_regs
[i
], AMD64_RSP
, 0x28, 8);
8085 amd64_mov_reg_reg (code
, param_regs
[i
], param_regs
[i
+ 1], 8);
8089 amd64_jump_membase (code
, AMD64_RAX
, MONO_STRUCT_OFFSET (MonoDelegate
, method_ptr
));
8091 g_assert ((code
- start
) < 64);
8094 nacl_global_codeman_validate (&start
, 64, &code
);
8095 mono_arch_flush_icache (start
, code
- start
);
8098 *info
= mono_tramp_info_create ("delegate_invoke_impl_has_target", start
, code
- start
, NULL
, unwind_ops
);
8100 char *name
= g_strdup_printf ("delegate_invoke_impl_target_%d", param_count
);
8101 *info
= mono_tramp_info_create (name
, start
, code
- start
, NULL
, unwind_ops
);
8105 if (mono_jit_map_is_enabled ()) {
8108 buff
= (char*)"delegate_invoke_has_target";
8110 buff
= g_strdup_printf ("delegate_invoke_no_target_%d", param_count
);
8111 mono_emit_jit_tramp (start
, code
- start
, buff
);
8115 mono_profiler_code_buffer_new (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE
, NULL
);
8120 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8123 get_delegate_virtual_invoke_impl (MonoTrampInfo
**info
, gboolean load_imt_reg
, int offset
)
8125 guint8
*code
, *start
;
8130 if (offset
/ (int)sizeof (gpointer
) > MAX_VIRTUAL_DELEGATE_OFFSET
)
8133 start
= code
= (guint8
*)mono_global_codeman_reserve (size
);
8135 unwind_ops
= mono_arch_get_cie_program ();
8137 /* Replace the this argument with the target */
8138 amd64_mov_reg_reg (code
, AMD64_RAX
, AMD64_ARG_REG1
, 8);
8139 amd64_mov_reg_membase (code
, AMD64_ARG_REG1
, AMD64_RAX
, MONO_STRUCT_OFFSET (MonoDelegate
, target
), 8);
8142 /* Load the IMT reg */
8143 amd64_mov_reg_membase (code
, MONO_ARCH_IMT_REG
, AMD64_RAX
, MONO_STRUCT_OFFSET (MonoDelegate
, method
), 8);
8146 /* Load the vtable */
8147 amd64_mov_reg_membase (code
, AMD64_RAX
, AMD64_ARG_REG1
, MONO_STRUCT_OFFSET (MonoObject
, vtable
), 8);
8148 amd64_jump_membase (code
, AMD64_RAX
, offset
);
8149 mono_profiler_code_buffer_new (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE
, NULL
);
8152 tramp_name
= g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset
/ sizeof (gpointer
));
8154 tramp_name
= g_strdup_printf ("delegate_virtual_invoke_%d", offset
/ sizeof (gpointer
));
8155 *info
= mono_tramp_info_create (tramp_name
, start
, code
- start
, NULL
, unwind_ops
);
8156 g_free (tramp_name
);
8162 * mono_arch_get_delegate_invoke_impls:
8164 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8168 mono_arch_get_delegate_invoke_impls (void)
8171 MonoTrampInfo
*info
;
8174 get_delegate_invoke_impl (&info
, TRUE
, 0);
8175 res
= g_slist_prepend (res
, info
);
8177 for (i
= 0; i
<= MAX_ARCH_DELEGATE_PARAMS
; ++i
) {
8178 get_delegate_invoke_impl (&info
, FALSE
, i
);
8179 res
= g_slist_prepend (res
, info
);
8182 for (i
= 0; i
<= MAX_VIRTUAL_DELEGATE_OFFSET
; ++i
) {
8183 get_delegate_virtual_invoke_impl (&info
, TRUE
, - i
* SIZEOF_VOID_P
);
8184 res
= g_slist_prepend (res
, info
);
8186 get_delegate_virtual_invoke_impl (&info
, FALSE
, i
* SIZEOF_VOID_P
);
8187 res
= g_slist_prepend (res
, info
);
8194 mono_arch_get_delegate_invoke_impl (MonoMethodSignature
*sig
, gboolean has_target
)
8196 guint8
*code
, *start
;
8199 if (sig
->param_count
> MAX_ARCH_DELEGATE_PARAMS
)
8202 /* FIXME: Support more cases */
8203 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig
->ret
)))
8207 static guint8
* cached
= NULL
;
8212 if (mono_aot_only
) {
8213 start
= (guint8
*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8215 MonoTrampInfo
*info
;
8216 start
= (guint8
*)get_delegate_invoke_impl (&info
, TRUE
, 0);
8217 mono_tramp_info_register (info
, NULL
);
8220 mono_memory_barrier ();
8224 static guint8
* cache
[MAX_ARCH_DELEGATE_PARAMS
+ 1] = {NULL
};
8225 for (i
= 0; i
< sig
->param_count
; ++i
)
8226 if (!mono_is_regsize_var (sig
->params
[i
]))
8228 if (sig
->param_count
> 4)
8231 code
= cache
[sig
->param_count
];
8235 if (mono_aot_only
) {
8236 char *name
= g_strdup_printf ("delegate_invoke_impl_target_%d", sig
->param_count
);
8237 start
= (guint8
*)mono_aot_get_trampoline (name
);
8240 MonoTrampInfo
*info
;
8241 start
= (guint8
*)get_delegate_invoke_impl (&info
, FALSE
, sig
->param_count
);
8242 mono_tramp_info_register (info
, NULL
);
8245 mono_memory_barrier ();
8247 cache
[sig
->param_count
] = start
;
8254 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature
*sig
, MonoMethod
*method
, int offset
, gboolean load_imt_reg
)
8256 MonoTrampInfo
*info
;
8259 code
= get_delegate_virtual_invoke_impl (&info
, load_imt_reg
, offset
);
8261 mono_tramp_info_register (info
, NULL
);
8266 mono_arch_finish_init (void)
8268 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8269 optimize_for_xen
= access ("/proc/xen", F_OK
) == 0;
8274 mono_arch_free_jit_tls_data (MonoJitTlsData
*tls
)
8278 #if defined(__default_codegen__)
8279 #define CMP_SIZE (6 + 1)
8280 #define CMP_REG_REG_SIZE (4 + 1)
8281 #define BR_SMALL_SIZE 2
8282 #define BR_LARGE_SIZE 6
8283 #define MOV_REG_IMM_SIZE 10
8284 #define MOV_REG_IMM_32BIT_SIZE 6
8285 #define JUMP_REG_SIZE (2 + 1)
8286 #elif defined(__native_client_codegen__)
8287 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8288 #define CMP_SIZE ((6 + 1) * 2 - 1)
8289 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8290 #define BR_SMALL_SIZE (2 * 2 - 1)
8291 #define BR_LARGE_SIZE (6 * 2 - 1)
8292 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8293 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8294 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8295 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8296 /* Jump membase's size is large and unpredictable */
8297 /* in native client, just pad it out a whole bundle. */
8298 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8302 imt_branch_distance (MonoIMTCheckItem
**imt_entries
, int start
, int target
)
8304 int i
, distance
= 0;
8305 for (i
= start
; i
< target
; ++i
)
8306 distance
+= imt_entries
[i
]->chunk_size
;
8311 * LOCKING: called with the domain lock held
8314 mono_arch_build_imt_thunk (MonoVTable
*vtable
, MonoDomain
*domain
, MonoIMTCheckItem
**imt_entries
, int count
,
8315 gpointer fail_tramp
)
8319 guint8
*code
, *start
;
8320 gboolean vtable_is_32bit
= ((gsize
)(vtable
) == (gsize
)(int)(gsize
)(vtable
));
8323 for (i
= 0; i
< count
; ++i
) {
8324 MonoIMTCheckItem
*item
= imt_entries
[i
];
8325 if (item
->is_equals
) {
8326 if (item
->check_target_idx
) {
8327 if (!item
->compare_done
) {
8328 if (amd64_use_imm32 ((gint64
)item
->key
))
8329 item
->chunk_size
+= CMP_SIZE
;
8331 item
->chunk_size
+= MOV_REG_IMM_SIZE
+ CMP_REG_REG_SIZE
;
8333 if (item
->has_target_code
) {
8334 item
->chunk_size
+= MOV_REG_IMM_SIZE
;
8336 if (vtable_is_32bit
)
8337 item
->chunk_size
+= MOV_REG_IMM_32BIT_SIZE
;
8339 item
->chunk_size
+= MOV_REG_IMM_SIZE
;
8340 #ifdef __native_client_codegen__
8341 item
->chunk_size
+= JUMP_MEMBASE_SIZE
;
8344 item
->chunk_size
+= BR_SMALL_SIZE
+ JUMP_REG_SIZE
;
8347 item
->chunk_size
+= MOV_REG_IMM_SIZE
* 3 + CMP_REG_REG_SIZE
+
8348 BR_SMALL_SIZE
+ JUMP_REG_SIZE
* 2;
8350 if (vtable_is_32bit
)
8351 item
->chunk_size
+= MOV_REG_IMM_32BIT_SIZE
;
8353 item
->chunk_size
+= MOV_REG_IMM_SIZE
;
8354 item
->chunk_size
+= JUMP_REG_SIZE
;
8355 /* with assert below:
8356 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8358 #ifdef __native_client_codegen__
8359 item
->chunk_size
+= JUMP_MEMBASE_SIZE
;
8364 if (amd64_use_imm32 ((gint64
)item
->key
))
8365 item
->chunk_size
+= CMP_SIZE
;
8367 item
->chunk_size
+= MOV_REG_IMM_SIZE
+ CMP_REG_REG_SIZE
;
8368 item
->chunk_size
+= BR_LARGE_SIZE
;
8369 imt_entries
[item
->check_target_idx
]->compare_done
= TRUE
;
8371 size
+= item
->chunk_size
;
8373 #if defined(__native_client__) && defined(__native_client_codegen__)
8374 /* In Native Client, we don't re-use thunks, allocate from the */
8375 /* normal code manager paths. */
8376 code
= mono_domain_code_reserve (domain
, size
);
8379 code
= (guint8
*)mono_method_alloc_generic_virtual_thunk (domain
, size
);
8381 code
= (guint8
*)mono_domain_code_reserve (domain
, size
);
8385 unwind_ops
= mono_arch_get_cie_program ();
8387 for (i
= 0; i
< count
; ++i
) {
8388 MonoIMTCheckItem
*item
= imt_entries
[i
];
8389 item
->code_target
= code
;
8390 if (item
->is_equals
) {
8391 gboolean fail_case
= !item
->check_target_idx
&& fail_tramp
;
8393 if (item
->check_target_idx
|| fail_case
) {
8394 if (!item
->compare_done
|| fail_case
) {
8395 if (amd64_use_imm32 ((gint64
)item
->key
))
8396 amd64_alu_reg_imm_size (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)(gssize
)item
->key
, sizeof(gpointer
));
8398 amd64_mov_reg_imm_size (code
, MONO_ARCH_IMT_SCRATCH_REG
, item
->key
, sizeof(gpointer
));
8399 amd64_alu_reg_reg (code
, X86_CMP
, MONO_ARCH_IMT_REG
, MONO_ARCH_IMT_SCRATCH_REG
);
8402 item
->jmp_code
= code
;
8403 amd64_branch8 (code
, X86_CC_NE
, 0, FALSE
);
8404 if (item
->has_target_code
) {
8405 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, item
->value
.target_code
);
8406 amd64_jump_reg (code
, MONO_ARCH_IMT_SCRATCH_REG
);
8408 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
8409 amd64_jump_membase (code
, MONO_ARCH_IMT_SCRATCH_REG
, 0);
8413 amd64_patch (item
->jmp_code
, code
);
8414 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, fail_tramp
);
8415 amd64_jump_reg (code
, MONO_ARCH_IMT_SCRATCH_REG
);
8416 item
->jmp_code
= NULL
;
8419 /* enable the commented code to assert on wrong method */
8421 if (amd64_is_imm32 (item
->key
))
8422 amd64_alu_reg_imm_size (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)(gssize
)item
->key
, sizeof(gpointer
));
8424 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, item
->key
);
8425 amd64_alu_reg_reg (code
, X86_CMP
, MONO_ARCH_IMT_REG
, MONO_ARCH_IMT_SCRATCH_REG
);
8427 item
->jmp_code
= code
;
8428 amd64_branch8 (code
, X86_CC_NE
, 0, FALSE
);
8429 /* See the comment below about R10 */
8430 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
8431 amd64_jump_membase (code
, MONO_ARCH_IMT_SCRATCH_REG
, 0);
8432 amd64_patch (item
->jmp_code
, code
);
8433 amd64_breakpoint (code
);
8434 item
->jmp_code
= NULL
;
8436 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8437 needs to be preserved. R10 needs
8438 to be preserved for calls which
8439 require a runtime generic context,
8440 but interface calls don't. */
8441 amd64_mov_reg_imm (code
, MONO_ARCH_IMT_SCRATCH_REG
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
8442 amd64_jump_membase (code
, MONO_ARCH_IMT_SCRATCH_REG
, 0);
8446 if (amd64_use_imm32 ((gint64
)item
->key
))
8447 amd64_alu_reg_imm_size (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)(gssize
)item
->key
, sizeof (gpointer
));
8449 amd64_mov_reg_imm_size (code
, MONO_ARCH_IMT_SCRATCH_REG
, item
->key
, sizeof (gpointer
));
8450 amd64_alu_reg_reg (code
, X86_CMP
, MONO_ARCH_IMT_REG
, MONO_ARCH_IMT_SCRATCH_REG
);
8452 item
->jmp_code
= code
;
8453 if (x86_is_imm8 (imt_branch_distance (imt_entries
, i
, item
->check_target_idx
)))
8454 x86_branch8 (code
, X86_CC_GE
, 0, FALSE
);
8456 x86_branch32 (code
, X86_CC_GE
, 0, FALSE
);
8458 g_assert (code
- item
->code_target
<= item
->chunk_size
);
8460 /* patch the branches to get to the target items */
8461 for (i
= 0; i
< count
; ++i
) {
8462 MonoIMTCheckItem
*item
= imt_entries
[i
];
8463 if (item
->jmp_code
) {
8464 if (item
->check_target_idx
) {
8465 amd64_patch (item
->jmp_code
, imt_entries
[item
->check_target_idx
]->code_target
);
8471 mono_stats
.imt_thunks_size
+= code
- start
;
8472 g_assert (code
- start
<= size
);
8474 nacl_domain_code_validate(domain
, &start
, size
, &code
);
8475 mono_profiler_code_buffer_new (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE
, NULL
);
8477 mono_tramp_info_register (mono_tramp_info_create (NULL
, start
, code
- start
, NULL
, unwind_ops
), domain
);
8483 mono_arch_find_imt_method (mgreg_t
*regs
, guint8
*code
)
8485 return (MonoMethod
*)regs
[MONO_ARCH_IMT_REG
];
8489 mono_arch_find_static_call_vtable (mgreg_t
*regs
, guint8
*code
)
8491 return (MonoVTable
*) regs
[MONO_ARCH_RGCTX_REG
];
8495 mono_arch_get_cie_program (void)
8499 mono_add_unwind_op_def_cfa (l
, (guint8
*)NULL
, (guint8
*)NULL
, AMD64_RSP
, 8);
8500 mono_add_unwind_op_offset (l
, (guint8
*)NULL
, (guint8
*)NULL
, AMD64_RIP
, -8);
8508 mono_arch_emit_inst_for_method (MonoCompile
*cfg
, MonoMethod
*cmethod
, MonoMethodSignature
*fsig
, MonoInst
**args
)
8510 MonoInst
*ins
= NULL
;
8513 if (cmethod
->klass
== mono_defaults
.math_class
) {
8514 if (strcmp (cmethod
->name
, "Sin") == 0) {
8516 } else if (strcmp (cmethod
->name
, "Cos") == 0) {
8518 } else if (strcmp (cmethod
->name
, "Sqrt") == 0) {
8520 } else if (strcmp (cmethod
->name
, "Abs") == 0 && fsig
->params
[0]->type
== MONO_TYPE_R8
) {
8524 if (opcode
&& fsig
->param_count
== 1) {
8525 MONO_INST_NEW (cfg
, ins
, opcode
);
8526 ins
->type
= STACK_R8
;
8527 ins
->dreg
= mono_alloc_freg (cfg
);
8528 ins
->sreg1
= args
[0]->dreg
;
8529 MONO_ADD_INS (cfg
->cbb
, ins
);
8533 if (cfg
->opt
& MONO_OPT_CMOV
) {
8534 if (strcmp (cmethod
->name
, "Min") == 0) {
8535 if (fsig
->params
[0]->type
== MONO_TYPE_I4
)
8537 if (fsig
->params
[0]->type
== MONO_TYPE_U4
)
8538 opcode
= OP_IMIN_UN
;
8539 else if (fsig
->params
[0]->type
== MONO_TYPE_I8
)
8541 else if (fsig
->params
[0]->type
== MONO_TYPE_U8
)
8542 opcode
= OP_LMIN_UN
;
8543 } else if (strcmp (cmethod
->name
, "Max") == 0) {
8544 if (fsig
->params
[0]->type
== MONO_TYPE_I4
)
8546 if (fsig
->params
[0]->type
== MONO_TYPE_U4
)
8547 opcode
= OP_IMAX_UN
;
8548 else if (fsig
->params
[0]->type
== MONO_TYPE_I8
)
8550 else if (fsig
->params
[0]->type
== MONO_TYPE_U8
)
8551 opcode
= OP_LMAX_UN
;
8555 if (opcode
&& fsig
->param_count
== 2) {
8556 MONO_INST_NEW (cfg
, ins
, opcode
);
8557 ins
->type
= fsig
->params
[0]->type
== MONO_TYPE_I4
? STACK_I4
: STACK_I8
;
8558 ins
->dreg
= mono_alloc_ireg (cfg
);
8559 ins
->sreg1
= args
[0]->dreg
;
8560 ins
->sreg2
= args
[1]->dreg
;
8561 MONO_ADD_INS (cfg
->cbb
, ins
);
8565 /* OP_FREM is not IEEE compatible */
8566 else if (strcmp (cmethod
->name
, "IEEERemainder") == 0 && fsig
->param_count
== 2) {
8567 MONO_INST_NEW (cfg
, ins
, OP_FREM
);
8568 ins
->inst_i0
= args
[0];
8569 ins
->inst_i1
= args
[1];
8579 mono_arch_print_tree (MonoInst
*tree
, int arity
)
8585 mono_arch_context_get_int_reg (MonoContext
*ctx
, int reg
)
8587 return ctx
->gregs
[reg
];
8591 mono_arch_context_set_int_reg (MonoContext
*ctx
, int reg
, mgreg_t val
)
8593 ctx
->gregs
[reg
] = val
;
8597 mono_arch_install_handler_block_guard (MonoJitInfo
*ji
, MonoJitExceptionInfo
*clause
, MonoContext
*ctx
, gpointer new_value
)
8599 gpointer
*sp
, old_value
;
8603 bp
= (char *)MONO_CONTEXT_GET_BP (ctx
);
8604 sp
= (gpointer
*)*(gpointer
*)(bp
+ clause
->exvar_offset
);
8607 if (old_value
< ji
->code_start
|| (char*)old_value
> ((char*)ji
->code_start
+ ji
->code_size
))
8616 * mono_arch_emit_load_aotconst:
8618 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8619 * TARGET from the mscorlib GOT in full-aot code.
8620 * On AMD64, the result is placed into R11.
8623 mono_arch_emit_load_aotconst (guint8
*start
, guint8
*code
, MonoJumpInfo
**ji
, MonoJumpInfoType tramp_type
, gconstpointer target
)
8625 *ji
= mono_patch_info_list_prepend (*ji
, code
- start
, tramp_type
, target
);
8626 amd64_mov_reg_membase (code
, AMD64_R11
, AMD64_RIP
, 0, 8);
8632 * mono_arch_get_trampolines:
8634 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8638 mono_arch_get_trampolines (gboolean aot
)
8640 return mono_amd64_get_exception_trampolines (aot
);
8643 /* Soft Debug support */
8644 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8647 * mono_arch_set_breakpoint:
8649 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8650 * The location should contain code emitted by OP_SEQ_POINT.
8653 mono_arch_set_breakpoint (MonoJitInfo
*ji
, guint8
*ip
)
8658 guint32 native_offset
= ip
- (guint8
*)ji
->code_start
;
8659 SeqPointInfo
*info
= (SeqPointInfo
*)mono_arch_get_seq_point_info (mono_domain_get (), (guint8
*)ji
->code_start
);
8661 g_assert (info
->bp_addrs
[native_offset
] == 0);
8662 info
->bp_addrs
[native_offset
] = mini_get_breakpoint_trampoline ();
8664 /* ip points to a mov r11, 0 */
8665 g_assert (code
[0] == 0x41);
8666 g_assert (code
[1] == 0xbb);
8667 amd64_mov_reg_imm (code
, AMD64_R11
, 1);
8672 * mono_arch_clear_breakpoint:
8674 * Clear the breakpoint at IP.
8677 mono_arch_clear_breakpoint (MonoJitInfo
*ji
, guint8
*ip
)
8682 guint32 native_offset
= ip
- (guint8
*)ji
->code_start
;
8683 SeqPointInfo
*info
= (SeqPointInfo
*)mono_arch_get_seq_point_info (mono_domain_get (), (guint8
*)ji
->code_start
);
8685 info
->bp_addrs
[native_offset
] = NULL
;
8687 amd64_mov_reg_imm (code
, AMD64_R11
, 0);
8692 mono_arch_is_breakpoint_event (void *info
, void *sigctx
)
8694 /* We use soft breakpoints on amd64 */
8699 * mono_arch_skip_breakpoint:
8701 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8702 * we resume, the instruction is not executed again.
8705 mono_arch_skip_breakpoint (MonoContext
*ctx
, MonoJitInfo
*ji
)
8707 g_assert_not_reached ();
8711 * mono_arch_start_single_stepping:
8713 * Start single stepping.
8716 mono_arch_start_single_stepping (void)
8718 ss_trampoline
= mini_get_single_step_trampoline ();
8722 * mono_arch_stop_single_stepping:
8724 * Stop single stepping.
8727 mono_arch_stop_single_stepping (void)
8729 ss_trampoline
= NULL
;
8733 * mono_arch_is_single_step_event:
8735 * Return whenever the machine state in SIGCTX corresponds to a single
8739 mono_arch_is_single_step_event (void *info
, void *sigctx
)
8741 /* We use soft breakpoints on amd64 */
8746 * mono_arch_skip_single_step:
8748 * Modify CTX so the ip is placed after the single step trigger instruction,
8749 * we resume, the instruction is not executed again.
8752 mono_arch_skip_single_step (MonoContext
*ctx
)
8754 g_assert_not_reached ();
8758 * mono_arch_create_seq_point_info:
8760 * Return a pointer to a data structure which is used by the sequence
8761 * point implementation in AOTed code.
8764 mono_arch_get_seq_point_info (MonoDomain
*domain
, guint8
*code
)
8769 // FIXME: Add a free function
8771 mono_domain_lock (domain
);
8772 info
= (SeqPointInfo
*)g_hash_table_lookup (domain_jit_info (domain
)->arch_seq_points
,
8774 mono_domain_unlock (domain
);
8777 ji
= mono_jit_info_table_find (domain
, (char*)code
);
8780 // FIXME: Optimize the size
8781 info
= (SeqPointInfo
*)g_malloc0 (sizeof (SeqPointInfo
) + (ji
->code_size
* sizeof (gpointer
)));
8783 info
->ss_tramp_addr
= &ss_trampoline
;
8785 mono_domain_lock (domain
);
8786 g_hash_table_insert (domain_jit_info (domain
)->arch_seq_points
,
8788 mono_domain_unlock (domain
);
8795 mono_arch_init_lmf_ext (MonoLMFExt
*ext
, gpointer prev_lmf
)
8797 ext
->lmf
.previous_lmf
= prev_lmf
;
8798 /* Mark that this is a MonoLMFExt */
8799 ext
->lmf
.previous_lmf
= (gpointer
)(((gssize
)ext
->lmf
.previous_lmf
) | 2);
8800 ext
->lmf
.rsp
= (gssize
)ext
;
8806 mono_arch_opcode_supported (int opcode
)
8809 case OP_ATOMIC_ADD_I4
:
8810 case OP_ATOMIC_ADD_I8
:
8811 case OP_ATOMIC_EXCHANGE_I4
:
8812 case OP_ATOMIC_EXCHANGE_I8
:
8813 case OP_ATOMIC_CAS_I4
:
8814 case OP_ATOMIC_CAS_I8
:
8815 case OP_ATOMIC_LOAD_I1
:
8816 case OP_ATOMIC_LOAD_I2
:
8817 case OP_ATOMIC_LOAD_I4
:
8818 case OP_ATOMIC_LOAD_I8
:
8819 case OP_ATOMIC_LOAD_U1
:
8820 case OP_ATOMIC_LOAD_U2
:
8821 case OP_ATOMIC_LOAD_U4
:
8822 case OP_ATOMIC_LOAD_U8
:
8823 case OP_ATOMIC_LOAD_R4
:
8824 case OP_ATOMIC_LOAD_R8
:
8825 case OP_ATOMIC_STORE_I1
:
8826 case OP_ATOMIC_STORE_I2
:
8827 case OP_ATOMIC_STORE_I4
:
8828 case OP_ATOMIC_STORE_I8
:
8829 case OP_ATOMIC_STORE_U1
:
8830 case OP_ATOMIC_STORE_U2
:
8831 case OP_ATOMIC_STORE_U4
:
8832 case OP_ATOMIC_STORE_U8
:
8833 case OP_ATOMIC_STORE_R4
:
8834 case OP_ATOMIC_STORE_R8
:
8841 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8843 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8845 #endif /* !ENABLE_GSHAREDVT */