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[mono-project.git] / mono / mini / mini-x86.c
blobd3cdf7f0c43c781b05d41958f3799b6912fd4e8c
1 /**
2 * \file
3 * x86 backend for the Mono code generator
4 *
5 * Authors:
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
8 * Patrik Torstensson
9 *
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
14 */
15 #include "mini.h"
16 #include <string.h>
17 #include <math.h>
18 #ifdef HAVE_UNISTD_H
19 #include <unistd.h>
20 #endif
21
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
36
37 #include "mini-x86.h"
38 #include "cpu-x86.h"
39 #include "ir-emit.h"
40 #include "mini-gc.h"
41 #include "aot-runtime.h"
42 #include "mini-runtime.h"
43
44 #ifndef TARGET_WIN32
45 #ifdef MONO_XEN_OPT
46 static gboolean optimize_for_xen = TRUE;
47 #else
48 #define optimize_for_xen 0
49 #endif
50 #endif
51
52 static GENERATE_TRY_GET_CLASS_WITH_CACHE (math, "System", "Math")
53
54
55 /* The single step trampoline */
56 static gpointer ss_trampoline;
57
58 /* The breakpoint trampoline */
59 static gpointer bp_trampoline;
60
61 #define ARGS_OFFSET 8
62
63 #ifdef TARGET_WIN32
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
66 #else
67 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
68 #endif
69
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
71
72 #define OP_SEQ_POINT_BP_OFFSET 7
73
74 const char*
75 mono_arch_regname (int reg)
76 {
77 switch (reg) {
78 case X86_EAX: return "%eax";
79 case X86_EBX: return "%ebx";
80 case X86_ECX: return "%ecx";
81 case X86_EDX: return "%edx";
82 case X86_ESP: return "%esp";
83 case X86_EBP: return "%ebp";
84 case X86_EDI: return "%edi";
85 case X86_ESI: return "%esi";
86 }
87 return "unknown";
88 }
89
90 const char*
91 mono_arch_fregname (int reg)
92 {
93 switch (reg) {
94 case 0:
95 return "%fr0";
96 case 1:
97 return "%fr1";
98 case 2:
99 return "%fr2";
100 case 3:
101 return "%fr3";
102 case 4:
103 return "%fr4";
104 case 5:
105 return "%fr5";
106 case 6:
107 return "%fr6";
108 case 7:
109 return "%fr7";
110 default:
111 return "unknown";
112 }
113 }
114
115 const char *
116 mono_arch_xregname (int reg)
117 {
118 switch (reg) {
119 case 0:
120 return "%xmm0";
121 case 1:
122 return "%xmm1";
123 case 2:
124 return "%xmm2";
125 case 3:
126 return "%xmm3";
127 case 4:
128 return "%xmm4";
129 case 5:
130 return "%xmm5";
131 case 6:
132 return "%xmm6";
133 case 7:
134 return "%xmm7";
135 default:
136 return "unknown";
137 }
138 }
139
140 void
141 mono_x86_patch (unsigned char* code, gpointer target)
142 {
143 mono_x86_patch_inline (code, target);
144 }
145
146 #define FLOAT_PARAM_REGS 0
147
148 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
149
150 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
151 {
152 if (!sig->pinvoke)
153 return NULL;
154
155 switch (sig->call_convention) {
156 case MONO_CALL_THISCALL:
157 return thiscall_param_regs;
158 default:
159 return NULL;
160 }
161 }
162
163 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
164 #define SMALL_STRUCTS_IN_REGS
165 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
166 #endif
167
168 static void inline
169 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
170 {
171 ainfo->offset = *stack_size;
172
173 if (!param_regs || param_regs [*gr] == X86_NREG) {
174 ainfo->storage = ArgOnStack;
175 ainfo->nslots = 1;
176 (*stack_size) += sizeof (target_mgreg_t);
177 }
178 else {
179 ainfo->storage = ArgInIReg;
180 ainfo->reg = param_regs [*gr];
181 (*gr) ++;
182 }
183 }
184
185 static void inline
186 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
187 {
188 ainfo->offset = *stack_size;
189
190 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
191
192 ainfo->storage = ArgOnStack;
193 (*stack_size) += sizeof (target_mgreg_t) * 2;
194 ainfo->nslots = 2;
195 }
196
197 static void inline
198 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
199 {
200 ainfo->offset = *stack_size;
201
202 if (*gr >= FLOAT_PARAM_REGS) {
203 ainfo->storage = ArgOnStack;
204 (*stack_size) += is_double ? 8 : 4;
205 ainfo->nslots = is_double ? 2 : 1;
206 }
207 else {
208 /* A double register */
209 if (is_double)
210 ainfo->storage = ArgInDoubleSSEReg;
211 else
212 ainfo->storage = ArgInFloatSSEReg;
213 ainfo->reg = *gr;
214 (*gr) += 1;
215 }
216 }
217
218
219 static void
220 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
221 gboolean is_return,
222 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
223 {
224 guint32 size;
225 MonoClass *klass;
226
227 klass = mono_class_from_mono_type_internal (type);
228 size = mini_type_stack_size_full (m_class_get_byval_arg (klass), NULL, sig->pinvoke);
229
230 #if defined(TARGET_WIN32)
231 /*
232 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
233 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
234 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
235 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
236 * it must be represented in call and cannot be dropped.
237 */
238 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
239 /* Empty structs (1 byte size) needs to be represented in a stack slot */
240 ainfo->pass_empty_struct = TRUE;
241 size = 1;
242 }
243 #endif
244
245 #ifdef SMALL_STRUCTS_IN_REGS
246 if (sig->pinvoke && is_return) {
247 MonoMarshalType *info;
248
249 info = mono_marshal_load_type_info (klass);
250 g_assert (info);
251
252 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
253
254 /* Ignore empty struct return value, if used. */
255 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
256 ainfo->storage = ArgValuetypeInReg;
257 return;
258 }
259
260 /*
261 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
262 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
263 * This is different compared to for example float or double return types (not in struct) that will be returned
264 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
265 *
266 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
267 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
268 * This means that structs with one float or double will be returned in ST(0). For more details,
269 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
270 */
271 #if !defined(TARGET_WIN32)
272
273 /* Special case structs with only a float member */
274 if (info->num_fields == 1) {
275 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
276 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
277 ainfo->storage = ArgValuetypeInReg;
278 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
279 return;
280 }
281 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
282 ainfo->storage = ArgValuetypeInReg;
283 ainfo->pair_storage [0] = ArgOnFloatFpStack;
284 return;
285 }
286 }
287 #endif
288
289 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
290 ainfo->storage = ArgValuetypeInReg;
291 ainfo->pair_storage [0] = ArgInIReg;
292 ainfo->pair_regs [0] = return_regs [0];
293 if (info->native_size > 4) {
294 ainfo->pair_storage [1] = ArgInIReg;
295 ainfo->pair_regs [1] = return_regs [1];
296 }
297 return;
298 }
299 }
300 #endif
301
302 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
303 g_assert (size <= 4);
304 ainfo->storage = ArgValuetypeInReg;
305 ainfo->reg = param_regs [*gr];
306 (*gr)++;
307 return;
308 }
309
310 ainfo->offset = *stack_size;
311 ainfo->storage = ArgOnStack;
312 *stack_size += ALIGN_TO (size, sizeof (target_mgreg_t));
313 ainfo->nslots = ALIGN_TO (size, sizeof (target_mgreg_t)) / sizeof (target_mgreg_t);
314 }
315
316 /*
317 * get_call_info:
318 *
319 * Obtain information about a call according to the calling convention.
320 * For x86 ELF, see the "System V Application Binary Interface Intel386
321 * Architecture Processor Supplment, Fourth Edition" document for more
322 * information.
323 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
324 */
325 static CallInfo*
326 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
327 {
328 guint32 i, gr, fr, pstart;
329 const guint32 *param_regs;
330 MonoType *ret_type;
331 int n = sig->hasthis + sig->param_count;
332 guint32 stack_size = 0;
333 gboolean is_pinvoke = sig->pinvoke;
334
335 gr = 0;
336 fr = 0;
337 cinfo->nargs = n;
338
339 param_regs = callconv_param_regs(sig);
340
341 /* return value */
342 {
343 ret_type = mini_get_underlying_type (sig->ret);
344 switch (ret_type->type) {
345 case MONO_TYPE_I1:
346 case MONO_TYPE_U1:
347 case MONO_TYPE_I2:
348 case MONO_TYPE_U2:
349 case MONO_TYPE_I4:
350 case MONO_TYPE_U4:
351 case MONO_TYPE_I:
352 case MONO_TYPE_U:
353 case MONO_TYPE_PTR:
354 case MONO_TYPE_FNPTR:
355 case MONO_TYPE_OBJECT:
356 cinfo->ret.storage = ArgInIReg;
357 cinfo->ret.reg = X86_EAX;
358 break;
359 case MONO_TYPE_U8:
360 case MONO_TYPE_I8:
361 cinfo->ret.storage = ArgInIReg;
362 cinfo->ret.reg = X86_EAX;
363 cinfo->ret.is_pair = TRUE;
364 break;
365 case MONO_TYPE_R4:
366 cinfo->ret.storage = ArgOnFloatFpStack;
367 break;
368 case MONO_TYPE_R8:
369 cinfo->ret.storage = ArgOnDoubleFpStack;
370 break;
371 case MONO_TYPE_GENERICINST:
372 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
373 cinfo->ret.storage = ArgInIReg;
374 cinfo->ret.reg = X86_EAX;
375 break;
376 }
377 if (mini_is_gsharedvt_type (ret_type)) {
378 cinfo->ret.storage = ArgOnStack;
379 cinfo->vtype_retaddr = TRUE;
380 break;
381 }
382 /* Fall through */
383 case MONO_TYPE_VALUETYPE:
384 case MONO_TYPE_TYPEDBYREF: {
385 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
386
387 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
388 if (cinfo->ret.storage == ArgOnStack) {
389 cinfo->vtype_retaddr = TRUE;
390 /* The caller passes the address where the value is stored */
391 }
392 break;
393 }
394 case MONO_TYPE_VAR:
395 case MONO_TYPE_MVAR:
396 g_assert (mini_is_gsharedvt_type (ret_type));
397 cinfo->ret.storage = ArgOnStack;
398 cinfo->vtype_retaddr = TRUE;
399 break;
400 case MONO_TYPE_VOID:
401 cinfo->ret.storage = ArgNone;
402 break;
403 default:
404 g_error ("Can't handle as return value 0x%x", ret_type->type);
405 }
406 }
407
408 pstart = 0;
409 /*
410 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
411 * the first argument, allowing 'this' to be always passed in the first arg reg.
412 * Also do this if the first argument is a reference type, since virtual calls
413 * are sometimes made using calli without sig->hasthis set, like in the delegate
414 * invoke wrappers.
415 */
416 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
417 if (sig->hasthis) {
418 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
419 } else {
420 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
421 pstart = 1;
422 }
423 cinfo->vret_arg_offset = stack_size;
424 add_general (&gr, NULL, &stack_size, &cinfo->ret);
425 cinfo->vret_arg_index = 1;
426 } else {
427 /* this */
428 if (sig->hasthis)
429 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
430
431 if (cinfo->vtype_retaddr)
432 add_general (&gr, NULL, &stack_size, &cinfo->ret);
433 }
434
435 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
436 fr = FLOAT_PARAM_REGS;
437
438 /* Emit the signature cookie just before the implicit arguments */
439 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
440 }
441
442 for (i = pstart; i < sig->param_count; ++i) {
443 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
444 MonoType *ptype;
445
446 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
447 /* We allways pass the sig cookie on the stack for simplicity */
448 /*
449 * Prevent implicit arguments + the sig cookie from being passed
450 * in registers.
451 */
452 fr = FLOAT_PARAM_REGS;
453
454 /* Emit the signature cookie just before the implicit arguments */
455 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
456 }
457
458 if (sig->params [i]->byref) {
459 add_general (&gr, param_regs, &stack_size, ainfo);
460 continue;
461 }
462 ptype = mini_get_underlying_type (sig->params [i]);
463 switch (ptype->type) {
464 case MONO_TYPE_I1:
465 case MONO_TYPE_U1:
466 add_general (&gr, param_regs, &stack_size, ainfo);
467 break;
468 case MONO_TYPE_I2:
469 case MONO_TYPE_U2:
470 add_general (&gr, param_regs, &stack_size, ainfo);
471 break;
472 case MONO_TYPE_I4:
473 case MONO_TYPE_U4:
474 add_general (&gr, param_regs, &stack_size, ainfo);
475 break;
476 case MONO_TYPE_I:
477 case MONO_TYPE_U:
478 case MONO_TYPE_PTR:
479 case MONO_TYPE_FNPTR:
480 case MONO_TYPE_OBJECT:
481 add_general (&gr, param_regs, &stack_size, ainfo);
482 break;
483 case MONO_TYPE_GENERICINST:
484 if (!mono_type_generic_inst_is_valuetype (ptype)) {
485 add_general (&gr, param_regs, &stack_size, ainfo);
486 break;
487 }
488 if (mini_is_gsharedvt_type (ptype)) {
489 /* gsharedvt arguments are passed by ref */
490 add_general (&gr, param_regs, &stack_size, ainfo);
491 g_assert (ainfo->storage == ArgOnStack);
492 ainfo->storage = ArgGSharedVt;
493 break;
494 }
495 /* Fall through */
496 case MONO_TYPE_VALUETYPE:
497 case MONO_TYPE_TYPEDBYREF:
498 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
499 break;
500 case MONO_TYPE_U8:
501 case MONO_TYPE_I8:
502 add_general_pair (&gr, param_regs, &stack_size, ainfo);
503 break;
504 case MONO_TYPE_R4:
505 add_float (&fr, &stack_size, ainfo, FALSE);
506 break;
507 case MONO_TYPE_R8:
508 add_float (&fr, &stack_size, ainfo, TRUE);
509 break;
510 case MONO_TYPE_VAR:
511 case MONO_TYPE_MVAR:
512 /* gsharedvt arguments are passed by ref */
513 g_assert (mini_is_gsharedvt_type (ptype));
514 add_general (&gr, param_regs, &stack_size, ainfo);
515 g_assert (ainfo->storage == ArgOnStack);
516 ainfo->storage = ArgGSharedVt;
517 break;
518 default:
519 g_error ("unexpected type 0x%x", ptype->type);
520 g_assert_not_reached ();
521 }
522 }
523
524 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
525 fr = FLOAT_PARAM_REGS;
526
527 /* Emit the signature cookie just before the implicit arguments */
528 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
529 }
530
531 if (cinfo->vtype_retaddr) {
532 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
533 cinfo->callee_stack_pop = 4;
534 } else if (CALLCONV_IS_STDCALL (sig)) {
535 /* Have to compensate for the stack space popped by the native callee */
536 cinfo->callee_stack_pop = stack_size;
537 }
538
539 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
540 cinfo->need_stack_align = TRUE;
541 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
542 stack_size += cinfo->stack_align_amount;
543 }
544
545 cinfo->stack_usage = stack_size;
546 cinfo->reg_usage = gr;
547 cinfo->freg_usage = fr;
548 return cinfo;
549 }
550
551 static CallInfo*
552 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
553 {
554 int n = sig->hasthis + sig->param_count;
555 CallInfo *cinfo;
556
557 if (mp)
558 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
559 else
560 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
561
562 return get_call_info_internal (cinfo, sig);
563 }
564
565 static gboolean storage_in_ireg (ArgStorage storage)
566 {
567 return (storage == ArgInIReg || storage == ArgValuetypeInReg);
568 }
569
570 static int
571 arg_need_temp (ArgInfo *ainfo)
572 {
573 /*
574 * We always fetch the double value from the fpstack. In that case, we
575 * need to have a separate tmp that is the double value casted to float
576 */
577 if (ainfo->storage == ArgOnFloatFpStack)
578 return sizeof (float);
579 return 0;
580 }
581
582 static gpointer
583 arg_get_storage (CallContext *ccontext, ArgInfo *ainfo)
584 {
585 switch (ainfo->storage) {
586 case ArgOnStack:
587 return ccontext->stack + ainfo->offset;
588 case ArgOnDoubleFpStack:
589 return &ccontext->fret;
590 case ArgInIReg:
591 /* If pair, the storage is for EDX:EAX */
592 return &ccontext->eax;
593 default:
594 g_error ("Arg storage type not yet supported");
595 }
596 }
597
598 static void
599 arg_get_val (CallContext *ccontext, ArgInfo *ainfo, gpointer dest)
600 {
601 g_assert (ainfo->storage == ArgOnFloatFpStack);
602
603 *(float*) dest = (float)ccontext->fret;
604 }
605
606 void
607 mono_arch_set_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
608 {
609 CallInfo *cinfo = get_call_info (NULL, sig);
610 const MonoEECallbacks *interp_cb = mini_get_interp_callbacks ();
611 gpointer storage;
612 ArgInfo *ainfo;
613
614 memset (ccontext, 0, sizeof (CallContext));
615
616 ccontext->stack_size = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
617 if (ccontext->stack_size)
618 ccontext->stack = (guint8*)g_calloc (1, ccontext->stack_size);
619
620 if (sig->ret->type != MONO_TYPE_VOID) {
621 ainfo = &cinfo->ret;
622 if (ainfo->storage == ArgOnStack) {
623 /* This is a value type return. The pointer to vt storage is pushed as first argument */
624 g_assert (ainfo->offset == 0);
625 g_assert (ainfo->nslots == 1);
626 storage = interp_cb->frame_arg_to_storage ((MonoInterpFrameHandle)frame, sig, -1);
627 *(host_mgreg_t*)ccontext->stack = (host_mgreg_t)storage;
628 }
629 }
630
631 g_assert (!sig->hasthis);
632
633 for (int i = 0; i < sig->param_count; i++) {
634 ainfo = &cinfo->args [i];
635
636 storage = arg_get_storage (ccontext, ainfo);
637
638 interp_cb->frame_arg_to_data ((MonoInterpFrameHandle)frame, sig, i, storage);
639 }
640
641 g_free (cinfo);
642 }
643
644 void
645 mono_arch_get_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
646 {
647 const MonoEECallbacks *interp_cb;
648 CallInfo *cinfo;
649 ArgInfo *ainfo;
650 gpointer storage;
651
652 /* No return value */
653 if (sig->ret->type == MONO_TYPE_VOID)
654 return;
655
656 interp_cb = mini_get_interp_callbacks ();
657 cinfo = get_call_info (NULL, sig);
658 ainfo = &cinfo->ret;
659
660 /* Check if return value was stored directly at address passed in reg */
661 if (cinfo->ret.storage != ArgOnStack) {
662 int temp_size = arg_need_temp (ainfo);
663
664 if (temp_size) {
665 storage = alloca (temp_size);
666 arg_get_val (ccontext, ainfo, storage);
667 } else {
668 storage = arg_get_storage (ccontext, ainfo);
669 }
670 interp_cb->data_to_frame_arg ((MonoInterpFrameHandle)frame, sig, -1, storage);
671 }
672
673 g_free (cinfo);
674 }
675
676 /*
677 * mono_arch_get_argument_info:
678 * @csig: a method signature
679 * @param_count: the number of parameters to consider
680 * @arg_info: an array to store the result infos
681 *
682 * Gathers information on parameters such as size, alignment and
683 * padding. arg_info should be large enought to hold param_count + 1 entries.
684 *
685 * Returns the size of the argument area on the stack.
686 * This should be signal safe, since it is called from
687 * mono_arch_unwind_frame ().
688 * FIXME: The metadata calls might not be signal safe.
689 */
690 int
691 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
692 {
693 int len, k, args_size = 0;
694 int size, pad;
695 guint32 align;
696 int offset = 8;
697 CallInfo *cinfo;
698 int prev_stackarg;
699 int num_regs;
700
701 /* Avoid g_malloc as it is not signal safe */
702 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
703 cinfo = (CallInfo*)g_alloca (len);
704 memset (cinfo, 0, len);
705
706 cinfo = get_call_info_internal (cinfo, csig);
707
708 arg_info [0].offset = offset;
709
710 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
711 args_size += sizeof (target_mgreg_t);
712 offset += 4;
713 }
714
715 if (csig->hasthis && !storage_in_ireg (cinfo->args [0].storage)) {
716 args_size += sizeof (target_mgreg_t);
717 offset += 4;
718 }
719
720 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
721 /* Emitted after this */
722 args_size += sizeof (target_mgreg_t);
723 offset += 4;
724 }
725
726 arg_info [0].size = args_size;
727 prev_stackarg = 0;
728
729 for (k = 0; k < param_count; k++) {
730 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
731
732 if (storage_in_ireg (cinfo->args [csig->hasthis + k].storage)) {
733 /* not in stack, we'll give it an offset at the end */
734 arg_info [k + 1].pad = 0;
735 arg_info [k + 1].size = size;
736 } else {
737 /* ignore alignment for now */
738 align = 1;
739
740 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
741 arg_info [prev_stackarg].pad = pad;
742 args_size += size;
743 arg_info [k + 1].pad = 0;
744 arg_info [k + 1].size = size;
745 offset += pad;
746 arg_info [k + 1].offset = offset;
747 offset += size;
748 prev_stackarg = k + 1;
749 }
750
751 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
752 /* Emitted after the first arg */
753 args_size += sizeof (target_mgreg_t);
754 offset += 4;
755 }
756 }
757
758 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
759 align = MONO_ARCH_FRAME_ALIGNMENT;
760 else
761 align = 4;
762 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
763 arg_info [k].pad = pad;
764
765 /* Add offsets for any reg parameters */
766 num_regs = 0;
767 if (csig->hasthis && storage_in_ireg (cinfo->args [0].storage))
768 arg_info [0].offset = args_size + 4 * num_regs++;
769 for (k=0; k < param_count; k++) {
770 if (storage_in_ireg (cinfo->args[csig->hasthis + k].storage)) {
771 arg_info [k + 1].offset = args_size + 4 * num_regs++;
772 }
773 }
774
775 return args_size;
776 }
777
778 #ifndef DISABLE_JIT
779
780 gboolean
781 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
782 {
783 g_assert (caller_sig);
784 g_assert (callee_sig);
785
786 // Direct AOT calls usually go through the PLT/GOT.
787 // Unless we can determine here if is_direct_callable will return TRUE?
788 // But the PLT/GOT is addressed with nonvolatile ebx, which
789 // gets restored before the jump.
790 // See https://github.com/mono/mono/commit/f5373adc8a89d4b0d1d549fdd6d9adc3ded4b400
791 // See https://github.com/mono/mono/issues/11265
792 if (!virtual_ && cfg->compile_aot && !cfg->full_aot)
793 return FALSE;
794
795 CallInfo *caller_info = get_call_info (NULL, caller_sig);
796 CallInfo *callee_info = get_call_info (NULL, callee_sig);
797
798 /*
799 * Tailcalls with more callee stack usage than the caller cannot be supported, since
800 * the extra stack space would be left on the stack after the tailcall.
801 */
802 gboolean res = IS_SUPPORTED_TAILCALL (callee_info->stack_usage <= caller_info->stack_usage)
803 && IS_SUPPORTED_TAILCALL (caller_info->ret.storage == callee_info->ret.storage);
804 if (!res && !mono_tailcall_print_enabled ())
805 goto exit;
806
807 // Limit stack_usage to 1G.
808 res &= IS_SUPPORTED_TAILCALL (callee_info->stack_usage < (1 << 30));
809 res &= IS_SUPPORTED_TAILCALL (caller_info->stack_usage < (1 << 30));
810
811 exit:
812 g_free (caller_info);
813 g_free (callee_info);
814
815 return res;
816 }
817
818 #endif
819
820 /*
821 * Initialize the cpu to execute managed code.
822 */
823 void
824 mono_arch_cpu_init (void)
825 {
826 /* spec compliance requires running with double precision */
827 #ifndef _MSC_VER
828 guint16 fpcw;
829
830 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
831 fpcw &= ~X86_FPCW_PRECC_MASK;
832 fpcw |= X86_FPCW_PREC_DOUBLE;
833 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
834 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
835 #else
836 _control87 (_PC_53, MCW_PC);
837 #endif
838 }
839
840 /*
841 * Initialize architecture specific code.
842 */
843 void
844 mono_arch_init (void)
845 {
846 if (!mono_aot_only)
847 bp_trampoline = mini_get_breakpoint_trampoline ();
848 }
849
850 /*
851 * Cleanup architecture specific code.
852 */
853 void
854 mono_arch_cleanup (void)
855 {
856 }
857
858 /*
859 * This function returns the optimizations supported on this cpu.
860 */
861 guint32
862 mono_arch_cpu_optimizations (guint32 *exclude_mask)
863 {
864 guint32 opts = 0;
865
866 *exclude_mask = 0;
867
868 if (mono_hwcap_x86_has_cmov) {
869 opts |= MONO_OPT_CMOV;
870
871 if (mono_hwcap_x86_has_fcmov)
872 opts |= MONO_OPT_FCMOV;
873 else
874 *exclude_mask |= MONO_OPT_FCMOV;
875 } else {
876 *exclude_mask |= MONO_OPT_CMOV;
877 }
878
879 if (mono_hwcap_x86_has_sse2)
880 opts |= MONO_OPT_SSE2;
881 else
882 *exclude_mask |= MONO_OPT_SSE2;
883
884 #ifdef MONO_ARCH_SIMD_INTRINSICS
885 /*SIMD intrinsics require at least SSE2.*/
886 if (!mono_hwcap_x86_has_sse2)
887 *exclude_mask |= MONO_OPT_SIMD;
888 #endif
889
890 return opts;
891 }
892
893 MonoCPUFeatures
894 mono_arch_get_cpu_features (void)
895 {
896 guint64 features = MONO_CPU_INITED;
897
898 if (mono_hwcap_x86_has_sse1)
899 features |= MONO_CPU_X86_SSE;
900
901 if (mono_hwcap_x86_has_sse2)
902 features |= MONO_CPU_X86_SSE2;
903
904 if (mono_hwcap_x86_has_sse3)
905 features |= MONO_CPU_X86_SSE3;
906
907 if (mono_hwcap_x86_has_ssse3)
908 features |= MONO_CPU_X86_SSSE3;
909
910 if (mono_hwcap_x86_has_sse41)
911 features |= MONO_CPU_X86_SSE41;
912
913 if (mono_hwcap_x86_has_sse42)
914 features |= MONO_CPU_X86_SSE42;
915
916 return (MonoCPUFeatures)features;
917 }
918
919 /*
920 * Determine whenever the trap whose info is in SIGINFO is caused by
921 * integer overflow.
922 */
923 gboolean
924 mono_arch_is_int_overflow (void *sigctx, void *info)
925 {
926 MonoContext ctx;
927 guint8* ip;
928
929 mono_sigctx_to_monoctx (sigctx, &ctx);
930
931 ip = (guint8*)ctx.eip;
932
933 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
934 gint32 reg;
935
936 /* idiv REG */
937 switch (x86_modrm_rm (ip [1])) {
938 case X86_EAX:
939 reg = ctx.eax;
940 break;
941 case X86_ECX:
942 reg = ctx.ecx;
943 break;
944 case X86_EDX:
945 reg = ctx.edx;
946 break;
947 case X86_EBX:
948 reg = ctx.ebx;
949 break;
950 case X86_ESI:
951 reg = ctx.esi;
952 break;
953 case X86_EDI:
954 reg = ctx.edi;
955 break;
956 default:
957 g_assert_not_reached ();
958 reg = -1;
959 }
960
961 if (reg == -1)
962 return TRUE;
963 }
964
965 return FALSE;
966 }
967
968 GList *
969 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
970 {
971 GList *vars = NULL;
972 int i;
973
974 for (i = 0; i < cfg->num_varinfo; i++) {
975 MonoInst *ins = cfg->varinfo [i];
976 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
977
978 /* unused vars */
979 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
980 continue;
981
982 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
983 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
984 continue;
985
986 /* we dont allocate I1 to registers because there is no simply way to sign extend
987 * 8bit quantities in caller saved registers on x86 */
988 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
989 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
990 g_assert (i == vmv->idx);
991 vars = g_list_prepend (vars, vmv);
992 }
993 }
994
995 vars = mono_varlist_sort (cfg, vars, 0);
996
997 return vars;
998 }
999
1000 GList *
1001 mono_arch_get_global_int_regs (MonoCompile *cfg)
1002 {
1003 GList *regs = NULL;
1004
1005 /* we can use 3 registers for global allocation */
1006 regs = g_list_prepend (regs, (gpointer)X86_EBX);
1007 regs = g_list_prepend (regs, (gpointer)X86_ESI);
1008 regs = g_list_prepend (regs, (gpointer)X86_EDI);
1009
1010 return regs;
1011 }
1012
1013 /*
1014 * mono_arch_regalloc_cost:
1015 *
1016 * Return the cost, in number of memory references, of the action of
1017 * allocating the variable VMV into a register during global register
1018 * allocation.
1019 */
1020 guint32
1021 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1022 {
1023 MonoInst *ins = cfg->varinfo [vmv->idx];
1024
1025 if (cfg->method->save_lmf)
1026 /* The register is already saved */
1027 return (ins->opcode == OP_ARG) ? 1 : 0;
1028 else
1029 /* push+pop+possible load if it is an argument */
1030 return (ins->opcode == OP_ARG) ? 3 : 2;
1031 }
1032
1033 static void
1034 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1035 {
1036 static int inited = FALSE;
1037 static int count = 0;
1038
1039 if (cfg->arch.need_stack_frame_inited) {
1040 g_assert (cfg->arch.need_stack_frame == flag);
1041 return;
1042 }
1043
1044 cfg->arch.need_stack_frame = flag;
1045 cfg->arch.need_stack_frame_inited = TRUE;
1046
1047 if (flag)
1048 return;
1049
1050 if (!inited) {
1051 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1052 inited = TRUE;
1053 }
1054 ++count;
1055
1056 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1057 }
1058
1059 static gboolean
1060 needs_stack_frame (MonoCompile *cfg)
1061 {
1062 MonoMethodSignature *sig;
1063 MonoMethodHeader *header;
1064 gboolean result = FALSE;
1065
1066 #if defined (__APPLE__)
1067 /*OSX requires stack frame code to have the correct alignment. */
1068 return TRUE;
1069 #endif
1070
1071 if (cfg->arch.need_stack_frame_inited)
1072 return cfg->arch.need_stack_frame;
1073
1074 header = cfg->header;
1075 sig = mono_method_signature_internal (cfg->method);
1076
1077 if (cfg->disable_omit_fp)
1078 result = TRUE;
1079 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1080 result = TRUE;
1081 else if (cfg->method->save_lmf)
1082 result = TRUE;
1083 else if (cfg->stack_offset)
1084 result = TRUE;
1085 else if (cfg->param_area)
1086 result = TRUE;
1087 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAILCALL))
1088 result = TRUE;
1089 else if (header->num_clauses)
1090 result = TRUE;
1091 else if (sig->param_count + sig->hasthis)
1092 result = TRUE;
1093 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1094 result = TRUE;
1095
1096 set_needs_stack_frame (cfg, result);
1097
1098 return cfg->arch.need_stack_frame;
1099 }
1100
1101 /*
1102 * Set var information according to the calling convention. X86 version.
1103 * The locals var stuff should most likely be split in another method.
1104 */
1105 void
1106 mono_arch_allocate_vars (MonoCompile *cfg)
1107 {
1108 MonoMethodSignature *sig;
1109 MonoInst *inst;
1110 guint32 locals_stack_size, locals_stack_align;
1111 int i, offset;
1112 gint32 *offsets;
1113 CallInfo *cinfo;
1114
1115 sig = mono_method_signature_internal (cfg->method);
1116
1117 if (!cfg->arch.cinfo)
1118 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1119 cinfo = cfg->arch.cinfo;
1120
1121 cfg->frame_reg = X86_EBP;
1122 offset = 0;
1123
1124 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1125 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1126 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1127 }
1128
1129 /* Reserve space to save LMF and caller saved registers */
1130
1131 if (cfg->method->save_lmf) {
1132 /* The LMF var is allocated normally */
1133 } else {
1134 if (cfg->used_int_regs & (1 << X86_EBX)) {
1135 offset += 4;
1136 }
1137
1138 if (cfg->used_int_regs & (1 << X86_EDI)) {
1139 offset += 4;
1140 }
1141
1142 if (cfg->used_int_regs & (1 << X86_ESI)) {
1143 offset += 4;
1144 }
1145 }
1146
1147 switch (cinfo->ret.storage) {
1148 case ArgValuetypeInReg:
1149 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1150 offset += 8;
1151 cfg->ret->opcode = OP_REGOFFSET;
1152 cfg->ret->inst_basereg = X86_EBP;
1153 cfg->ret->inst_offset = - offset;
1154 break;
1155 default:
1156 break;
1157 }
1158
1159 /* Allocate a local for any register arguments that need them. */
1160 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1161 ArgInfo *ainfo = &cinfo->args [i];
1162 inst = cfg->args [i];
1163 if (inst->opcode != OP_REGVAR && storage_in_ireg (ainfo->storage)) {
1164 offset += 4;
1165 cfg->args[i]->opcode = OP_REGOFFSET;
1166 cfg->args[i]->inst_basereg = X86_EBP;
1167 cfg->args[i]->inst_offset = - offset;
1168 }
1169 }
1170
1171 /* Allocate locals */
1172 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1173 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1174 char *mname = mono_method_full_name (cfg->method, TRUE);
1175 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1176 g_free (mname);
1177 return;
1178 }
1179 if (locals_stack_align) {
1180 int prev_offset = offset;
1181
1182 offset += (locals_stack_align - 1);
1183 offset &= ~(locals_stack_align - 1);
1184
1185 while (prev_offset < offset) {
1186 prev_offset += 4;
1187 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1188 }
1189 }
1190 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1191 cfg->locals_max_stack_offset = - offset;
1192 /*
1193 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1194 * have locals larger than 8 bytes we need to make sure that
1195 * they have the appropriate offset.
1196 */
1197 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1198 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (target_mgreg_t) * 2;
1199 offset += extra_size;
1200 locals_stack_size += extra_size;
1201 }
1202 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1203 if (offsets [i] != -1) {
1204 MonoInst *inst = cfg->varinfo [i];
1205 inst->opcode = OP_REGOFFSET;
1206 inst->inst_basereg = X86_EBP;
1207 inst->inst_offset = - (offset + offsets [i]);
1208 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1209 }
1210 }
1211 offset += locals_stack_size;
1212
1213
1214 /*
1215 * Allocate arguments+return value
1216 */
1217
1218 switch (cinfo->ret.storage) {
1219 case ArgOnStack:
1220 if (cfg->vret_addr) {
1221 /*
1222 * In the new IR, the cfg->vret_addr variable represents the
1223 * vtype return value.
1224 */
1225 cfg->vret_addr->opcode = OP_REGOFFSET;
1226 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1227 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1228 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1229 printf ("vret_addr =");
1230 mono_print_ins (cfg->vret_addr);
1231 }
1232 } else {
1233 cfg->ret->opcode = OP_REGOFFSET;
1234 cfg->ret->inst_basereg = X86_EBP;
1235 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1236 }
1237 break;
1238 case ArgValuetypeInReg:
1239 break;
1240 case ArgInIReg:
1241 cfg->ret->opcode = OP_REGVAR;
1242 cfg->ret->inst_c0 = cinfo->ret.reg;
1243 cfg->ret->dreg = cinfo->ret.reg;
1244 break;
1245 case ArgNone:
1246 case ArgOnFloatFpStack:
1247 case ArgOnDoubleFpStack:
1248 break;
1249 default:
1250 g_assert_not_reached ();
1251 }
1252
1253 if (sig->call_convention == MONO_CALL_VARARG) {
1254 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1255 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1256 }
1257
1258 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1259 ArgInfo *ainfo = &cinfo->args [i];
1260 inst = cfg->args [i];
1261 if (inst->opcode != OP_REGVAR) {
1262 if (storage_in_ireg (ainfo->storage)) {
1263 /* We already allocated locals for register arguments. */
1264 } else {
1265 inst->opcode = OP_REGOFFSET;
1266 inst->inst_basereg = X86_EBP;
1267 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1268 }
1269 }
1270 }
1271
1272 cfg->stack_offset = offset;
1273 }
1274
1275 void
1276 mono_arch_create_vars (MonoCompile *cfg)
1277 {
1278 MonoType *sig_ret;
1279 MonoMethodSignature *sig;
1280 CallInfo *cinfo;
1281
1282 sig = mono_method_signature_internal (cfg->method);
1283
1284 if (!cfg->arch.cinfo)
1285 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1286 cinfo = cfg->arch.cinfo;
1287
1288 sig_ret = mini_get_underlying_type (sig->ret);
1289
1290 if (cinfo->ret.storage == ArgValuetypeInReg)
1291 cfg->ret_var_is_local = TRUE;
1292 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1293 cfg->vret_addr = mono_compile_create_var (cfg, mono_get_int_type (), OP_ARG);
1294 }
1295
1296 if (cfg->gen_sdb_seq_points) {
1297 MonoInst *ins;
1298
1299 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1300 ins->flags |= MONO_INST_VOLATILE;
1301 cfg->arch.ss_tramp_var = ins;
1302
1303 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1304 ins->flags |= MONO_INST_VOLATILE;
1305 cfg->arch.bp_tramp_var = ins;
1306 }
1307
1308 if (cfg->method->save_lmf) {
1309 cfg->create_lmf_var = TRUE;
1310 cfg->lmf_ir = TRUE;
1311 }
1312
1313 cfg->arch_eh_jit_info = 1;
1314 }
1315
1316 /*
1317 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1318 * so we try to do it just once when we have multiple fp arguments in a row.
1319 * We don't use this mechanism generally because for int arguments the generated code
1320 * is slightly bigger and new generation cpus optimize away the dependency chains
1321 * created by push instructions on the esp value.
1322 * fp_arg_setup is the first argument in the execution sequence where the esp register
1323 * is modified.
1324 */
1325 static G_GNUC_UNUSED int
1326 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1327 {
1328 int fp_space = 0;
1329 MonoType *t;
1330
1331 for (; start_arg < sig->param_count; ++start_arg) {
1332 t = mini_get_underlying_type (sig->params [start_arg]);
1333 if (!t->byref && t->type == MONO_TYPE_R8) {
1334 fp_space += sizeof (double);
1335 *fp_arg_setup = start_arg;
1336 } else {
1337 break;
1338 }
1339 }
1340 return fp_space;
1341 }
1342
1343 static void
1344 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1345 {
1346 MonoMethodSignature *tmp_sig;
1347 int sig_reg;
1348
1349 /*
1350 * mono_ArgIterator_Setup assumes the signature cookie is
1351 * passed first and all the arguments which were before it are
1352 * passed on the stack after the signature. So compensate by
1353 * passing a different signature.
1354 */
1355 tmp_sig = mono_metadata_signature_dup (call->signature);
1356 tmp_sig->param_count -= call->signature->sentinelpos;
1357 tmp_sig->sentinelpos = 0;
1358 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1359
1360 if (cfg->compile_aot) {
1361 sig_reg = mono_alloc_ireg (cfg);
1362 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1363 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1364 } else {
1365 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, (gsize)tmp_sig);
1366 }
1367 }
1368
1369 #ifdef ENABLE_LLVM
1370 LLVMCallInfo*
1371 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1372 {
1373 int i, n;
1374 CallInfo *cinfo;
1375 ArgInfo *ainfo;
1376 LLVMCallInfo *linfo;
1377 MonoType *t, *sig_ret;
1378
1379 n = sig->param_count + sig->hasthis;
1380
1381 cinfo = get_call_info (cfg->mempool, sig);
1382 sig_ret = sig->ret;
1383
1384 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1385
1386 /*
1387 * LLVM always uses the native ABI while we use our own ABI, the
1388 * only difference is the handling of vtypes:
1389 * - we only pass/receive them in registers in some cases, and only
1390 * in 1 or 2 integer registers.
1391 */
1392 if (cinfo->ret.storage == ArgValuetypeInReg) {
1393 if (sig->pinvoke) {
1394 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1395 cfg->disable_llvm = TRUE;
1396 return linfo;
1397 }
1398
1399 cfg->exception_message = g_strdup ("vtype ret in call");
1400 cfg->disable_llvm = TRUE;
1401 /*
1402 linfo->ret.storage = LLVMArgVtypeInReg;
1403 for (j = 0; j < 2; ++j)
1404 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1405 */
1406 }
1407
1408 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1409 /* Vtype returned using a hidden argument */
1410 linfo->ret.storage = LLVMArgVtypeRetAddr;
1411 linfo->vret_arg_index = cinfo->vret_arg_index;
1412 }
1413
1414 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1415 // FIXME:
1416 cfg->exception_message = g_strdup ("vtype ret in call");
1417 cfg->disable_llvm = TRUE;
1418 }
1419
1420 for (i = 0; i < n; ++i) {
1421 ainfo = cinfo->args + i;
1422
1423 if (i >= sig->hasthis)
1424 t = sig->params [i - sig->hasthis];
1425 else
1426 t = mono_get_int_type ();
1427
1428 linfo->args [i].storage = LLVMArgNone;
1429
1430 switch (ainfo->storage) {
1431 case ArgInIReg:
1432 linfo->args [i].storage = LLVMArgNormal;
1433 break;
1434 case ArgInDoubleSSEReg:
1435 case ArgInFloatSSEReg:
1436 linfo->args [i].storage = LLVMArgNormal;
1437 break;
1438 case ArgOnStack:
1439 if (mini_type_is_vtype (t)) {
1440 if (mono_class_value_size (mono_class_from_mono_type_internal (t), NULL) == 0)
1441 /* LLVM seems to allocate argument space for empty structures too */
1442 linfo->args [i].storage = LLVMArgNone;
1443 else
1444 linfo->args [i].storage = LLVMArgVtypeByVal;
1445 } else {
1446 linfo->args [i].storage = LLVMArgNormal;
1447 }
1448 break;
1449 case ArgValuetypeInReg:
1450 if (sig->pinvoke) {
1451 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1452 cfg->disable_llvm = TRUE;
1453 return linfo;
1454 }
1455
1456 cfg->exception_message = g_strdup ("vtype arg");
1457 cfg->disable_llvm = TRUE;
1458 /*
1459 linfo->args [i].storage = LLVMArgVtypeInReg;
1460 for (j = 0; j < 2; ++j)
1461 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1462 */
1463 break;
1464 case ArgGSharedVt:
1465 linfo->args [i].storage = LLVMArgGSharedVt;
1466 break;
1467 default:
1468 cfg->exception_message = g_strdup ("ainfo->storage");
1469 cfg->disable_llvm = TRUE;
1470 break;
1471 }
1472 }
1473
1474 return linfo;
1475 }
1476 #endif
1477
1478 static void
1479 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1480 {
1481 if (cfg->compute_gc_maps) {
1482 MonoInst *def;
1483
1484 /* Needs checking if the feature will be enabled again */
1485 g_assert_not_reached ();
1486
1487 /* On x86, the offsets are from the sp value before the start of the call sequence */
1488 if (t == NULL)
1489 t = mono_get_int_type ();
1490 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1491 }
1492 }
1493
1494 void
1495 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1496 {
1497 MonoType *sig_ret;
1498 MonoInst *arg, *in;
1499 MonoMethodSignature *sig;
1500 int i, j, n;
1501 CallInfo *cinfo;
1502 int sentinelpos = 0, sp_offset = 0;
1503
1504 sig = call->signature;
1505 n = sig->param_count + sig->hasthis;
1506 sig_ret = mini_get_underlying_type (sig->ret);
1507
1508 cinfo = get_call_info (cfg->mempool, sig);
1509 call->call_info = cinfo;
1510
1511 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1512 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1513
1514 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1515 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1516 /*
1517 * Tell the JIT to use a more efficient calling convention: call using
1518 * OP_CALL, compute the result location after the call, and save the
1519 * result there.
1520 */
1521 call->vret_in_reg = TRUE;
1522 #if defined (__APPLE__)
1523 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1524 call->vret_in_reg_fp = TRUE;
1525 #endif
1526 if (call->vret_var)
1527 NULLIFY_INS (call->vret_var);
1528 }
1529 }
1530
1531 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1532
1533 /* Handle the case where there are no implicit arguments */
1534 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1535 emit_sig_cookie (cfg, call, cinfo);
1536 sp_offset = cinfo->sig_cookie.offset;
1537 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1538 }
1539
1540 /* Arguments are pushed in the reverse order */
1541 for (i = n - 1; i >= 0; i --) {
1542 ArgInfo *ainfo = cinfo->args + i;
1543 MonoType *orig_type, *t;
1544 int argsize;
1545
1546 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1547 MonoInst *vtarg;
1548
1549 /* Push the vret arg before the first argument */
1550 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1551 vtarg->type = STACK_MP;
1552 vtarg->inst_destbasereg = X86_ESP;
1553 vtarg->sreg1 = call->vret_var->dreg;
1554 vtarg->inst_offset = cinfo->ret.offset;
1555 MONO_ADD_INS (cfg->cbb, vtarg);
1556 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1557 }
1558
1559 if (i >= sig->hasthis)
1560 t = sig->params [i - sig->hasthis];
1561 else
1562 t = mono_get_int_type ();
1563 orig_type = t;
1564 t = mini_get_underlying_type (t);
1565
1566 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1567
1568 in = call->args [i];
1569 arg->cil_code = in->cil_code;
1570 arg->sreg1 = in->dreg;
1571 arg->type = in->type;
1572
1573 g_assert (in->dreg != -1);
1574
1575 if (ainfo->storage == ArgGSharedVt) {
1576 arg->opcode = OP_OUTARG_VT;
1577 arg->sreg1 = in->dreg;
1578 arg->klass = in->klass;
1579 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1580 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1581 sp_offset += 4;
1582 MONO_ADD_INS (cfg->cbb, arg);
1583 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1584 guint32 align;
1585 guint32 size;
1586
1587 g_assert (in->klass);
1588
1589 if (t->type == MONO_TYPE_TYPEDBYREF) {
1590 size = MONO_ABI_SIZEOF (MonoTypedRef);
1591 align = sizeof (target_mgreg_t);
1592 }
1593 else {
1594 size = mini_type_stack_size_full (m_class_get_byval_arg (in->klass), &align, sig->pinvoke);
1595 }
1596
1597 if (size > 0 || ainfo->pass_empty_struct) {
1598 arg->opcode = OP_OUTARG_VT;
1599 arg->sreg1 = in->dreg;
1600 arg->klass = in->klass;
1601 arg->backend.size = size;
1602 arg->inst_p0 = call;
1603 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1604 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1605
1606 MONO_ADD_INS (cfg->cbb, arg);
1607 if (ainfo->storage != ArgValuetypeInReg) {
1608 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1609 }
1610 }
1611 } else {
1612 switch (ainfo->storage) {
1613 case ArgOnStack:
1614 if (!t->byref) {
1615 if (t->type == MONO_TYPE_R4) {
1616 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1617 argsize = 4;
1618 } else if (t->type == MONO_TYPE_R8) {
1619 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1620 argsize = 8;
1621 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1622 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1623 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1624 argsize = 4;
1625 } else {
1626 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1627 argsize = 4;
1628 }
1629 } else {
1630 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1631 argsize = 4;
1632 }
1633 break;
1634 case ArgInIReg:
1635 arg->opcode = OP_MOVE;
1636 arg->dreg = ainfo->reg;
1637 MONO_ADD_INS (cfg->cbb, arg);
1638 argsize = 0;
1639 break;
1640 default:
1641 g_assert_not_reached ();
1642 }
1643
1644 if (cfg->compute_gc_maps) {
1645 if (argsize == 4) {
1646 /* FIXME: The == STACK_OBJ check might be fragile ? */
1647 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1648 /* this */
1649 if (call->need_unbox_trampoline)
1650 /* The unbox trampoline transforms this into a managed pointer */
1651 emit_gc_param_slot_def (cfg, ainfo->offset, m_class_get_this_arg (mono_defaults.int_class));
1652 else
1653 emit_gc_param_slot_def (cfg, ainfo->offset, mono_get_object_type ());
1654 } else {
1655 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1656 }
1657 } else {
1658 /* i8/r8 */
1659 for (j = 0; j < argsize; j += 4)
1660 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1661 }
1662 }
1663 }
1664
1665 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1666 /* Emit the signature cookie just before the implicit arguments */
1667 emit_sig_cookie (cfg, call, cinfo);
1668 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1669 }
1670 }
1671
1672 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1673 MonoInst *vtarg;
1674
1675 if (cinfo->ret.storage == ArgValuetypeInReg) {
1676 /* Already done */
1677 }
1678 else if (cinfo->ret.storage == ArgInIReg) {
1679 NOT_IMPLEMENTED;
1680 /* The return address is passed in a register */
1681 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1682 vtarg->sreg1 = call->inst.dreg;
1683 vtarg->dreg = mono_alloc_ireg (cfg);
1684 MONO_ADD_INS (cfg->cbb, vtarg);
1685
1686 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1687 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1688 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1689 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1690 }
1691 }
1692
1693 call->stack_usage = cinfo->stack_usage;
1694 call->stack_align_amount = cinfo->stack_align_amount;
1695 }
1696
1697 void
1698 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1699 {
1700 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1701 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1702 int size = ins->backend.size;
1703
1704 if (ainfo->storage == ArgValuetypeInReg) {
1705 int dreg = mono_alloc_ireg (cfg);
1706 switch (size) {
1707 case 1:
1708 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1709 break;
1710 case 2:
1711 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1712 break;
1713 case 4:
1714 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1715 break;
1716 case 3: /* FIXME */
1717 default:
1718 g_assert_not_reached ();
1719 }
1720 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1721 }
1722 else {
1723 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1724 /* Pass by addr */
1725 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1726 } else if (size <= 4) {
1727 int dreg = mono_alloc_ireg (cfg);
1728 if (ainfo->pass_empty_struct) {
1729 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1730 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1731 } else {
1732 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1733 }
1734 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1735 } else if (size <= 20) {
1736 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1737 } else {
1738 // FIXME: Code growth
1739 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1740 }
1741 }
1742 }
1743
1744 void
1745 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1746 {
1747 MonoType *ret = mini_get_underlying_type (mono_method_signature_internal (method)->ret);
1748
1749 if (!ret->byref) {
1750 if (ret->type == MONO_TYPE_R4) {
1751 if (COMPILE_LLVM (cfg))
1752 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1753 /* Nothing to do */
1754 return;
1755 } else if (ret->type == MONO_TYPE_R8) {
1756 if (COMPILE_LLVM (cfg))
1757 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1758 /* Nothing to do */
1759 return;
1760 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1761 if (COMPILE_LLVM (cfg))
1762 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1763 else {
1764 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1765 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1766 }
1767 return;
1768 }
1769 }
1770
1771 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1772 }
1773
1774 #define EMIT_COND_BRANCH(ins,cond,sign) \
1775 if (ins->inst_true_bb->native_offset) { \
1776 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1777 } else { \
1778 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1779 if ((cfg->opt & MONO_OPT_BRANCH) && \
1780 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1781 x86_branch8 (code, cond, 0, sign); \
1782 else \
1783 x86_branch32 (code, cond, 0, sign); \
1784 }
1785
1786 /*
1787 * Emit an exception if condition is fail and
1788 * if possible do a directly branch to target
1789 */
1790 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1791 do { \
1792 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1793 if (tins == NULL) { \
1794 mono_add_patch_info (cfg, code - cfg->native_code, \
1795 MONO_PATCH_INFO_EXC, exc_name); \
1796 x86_branch32 (code, cond, 0, signed); \
1797 } else { \
1798 EMIT_COND_BRANCH (tins, cond, signed); \
1799 } \
1800 } while (0);
1801
1802 #define EMIT_FPCOMPARE(code) do { \
1803 x86_fcompp (code); \
1804 x86_fnstsw (code); \
1805 } while (0);
1806
1807 static guint8*
1808 x86_align_and_patch (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1809 {
1810 gboolean needs_paddings = TRUE;
1811 guint32 pad_size;
1812 MonoJumpInfo *jinfo = NULL;
1813
1814 if (cfg->abs_patches) {
1815 jinfo = (MonoJumpInfo*)g_hash_table_lookup (cfg->abs_patches, data);
1816 if (jinfo && (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR
1817 || jinfo->type == MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR))
1818 needs_paddings = FALSE;
1819 }
1820
1821 if (cfg->compile_aot)
1822 needs_paddings = FALSE;
1823 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1824 This is required for code patching to be safe on SMP machines.
1825 */
1826 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1827 if (needs_paddings && pad_size)
1828 x86_padding (code, 4 - pad_size);
1829
1830 mono_add_patch_info (cfg, code - cfg->native_code, (MonoJumpInfoType)patch_type, data);
1831
1832 return code;
1833 }
1834
1835 static guint8*
1836 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1837 {
1838 code = x86_align_and_patch (cfg, code, patch_type, data);
1839
1840 x86_call_code (code, 0);
1841
1842 return code;
1843 }
1844
1845 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1846
1847 /*
1848 * mono_peephole_pass_1:
1849 *
1850 * Perform peephole opts which should/can be performed before local regalloc
1851 */
1852 void
1853 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1854 {
1855 MonoInst *ins, *n;
1856
1857 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1858 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1859
1860 switch (ins->opcode) {
1861 case OP_IADD_IMM:
1862 case OP_ADD_IMM:
1863 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1864 /*
1865 * X86_LEA is like ADD, but doesn't have the
1866 * sreg1==dreg restriction.
1867 */
1868 ins->opcode = OP_X86_LEA_MEMBASE;
1869 ins->inst_basereg = ins->sreg1;
1870 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1871 ins->opcode = OP_X86_INC_REG;
1872 break;
1873 case OP_SUB_IMM:
1874 case OP_ISUB_IMM:
1875 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1876 ins->opcode = OP_X86_LEA_MEMBASE;
1877 ins->inst_basereg = ins->sreg1;
1878 ins->inst_imm = -ins->inst_imm;
1879 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1880 ins->opcode = OP_X86_DEC_REG;
1881 break;
1882 case OP_COMPARE_IMM:
1883 case OP_ICOMPARE_IMM:
1884 /* OP_COMPARE_IMM (reg, 0)
1885 * -->
1886 * OP_X86_TEST_NULL (reg)
1887 */
1888 if (!ins->inst_imm)
1889 ins->opcode = OP_X86_TEST_NULL;
1890 break;
1891 case OP_X86_COMPARE_MEMBASE_IMM:
1892 /*
1893 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1894 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1895 * -->
1896 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1897 * OP_COMPARE_IMM reg, imm
1898 *
1899 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1900 */
1901 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1902 ins->inst_basereg == last_ins->inst_destbasereg &&
1903 ins->inst_offset == last_ins->inst_offset) {
1904 ins->opcode = OP_COMPARE_IMM;
1905 ins->sreg1 = last_ins->sreg1;
1906
1907 /* check if we can remove cmp reg,0 with test null */
1908 if (!ins->inst_imm)
1909 ins->opcode = OP_X86_TEST_NULL;
1910 }
1911
1912 break;
1913 case OP_X86_PUSH_MEMBASE:
1914 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1915 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1916 ins->inst_basereg == last_ins->inst_destbasereg &&
1917 ins->inst_offset == last_ins->inst_offset) {
1918 ins->opcode = OP_X86_PUSH;
1919 ins->sreg1 = last_ins->sreg1;
1920 }
1921 break;
1922 }
1923
1924 mono_peephole_ins (bb, ins);
1925 }
1926 }
1927
1928 void
1929 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1930 {
1931 MonoInst *ins, *n;
1932
1933 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1934 switch (ins->opcode) {
1935 case OP_ICONST:
1936 /* reg = 0 -> XOR (reg, reg) */
1937 /* XOR sets cflags on x86, so we cant do it always */
1938 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1939 MonoInst *ins2;
1940
1941 ins->opcode = OP_IXOR;
1942 ins->sreg1 = ins->dreg;
1943 ins->sreg2 = ins->dreg;
1944
1945 /*
1946 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1947 * since it takes 3 bytes instead of 7.
1948 */
1949 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1950 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1951 ins2->opcode = OP_STORE_MEMBASE_REG;
1952 ins2->sreg1 = ins->dreg;
1953 }
1954 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1955 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1956 ins2->sreg1 = ins->dreg;
1957 }
1958 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1959 /* Continue iteration */
1960 }
1961 else
1962 break;
1963 }
1964 }
1965 break;
1966 case OP_IADD_IMM:
1967 case OP_ADD_IMM:
1968 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1969 ins->opcode = OP_X86_INC_REG;
1970 break;
1971 case OP_ISUB_IMM:
1972 case OP_SUB_IMM:
1973 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1974 ins->opcode = OP_X86_DEC_REG;
1975 break;
1976 }
1977
1978 mono_peephole_ins (bb, ins);
1979 }
1980 }
1981
1982 #define NEW_INS(cfg,ins,dest,op) do { \
1983 MONO_INST_NEW ((cfg), (dest), (op)); \
1984 (dest)->cil_code = (ins)->cil_code; \
1985 mono_bblock_insert_before_ins (bb, ins, (dest)); \
1986 } while (0)
1987
1988 /*
1989 * mono_arch_lowering_pass:
1990 *
1991 * Converts complex opcodes into simpler ones so that each IR instruction
1992 * corresponds to one machine instruction.
1993 */
1994 void
1995 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1996 {
1997 MonoInst *ins, *next;
1998
1999 /*
2000 * FIXME: Need to add more instructions, but the current machine
2001 * description can't model some parts of the composite instructions like
2002 * cdq.
2003 */
2004 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2005 switch (ins->opcode) {
2006 case OP_IREM_IMM:
2007 case OP_IDIV_IMM:
2008 case OP_IDIV_UN_IMM:
2009 case OP_IREM_UN_IMM:
2010 /*
2011 * Keep the cases where we could generated optimized code, otherwise convert
2012 * to the non-imm variant.
2013 */
2014 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2015 break;
2016 mono_decompose_op_imm (cfg, bb, ins);
2017 break;
2018 #ifdef MONO_ARCH_SIMD_INTRINSICS
2019 case OP_EXPAND_I1: {
2020 MonoInst *temp;
2021 int temp_reg1 = mono_alloc_ireg (cfg);
2022 int temp_reg2 = mono_alloc_ireg (cfg);
2023 int original_reg = ins->sreg1;
2024
2025 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2026 temp->sreg1 = original_reg;
2027 temp->dreg = temp_reg1;
2028
2029 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2030 temp->sreg1 = temp_reg1;
2031 temp->dreg = temp_reg2;
2032 temp->inst_imm = 8;
2033
2034 NEW_INS (cfg, ins, temp, OP_IOR);
2035 temp->sreg1 = temp->dreg = temp_reg2;
2036 temp->sreg2 = temp_reg1;
2037
2038 ins->opcode = OP_EXPAND_I2;
2039 ins->sreg1 = temp_reg2;
2040 }
2041 break;
2042 #endif
2043 default:
2044 break;
2045 }
2046 }
2047
2048 bb->max_vreg = cfg->next_vreg;
2049 }
2050
2051 static const int
2052 branch_cc_table [] = {
2053 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2054 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2055 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2056 };
2057
2058 /* Maps CMP_... constants to X86_CC_... constants */
2059 static const int
2060 cc_table [] = {
2061 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2062 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2063 };
2064
2065 static const int
2066 cc_signed_table [] = {
2067 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2068 FALSE, FALSE, FALSE, FALSE
2069 };
2070
2071 static unsigned char*
2072 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2073 {
2074 #define XMM_TEMP_REG 0
2075 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2076 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2077 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2078 /* optimize by assigning a local var for this use so we avoid
2079 * the stack manipulations */
2080 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2081 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2082 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2083 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2084 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2085 if (size == 1)
2086 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2087 else if (size == 2)
2088 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2089 return code;
2090 }
2091 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2092 x86_fnstcw_membase(code, X86_ESP, 0);
2093 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2094 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2095 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2096 x86_fldcw_membase (code, X86_ESP, 2);
2097 if (size == 8) {
2098 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2099 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2100 x86_pop_reg (code, dreg);
2101 /* FIXME: need the high register
2102 * x86_pop_reg (code, dreg_high);
2103 */
2104 } else {
2105 x86_push_reg (code, X86_EAX); // SP = SP - 4
2106 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2107 x86_pop_reg (code, dreg);
2108 }
2109 x86_fldcw_membase (code, X86_ESP, 0);
2110 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2111
2112 if (size == 1)
2113 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2114 else if (size == 2)
2115 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2116 return code;
2117 }
2118
2119 static unsigned char*
2120 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2121 {
2122 int sreg = tree->sreg1;
2123 int need_touch = FALSE;
2124
2125 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2126 need_touch = TRUE;
2127 #endif
2128
2129 if (need_touch) {
2130 guint8* br[5];
2131
2132 /*
2133 * Under Windows:
2134 * If requested stack size is larger than one page,
2135 * perform stack-touch operation
2136 */
2137 /*
2138 * Generate stack probe code.
2139 * Under Windows, it is necessary to allocate one page at a time,
2140 * "touching" stack after each successful sub-allocation. This is
2141 * because of the way stack growth is implemented - there is a
2142 * guard page before the lowest stack page that is currently commited.
2143 * Stack normally grows sequentially so OS traps access to the
2144 * guard page and commits more pages when needed.
2145 */
2146 x86_test_reg_imm (code, sreg, ~0xFFF);
2147 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2148
2149 br[2] = code; /* loop */
2150 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2151 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2152
2153 /*
2154 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2155 * that follows only initializes the last part of the area.
2156 */
2157 /* Same as the init code below with size==0x1000 */
2158 if (tree->flags & MONO_INST_INIT) {
2159 x86_push_reg (code, X86_EAX);
2160 x86_push_reg (code, X86_ECX);
2161 x86_push_reg (code, X86_EDI);
2162 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2163 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2164 if (cfg->param_area)
2165 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2166 else
2167 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2168 x86_cld (code);
2169 x86_prefix (code, X86_REP_PREFIX);
2170 x86_stosl (code);
2171 x86_pop_reg (code, X86_EDI);
2172 x86_pop_reg (code, X86_ECX);
2173 x86_pop_reg (code, X86_EAX);
2174 }
2175
2176 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2177 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2178 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2179 x86_patch (br[3], br[2]);
2180 x86_test_reg_reg (code, sreg, sreg);
2181 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2182 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2183
2184 br[1] = code; x86_jump8 (code, 0);
2185
2186 x86_patch (br[0], code);
2187 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2188 x86_patch (br[1], code);
2189 x86_patch (br[4], code);
2190 }
2191 else
2192 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2193
2194 if (tree->flags & MONO_INST_INIT) {
2195 int offset = 0;
2196 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2197 x86_push_reg (code, X86_EAX);
2198 offset += 4;
2199 }
2200 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2201 x86_push_reg (code, X86_ECX);
2202 offset += 4;
2203 }
2204 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2205 x86_push_reg (code, X86_EDI);
2206 offset += 4;
2207 }
2208
2209 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2210 x86_mov_reg_reg (code, X86_ECX, sreg);
2211 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2212
2213 if (cfg->param_area)
2214 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2215 else
2216 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2217 x86_cld (code);
2218 x86_prefix (code, X86_REP_PREFIX);
2219 x86_stosl (code);
2220
2221 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2222 x86_pop_reg (code, X86_EDI);
2223 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2224 x86_pop_reg (code, X86_ECX);
2225 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2226 x86_pop_reg (code, X86_EAX);
2227 }
2228 return code;
2229 }
2230
2231
2232 static guint8*
2233 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2234 {
2235 /* Move return value to the target register */
2236 switch (ins->opcode) {
2237 case OP_CALL:
2238 case OP_CALL_REG:
2239 case OP_CALL_MEMBASE:
2240 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2241 break;
2242 default:
2243 break;
2244 }
2245
2246 return code;
2247 }
2248
2249 #ifdef TARGET_MACH
2250 static int tls_gs_offset;
2251 #endif
2252
2253 gboolean
2254 mono_arch_have_fast_tls (void)
2255 {
2256 #ifdef TARGET_MACH
2257 static gboolean have_fast_tls = FALSE;
2258 static gboolean inited = FALSE;
2259 guint32 *ins;
2260
2261 if (mini_debug_options.use_fallback_tls)
2262 return FALSE;
2263 if (inited)
2264 return have_fast_tls;
2265
2266 ins = (guint32*)pthread_getspecific;
2267 /*
2268 * We're looking for these two instructions:
2269 *
2270 * mov 0x4(%esp),%eax
2271 * mov %gs:[offset](,%eax,4),%eax
2272 */
2273 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2274 tls_gs_offset = ins [2];
2275 inited = TRUE;
2276
2277 return have_fast_tls;
2278 #elif defined(TARGET_ANDROID)
2279 return FALSE;
2280 #else
2281 if (mini_debug_options.use_fallback_tls)
2282 return FALSE;
2283 return TRUE;
2284 #endif
2285 }
2286
2287 static guint8*
2288 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2289 {
2290 #if defined (TARGET_MACH)
2291 x86_prefix (code, X86_GS_PREFIX);
2292 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2293 #elif defined (TARGET_WIN32)
2294 /*
2295 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2296 * Journal and/or a disassembly of the TlsGet () function.
2297 */
2298 x86_prefix (code, X86_FS_PREFIX);
2299 x86_mov_reg_mem (code, dreg, 0x18, 4);
2300 if (tls_offset < 64) {
2301 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2302 } else {
2303 guint8 *buf [16];
2304
2305 g_assert (tls_offset < 0x440);
2306 /* Load TEB->TlsExpansionSlots */
2307 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2308 x86_test_reg_reg (code, dreg, dreg);
2309 buf [0] = code;
2310 x86_branch (code, X86_CC_EQ, code, TRUE);
2311 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2312 x86_patch (buf [0], code);
2313 }
2314 #else
2315 if (optimize_for_xen) {
2316 x86_prefix (code, X86_GS_PREFIX);
2317 x86_mov_reg_mem (code, dreg, 0, 4);
2318 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2319 } else {
2320 x86_prefix (code, X86_GS_PREFIX);
2321 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2322 }
2323 #endif
2324 return code;
2325 }
2326
2327 static guint8*
2328 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2329 {
2330 #if defined (TARGET_MACH)
2331 x86_prefix (code, X86_GS_PREFIX);
2332 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2333 #elif defined (TARGET_WIN32)
2334 g_assert_not_reached ();
2335 #else
2336 x86_prefix (code, X86_GS_PREFIX);
2337 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2338 #endif
2339 return code;
2340 }
2341
2342 /*
2343 * emit_setup_lmf:
2344 *
2345 * Emit code to initialize an LMF structure at LMF_OFFSET.
2346 */
2347 static guint8*
2348 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2349 {
2350 /* save all caller saved regs */
2351 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (target_mgreg_t));
2352 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2353 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (target_mgreg_t));
2354 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2355 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (target_mgreg_t));
2356 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2357 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (target_mgreg_t));
2358
2359 /* save the current IP */
2360 if (cfg->compile_aot) {
2361 /* This pushes the current ip */
2362 x86_call_imm (code, 0);
2363 x86_pop_reg (code, X86_EAX);
2364 } else {
2365 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2366 x86_mov_reg_imm (code, X86_EAX, 0);
2367 }
2368 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (target_mgreg_t));
2369
2370 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2371 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2372 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2373 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2374 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2375 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2376 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2377 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2378 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2379
2380 return code;
2381 }
2382
2383 #ifdef TARGET_WIN32
2384
2385 #define TEB_LAST_ERROR_OFFSET 0x34
2386
2387 static guint8*
2388 emit_get_last_error (guint8* code, int dreg)
2389 {
2390 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
2391 x86_prefix (code, X86_FS_PREFIX);
2392 x86_mov_reg_mem (code, dreg, TEB_LAST_ERROR_OFFSET, sizeof (guint32));
2393 return code;
2394 }
2395
2396 #else
2397
2398 static guint8*
2399 emit_get_last_error (guint8* code, int dreg)
2400 {
2401 g_assert_not_reached ();
2402 }
2403
2404 #endif
2405
2406 /* benchmark and set based on cpu */
2407 #define LOOP_ALIGNMENT 8
2408 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2409
2410 #ifndef DISABLE_JIT
2411 void
2412 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2413 {
2414 MonoInst *ins;
2415 MonoCallInst *call;
2416 guint8 *code = cfg->native_code + cfg->code_len;
2417
2418 if (cfg->opt & MONO_OPT_LOOP) {
2419 int pad, align = LOOP_ALIGNMENT;
2420 /* set alignment depending on cpu */
2421 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2422 pad = align - pad;
2423 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2424 x86_padding (code, pad);
2425 cfg->code_len += pad;
2426 bb->native_offset = cfg->code_len;
2427 }
2428 }
2429
2430 if (cfg->verbose_level > 2)
2431 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2432
2433 int cpos = bb->max_offset;
2434
2435 set_code_cursor (cfg, code);
2436
2437 mono_debug_open_block (cfg, bb, code - cfg->native_code);
2438
2439 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2440 x86_breakpoint (code);
2441
2442 MONO_BB_FOR_EACH_INS (bb, ins) {
2443 const guint offset = code - cfg->native_code;
2444 set_code_cursor (cfg, code);
2445 int max_len = ins_get_size (ins->opcode);
2446 code = realloc_code (cfg, max_len);
2447
2448 if (cfg->debug_info)
2449 mono_debug_record_line_number (cfg, ins, offset);
2450
2451 switch (ins->opcode) {
2452 case OP_BIGMUL:
2453 x86_mul_reg (code, ins->sreg2, TRUE);
2454 break;
2455 case OP_BIGMUL_UN:
2456 x86_mul_reg (code, ins->sreg2, FALSE);
2457 break;
2458 case OP_X86_SETEQ_MEMBASE:
2459 case OP_X86_SETNE_MEMBASE:
2460 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2461 ins->inst_basereg, ins->inst_offset, TRUE);
2462 break;
2463 case OP_STOREI1_MEMBASE_IMM:
2464 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2465 break;
2466 case OP_STOREI2_MEMBASE_IMM:
2467 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2468 break;
2469 case OP_STORE_MEMBASE_IMM:
2470 case OP_STOREI4_MEMBASE_IMM:
2471 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2472 break;
2473 case OP_STOREI1_MEMBASE_REG:
2474 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2475 break;
2476 case OP_STOREI2_MEMBASE_REG:
2477 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2478 break;
2479 case OP_STORE_MEMBASE_REG:
2480 case OP_STOREI4_MEMBASE_REG:
2481 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2482 break;
2483 case OP_LOADU4_MEM:
2484 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2485 break;
2486 case OP_LOAD_MEM:
2487 case OP_LOADI4_MEM:
2488 /* These are created by the cprop pass so they use inst_imm as the source */
2489 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2490 break;
2491 case OP_LOADU1_MEM:
2492 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2493 break;
2494 case OP_LOADU2_MEM:
2495 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2496 break;
2497 case OP_LOAD_MEMBASE:
2498 case OP_LOADI4_MEMBASE:
2499 case OP_LOADU4_MEMBASE:
2500 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2501 break;
2502 case OP_LOADU1_MEMBASE:
2503 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2504 break;
2505 case OP_LOADI1_MEMBASE:
2506 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2507 break;
2508 case OP_LOADU2_MEMBASE:
2509 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2510 break;
2511 case OP_LOADI2_MEMBASE:
2512 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2513 break;
2514 case OP_ICONV_TO_I1:
2515 case OP_SEXT_I1:
2516 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2517 break;
2518 case OP_ICONV_TO_I2:
2519 case OP_SEXT_I2:
2520 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2521 break;
2522 case OP_ICONV_TO_U1:
2523 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2524 break;
2525 case OP_ICONV_TO_U2:
2526 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2527 break;
2528 case OP_COMPARE:
2529 case OP_ICOMPARE:
2530 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2531 break;
2532 case OP_COMPARE_IMM:
2533 case OP_ICOMPARE_IMM:
2534 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2535 break;
2536 case OP_X86_COMPARE_MEMBASE_REG:
2537 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2538 break;
2539 case OP_X86_COMPARE_MEMBASE_IMM:
2540 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2541 break;
2542 case OP_X86_COMPARE_MEMBASE8_IMM:
2543 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2544 break;
2545 case OP_X86_COMPARE_REG_MEMBASE:
2546 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2547 break;
2548 case OP_X86_COMPARE_MEM_IMM:
2549 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2550 break;
2551 case OP_X86_TEST_NULL:
2552 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2553 break;
2554 case OP_X86_ADD_MEMBASE_IMM:
2555 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2556 break;
2557 case OP_X86_ADD_REG_MEMBASE:
2558 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2559 break;
2560 case OP_X86_SUB_MEMBASE_IMM:
2561 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2562 break;
2563 case OP_X86_SUB_REG_MEMBASE:
2564 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2565 break;
2566 case OP_X86_AND_MEMBASE_IMM:
2567 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2568 break;
2569 case OP_X86_OR_MEMBASE_IMM:
2570 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2571 break;
2572 case OP_X86_XOR_MEMBASE_IMM:
2573 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2574 break;
2575 case OP_X86_ADD_MEMBASE_REG:
2576 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2577 break;
2578 case OP_X86_SUB_MEMBASE_REG:
2579 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2580 break;
2581 case OP_X86_AND_MEMBASE_REG:
2582 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2583 break;
2584 case OP_X86_OR_MEMBASE_REG:
2585 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2586 break;
2587 case OP_X86_XOR_MEMBASE_REG:
2588 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2589 break;
2590 case OP_X86_INC_MEMBASE:
2591 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2592 break;
2593 case OP_X86_INC_REG:
2594 x86_inc_reg (code, ins->dreg);
2595 break;
2596 case OP_X86_DEC_MEMBASE:
2597 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2598 break;
2599 case OP_X86_DEC_REG:
2600 x86_dec_reg (code, ins->dreg);
2601 break;
2602 case OP_X86_MUL_REG_MEMBASE:
2603 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2604 break;
2605 case OP_X86_AND_REG_MEMBASE:
2606 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2607 break;
2608 case OP_X86_OR_REG_MEMBASE:
2609 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2610 break;
2611 case OP_X86_XOR_REG_MEMBASE:
2612 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2613 break;
2614 case OP_BREAK:
2615 x86_breakpoint (code);
2616 break;
2617 case OP_RELAXED_NOP:
2618 x86_prefix (code, X86_REP_PREFIX);
2619 x86_nop (code);
2620 break;
2621 case OP_HARD_NOP:
2622 x86_nop (code);
2623 break;
2624 case OP_NOP:
2625 case OP_DUMMY_USE:
2626 case OP_DUMMY_ICONST:
2627 case OP_DUMMY_R8CONST:
2628 case OP_DUMMY_R4CONST:
2629 case OP_NOT_REACHED:
2630 case OP_NOT_NULL:
2631 break;
2632 case OP_IL_SEQ_POINT:
2633 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2634 break;
2635 case OP_SEQ_POINT: {
2636 int i;
2637
2638 if (cfg->compile_aot)
2639 NOT_IMPLEMENTED;
2640
2641 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2642
2643 /*
2644 * We do this _before_ the breakpoint, so single stepping after
2645 * a breakpoint is hit will step to the next IL offset.
2646 */
2647 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2648 MonoInst *var = cfg->arch.ss_tramp_var;
2649 guint8 *br [1];
2650
2651 g_assert (var);
2652 g_assert (var->opcode == OP_REGOFFSET);
2653 /* Load ss_tramp_var */
2654 /* This is equal to &ss_trampoline */
2655 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (target_mgreg_t));
2656 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (target_mgreg_t));
2657 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2658 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2659 x86_call_reg (code, X86_ECX);
2660 x86_patch (br [0], code);
2661 }
2662
2663 /*
2664 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2665 * This means we have to put the loading of bp_tramp_var after the offset.
2666 */
2667
2668 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2669
2670 MonoInst *var = cfg->arch.bp_tramp_var;
2671
2672 g_assert (var);
2673 g_assert (var->opcode == OP_REGOFFSET);
2674 /* Load the address of the bp trampoline */
2675 /* This needs to be constant size */
2676 guint8 *start = code;
2677 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2678 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2679 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2680 x86_padding (code, size);
2681 }
2682 /*
2683 * A placeholder for a possible breakpoint inserted by
2684 * mono_arch_set_breakpoint ().
2685 */
2686 for (i = 0; i < 2; ++i)
2687 x86_nop (code);
2688 /*
2689 * Add an additional nop so skipping the bp doesn't cause the ip to point
2690 * to another IL offset.
2691 */
2692 x86_nop (code);
2693 break;
2694 }
2695 case OP_ADDCC:
2696 case OP_IADDCC:
2697 case OP_IADD:
2698 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2699 break;
2700 case OP_ADC:
2701 case OP_IADC:
2702 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2703 break;
2704 case OP_ADDCC_IMM:
2705 case OP_ADD_IMM:
2706 case OP_IADD_IMM:
2707 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2708 break;
2709 case OP_ADC_IMM:
2710 case OP_IADC_IMM:
2711 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2712 break;
2713 case OP_SUBCC:
2714 case OP_ISUBCC:
2715 case OP_ISUB:
2716 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2717 break;
2718 case OP_SBB:
2719 case OP_ISBB:
2720 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2721 break;
2722 case OP_SUBCC_IMM:
2723 case OP_SUB_IMM:
2724 case OP_ISUB_IMM:
2725 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2726 break;
2727 case OP_SBB_IMM:
2728 case OP_ISBB_IMM:
2729 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2730 break;
2731 case OP_IAND:
2732 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2733 break;
2734 case OP_AND_IMM:
2735 case OP_IAND_IMM:
2736 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2737 break;
2738 case OP_IDIV:
2739 case OP_IREM:
2740 /*
2741 * The code is the same for div/rem, the allocator will allocate dreg
2742 * to RAX/RDX as appropriate.
2743 */
2744 if (ins->sreg2 == X86_EDX) {
2745 /* cdq clobbers this */
2746 x86_push_reg (code, ins->sreg2);
2747 x86_cdq (code);
2748 x86_div_membase (code, X86_ESP, 0, TRUE);
2749 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2750 } else {
2751 x86_cdq (code);
2752 x86_div_reg (code, ins->sreg2, TRUE);
2753 }
2754 break;
2755 case OP_IDIV_UN:
2756 case OP_IREM_UN:
2757 if (ins->sreg2 == X86_EDX) {
2758 x86_push_reg (code, ins->sreg2);
2759 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2760 x86_div_membase (code, X86_ESP, 0, FALSE);
2761 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2762 } else {
2763 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2764 x86_div_reg (code, ins->sreg2, FALSE);
2765 }
2766 break;
2767 case OP_DIV_IMM:
2768 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2769 x86_cdq (code);
2770 x86_div_reg (code, ins->sreg2, TRUE);
2771 break;
2772 case OP_IREM_IMM: {
2773 int power = mono_is_power_of_two (ins->inst_imm);
2774
2775 g_assert (ins->sreg1 == X86_EAX);
2776 g_assert (ins->dreg == X86_EAX);
2777 g_assert (power >= 0);
2778
2779 if (power == 1) {
2780 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2781 x86_cdq (code);
2782 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2783 /*
2784 * If the divident is >= 0, this does not nothing. If it is positive, it
2785 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2786 */
2787 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2788 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2789 } else if (power == 0) {
2790 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2791 } else {
2792 /* Based on gcc code */
2793
2794 /* Add compensation for negative dividents */
2795 x86_cdq (code);
2796 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2797 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2798 /* Compute remainder */
2799 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2800 /* Remove compensation */
2801 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2802 }
2803 break;
2804 }
2805 case OP_IOR:
2806 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2807 break;
2808 case OP_OR_IMM:
2809 case OP_IOR_IMM:
2810 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2811 break;
2812 case OP_IXOR:
2813 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2814 break;
2815 case OP_XOR_IMM:
2816 case OP_IXOR_IMM:
2817 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2818 break;
2819 case OP_ISHL:
2820 g_assert (ins->sreg2 == X86_ECX);
2821 x86_shift_reg (code, X86_SHL, ins->dreg);
2822 break;
2823 case OP_ISHR:
2824 g_assert (ins->sreg2 == X86_ECX);
2825 x86_shift_reg (code, X86_SAR, ins->dreg);
2826 break;
2827 case OP_SHR_IMM:
2828 case OP_ISHR_IMM:
2829 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2830 break;
2831 case OP_SHR_UN_IMM:
2832 case OP_ISHR_UN_IMM:
2833 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2834 break;
2835 case OP_ISHR_UN:
2836 g_assert (ins->sreg2 == X86_ECX);
2837 x86_shift_reg (code, X86_SHR, ins->dreg);
2838 break;
2839 case OP_SHL_IMM:
2840 case OP_ISHL_IMM:
2841 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2842 break;
2843 case OP_LSHL: {
2844 guint8 *jump_to_end;
2845
2846 /* handle shifts below 32 bits */
2847 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2848 x86_shift_reg (code, X86_SHL, ins->sreg1);
2849
2850 x86_test_reg_imm (code, X86_ECX, 32);
2851 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2852
2853 /* handle shift over 32 bit */
2854 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2855 x86_clear_reg (code, ins->sreg1);
2856
2857 x86_patch (jump_to_end, code);
2858 }
2859 break;
2860 case OP_LSHR: {
2861 guint8 *jump_to_end;
2862
2863 /* handle shifts below 32 bits */
2864 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2865 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2866
2867 x86_test_reg_imm (code, X86_ECX, 32);
2868 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2869
2870 /* handle shifts over 31 bits */
2871 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2872 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2873
2874 x86_patch (jump_to_end, code);
2875 }
2876 break;
2877 case OP_LSHR_UN: {
2878 guint8 *jump_to_end;
2879
2880 /* handle shifts below 32 bits */
2881 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2882 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2883
2884 x86_test_reg_imm (code, X86_ECX, 32);
2885 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2886
2887 /* handle shifts over 31 bits */
2888 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2889 x86_clear_reg (code, ins->backend.reg3);
2890
2891 x86_patch (jump_to_end, code);
2892 }
2893 break;
2894 case OP_LSHL_IMM:
2895 if (ins->inst_imm >= 32) {
2896 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2897 x86_clear_reg (code, ins->sreg1);
2898 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2899 } else {
2900 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2901 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2902 }
2903 break;
2904 case OP_LSHR_IMM:
2905 if (ins->inst_imm >= 32) {
2906 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2907 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2908 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2909 } else {
2910 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2911 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2912 }
2913 break;
2914 case OP_LSHR_UN_IMM:
2915 if (ins->inst_imm >= 32) {
2916 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2917 x86_clear_reg (code, ins->backend.reg3);
2918 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2919 } else {
2920 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2921 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2922 }
2923 break;
2924 case OP_INOT:
2925 x86_not_reg (code, ins->sreg1);
2926 break;
2927 case OP_INEG:
2928 x86_neg_reg (code, ins->sreg1);
2929 break;
2930
2931 case OP_IMUL:
2932 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2933 break;
2934 case OP_MUL_IMM:
2935 case OP_IMUL_IMM:
2936 switch (ins->inst_imm) {
2937 case 2:
2938 /* MOV r1, r2 */
2939 /* ADD r1, r1 */
2940 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2941 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2942 break;
2943 case 3:
2944 /* LEA r1, [r2 + r2*2] */
2945 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2946 break;
2947 case 5:
2948 /* LEA r1, [r2 + r2*4] */
2949 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2950 break;
2951 case 6:
2952 /* LEA r1, [r2 + r2*2] */
2953 /* ADD r1, r1 */
2954 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2955 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2956 break;
2957 case 9:
2958 /* LEA r1, [r2 + r2*8] */
2959 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2960 break;
2961 case 10:
2962 /* LEA r1, [r2 + r2*4] */
2963 /* ADD r1, r1 */
2964 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2965 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2966 break;
2967 case 12:
2968 /* LEA r1, [r2 + r2*2] */
2969 /* SHL r1, 2 */
2970 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2971 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2972 break;
2973 case 25:
2974 /* LEA r1, [r2 + r2*4] */
2975 /* LEA r1, [r1 + r1*4] */
2976 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2977 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2978 break;
2979 case 100:
2980 /* LEA r1, [r2 + r2*4] */
2981 /* SHL r1, 2 */
2982 /* LEA r1, [r1 + r1*4] */
2983 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2984 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2985 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2986 break;
2987 default:
2988 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2989 break;
2990 }
2991 break;
2992 case OP_IMUL_OVF:
2993 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2994 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2995 break;
2996 case OP_IMUL_OVF_UN: {
2997 /* the mul operation and the exception check should most likely be split */
2998 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2999 /*g_assert (ins->sreg2 == X86_EAX);
3000 g_assert (ins->dreg == X86_EAX);*/
3001 if (ins->sreg2 == X86_EAX) {
3002 non_eax_reg = ins->sreg1;
3003 } else if (ins->sreg1 == X86_EAX) {
3004 non_eax_reg = ins->sreg2;
3005 } else {
3006 /* no need to save since we're going to store to it anyway */
3007 if (ins->dreg != X86_EAX) {
3008 saved_eax = TRUE;
3009 x86_push_reg (code, X86_EAX);
3010 }
3011 x86_mov_reg_reg (code, X86_EAX, ins->sreg1);
3012 non_eax_reg = ins->sreg2;
3013 }
3014 if (ins->dreg == X86_EDX) {
3015 if (!saved_eax) {
3016 saved_eax = TRUE;
3017 x86_push_reg (code, X86_EAX);
3018 }
3019 } else {
3020 saved_edx = TRUE;
3021 x86_push_reg (code, X86_EDX);
3022 }
3023 x86_mul_reg (code, non_eax_reg, FALSE);
3024 /* save before the check since pop and mov don't change the flags */
3025 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
3026 if (saved_edx)
3027 x86_pop_reg (code, X86_EDX);
3028 if (saved_eax)
3029 x86_pop_reg (code, X86_EAX);
3030 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3031 break;
3032 }
3033 case OP_ICONST:
3034 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3035 break;
3036 case OP_AOTCONST:
3037 g_assert_not_reached ();
3038 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
3039 x86_mov_reg_imm (code, ins->dreg, 0);
3040 break;
3041 case OP_JUMP_TABLE:
3042 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
3043 x86_mov_reg_imm (code, ins->dreg, 0);
3044 break;
3045 case OP_LOAD_GOTADDR:
3046 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3047 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3048 break;
3049 case OP_GOT_ENTRY:
3050 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3051 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3052 break;
3053 case OP_X86_PUSH_GOT_ENTRY:
3054 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3055 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3056 break;
3057 case OP_MOVE:
3058 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
3059 break;
3060
3061 case OP_TAILCALL_PARAMETER:
3062 // This opcode helps compute sizes, i.e.
3063 // of the subsequent OP_TAILCALL, but contributes no code.
3064 g_assert (ins->next);
3065 break;
3066
3067 case OP_TAILCALL:
3068 case OP_TAILCALL_MEMBASE:
3069 case OP_TAILCALL_REG: {
3070 call = (MonoCallInst*)ins;
3071 int pos = 0, i;
3072 gboolean const tailcall_membase = ins->opcode == OP_TAILCALL_MEMBASE;
3073 gboolean const tailcall_reg = (ins->opcode == OP_TAILCALL_REG);
3074 int const sreg1 = ins->sreg1;
3075 gboolean const sreg1_ecx = sreg1 == X86_ECX;
3076 gboolean const tailcall_membase_ecx = tailcall_membase && sreg1_ecx;
3077 gboolean const tailcall_membase_not_ecx = tailcall_membase && !sreg1_ecx;
3078
3079 max_len += (call->stack_usage - call->stack_align_amount) / sizeof (target_mgreg_t) * ins_get_size (OP_TAILCALL_PARAMETER);
3080 code = realloc_code (cfg, max_len);
3081
3082 ins->flags |= MONO_INST_GC_CALLSITE;
3083 ins->backend.pc_offset = code - cfg->native_code;
3084
3085 g_assert (!cfg->method->save_lmf);
3086
3087 // Ecx is volatile, not used for parameters, or rgctx/imt (edx).
3088 // It is also not used for return value, though that does not matter.
3089 // Ecx is preserved across the tailcall formation.
3090 //
3091 // Eax could also be used here at the cost of a push/pop moving the parameters.
3092 // Edx must be preserved as it is rgctx/imt.
3093 //
3094 // If ecx happens to be the base of the tailcall_membase, then
3095 // just end with jmp [ecx+offset] -- one instruction.
3096 // if ecx is not the base, then move ecx, [reg+offset] and later jmp [ecx] -- two instructions.
3097
3098 if (tailcall_reg) {
3099 g_assert (sreg1 > -1);
3100 x86_mov_reg_reg (code, X86_ECX, sreg1);
3101 } else if (tailcall_membase_not_ecx) {
3102 g_assert (sreg1 > -1);
3103 x86_mov_reg_membase (code, X86_ECX, sreg1, ins->inst_offset, 4);
3104 }
3105
3106 /* restore callee saved registers */
3107 for (i = 0; i < X86_NREG; ++i)
3108 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3109 pos -= 4;
3110 if (cfg->used_int_regs & (1 << X86_ESI)) {
3111 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3112 pos += 4;
3113 }
3114 if (cfg->used_int_regs & (1 << X86_EDI)) {
3115 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3116 pos += 4;
3117 }
3118 if (cfg->used_int_regs & (1 << X86_EBX)) {
3119 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3120 pos += 4;
3121 }
3122
3123 /* Copy arguments on the stack to our argument area */
3124 // FIXME use rep mov for constant code size, before nonvolatiles
3125 // restored, first saving esi, edi into volatiles
3126 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3127 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3128 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3129 }
3130
3131 /* restore ESP/EBP */
3132 x86_leave (code);
3133
3134 if (tailcall_membase_ecx) {
3135 x86_jump_membase (code, X86_ECX, ins->inst_offset);
3136 } else if (tailcall_reg || tailcall_membase_not_ecx) {
3137 x86_jump_reg (code, X86_ECX);
3138 } else {
3139 // FIXME Patch data instead of code.
3140 code = x86_align_and_patch (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3141 x86_jump32 (code, 0);
3142 }
3143
3144 ins->flags |= MONO_INST_GC_CALLSITE;
3145 break;
3146 }
3147 case OP_CHECK_THIS:
3148 /* ensure ins->sreg1 is not NULL
3149 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3150 * cmp DWORD PTR [eax], 0
3151 */
3152 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3153 break;
3154 case OP_ARGLIST: {
3155 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3156 x86_push_reg (code, hreg);
3157 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3158 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3159 x86_pop_reg (code, hreg);
3160 break;
3161 }
3162 case OP_FCALL:
3163 case OP_LCALL:
3164 case OP_VCALL:
3165 case OP_VCALL2:
3166 case OP_VOIDCALL:
3167 case OP_CALL:
3168 case OP_FCALL_REG:
3169 case OP_LCALL_REG:
3170 case OP_VCALL_REG:
3171 case OP_VCALL2_REG:
3172 case OP_VOIDCALL_REG:
3173 case OP_CALL_REG:
3174 case OP_FCALL_MEMBASE:
3175 case OP_LCALL_MEMBASE:
3176 case OP_VCALL_MEMBASE:
3177 case OP_VCALL2_MEMBASE:
3178 case OP_VOIDCALL_MEMBASE:
3179 case OP_CALL_MEMBASE: {
3180 CallInfo *cinfo;
3181
3182 call = (MonoCallInst*)ins;
3183 cinfo = call->call_info;
3184
3185 switch (ins->opcode) {
3186 case OP_FCALL:
3187 case OP_LCALL:
3188 case OP_VCALL:
3189 case OP_VCALL2:
3190 case OP_VOIDCALL:
3191 case OP_CALL: {
3192 const MonoJumpInfoTarget patch = mono_call_to_patch (call);
3193 code = emit_call (cfg, code, patch.type, patch.target);
3194 break;
3195 }
3196 case OP_FCALL_REG:
3197 case OP_LCALL_REG:
3198 case OP_VCALL_REG:
3199 case OP_VCALL2_REG:
3200 case OP_VOIDCALL_REG:
3201 case OP_CALL_REG:
3202 x86_call_reg (code, ins->sreg1);
3203 break;
3204 case OP_FCALL_MEMBASE:
3205 case OP_LCALL_MEMBASE:
3206 case OP_VCALL_MEMBASE:
3207 case OP_VCALL2_MEMBASE:
3208 case OP_VOIDCALL_MEMBASE:
3209 case OP_CALL_MEMBASE:
3210 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3211 break;
3212 default:
3213 g_assert_not_reached ();
3214 break;
3215 }
3216 ins->flags |= MONO_INST_GC_CALLSITE;
3217 ins->backend.pc_offset = code - cfg->native_code;
3218 if (cinfo->callee_stack_pop) {
3219 /* Have to compensate for the stack space popped by the callee */
3220 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3221 }
3222 code = emit_move_return_value (cfg, ins, code);
3223 break;
3224 }
3225 case OP_X86_LEA:
3226 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3227 break;
3228 case OP_X86_LEA_MEMBASE:
3229 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3230 break;
3231 case OP_X86_XCHG:
3232 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3233 break;
3234 case OP_LOCALLOC:
3235 /* keep alignment */
3236 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3237 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3238 code = mono_emit_stack_alloc (cfg, code, ins);
3239 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3240 if (cfg->param_area)
3241 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3242 break;
3243 case OP_LOCALLOC_IMM: {
3244 guint32 size = ins->inst_imm;
3245 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3246
3247 if (ins->flags & MONO_INST_INIT) {
3248 /* FIXME: Optimize this */
3249 x86_mov_reg_imm (code, ins->dreg, size);
3250 ins->sreg1 = ins->dreg;
3251
3252 code = mono_emit_stack_alloc (cfg, code, ins);
3253 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3254 } else {
3255 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3256 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3257 }
3258 if (cfg->param_area)
3259 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3260 break;
3261 }
3262 case OP_THROW: {
3263 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3264 x86_push_reg (code, ins->sreg1);
3265 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3266 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_throw_exception));
3267 ins->flags |= MONO_INST_GC_CALLSITE;
3268 ins->backend.pc_offset = code - cfg->native_code;
3269 break;
3270 }
3271 case OP_RETHROW: {
3272 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3273 x86_push_reg (code, ins->sreg1);
3274 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3275 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_rethrow_exception));
3276 ins->flags |= MONO_INST_GC_CALLSITE;
3277 ins->backend.pc_offset = code - cfg->native_code;
3278 break;
3279 }
3280 case OP_CALL_HANDLER:
3281 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3282 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3283 x86_call_imm (code, 0);
3284 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
3285 mono_cfg_add_try_hole (cfg, ((MonoLeaveClause *) tmp->data)->clause, code, bb);
3286 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3287 break;
3288 case OP_START_HANDLER: {
3289 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3290 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3291 if (cfg->param_area)
3292 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3293 break;
3294 }
3295 case OP_ENDFINALLY: {
3296 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3297 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3298 x86_ret (code);
3299 break;
3300 }
3301 case OP_ENDFILTER: {
3302 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3303 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3304 /* The local allocator will put the result into EAX */
3305 x86_ret (code);
3306 break;
3307 }
3308 case OP_GET_EX_OBJ:
3309 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
3310 break;
3311
3312 case OP_LABEL:
3313 ins->inst_c0 = code - cfg->native_code;
3314 break;
3315 case OP_BR:
3316 if (ins->inst_target_bb->native_offset) {
3317 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3318 } else {
3319 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3320 if ((cfg->opt & MONO_OPT_BRANCH) &&
3321 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3322 x86_jump8 (code, 0);
3323 else
3324 x86_jump32 (code, 0);
3325 }
3326 break;
3327 case OP_BR_REG:
3328 x86_jump_reg (code, ins->sreg1);
3329 break;
3330 case OP_ICNEQ:
3331 case OP_ICGE:
3332 case OP_ICLE:
3333 case OP_ICGE_UN:
3334 case OP_ICLE_UN:
3335
3336 case OP_CEQ:
3337 case OP_CLT:
3338 case OP_CLT_UN:
3339 case OP_CGT:
3340 case OP_CGT_UN:
3341 case OP_CNE:
3342 case OP_ICEQ:
3343 case OP_ICLT:
3344 case OP_ICLT_UN:
3345 case OP_ICGT:
3346 case OP_ICGT_UN:
3347 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3348 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3349 break;
3350 case OP_COND_EXC_EQ:
3351 case OP_COND_EXC_NE_UN:
3352 case OP_COND_EXC_LT:
3353 case OP_COND_EXC_LT_UN:
3354 case OP_COND_EXC_GT:
3355 case OP_COND_EXC_GT_UN:
3356 case OP_COND_EXC_GE:
3357 case OP_COND_EXC_GE_UN:
3358 case OP_COND_EXC_LE:
3359 case OP_COND_EXC_LE_UN:
3360 case OP_COND_EXC_IEQ:
3361 case OP_COND_EXC_INE_UN:
3362 case OP_COND_EXC_ILT:
3363 case OP_COND_EXC_ILT_UN:
3364 case OP_COND_EXC_IGT:
3365 case OP_COND_EXC_IGT_UN:
3366 case OP_COND_EXC_IGE:
3367 case OP_COND_EXC_IGE_UN:
3368 case OP_COND_EXC_ILE:
3369 case OP_COND_EXC_ILE_UN:
3370 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char*)ins->inst_p1);
3371 break;
3372 case OP_COND_EXC_OV:
3373 case OP_COND_EXC_NO:
3374 case OP_COND_EXC_C:
3375 case OP_COND_EXC_NC:
3376 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), (const char*)ins->inst_p1);
3377 break;
3378 case OP_COND_EXC_IOV:
3379 case OP_COND_EXC_INO:
3380 case OP_COND_EXC_IC:
3381 case OP_COND_EXC_INC:
3382 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), (const char*)ins->inst_p1);
3383 break;
3384 case OP_IBEQ:
3385 case OP_IBNE_UN:
3386 case OP_IBLT:
3387 case OP_IBLT_UN:
3388 case OP_IBGT:
3389 case OP_IBGT_UN:
3390 case OP_IBGE:
3391 case OP_IBGE_UN:
3392 case OP_IBLE:
3393 case OP_IBLE_UN:
3394 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3395 break;
3396
3397 case OP_CMOV_IEQ:
3398 case OP_CMOV_IGE:
3399 case OP_CMOV_IGT:
3400 case OP_CMOV_ILE:
3401 case OP_CMOV_ILT:
3402 case OP_CMOV_INE_UN:
3403 case OP_CMOV_IGE_UN:
3404 case OP_CMOV_IGT_UN:
3405 case OP_CMOV_ILE_UN:
3406 case OP_CMOV_ILT_UN:
3407 g_assert (ins->dreg == ins->sreg1);
3408 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3409 break;
3410
3411 /* floating point opcodes */
3412 case OP_R8CONST: {
3413 double d = *(double *)ins->inst_p0;
3414
3415 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3416 x86_fldz (code);
3417 } else if (d == 1.0) {
3418 x86_fld1 (code);
3419 } else {
3420 if (cfg->compile_aot) {
3421 guint32 *val = (guint32*)&d;
3422 x86_push_imm (code, val [1]);
3423 x86_push_imm (code, val [0]);
3424 x86_fld_membase (code, X86_ESP, 0, TRUE);
3425 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3426 }
3427 else {
3428 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3429 x86_fld (code, NULL, TRUE);
3430 }
3431 }
3432 break;
3433 }
3434 case OP_R4CONST: {
3435 float f = *(float *)ins->inst_p0;
3436
3437 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3438 x86_fldz (code);
3439 } else if (f == 1.0) {
3440 x86_fld1 (code);
3441 } else {
3442 if (cfg->compile_aot) {
3443 guint32 val = *(guint32*)&f;
3444 x86_push_imm (code, val);
3445 x86_fld_membase (code, X86_ESP, 0, FALSE);
3446 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3447 }
3448 else {
3449 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3450 x86_fld (code, NULL, FALSE);
3451 }
3452 }
3453 break;
3454 }
3455 case OP_STORER8_MEMBASE_REG:
3456 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3457 break;
3458 case OP_LOADR8_MEMBASE:
3459 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3460 break;
3461 case OP_STORER4_MEMBASE_REG:
3462 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3463 break;
3464 case OP_LOADR4_MEMBASE:
3465 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3466 break;
3467 case OP_ICONV_TO_R4:
3468 x86_push_reg (code, ins->sreg1);
3469 x86_fild_membase (code, X86_ESP, 0, FALSE);
3470 /* Change precision */
3471 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3472 x86_fld_membase (code, X86_ESP, 0, FALSE);
3473 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3474 break;
3475 case OP_ICONV_TO_R8:
3476 x86_push_reg (code, ins->sreg1);
3477 x86_fild_membase (code, X86_ESP, 0, FALSE);
3478 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3479 break;
3480 case OP_ICONV_TO_R_UN:
3481 x86_push_imm (code, 0);
3482 x86_push_reg (code, ins->sreg1);
3483 x86_fild_membase (code, X86_ESP, 0, TRUE);
3484 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3485 break;
3486 case OP_X86_FP_LOAD_I8:
3487 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3488 break;
3489 case OP_X86_FP_LOAD_I4:
3490 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3491 break;
3492 case OP_FCONV_TO_R4:
3493 /* Change precision */
3494 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3495 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3496 x86_fld_membase (code, X86_ESP, 0, FALSE);
3497 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3498 break;
3499 case OP_FCONV_TO_I1:
3500 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3501 break;
3502 case OP_FCONV_TO_U1:
3503 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3504 break;
3505 case OP_FCONV_TO_I2:
3506 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3507 break;
3508 case OP_FCONV_TO_U2:
3509 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3510 break;
3511 case OP_FCONV_TO_I4:
3512 case OP_FCONV_TO_I:
3513 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3514 break;
3515 case OP_FCONV_TO_I8:
3516 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3517 x86_fnstcw_membase(code, X86_ESP, 0);
3518 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3519 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3520 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3521 x86_fldcw_membase (code, X86_ESP, 2);
3522 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3523 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3524 x86_pop_reg (code, ins->dreg);
3525 x86_pop_reg (code, ins->backend.reg3);
3526 x86_fldcw_membase (code, X86_ESP, 0);
3527 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3528 break;
3529 case OP_LCONV_TO_R8_2:
3530 x86_push_reg (code, ins->sreg2);
3531 x86_push_reg (code, ins->sreg1);
3532 x86_fild_membase (code, X86_ESP, 0, TRUE);
3533 /* Change precision */
3534 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3535 x86_fld_membase (code, X86_ESP, 0, TRUE);
3536 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3537 break;
3538 case OP_LCONV_TO_R4_2:
3539 x86_push_reg (code, ins->sreg2);
3540 x86_push_reg (code, ins->sreg1);
3541 x86_fild_membase (code, X86_ESP, 0, TRUE);
3542 /* Change precision */
3543 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3544 x86_fld_membase (code, X86_ESP, 0, FALSE);
3545 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3546 break;
3547 case OP_LCONV_TO_R_UN_2: {
3548 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3549 guint8 *br;
3550
3551 /* load 64bit integer to FP stack */
3552 x86_push_reg (code, ins->sreg2);
3553 x86_push_reg (code, ins->sreg1);
3554 x86_fild_membase (code, X86_ESP, 0, TRUE);
3555
3556 /* test if lreg is negative */
3557 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3558 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3559
3560 /* add correction constant mn */
3561 if (cfg->compile_aot) {
3562 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3563 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3564 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3565 x86_fld80_membase (code, X86_ESP, 2);
3566 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3567 } else {
3568 x86_fld80_mem (code, (gsize)&mn);
3569 }
3570 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3571
3572 x86_patch (br, code);
3573
3574 /* Change precision */
3575 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3576 x86_fld_membase (code, X86_ESP, 0, TRUE);
3577
3578 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3579
3580 break;
3581 }
3582 case OP_LCONV_TO_OVF_I:
3583 case OP_LCONV_TO_OVF_I4_2: {
3584 guint8 *br [3], *label [1];
3585 MonoInst *tins;
3586
3587 /*
3588 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3589 */
3590 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3591
3592 /* If the low word top bit is set, see if we are negative */
3593 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3594 /* We are not negative (no top bit set, check for our top word to be zero */
3595 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3596 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3597 label [0] = code;
3598
3599 /* throw exception */
3600 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3601 if (tins) {
3602 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3603 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3604 x86_jump8 (code, 0);
3605 else
3606 x86_jump32 (code, 0);
3607 } else {
3608 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3609 x86_jump32 (code, 0);
3610 }
3611
3612
3613 x86_patch (br [0], code);
3614 /* our top bit is set, check that top word is 0xfffffff */
3615 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3616
3617 x86_patch (br [1], code);
3618 /* nope, emit exception */
3619 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3620 x86_patch (br [2], label [0]);
3621
3622 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
3623 break;
3624 }
3625 case OP_FMOVE:
3626 /* Not needed on the fp stack */
3627 break;
3628 case OP_MOVE_F_TO_I4:
3629 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3630 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3631 break;
3632 case OP_MOVE_I4_TO_F:
3633 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3634 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3635 break;
3636 case OP_FADD:
3637 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3638 break;
3639 case OP_FSUB:
3640 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3641 break;
3642 case OP_FMUL:
3643 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3644 break;
3645 case OP_FDIV:
3646 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3647 break;
3648 case OP_FNEG:
3649 x86_fchs (code);
3650 break;
3651 case OP_ABS:
3652 x86_fabs (code);
3653 break;
3654 case OP_TAN: {
3655 /*
3656 * it really doesn't make sense to inline all this code,
3657 * it's here just to show that things may not be as simple
3658 * as they appear.
3659 */
3660 guchar *check_pos, *end_tan, *pop_jump;
3661 x86_push_reg (code, X86_EAX);
3662 x86_fptan (code);
3663 x86_fnstsw (code);
3664 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3665 check_pos = code;
3666 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3667 x86_fstp (code, 0); /* pop the 1.0 */
3668 end_tan = code;
3669 x86_jump8 (code, 0);
3670 x86_fldpi (code);
3671 x86_fp_op (code, X86_FADD, 0);
3672 x86_fxch (code, 1);
3673 x86_fprem1 (code);
3674 x86_fstsw (code);
3675 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3676 pop_jump = code;
3677 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3678 x86_fstp (code, 1);
3679 x86_fptan (code);
3680 x86_patch (pop_jump, code);
3681 x86_fstp (code, 0); /* pop the 1.0 */
3682 x86_patch (check_pos, code);
3683 x86_patch (end_tan, code);
3684 x86_fldz (code);
3685 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3686 x86_pop_reg (code, X86_EAX);
3687 break;
3688 }
3689 case OP_ATAN:
3690 x86_fld1 (code);
3691 x86_fpatan (code);
3692 x86_fldz (code);
3693 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3694 break;
3695 case OP_SQRT:
3696 x86_fsqrt (code);
3697 break;
3698 case OP_ROUND:
3699 x86_frndint (code);
3700 break;
3701 case OP_IMIN:
3702 g_assert (cfg->opt & MONO_OPT_CMOV);
3703 g_assert (ins->dreg == ins->sreg1);
3704 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3705 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3706 break;
3707 case OP_IMIN_UN:
3708 g_assert (cfg->opt & MONO_OPT_CMOV);
3709 g_assert (ins->dreg == ins->sreg1);
3710 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3711 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3712 break;
3713 case OP_IMAX:
3714 g_assert (cfg->opt & MONO_OPT_CMOV);
3715 g_assert (ins->dreg == ins->sreg1);
3716 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3717 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3718 break;
3719 case OP_IMAX_UN:
3720 g_assert (cfg->opt & MONO_OPT_CMOV);
3721 g_assert (ins->dreg == ins->sreg1);
3722 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3723 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3724 break;
3725 case OP_X86_FPOP:
3726 x86_fstp (code, 0);
3727 break;
3728 case OP_X86_FXCH:
3729 x86_fxch (code, ins->inst_imm);
3730 break;
3731 case OP_FREM: {
3732 guint8 *l1, *l2;
3733
3734 x86_push_reg (code, X86_EAX);
3735 /* we need to exchange ST(0) with ST(1) */
3736 x86_fxch (code, 1);
3737
3738 /* this requires a loop, because fprem somtimes
3739 * returns a partial remainder */
3740 l1 = code;
3741 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3742 /* x86_fprem1 (code); */
3743 x86_fprem (code);
3744 x86_fnstsw (code);
3745 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3746 l2 = code;
3747 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3748 x86_patch (l2, l1);
3749
3750 /* pop result */
3751 x86_fstp (code, 1);
3752
3753 x86_pop_reg (code, X86_EAX);
3754 break;
3755 }
3756 case OP_FCOMPARE:
3757 if (cfg->opt & MONO_OPT_FCMOV) {
3758 x86_fcomip (code, 1);
3759 x86_fstp (code, 0);
3760 break;
3761 }
3762 /* this overwrites EAX */
3763 EMIT_FPCOMPARE(code);
3764 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3765 break;
3766 case OP_FCEQ:
3767 case OP_FCNEQ:
3768 if (cfg->opt & MONO_OPT_FCMOV) {
3769 /* zeroing the register at the start results in
3770 * shorter and faster code (we can also remove the widening op)
3771 */
3772 guchar *unordered_check;
3773 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3774 x86_fcomip (code, 1);
3775 x86_fstp (code, 0);
3776 unordered_check = code;
3777 x86_branch8 (code, X86_CC_P, 0, FALSE);
3778 if (ins->opcode == OP_FCEQ) {
3779 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3780 x86_patch (unordered_check, code);
3781 } else {
3782 guchar *jump_to_end;
3783 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3784 jump_to_end = code;
3785 x86_jump8 (code, 0);
3786 x86_patch (unordered_check, code);
3787 x86_inc_reg (code, ins->dreg);
3788 x86_patch (jump_to_end, code);
3789 }
3790
3791 break;
3792 }
3793 if (ins->dreg != X86_EAX)
3794 x86_push_reg (code, X86_EAX);
3795
3796 EMIT_FPCOMPARE(code);
3797 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3798 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3799 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3800 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3801
3802 if (ins->dreg != X86_EAX)
3803 x86_pop_reg (code, X86_EAX);
3804 break;
3805 case OP_FCLT:
3806 case OP_FCLT_UN:
3807 if (cfg->opt & MONO_OPT_FCMOV) {
3808 /* zeroing the register at the start results in
3809 * shorter and faster code (we can also remove the widening op)
3810 */
3811 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3812 x86_fcomip (code, 1);
3813 x86_fstp (code, 0);
3814 if (ins->opcode == OP_FCLT_UN) {
3815 guchar *unordered_check = code;
3816 guchar *jump_to_end;
3817 x86_branch8 (code, X86_CC_P, 0, FALSE);
3818 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3819 jump_to_end = code;
3820 x86_jump8 (code, 0);
3821 x86_patch (unordered_check, code);
3822 x86_inc_reg (code, ins->dreg);
3823 x86_patch (jump_to_end, code);
3824 } else {
3825 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3826 }
3827 break;
3828 }
3829 if (ins->dreg != X86_EAX)
3830 x86_push_reg (code, X86_EAX);
3831
3832 EMIT_FPCOMPARE(code);
3833 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3834 if (ins->opcode == OP_FCLT_UN) {
3835 guchar *is_not_zero_check, *end_jump;
3836 is_not_zero_check = code;
3837 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3838 end_jump = code;
3839 x86_jump8 (code, 0);
3840 x86_patch (is_not_zero_check, code);
3841 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3842
3843 x86_patch (end_jump, code);
3844 }
3845 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3846 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3847
3848 if (ins->dreg != X86_EAX)
3849 x86_pop_reg (code, X86_EAX);
3850 break;
3851 case OP_FCLE: {
3852 guchar *unordered_check;
3853 guchar *jump_to_end;
3854 if (cfg->opt & MONO_OPT_FCMOV) {
3855 /* zeroing the register at the start results in
3856 * shorter and faster code (we can also remove the widening op)
3857 */
3858 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3859 x86_fcomip (code, 1);
3860 x86_fstp (code, 0);
3861 unordered_check = code;
3862 x86_branch8 (code, X86_CC_P, 0, FALSE);
3863 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3864 x86_patch (unordered_check, code);
3865 break;
3866 }
3867 if (ins->dreg != X86_EAX)
3868 x86_push_reg (code, X86_EAX);
3869
3870 EMIT_FPCOMPARE(code);
3871 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3872 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3873 unordered_check = code;
3874 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3875
3876 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3877 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3878 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3879 jump_to_end = code;
3880 x86_jump8 (code, 0);
3881 x86_patch (unordered_check, code);
3882 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3883 x86_patch (jump_to_end, code);
3884
3885 if (ins->dreg != X86_EAX)
3886 x86_pop_reg (code, X86_EAX);
3887 break;
3888 }
3889 case OP_FCGT:
3890 case OP_FCGT_UN:
3891 if (cfg->opt & MONO_OPT_FCMOV) {
3892 /* zeroing the register at the start results in
3893 * shorter and faster code (we can also remove the widening op)
3894 */
3895 guchar *unordered_check;
3896 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3897 x86_fcomip (code, 1);
3898 x86_fstp (code, 0);
3899 if (ins->opcode == OP_FCGT) {
3900 unordered_check = code;
3901 x86_branch8 (code, X86_CC_P, 0, FALSE);
3902 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3903 x86_patch (unordered_check, code);
3904 } else {
3905 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3906 }
3907 break;
3908 }
3909 if (ins->dreg != X86_EAX)
3910 x86_push_reg (code, X86_EAX);
3911
3912 EMIT_FPCOMPARE(code);
3913 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3914 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3915 if (ins->opcode == OP_FCGT_UN) {
3916 guchar *is_not_zero_check, *end_jump;
3917 is_not_zero_check = code;
3918 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3919 end_jump = code;
3920 x86_jump8 (code, 0);
3921 x86_patch (is_not_zero_check, code);
3922 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3923
3924 x86_patch (end_jump, code);
3925 }
3926 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3927 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3928
3929 if (ins->dreg != X86_EAX)
3930 x86_pop_reg (code, X86_EAX);
3931 break;
3932 case OP_FCGE: {
3933 guchar *unordered_check;
3934 guchar *jump_to_end;
3935 if (cfg->opt & MONO_OPT_FCMOV) {
3936 /* zeroing the register at the start results in
3937 * shorter and faster code (we can also remove the widening op)
3938 */
3939 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3940 x86_fcomip (code, 1);
3941 x86_fstp (code, 0);
3942 unordered_check = code;
3943 x86_branch8 (code, X86_CC_P, 0, FALSE);
3944 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3945 x86_patch (unordered_check, code);
3946 break;
3947 }
3948 if (ins->dreg != X86_EAX)
3949 x86_push_reg (code, X86_EAX);
3950
3951 EMIT_FPCOMPARE(code);
3952 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3953 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3954 unordered_check = code;
3955 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3956
3957 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3958 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3959 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3960 jump_to_end = code;
3961 x86_jump8 (code, 0);
3962 x86_patch (unordered_check, code);
3963 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3964 x86_patch (jump_to_end, code);
3965
3966 if (ins->dreg != X86_EAX)
3967 x86_pop_reg (code, X86_EAX);
3968 break;
3969 }
3970 case OP_FBEQ:
3971 if (cfg->opt & MONO_OPT_FCMOV) {
3972 guchar *jump = code;
3973 x86_branch8 (code, X86_CC_P, 0, TRUE);
3974 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3975 x86_patch (jump, code);
3976 break;
3977 }
3978 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3979 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3980 break;
3981 case OP_FBNE_UN:
3982 /* Branch if C013 != 100 */
3983 if (cfg->opt & MONO_OPT_FCMOV) {
3984 /* branch if !ZF or (PF|CF) */
3985 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3986 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3987 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3988 break;
3989 }
3990 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3991 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3992 break;
3993 case OP_FBLT:
3994 if (cfg->opt & MONO_OPT_FCMOV) {
3995 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3996 break;
3997 }
3998 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3999 break;
4000 case OP_FBLT_UN:
4001 if (cfg->opt & MONO_OPT_FCMOV) {
4002 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4003 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4004 break;
4005 }
4006 if (ins->opcode == OP_FBLT_UN) {
4007 guchar *is_not_zero_check, *end_jump;
4008 is_not_zero_check = code;
4009 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4010 end_jump = code;
4011 x86_jump8 (code, 0);
4012 x86_patch (is_not_zero_check, code);
4013 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4014
4015 x86_patch (end_jump, code);
4016 }
4017 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4018 break;
4019 case OP_FBGT:
4020 case OP_FBGT_UN:
4021 if (cfg->opt & MONO_OPT_FCMOV) {
4022 if (ins->opcode == OP_FBGT) {
4023 guchar *br1;
4024
4025 /* skip branch if C1=1 */
4026 br1 = code;
4027 x86_branch8 (code, X86_CC_P, 0, FALSE);
4028 /* branch if (C0 | C3) = 1 */
4029 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4030 x86_patch (br1, code);
4031 } else {
4032 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4033 }
4034 break;
4035 }
4036 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4037 if (ins->opcode == OP_FBGT_UN) {
4038 guchar *is_not_zero_check, *end_jump;
4039 is_not_zero_check = code;
4040 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4041 end_jump = code;
4042 x86_jump8 (code, 0);
4043 x86_patch (is_not_zero_check, code);
4044 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4045
4046 x86_patch (end_jump, code);
4047 }
4048 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4049 break;
4050 case OP_FBGE:
4051 /* Branch if C013 == 100 or 001 */
4052 if (cfg->opt & MONO_OPT_FCMOV) {
4053 guchar *br1;
4054
4055 /* skip branch if C1=1 */
4056 br1 = code;
4057 x86_branch8 (code, X86_CC_P, 0, FALSE);
4058 /* branch if (C0 | C3) = 1 */
4059 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4060 x86_patch (br1, code);
4061 break;
4062 }
4063 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4064 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4065 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4066 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4067 break;
4068 case OP_FBGE_UN:
4069 /* Branch if C013 == 000 */
4070 if (cfg->opt & MONO_OPT_FCMOV) {
4071 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4072 break;
4073 }
4074 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4075 break;
4076 case OP_FBLE:
4077 /* Branch if C013=000 or 100 */
4078 if (cfg->opt & MONO_OPT_FCMOV) {
4079 guchar *br1;
4080
4081 /* skip branch if C1=1 */
4082 br1 = code;
4083 x86_branch8 (code, X86_CC_P, 0, FALSE);
4084 /* branch if C0=0 */
4085 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4086 x86_patch (br1, code);
4087 break;
4088 }
4089 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4090 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4091 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4092 break;
4093 case OP_FBLE_UN:
4094 /* Branch if C013 != 001 */
4095 if (cfg->opt & MONO_OPT_FCMOV) {
4096 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4097 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4098 break;
4099 }
4100 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4101 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4102 break;
4103 case OP_CKFINITE: {
4104 guchar *br1;
4105 x86_push_reg (code, X86_EAX);
4106 x86_fxam (code);
4107 x86_fnstsw (code);
4108 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4109 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4110 x86_pop_reg (code, X86_EAX);
4111
4112 /* Have to clean up the fp stack before throwing the exception */
4113 br1 = code;
4114 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4115
4116 x86_fstp (code, 0);
4117 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4118
4119 x86_patch (br1, code);
4120 break;
4121 }
4122 case OP_TLS_GET: {
4123 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4124 break;
4125 }
4126 case OP_TLS_SET: {
4127 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4128 break;
4129 }
4130 case OP_MEMORY_BARRIER: {
4131 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4132 x86_prefix (code, X86_LOCK_PREFIX);
4133 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4134 }
4135 break;
4136 }
4137 case OP_ATOMIC_ADD_I4: {
4138 int dreg = ins->dreg;
4139
4140 g_assert (cfg->has_atomic_add_i4);
4141
4142 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4143 if (ins->sreg2 == dreg) {
4144 if (dreg == X86_EBX) {
4145 dreg = X86_EDI;
4146 if (ins->inst_basereg == X86_EDI)
4147 dreg = X86_ESI;
4148 } else {
4149 dreg = X86_EBX;
4150 if (ins->inst_basereg == X86_EBX)
4151 dreg = X86_EDI;
4152 }
4153 } else if (ins->inst_basereg == dreg) {
4154 if (dreg == X86_EBX) {
4155 dreg = X86_EDI;
4156 if (ins->sreg2 == X86_EDI)
4157 dreg = X86_ESI;
4158 } else {
4159 dreg = X86_EBX;
4160 if (ins->sreg2 == X86_EBX)
4161 dreg = X86_EDI;
4162 }
4163 }
4164
4165 if (dreg != ins->dreg) {
4166 x86_push_reg (code, dreg);
4167 }
4168
4169 x86_mov_reg_reg (code, dreg, ins->sreg2);
4170 x86_prefix (code, X86_LOCK_PREFIX);
4171 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4172 /* dreg contains the old value, add with sreg2 value */
4173 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4174
4175 if (ins->dreg != dreg) {
4176 x86_mov_reg_reg (code, ins->dreg, dreg);
4177 x86_pop_reg (code, dreg);
4178 }
4179
4180 break;
4181 }
4182 case OP_ATOMIC_EXCHANGE_I4: {
4183 guchar *br[2];
4184 int sreg2 = ins->sreg2;
4185 int breg = ins->inst_basereg;
4186
4187 g_assert (cfg->has_atomic_exchange_i4);
4188
4189 /* cmpxchg uses eax as comperand, need to make sure we can use it
4190 * hack to overcome limits in x86 reg allocator
4191 * (req: dreg == eax and sreg2 != eax and breg != eax)
4192 */
4193 g_assert (ins->dreg == X86_EAX);
4194
4195 /* We need the EAX reg for the cmpxchg */
4196 if (ins->sreg2 == X86_EAX) {
4197 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4198 x86_push_reg (code, sreg2);
4199 x86_mov_reg_reg (code, sreg2, X86_EAX);
4200 }
4201
4202 if (breg == X86_EAX) {
4203 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4204 x86_push_reg (code, breg);
4205 x86_mov_reg_reg (code, breg, X86_EAX);
4206 }
4207
4208 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4209
4210 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4211 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4212 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4213 x86_patch (br [1], br [0]);
4214
4215 if (breg != ins->inst_basereg)
4216 x86_pop_reg (code, breg);
4217
4218 if (ins->sreg2 != sreg2)
4219 x86_pop_reg (code, sreg2);
4220
4221 break;
4222 }
4223 case OP_ATOMIC_CAS_I4: {
4224 g_assert (ins->dreg == X86_EAX);
4225 g_assert (ins->sreg3 == X86_EAX);
4226 g_assert (ins->sreg1 != X86_EAX);
4227 g_assert (ins->sreg1 != ins->sreg2);
4228
4229 x86_prefix (code, X86_LOCK_PREFIX);
4230 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4231 break;
4232 }
4233 case OP_ATOMIC_LOAD_I1: {
4234 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4235 break;
4236 }
4237 case OP_ATOMIC_LOAD_U1: {
4238 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4239 break;
4240 }
4241 case OP_ATOMIC_LOAD_I2: {
4242 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4243 break;
4244 }
4245 case OP_ATOMIC_LOAD_U2: {
4246 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4247 break;
4248 }
4249 case OP_ATOMIC_LOAD_I4:
4250 case OP_ATOMIC_LOAD_U4: {
4251 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4252 break;
4253 }
4254 case OP_ATOMIC_LOAD_R4:
4255 case OP_ATOMIC_LOAD_R8: {
4256 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4257 break;
4258 }
4259 case OP_ATOMIC_STORE_I1:
4260 case OP_ATOMIC_STORE_U1:
4261 case OP_ATOMIC_STORE_I2:
4262 case OP_ATOMIC_STORE_U2:
4263 case OP_ATOMIC_STORE_I4:
4264 case OP_ATOMIC_STORE_U4: {
4265 int size;
4266
4267 switch (ins->opcode) {
4268 case OP_ATOMIC_STORE_I1:
4269 case OP_ATOMIC_STORE_U1:
4270 size = 1;
4271 break;
4272 case OP_ATOMIC_STORE_I2:
4273 case OP_ATOMIC_STORE_U2:
4274 size = 2;
4275 break;
4276 case OP_ATOMIC_STORE_I4:
4277 case OP_ATOMIC_STORE_U4:
4278 size = 4;
4279 break;
4280 }
4281
4282 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4283
4284 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4285 x86_mfence (code);
4286 break;
4287 }
4288 case OP_ATOMIC_STORE_R4:
4289 case OP_ATOMIC_STORE_R8: {
4290 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4291
4292 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4293 x86_mfence (code);
4294 break;
4295 }
4296 case OP_CARD_TABLE_WBARRIER: {
4297 int ptr = ins->sreg1;
4298 int value = ins->sreg2;
4299 guchar *br = NULL;
4300 int nursery_shift, card_table_shift;
4301 gpointer card_table_mask;
4302 size_t nursery_size;
4303 gulong card_table = (gsize)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4304 gulong nursery_start = (gsize)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4305 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4306
4307 /*
4308 * We need one register we can clobber, we choose EDX and make sreg1
4309 * fixed EAX to work around limitations in the local register allocator.
4310 * sreg2 might get allocated to EDX, but that is not a problem since
4311 * we use it before clobbering EDX.
4312 */
4313 g_assert (ins->sreg1 == X86_EAX);
4314
4315 /*
4316 * This is the code we produce:
4317 *
4318 * edx = value
4319 * edx >>= nursery_shift
4320 * cmp edx, (nursery_start >> nursery_shift)
4321 * jne done
4322 * edx = ptr
4323 * edx >>= card_table_shift
4324 * card_table[edx] = 1
4325 * done:
4326 */
4327
4328 if (card_table_nursery_check) {
4329 if (value != X86_EDX)
4330 x86_mov_reg_reg (code, X86_EDX, value);
4331 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4332 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4333 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4334 }
4335 x86_mov_reg_reg (code, X86_EDX, ptr);
4336 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4337 if (card_table_mask)
4338 x86_alu_reg_imm (code, X86_AND, X86_EDX, (gsize)card_table_mask);
4339 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4340 if (card_table_nursery_check)
4341 x86_patch (br, code);
4342 break;
4343 }
4344 #ifdef MONO_ARCH_SIMD_INTRINSICS
4345 case OP_ADDPS:
4346 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4347 break;
4348 case OP_DIVPS:
4349 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4350 break;
4351 case OP_MULPS:
4352 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4353 break;
4354 case OP_SUBPS:
4355 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4356 break;
4357 case OP_MAXPS:
4358 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4359 break;
4360 case OP_MINPS:
4361 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4362 break;
4363 case OP_COMPPS:
4364 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4365 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4366 break;
4367 case OP_ANDPS:
4368 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4369 break;
4370 case OP_ANDNPS:
4371 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4372 break;
4373 case OP_ORPS:
4374 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4375 break;
4376 case OP_XORPS:
4377 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4378 break;
4379 case OP_SQRTPS:
4380 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4381 break;
4382 case OP_RSQRTPS:
4383 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4384 break;
4385 case OP_RCPPS:
4386 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4387 break;
4388 case OP_ADDSUBPS:
4389 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4390 break;
4391 case OP_HADDPS:
4392 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4393 break;
4394 case OP_HSUBPS:
4395 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4396 break;
4397 case OP_DUPPS_HIGH:
4398 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4399 break;
4400 case OP_DUPPS_LOW:
4401 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4402 break;
4403
4404 case OP_PSHUFLEW_HIGH:
4405 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4406 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4407 break;
4408 case OP_PSHUFLEW_LOW:
4409 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4410 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4411 break;
4412 case OP_PSHUFLED:
4413 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4414 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4415 break;
4416 case OP_SHUFPS:
4417 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4418 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4419 break;
4420 case OP_SHUFPD:
4421 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4422 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4423 break;
4424
4425 case OP_ADDPD:
4426 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4427 break;
4428 case OP_DIVPD:
4429 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4430 break;
4431 case OP_MULPD:
4432 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4433 break;
4434 case OP_SUBPD:
4435 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4436 break;
4437 case OP_MAXPD:
4438 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4439 break;
4440 case OP_MINPD:
4441 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4442 break;
4443 case OP_COMPPD:
4444 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4445 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4446 break;
4447 case OP_ANDPD:
4448 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4449 break;
4450 case OP_ANDNPD:
4451 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4452 break;
4453 case OP_ORPD:
4454 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4455 break;
4456 case OP_XORPD:
4457 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4458 break;
4459 case OP_SQRTPD:
4460 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4461 break;
4462 case OP_ADDSUBPD:
4463 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4464 break;
4465 case OP_HADDPD:
4466 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4467 break;
4468 case OP_HSUBPD:
4469 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4470 break;
4471 case OP_DUPPD:
4472 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4473 break;
4474
4475 case OP_EXTRACT_MASK:
4476 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4477 break;
4478
4479 case OP_PAND:
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4481 break;
4482 case OP_POR:
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4484 break;
4485 case OP_PXOR:
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4487 break;
4488
4489 case OP_PADDB:
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4491 break;
4492 case OP_PADDW:
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4494 break;
4495 case OP_PADDD:
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4497 break;
4498 case OP_PADDQ:
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4500 break;
4501
4502 case OP_PSUBB:
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4504 break;
4505 case OP_PSUBW:
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4507 break;
4508 case OP_PSUBD:
4509 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4510 break;
4511 case OP_PSUBQ:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4513 break;
4514
4515 case OP_PMAXB_UN:
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4517 break;
4518 case OP_PMAXW_UN:
4519 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4520 break;
4521 case OP_PMAXD_UN:
4522 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4523 break;
4524
4525 case OP_PMAXB:
4526 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4527 break;
4528 case OP_PMAXW:
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4530 break;
4531 case OP_PMAXD:
4532 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4533 break;
4534
4535 case OP_PAVGB_UN:
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4537 break;
4538 case OP_PAVGW_UN:
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4540 break;
4541
4542 case OP_PMINB_UN:
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4544 break;
4545 case OP_PMINW_UN:
4546 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4547 break;
4548 case OP_PMIND_UN:
4549 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4550 break;
4551
4552 case OP_PMINB:
4553 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4554 break;
4555 case OP_PMINW:
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4557 break;
4558 case OP_PMIND:
4559 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4560 break;
4561
4562 case OP_PCMPEQB:
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4564 break;
4565 case OP_PCMPEQW:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4567 break;
4568 case OP_PCMPEQD:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4570 break;
4571 case OP_PCMPEQQ:
4572 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4573 break;
4574
4575 case OP_PCMPGTB:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4577 break;
4578 case OP_PCMPGTW:
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4580 break;
4581 case OP_PCMPGTD:
4582 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4583 break;
4584 case OP_PCMPGTQ:
4585 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4586 break;
4587
4588 case OP_PSUM_ABS_DIFF:
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4590 break;
4591
4592 case OP_UNPACK_LOWB:
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4594 break;
4595 case OP_UNPACK_LOWW:
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4597 break;
4598 case OP_UNPACK_LOWD:
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4600 break;
4601 case OP_UNPACK_LOWQ:
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4603 break;
4604 case OP_UNPACK_LOWPS:
4605 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4606 break;
4607 case OP_UNPACK_LOWPD:
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4609 break;
4610
4611 case OP_UNPACK_HIGHB:
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4613 break;
4614 case OP_UNPACK_HIGHW:
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4616 break;
4617 case OP_UNPACK_HIGHD:
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4619 break;
4620 case OP_UNPACK_HIGHQ:
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4622 break;
4623 case OP_UNPACK_HIGHPS:
4624 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4625 break;
4626 case OP_UNPACK_HIGHPD:
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4628 break;
4629
4630 case OP_PACKW:
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4632 break;
4633 case OP_PACKD:
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4635 break;
4636 case OP_PACKW_UN:
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4638 break;
4639 case OP_PACKD_UN:
4640 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4641 break;
4642
4643 case OP_PADDB_SAT_UN:
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4645 break;
4646 case OP_PSUBB_SAT_UN:
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4648 break;
4649 case OP_PADDW_SAT_UN:
4650 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4651 break;
4652 case OP_PSUBW_SAT_UN:
4653 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4654 break;
4655
4656 case OP_PADDB_SAT:
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4658 break;
4659 case OP_PSUBB_SAT:
4660 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4661 break;
4662 case OP_PADDW_SAT:
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4664 break;
4665 case OP_PSUBW_SAT:
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4667 break;
4668
4669 case OP_PMULW:
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4671 break;
4672 case OP_PMULD:
4673 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4674 break;
4675 case OP_PMULQ:
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4677 break;
4678 case OP_PMULW_HIGH_UN:
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4680 break;
4681 case OP_PMULW_HIGH:
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4683 break;
4684
4685 case OP_PSHRW:
4686 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4687 break;
4688 case OP_PSHRW_REG:
4689 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4690 break;
4691
4692 case OP_PSARW:
4693 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4694 break;
4695 case OP_PSARW_REG:
4696 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4697 break;
4698
4699 case OP_PSHLW:
4700 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4701 break;
4702 case OP_PSHLW_REG:
4703 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4704 break;
4705
4706 case OP_PSHRD:
4707 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4708 break;
4709 case OP_PSHRD_REG:
4710 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4711 break;
4712
4713 case OP_PSARD:
4714 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4715 break;
4716 case OP_PSARD_REG:
4717 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4718 break;
4719
4720 case OP_PSHLD:
4721 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4722 break;
4723 case OP_PSHLD_REG:
4724 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4725 break;
4726
4727 case OP_PSHRQ:
4728 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4729 break;
4730 case OP_PSHRQ_REG:
4731 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4732 break;
4733
4734 case OP_PSHLQ:
4735 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4736 break;
4737 case OP_PSHLQ_REG:
4738 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4739 break;
4740
4741 case OP_ICONV_TO_X:
4742 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4743 break;
4744 case OP_EXTRACT_I4:
4745 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4746 break;
4747 case OP_EXTRACT_I1:
4748 case OP_EXTRACT_U1:
4749 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4750 if (ins->inst_c0)
4751 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4752 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4753 break;
4754 case OP_EXTRACT_I2:
4755 case OP_EXTRACT_U2:
4756 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4757 if (ins->inst_c0)
4758 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4759 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4760 break;
4761 case OP_EXTRACT_R8:
4762 if (ins->inst_c0)
4763 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4764 else
4765 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4766 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4767 break;
4768
4769 case OP_INSERT_I2:
4770 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4771 break;
4772 case OP_EXTRACTX_U2:
4773 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4774 break;
4775 case OP_INSERTX_U1_SLOW:
4776 /*sreg1 is the extracted ireg (scratch)
4777 /sreg2 is the to be inserted ireg (scratch)
4778 /dreg is the xreg to receive the value*/
4779
4780 /*clear the bits from the extracted word*/
4781 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4782 /*shift the value to insert if needed*/
4783 if (ins->inst_c0 & 1)
4784 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4785 /*join them together*/
4786 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4787 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4788 break;
4789 case OP_INSERTX_I4_SLOW:
4790 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4791 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4792 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4793 break;
4794
4795 case OP_INSERTX_R4_SLOW:
4796 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4797 /*TODO if inst_c0 == 0 use movss*/
4798 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4799 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4800 break;
4801 case OP_INSERTX_R8_SLOW:
4802 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4803 if (cfg->verbose_level)
4804 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4805 if (ins->inst_c0)
4806 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4807 else
4808 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4809 break;
4810
4811 case OP_STOREX_MEMBASE_REG:
4812 case OP_STOREX_MEMBASE:
4813 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4814 break;
4815 case OP_LOADX_MEMBASE:
4816 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4817 break;
4818 case OP_LOADX_ALIGNED_MEMBASE:
4819 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4820 break;
4821 case OP_STOREX_ALIGNED_MEMBASE_REG:
4822 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4823 break;
4824 case OP_STOREX_NTA_MEMBASE_REG:
4825 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4826 break;
4827 case OP_PREFETCH_MEMBASE:
4828 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4829
4830 break;
4831 case OP_XMOVE:
4832 /*FIXME the peephole pass should have killed this*/
4833 if (ins->dreg != ins->sreg1)
4834 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4835 break;
4836 case OP_XZERO:
4837 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4838 break;
4839 case OP_XONES:
4840 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4841 break;
4842
4843 case OP_FCONV_TO_R8_X:
4844 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4845 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4846 break;
4847
4848 case OP_XCONV_R8_TO_I4:
4849 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4850 switch (ins->backend.source_opcode) {
4851 case OP_FCONV_TO_I1:
4852 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4853 break;
4854 case OP_FCONV_TO_U1:
4855 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4856 break;
4857 case OP_FCONV_TO_I2:
4858 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4859 break;
4860 case OP_FCONV_TO_U2:
4861 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4862 break;
4863 }
4864 break;
4865
4866 case OP_EXPAND_I2:
4867 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4868 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4869 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4870 break;
4871 case OP_EXPAND_I4:
4872 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4873 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4874 break;
4875 case OP_EXPAND_R4:
4876 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4877 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4878 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4879 break;
4880 case OP_EXPAND_R8:
4881 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4882 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4883 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4884 break;
4885
4886 case OP_CVTDQ2PD:
4887 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4888 break;
4889 case OP_CVTDQ2PS:
4890 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4891 break;
4892 case OP_CVTPD2DQ:
4893 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4894 break;
4895 case OP_CVTPD2PS:
4896 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4897 break;
4898 case OP_CVTPS2DQ:
4899 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4900 break;
4901 case OP_CVTPS2PD:
4902 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4903 break;
4904 case OP_CVTTPD2DQ:
4905 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4906 break;
4907 case OP_CVTTPS2DQ:
4908 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4909 break;
4910
4911 #endif
4912 case OP_LIVERANGE_START: {
4913 if (cfg->verbose_level > 1)
4914 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4915 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4916 break;
4917 }
4918 case OP_LIVERANGE_END: {
4919 if (cfg->verbose_level > 1)
4920 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4921 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4922 break;
4923 }
4924 case OP_GC_SAFE_POINT: {
4925 guint8 *br [1];
4926
4927 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4928 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4929 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_threads_state_poll));
4930 x86_patch (br [0], code);
4931
4932 break;
4933 }
4934 case OP_GC_LIVENESS_DEF:
4935 case OP_GC_LIVENESS_USE:
4936 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4937 ins->backend.pc_offset = code - cfg->native_code;
4938 break;
4939 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4940 ins->backend.pc_offset = code - cfg->native_code;
4941 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4942 break;
4943 case OP_GET_SP:
4944 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
4945 break;
4946 case OP_SET_SP:
4947 x86_mov_reg_reg (code, X86_ESP, ins->sreg1);
4948 break;
4949 case OP_FILL_PROF_CALL_CTX:
4950 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (target_mgreg_t));
4951 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (target_mgreg_t));
4952 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (target_mgreg_t));
4953 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (target_mgreg_t));
4954 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (target_mgreg_t));
4955 break;
4956 case OP_GET_LAST_ERROR:
4957 code = emit_get_last_error (code, ins->dreg);
4958 break;
4959 default:
4960 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4961 g_assert_not_reached ();
4962 }
4963
4964 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4965 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4966 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4967 g_assert_not_reached ();
4968 }
4969
4970 cpos += max_len;
4971 }
4972
4973 set_code_cursor (cfg, code);
4974 }
4975
4976 #endif /* DISABLE_JIT */
4977
4978 void
4979 mono_arch_register_lowlevel_calls (void)
4980 {
4981 }
4982
4983 void
4984 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4985 {
4986 unsigned char *ip = ji->ip.i + code;
4987
4988 switch (ji->type) {
4989 case MONO_PATCH_INFO_IP:
4990 *((gconstpointer *)(ip)) = target;
4991 break;
4992 case MONO_PATCH_INFO_ABS:
4993 case MONO_PATCH_INFO_METHOD:
4994 case MONO_PATCH_INFO_METHOD_JUMP:
4995 case MONO_PATCH_INFO_JIT_ICALL_ID:
4996 case MONO_PATCH_INFO_BB:
4997 case MONO_PATCH_INFO_LABEL:
4998 case MONO_PATCH_INFO_RGCTX_FETCH:
4999 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5000 case MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR:
5001 x86_patch (ip, (unsigned char*)target);
5002 break;
5003 case MONO_PATCH_INFO_NONE:
5004 break;
5005 case MONO_PATCH_INFO_R4:
5006 case MONO_PATCH_INFO_R8: {
5007 guint32 offset = mono_arch_get_patch_offset (ip);
5008 *((gconstpointer *)(ip + offset)) = target;
5009 break;
5010 }
5011 default: {
5012 guint32 offset = mono_arch_get_patch_offset (ip);
5013 *((gconstpointer *)(ip + offset)) = target;
5014 break;
5015 }
5016 }
5017 }
5018
5019 static G_GNUC_UNUSED void
5020 stack_unaligned (MonoMethod *m, gpointer caller)
5021 {
5022 printf ("%s\n", mono_method_full_name (m, TRUE));
5023 g_assert_not_reached ();
5024 }
5025
5026 #ifndef DISABLE_JIT
5027
5028 guint8 *
5029 mono_arch_emit_prolog (MonoCompile *cfg)
5030 {
5031 MonoMethod *method = cfg->method;
5032 MonoBasicBlock *bb;
5033 MonoMethodSignature *sig;
5034 MonoInst *inst;
5035 CallInfo *cinfo;
5036 ArgInfo *ainfo;
5037 int alloc_size, pos, max_offset, i, cfa_offset;
5038 guint8 *code;
5039 gboolean need_stack_frame;
5040
5041 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5042
5043 code = cfg->native_code = g_malloc (cfg->code_size);
5044
5045 #if 0
5046 {
5047 guint8 *br [16];
5048
5049 /* Check that the stack is aligned on osx */
5050 x86_mov_reg_reg (code, X86_EAX, X86_ESP);
5051 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5052 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5053 br [0] = code;
5054 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5055 x86_push_membase (code, X86_ESP, 0);
5056 x86_push_imm (code, cfg->method);
5057 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5058 x86_call_reg (code, X86_EAX);
5059 x86_patch (br [0], code);
5060 }
5061 #endif
5062
5063 /* Offset between RSP and the CFA */
5064 cfa_offset = 0;
5065
5066 // CFA = sp + 4
5067 cfa_offset = 4;
5068 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, cfa_offset);
5069 // IP saved at CFA - 4
5070 /* There is no IP reg on x86 */
5071 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5072 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5073
5074 need_stack_frame = needs_stack_frame (cfg);
5075
5076 if (need_stack_frame) {
5077 x86_push_reg (code, X86_EBP);
5078 cfa_offset += 4;
5079 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5080 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5081 x86_mov_reg_reg (code, X86_EBP, X86_ESP);
5082 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5083 /* These are handled automatically by the stack marking code */
5084 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5085 } else {
5086 cfg->frame_reg = X86_ESP;
5087 }
5088
5089 cfg->stack_offset += cfg->param_area;
5090 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5091
5092 alloc_size = cfg->stack_offset;
5093 pos = 0;
5094
5095 if (!method->save_lmf) {
5096 if (cfg->used_int_regs & (1 << X86_EBX)) {
5097 x86_push_reg (code, X86_EBX);
5098 pos += 4;
5099 cfa_offset += 4;
5100 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5101 /* These are handled automatically by the stack marking code */
5102 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5103 }
5104
5105 if (cfg->used_int_regs & (1 << X86_EDI)) {
5106 x86_push_reg (code, X86_EDI);
5107 pos += 4;
5108 cfa_offset += 4;
5109 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5110 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5111 }
5112
5113 if (cfg->used_int_regs & (1 << X86_ESI)) {
5114 x86_push_reg (code, X86_ESI);
5115 pos += 4;
5116 cfa_offset += 4;
5117 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5118 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5119 }
5120 }
5121
5122 alloc_size -= pos;
5123
5124 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5125 if (mono_do_x86_stack_align && need_stack_frame) {
5126 int tot = alloc_size + pos + 4; /* ret ip */
5127 if (need_stack_frame)
5128 tot += 4; /* ebp */
5129 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5130 if (tot) {
5131 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5132 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (target_mgreg_t))
5133 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5134 }
5135 }
5136
5137 cfg->arch.sp_fp_offset = alloc_size + pos;
5138
5139 if (alloc_size) {
5140 /* See mono_emit_stack_alloc */
5141 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5142 guint32 remaining_size = alloc_size;
5143 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5144 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5145 set_code_cursor (cfg, code);
5146 code = realloc_code (cfg, required_code_size);
5147 while (remaining_size >= 0x1000) {
5148 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5149 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5150 remaining_size -= 0x1000;
5151 }
5152 if (remaining_size)
5153 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5154 #else
5155 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5156 #endif
5157
5158 g_assert (need_stack_frame);
5159 }
5160
5161 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5162 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5163 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5164 }
5165
5166 #if DEBUG_STACK_ALIGNMENT
5167 /* check the stack is aligned */
5168 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5169 x86_mov_reg_reg (code, X86_ECX, X86_ESP);
5170 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5171 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5172 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5173 x86_breakpoint (code);
5174 }
5175 #endif
5176
5177 /* compute max_offset in order to use short forward jumps */
5178 max_offset = 0;
5179 if (cfg->opt & MONO_OPT_BRANCH) {
5180 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5181 MonoInst *ins;
5182 bb->max_offset = max_offset;
5183
5184 /* max alignment for loops */
5185 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5186 max_offset += LOOP_ALIGNMENT;
5187 MONO_BB_FOR_EACH_INS (bb, ins) {
5188 if (ins->opcode == OP_LABEL)
5189 ins->inst_c1 = max_offset;
5190 max_offset += ins_get_size (ins->opcode);
5191 }
5192 }
5193 }
5194
5195 /* store runtime generic context */
5196 if (cfg->rgctx_var) {
5197 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5198
5199 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5200 }
5201
5202 if (method->save_lmf)
5203 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5204
5205 {
5206 MonoInst *ins;
5207
5208 if (cfg->arch.ss_tramp_var) {
5209 /* Initialize ss_tramp_var */
5210 ins = cfg->arch.ss_tramp_var;
5211 g_assert (ins->opcode == OP_REGOFFSET);
5212
5213 g_assert (!cfg->compile_aot);
5214 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (gsize)&ss_trampoline, 4);
5215 }
5216
5217 if (cfg->arch.bp_tramp_var) {
5218 /* Initialize bp_tramp_var */
5219 ins = cfg->arch.bp_tramp_var;
5220 g_assert (ins->opcode == OP_REGOFFSET);
5221
5222 g_assert (!cfg->compile_aot);
5223 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (gsize)&bp_trampoline, 4);
5224 }
5225 }
5226
5227 /* load arguments allocated to register from the stack */
5228 sig = mono_method_signature_internal (method);
5229 pos = 0;
5230
5231 cinfo = cfg->arch.cinfo;
5232
5233 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5234 inst = cfg->args [pos];
5235 ainfo = &cinfo->args [pos];
5236 if (inst->opcode == OP_REGVAR) {
5237 if (storage_in_ireg (ainfo->storage)) {
5238 x86_mov_reg_reg (code, inst->dreg, ainfo->reg);
5239 } else {
5240 g_assert (need_stack_frame);
5241 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5242 }
5243 if (cfg->verbose_level > 2)
5244 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5245 } else {
5246 if (storage_in_ireg (ainfo->storage)) {
5247 x86_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, 4);
5248 }
5249 }
5250 pos++;
5251 }
5252
5253 set_code_cursor (cfg, code);
5254
5255 return code;
5256 }
5257
5258 #endif
5259
5260 void
5261 mono_arch_emit_epilog (MonoCompile *cfg)
5262 {
5263 MonoMethod *method = cfg->method;
5264 MonoMethodSignature *sig = mono_method_signature_internal (method);
5265 int i, quad, pos;
5266 guint32 stack_to_pop;
5267 guint8 *code;
5268 int max_epilog_size = 16;
5269 CallInfo *cinfo;
5270 gboolean need_stack_frame = needs_stack_frame (cfg);
5271
5272 if (cfg->method->save_lmf)
5273 max_epilog_size += 128;
5274
5275 code = realloc_code (cfg, max_epilog_size);
5276
5277 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5278 pos = 0;
5279
5280 if (method->save_lmf) {
5281 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5282
5283 /* restore caller saved regs */
5284 if (cfg->used_int_regs & (1 << X86_EBX)) {
5285 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5286 }
5287
5288 if (cfg->used_int_regs & (1 << X86_EDI)) {
5289 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5290 }
5291 if (cfg->used_int_regs & (1 << X86_ESI)) {
5292 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5293 }
5294
5295 /* EBP is restored by LEAVE */
5296 } else {
5297 for (i = 0; i < X86_NREG; ++i) {
5298 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5299 pos -= 4;
5300 }
5301 }
5302
5303 g_assert (!pos || need_stack_frame);
5304 if (pos) {
5305 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5306 }
5307
5308 if (cfg->used_int_regs & (1 << X86_ESI)) {
5309 x86_pop_reg (code, X86_ESI);
5310 }
5311 if (cfg->used_int_regs & (1 << X86_EDI)) {
5312 x86_pop_reg (code, X86_EDI);
5313 }
5314 if (cfg->used_int_regs & (1 << X86_EBX)) {
5315 x86_pop_reg (code, X86_EBX);
5316 }
5317 }
5318
5319 /* Load returned vtypes into registers if needed */
5320 cinfo = cfg->arch.cinfo;
5321 if (cinfo->ret.storage == ArgValuetypeInReg) {
5322 for (quad = 0; quad < 2; quad ++) {
5323 switch (cinfo->ret.pair_storage [quad]) {
5324 case ArgInIReg:
5325 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), 4);
5326 break;
5327 case ArgOnFloatFpStack:
5328 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), FALSE);
5329 break;
5330 case ArgOnDoubleFpStack:
5331 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), TRUE);
5332 break;
5333 case ArgNone:
5334 break;
5335 default:
5336 g_assert_not_reached ();
5337 }
5338 }
5339 }
5340
5341 if (need_stack_frame)
5342 x86_leave (code);
5343
5344 if (CALLCONV_IS_STDCALL (sig)) {
5345 MonoJitArgumentInfo *arg_info = g_newa (MonoJitArgumentInfo, sig->param_count + 1);
5346
5347 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5348 } else if (cinfo->callee_stack_pop)
5349 stack_to_pop = cinfo->callee_stack_pop;
5350 else
5351 stack_to_pop = 0;
5352
5353 if (stack_to_pop) {
5354 g_assert (need_stack_frame);
5355 x86_ret_imm (code, stack_to_pop);
5356 } else {
5357 x86_ret (code);
5358 }
5359
5360 set_code_cursor (cfg, code);
5361 }
5362
5363 void
5364 mono_arch_emit_exceptions (MonoCompile *cfg)
5365 {
5366 MonoJumpInfo *patch_info;
5367 int nthrows, i;
5368 guint8 *code;
5369 MonoClass *exc_classes [16];
5370 guint8 *exc_throw_start [16], *exc_throw_end [16];
5371 guint32 code_size;
5372 int exc_count = 0;
5373
5374 /* Compute needed space */
5375 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5376 if (patch_info->type == MONO_PATCH_INFO_EXC)
5377 exc_count++;
5378 }
5379
5380 /*
5381 * make sure we have enough space for exceptions
5382 * 16 is the size of two push_imm instructions and a call
5383 */
5384 if (cfg->compile_aot)
5385 code_size = exc_count * 32;
5386 else
5387 code_size = exc_count * 16;
5388
5389 code = realloc_code (cfg, code_size);
5390
5391 nthrows = 0;
5392 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5393 switch (patch_info->type) {
5394 case MONO_PATCH_INFO_EXC: {
5395 MonoClass *exc_class;
5396 guint8 *buf, *buf2;
5397 guint32 throw_ip;
5398
5399 x86_patch (patch_info->ip.i + cfg->native_code, code);
5400
5401 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5402 throw_ip = patch_info->ip.i;
5403
5404 /* Find a throw sequence for the same exception class */
5405 for (i = 0; i < nthrows; ++i)
5406 if (exc_classes [i] == exc_class)
5407 break;
5408 if (i < nthrows) {
5409 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5410 x86_jump_code (code, exc_throw_start [i]);
5411 patch_info->type = MONO_PATCH_INFO_NONE;
5412 }
5413 else {
5414 guint32 size;
5415
5416 /* Compute size of code following the push <OFFSET> */
5417 size = 5 + 5;
5418
5419 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5420
5421 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5422 /* Use the shorter form */
5423 buf = buf2 = code;
5424 x86_push_imm (code, 0);
5425 }
5426 else {
5427 buf = code;
5428 x86_push_imm (code, 0xf0f0f0f0);
5429 buf2 = code;
5430 }
5431
5432 if (nthrows < 16) {
5433 exc_classes [nthrows] = exc_class;
5434 exc_throw_start [nthrows] = code;
5435 }
5436
5437 x86_push_imm (code, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
5438 patch_info->data.jit_icall_id = MONO_JIT_ICALL_mono_arch_throw_corlib_exception;
5439 patch_info->type = MONO_PATCH_INFO_JIT_ICALL_ID;
5440 patch_info->ip.i = code - cfg->native_code;
5441 x86_call_code (code, 0);
5442 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5443 while (buf < buf2)
5444 x86_nop (buf);
5445
5446 if (nthrows < 16) {
5447 exc_throw_end [nthrows] = code;
5448 nthrows ++;
5449 }
5450 }
5451 break;
5452 }
5453 default:
5454 /* do nothing */
5455 break;
5456 }
5457 set_code_cursor (cfg, code);
5458 }
5459 set_code_cursor (cfg, code);
5460 }
5461
5462 MONO_NEVER_INLINE
5463 void
5464 mono_arch_flush_icache (guint8 *code, gint size)
5465 {
5466 /* call/ret required (or likely other control transfer) */
5467 }
5468
5469 void
5470 mono_arch_flush_register_windows (void)
5471 {
5472 }
5473
5474 gboolean
5475 mono_arch_is_inst_imm (int opcode, int imm_opcode, gint64 imm)
5476 {
5477 return TRUE;
5478 }
5479
5480 void
5481 mono_arch_finish_init (void)
5482 {
5483 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5484 if (!mono_no_tls) {
5485 #ifndef TARGET_WIN32
5486 #if MONO_XEN_OPT
5487 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5488 #endif
5489 #endif
5490 } else {
5491 g_free (mono_no_tls);
5492 }
5493 }
5494
5495 // Linear handler, the bsearch head compare is shorter
5496 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5497 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5498 // x86_patch(ins,target)
5499 //[1 + 5] x86_jump_mem(inst,mem)
5500
5501 #define CMP_SIZE 6
5502 #define BR_SMALL_SIZE 2
5503 #define BR_LARGE_SIZE 5
5504 #define JUMP_IMM_SIZE 6
5505 #define ENABLE_WRONG_METHOD_CHECK 0
5506 #define DEBUG_IMT 0
5507
5508 static int
5509 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5510 {
5511 int i, distance = 0;
5512 for (i = start; i < target; ++i)
5513 distance += imt_entries [i]->chunk_size;
5514 return distance;
5515 }
5516
5517 /*
5518 * LOCKING: called with the domain lock held
5519 */
5520 gpointer
5521 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5522 gpointer fail_tramp)
5523 {
5524 int i;
5525 int size = 0;
5526 guint8 *code, *start;
5527 GSList *unwind_ops;
5528
5529 for (i = 0; i < count; ++i) {
5530 MonoIMTCheckItem *item = imt_entries [i];
5531 if (item->is_equals) {
5532 if (item->check_target_idx) {
5533 if (!item->compare_done)
5534 item->chunk_size += CMP_SIZE;
5535 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5536 } else {
5537 if (fail_tramp) {
5538 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5539 } else {
5540 item->chunk_size += JUMP_IMM_SIZE;
5541 #if ENABLE_WRONG_METHOD_CHECK
5542 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5543 #endif
5544 }
5545 }
5546 } else {
5547 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5548 imt_entries [item->check_target_idx]->compare_done = TRUE;
5549 }
5550 size += item->chunk_size;
5551 }
5552 if (fail_tramp) {
5553 code = (guint8*)mono_method_alloc_generic_virtual_trampoline (mono_domain_ambient_memory_manager (domain), size);
5554 } else {
5555 MonoMemoryManager *mem_manager = m_class_get_mem_manager (domain, vtable->klass);
5556 code = mono_mem_manager_code_reserve (mem_manager, size);
5557 }
5558 start = code;
5559
5560 unwind_ops = mono_arch_get_cie_program ();
5561
5562 for (i = 0; i < count; ++i) {
5563 MonoIMTCheckItem *item = imt_entries [i];
5564 item->code_target = code;
5565 if (item->is_equals) {
5566 if (item->check_target_idx) {
5567 if (!item->compare_done)
5568 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gsize)item->key);
5569 item->jmp_code = code;
5570 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5571 if (item->has_target_code)
5572 x86_jump_code (code, item->value.target_code);
5573 else
5574 x86_jump_mem (code, (gsize)&vtable->vtable [item->value.vtable_slot]);
5575 } else {
5576 if (fail_tramp) {
5577 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gsize)item->key);
5578 item->jmp_code = code;
5579 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5580 if (item->has_target_code)
5581 x86_jump_code (code, item->value.target_code);
5582 else
5583 x86_jump_mem (code, (gsize)&vtable->vtable [item->value.vtable_slot]);
5584 x86_patch (item->jmp_code, code);
5585 x86_jump_code (code, fail_tramp);
5586 item->jmp_code = NULL;
5587 } else {
5588 /* enable the commented code to assert on wrong method */
5589 #if ENABLE_WRONG_METHOD_CHECK
5590 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gsize)item->key);
5591 item->jmp_code = code;
5592 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5593 #endif
5594 if (item->has_target_code)
5595 x86_jump_code (code, item->value.target_code);
5596 else
5597 x86_jump_mem (code, (gsize)&vtable->vtable [item->value.vtable_slot]);
5598 #if ENABLE_WRONG_METHOD_CHECK
5599 x86_patch (item->jmp_code, code);
5600 x86_breakpoint (code);
5601 item->jmp_code = NULL;
5602 #endif
5603 }
5604 }
5605 } else {
5606 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gsize)item->key);
5607 item->jmp_code = code;
5608 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5609 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5610 else
5611 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5612 }
5613 }
5614 /* patch the branches to get to the target items */
5615 for (i = 0; i < count; ++i) {
5616 MonoIMTCheckItem *item = imt_entries [i];
5617 if (item->jmp_code) {
5618 if (item->check_target_idx) {
5619 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5620 }
5621 }
5622 }
5623
5624 if (!fail_tramp)
5625 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
5626 g_assertf (code - start <= size, "%d %d", (int)(code - start), size);
5627
5628 #if DEBUG_IMT
5629 {
5630 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5631 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5632 g_free (buff);
5633 }
5634 #endif
5635 if (mono_jit_map_is_enabled ()) {
5636 char *buff;
5637 if (vtable)
5638 buff = g_strdup_printf ("imt_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5639 else
5640 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5641 mono_emit_jit_tramp (start, code - start, buff);
5642 g_free (buff);
5643 }
5644
5645 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5646
5647 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5648
5649 return start;
5650 }
5651
5652 MonoMethod*
5653 mono_arch_find_imt_method (host_mgreg_t *regs, guint8 *code)
5654 {
5655 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5656 }
5657
5658 MonoVTable*
5659 mono_arch_find_static_call_vtable (host_mgreg_t *regs, guint8 *code)
5660 {
5661 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5662 }
5663
5664 GSList*
5665 mono_arch_get_cie_program (void)
5666 {
5667 GSList *l = NULL;
5668
5669 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5670 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5671
5672 return l;
5673 }
5674
5675 MonoInst*
5676 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5677 {
5678 MonoInst *ins = NULL;
5679 int opcode = 0;
5680
5681 if (cmethod->klass == mono_class_try_get_math_class ()) {
5682 if (strcmp (cmethod->name, "Tan") == 0) {
5683 opcode = OP_TAN;
5684 } else if (strcmp (cmethod->name, "Atan") == 0) {
5685 opcode = OP_ATAN;
5686 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5687 opcode = OP_SQRT;
5688 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5689 opcode = OP_ABS;
5690 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5691 opcode = OP_ROUND;
5692 }
5693
5694 if (opcode && fsig->param_count == 1) {
5695 MONO_INST_NEW (cfg, ins, opcode);
5696 ins->type = STACK_R8;
5697 ins->dreg = mono_alloc_freg (cfg);
5698 ins->sreg1 = args [0]->dreg;
5699 MONO_ADD_INS (cfg->cbb, ins);
5700 }
5701
5702 if (cfg->opt & MONO_OPT_CMOV) {
5703 opcode = 0;
5704
5705 if (strcmp (cmethod->name, "Min") == 0) {
5706 if (fsig->params [0]->type == MONO_TYPE_I4)
5707 opcode = OP_IMIN;
5708 } else if (strcmp (cmethod->name, "Max") == 0) {
5709 if (fsig->params [0]->type == MONO_TYPE_I4)
5710 opcode = OP_IMAX;
5711 }
5712
5713 if (opcode && fsig->param_count == 2) {
5714 MONO_INST_NEW (cfg, ins, opcode);
5715 ins->type = STACK_I4;
5716 ins->dreg = mono_alloc_ireg (cfg);
5717 ins->sreg1 = args [0]->dreg;
5718 ins->sreg2 = args [1]->dreg;
5719 MONO_ADD_INS (cfg->cbb, ins);
5720 }
5721 }
5722
5723 #if 0
5724 /* OP_FREM is not IEEE compatible */
5725 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5726 MONO_INST_NEW (cfg, ins, OP_FREM);
5727 ins->inst_i0 = args [0];
5728 ins->inst_i1 = args [1];
5729 }
5730 #endif
5731 }
5732
5733 return ins;
5734 }
5735
5736 guint32
5737 mono_arch_get_patch_offset (guint8 *code)
5738 {
5739 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5740 return 2;
5741 else if (code [0] == 0xba)
5742 return 1;
5743 else if (code [0] == 0x68)
5744 /* push IMM */
5745 return 1;
5746 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5747 /* push <OFFSET>(<REG>) */
5748 return 2;
5749 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5750 /* call *<OFFSET>(<REG>) */
5751 return 2;
5752 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5753 /* fldl <ADDR> */
5754 return 2;
5755 else if ((code [0] == 0x58) && (code [1] == 0x05))
5756 /* pop %eax; add <OFFSET>, %eax */
5757 return 2;
5758 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5759 /* pop <REG>; add <OFFSET>, <REG> */
5760 return 3;
5761 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5762 /* mov <REG>, imm */
5763 return 1;
5764 else if (code [0] == 0xE9)
5765 /* jmp eip+32b */
5766 return 1;
5767 g_assert_not_reached ();
5768 return -1;
5769 }
5770
5771 /**
5772 * \return TRUE if no sw breakpoint was present.
5773 *
5774 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5775 * breakpoints in the original code, they are removed in the copy.
5776 */
5777 gboolean
5778 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5779 {
5780 /*
5781 * If method_start is non-NULL we need to perform bound checks, since we access memory
5782 * at code - offset we could go before the start of the method and end up in a different
5783 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5784 * instead.
5785 */
5786 if (!method_start || code - offset >= method_start) {
5787 memcpy (buf, code - offset, size);
5788 } else {
5789 int diff = code - method_start;
5790 memset (buf, 0, size);
5791 memcpy (buf + offset - diff, method_start, diff + size - offset);
5792 }
5793 return TRUE;
5794 }
5795
5796 /*
5797 * mono_x86_get_this_arg_offset:
5798 *
5799 * Return the offset of the stack location where this is passed during a virtual
5800 * call.
5801 */
5802 guint32
5803 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5804 {
5805 return 0;
5806 }
5807
5808 gpointer
5809 mono_arch_get_this_arg_from_call (host_mgreg_t *regs, guint8 *code)
5810 {
5811 host_mgreg_t esp = regs [X86_ESP];
5812 gpointer res;
5813 int offset;
5814
5815 offset = 0;
5816
5817 /*
5818 * The stack looks like:
5819 * <other args>
5820 * <this=delegate>
5821 */
5822 res = ((MonoObject**)esp) [0];
5823 return res;
5824 }
5825
5826 #define MAX_ARCH_DELEGATE_PARAMS 10
5827
5828 static gpointer
5829 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5830 {
5831 guint8 *code, *start;
5832 int code_reserve = 64;
5833 GSList *unwind_ops;
5834
5835 unwind_ops = mono_arch_get_cie_program ();
5836
5837 /*
5838 * The stack contains:
5839 * <delegate>
5840 * <return addr>
5841 */
5842
5843 if (has_target) {
5844 start = code = mono_global_codeman_reserve (code_reserve);
5845
5846 /* Replace the this argument with the target */
5847 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5848 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5849 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5850 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5851 } else {
5852 int i = 0;
5853 /* 8 for mov_reg and jump, plus 8 for each parameter */
5854 code_reserve = 8 + (param_count * 8);
5855 /*
5856 * The stack contains:
5857 * <args in reverse order>
5858 * <delegate>
5859 * <return addr>
5860 *
5861 * and we need:
5862 * <args in reverse order>
5863 * <return addr>
5864 *
5865 * without unbalancing the stack.
5866 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5867 * and leaving original spot of first arg as placeholder in stack so
5868 * when callee pops stack everything works.
5869 */
5870
5871 start = code = mono_global_codeman_reserve (code_reserve);
5872
5873 /* store delegate for access to method_ptr */
5874 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5875
5876 /* move args up */
5877 for (i = 0; i < param_count; ++i) {
5878 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5879 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5880 }
5881
5882 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5883 }
5884
5885 g_assertf ((code - start) <= code_reserve, "%d %d", (int)(code - start), code_reserve);
5886
5887 if (has_target) {
5888 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5889 } else {
5890 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5891 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5892 g_free (name);
5893 }
5894
5895 if (mono_jit_map_is_enabled ()) {
5896 char *buff;
5897 if (has_target)
5898 buff = (char*)"delegate_invoke_has_target";
5899 else
5900 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5901 mono_emit_jit_tramp (start, code - start, buff);
5902 if (!has_target)
5903 g_free (buff);
5904 }
5905 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5906
5907 return start;
5908 }
5909
5910 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5911
5912 static gpointer
5913 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5914 {
5915 guint8 *code, *start;
5916 int size = 24;
5917 char *tramp_name;
5918 GSList *unwind_ops;
5919
5920 if (offset / (int)sizeof (target_mgreg_t) > MAX_VIRTUAL_DELEGATE_OFFSET)
5921 return NULL;
5922
5923 /*
5924 * The stack contains:
5925 * <delegate>
5926 * <return addr>
5927 */
5928 start = code = mono_global_codeman_reserve (size);
5929
5930 unwind_ops = mono_arch_get_cie_program ();
5931
5932 /* Replace the this argument with the target */
5933 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5934 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5935 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5936
5937 if (load_imt_reg) {
5938 /* Load the IMT reg */
5939 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5940 }
5941
5942 /* Load the vtable */
5943 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5944 x86_jump_membase (code, X86_EAX, offset);
5945
5946 g_assertf ((code - start) <= size, "%d %d", (int)(code - start), size);
5947
5948 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5949
5950 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5951 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5952 g_free (tramp_name);
5953
5954
5955 return start;
5956 }
5957
5958 GSList*
5959 mono_arch_get_delegate_invoke_impls (void)
5960 {
5961 GSList *res = NULL;
5962 MonoTrampInfo *info;
5963 int i;
5964
5965 get_delegate_invoke_impl (&info, TRUE, 0);
5966 res = g_slist_prepend (res, info);
5967
5968 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5969 get_delegate_invoke_impl (&info, FALSE, i);
5970 res = g_slist_prepend (res, info);
5971 }
5972
5973 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5974 get_delegate_virtual_invoke_impl (&info, TRUE, - i * TARGET_SIZEOF_VOID_P);
5975 res = g_slist_prepend (res, info);
5976
5977 get_delegate_virtual_invoke_impl (&info, FALSE, i * TARGET_SIZEOF_VOID_P);
5978 res = g_slist_prepend (res, info);
5979 }
5980
5981 return res;
5982 }
5983
5984 gpointer
5985 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5986 {
5987 guint8 *code, *start;
5988
5989 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5990 return NULL;
5991
5992 /* FIXME: Support more cases */
5993 if (MONO_TYPE_ISSTRUCT (sig->ret))
5994 return NULL;
5995
5996 /*
5997 * The stack contains:
5998 * <delegate>
5999 * <return addr>
6000 */
6001
6002 if (has_target) {
6003 static guint8* cached = NULL;
6004 if (cached)
6005 return cached;
6006
6007 if (mono_ee_features.use_aot_trampolines) {
6008 start = (guint8*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6009 } else {
6010 MonoTrampInfo *info;
6011 start = (guint8*)get_delegate_invoke_impl (&info, TRUE, 0);
6012 mono_tramp_info_register (info, NULL);
6013 }
6014
6015 mono_memory_barrier ();
6016
6017 cached = start;
6018 } else {
6019 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6020 int i = 0;
6021
6022 for (i = 0; i < sig->param_count; ++i)
6023 if (!mono_is_regsize_var (sig->params [i]))
6024 return NULL;
6025
6026 code = cache [sig->param_count];
6027 if (code)
6028 return code;
6029
6030 if (mono_ee_features.use_aot_trampolines) {
6031 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6032 start = (guint8*)mono_aot_get_trampoline (name);
6033 g_free (name);
6034 } else {
6035 MonoTrampInfo *info;
6036 start = (guint8*)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6037 mono_tramp_info_register (info, NULL);
6038 }
6039
6040 mono_memory_barrier ();
6041
6042 cache [sig->param_count] = start;
6043 }
6044
6045 return start;
6046 }
6047
6048 gpointer
6049 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6050 {
6051 MonoTrampInfo *info;
6052 gpointer code;
6053
6054 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6055 if (code)
6056 mono_tramp_info_register (info, NULL);
6057 return code;
6058 }
6059
6060 host_mgreg_t
6061 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6062 {
6063 switch (reg) {
6064 case X86_EAX: return ctx->eax;
6065 case X86_EBX: return ctx->ebx;
6066 case X86_ECX: return ctx->ecx;
6067 case X86_EDX: return ctx->edx;
6068 case X86_ESP: return ctx->esp;
6069 case X86_EBP: return ctx->ebp;
6070 case X86_ESI: return ctx->esi;
6071 case X86_EDI: return ctx->edi;
6072 default:
6073 g_assert_not_reached ();
6074 return 0;
6075 }
6076 }
6077
6078 void
6079 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, host_mgreg_t val)
6080 {
6081 switch (reg) {
6082 case X86_EAX:
6083 ctx->eax = val;
6084 break;
6085 case X86_EBX:
6086 ctx->ebx = val;
6087 break;
6088 case X86_ECX:
6089 ctx->ecx = val;
6090 break;
6091 case X86_EDX:
6092 ctx->edx = val;
6093 break;
6094 case X86_ESP:
6095 ctx->esp = val;
6096 break;
6097 case X86_EBP:
6098 ctx->ebp = val;
6099 break;
6100 case X86_ESI:
6101 ctx->esi = val;
6102 break;
6103 case X86_EDI:
6104 ctx->edi = val;
6105 break;
6106 default:
6107 g_assert_not_reached ();
6108 }
6109 }
6110
6111 #ifdef MONO_ARCH_SIMD_INTRINSICS
6112
6113 static MonoInst*
6114 get_float_to_x_spill_area (MonoCompile *cfg)
6115 {
6116 if (!cfg->fconv_to_r8_x_var) {
6117 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
6118 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6119 }
6120 return cfg->fconv_to_r8_x_var;
6121 }
6122
6123 /*
6124 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6125 */
6126 void
6127 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6128 {
6129 MonoInst *fconv;
6130 int dreg, src_opcode;
6131
6132 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6133 return;
6134
6135 switch (src_opcode = ins->opcode) {
6136 case OP_FCONV_TO_I1:
6137 case OP_FCONV_TO_U1:
6138 case OP_FCONV_TO_I2:
6139 case OP_FCONV_TO_U2:
6140 case OP_FCONV_TO_I4:
6141 case OP_FCONV_TO_I:
6142 break;
6143 default:
6144 return;
6145 }
6146
6147 /* dreg is the IREG and sreg1 is the FREG */
6148 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6149 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6150 fconv->sreg1 = ins->sreg1;
6151 fconv->dreg = mono_alloc_ireg (cfg);
6152 fconv->type = STACK_VTYPE;
6153 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6154
6155 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6156
6157 dreg = ins->dreg;
6158 NULLIFY_INS (ins);
6159 ins->opcode = OP_XCONV_R8_TO_I4;
6160
6161 ins->klass = mono_defaults.int32_class;
6162 ins->sreg1 = fconv->dreg;
6163 ins->dreg = dreg;
6164 ins->type = STACK_I4;
6165 ins->backend.source_opcode = src_opcode;
6166 }
6167
6168 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6169
6170 void
6171 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6172 {
6173 MonoInst *ins;
6174 int vreg;
6175
6176 if (long_ins->opcode == OP_LNEG) {
6177 ins = long_ins;
6178 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6179 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6180 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6181 NULLIFY_INS (ins);
6182 return;
6183 }
6184
6185 #ifdef MONO_ARCH_SIMD_INTRINSICS
6186
6187 if (!(cfg->opt & MONO_OPT_SIMD))
6188 return;
6189
6190 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6191 switch (long_ins->opcode) {
6192 case OP_EXTRACT_I8:
6193 vreg = long_ins->sreg1;
6194
6195 if (long_ins->inst_c0) {
6196 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6197 ins->klass = long_ins->klass;
6198 ins->sreg1 = long_ins->sreg1;
6199 ins->inst_c0 = 2;
6200 ins->type = STACK_VTYPE;
6201 ins->dreg = vreg = alloc_ireg (cfg);
6202 MONO_ADD_INS (cfg->cbb, ins);
6203 }
6204
6205 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6206 ins->klass = mono_defaults.int32_class;
6207 ins->sreg1 = vreg;
6208 ins->type = STACK_I4;
6209 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6210 MONO_ADD_INS (cfg->cbb, ins);
6211
6212 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6213 ins->klass = long_ins->klass;
6214 ins->sreg1 = long_ins->sreg1;
6215 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6216 ins->type = STACK_VTYPE;
6217 ins->dreg = vreg = alloc_ireg (cfg);
6218 MONO_ADD_INS (cfg->cbb, ins);
6219
6220 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6221 ins->klass = mono_defaults.int32_class;
6222 ins->sreg1 = vreg;
6223 ins->type = STACK_I4;
6224 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6225 MONO_ADD_INS (cfg->cbb, ins);
6226
6227 long_ins->opcode = OP_NOP;
6228 break;
6229 case OP_INSERTX_I8_SLOW:
6230 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6231 ins->dreg = long_ins->dreg;
6232 ins->sreg1 = long_ins->dreg;
6233 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6234 ins->inst_c0 = long_ins->inst_c0 * 2;
6235 MONO_ADD_INS (cfg->cbb, ins);
6236
6237 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6238 ins->dreg = long_ins->dreg;
6239 ins->sreg1 = long_ins->dreg;
6240 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6241 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6242 MONO_ADD_INS (cfg->cbb, ins);
6243
6244 long_ins->opcode = OP_NOP;
6245 break;
6246 case OP_EXPAND_I8:
6247 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6248 ins->dreg = long_ins->dreg;
6249 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6250 ins->klass = long_ins->klass;
6251 ins->type = STACK_VTYPE;
6252 MONO_ADD_INS (cfg->cbb, ins);
6253
6254 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6255 ins->dreg = long_ins->dreg;
6256 ins->sreg1 = long_ins->dreg;
6257 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6258 ins->inst_c0 = 1;
6259 ins->klass = long_ins->klass;
6260 ins->type = STACK_VTYPE;
6261 MONO_ADD_INS (cfg->cbb, ins);
6262
6263 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6264 ins->dreg = long_ins->dreg;
6265 ins->sreg1 = long_ins->dreg;
6266 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6267 ins->klass = long_ins->klass;
6268 ins->type = STACK_VTYPE;
6269 MONO_ADD_INS (cfg->cbb, ins);
6270
6271 long_ins->opcode = OP_NOP;
6272 break;
6273 }
6274 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6275 }
6276
6277 /*
6278 * mono_aot_emit_load_got_addr:
6279 *
6280 * Emit code to load the got address.
6281 * On x86, the result is placed into EBX.
6282 */
6283 guint8*
6284 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6285 {
6286 x86_call_imm (code, 0);
6287 /*
6288 * The patch needs to point to the pop, since the GOT offset needs
6289 * to be added to that address.
6290 */
6291 if (cfg)
6292 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6293 else
6294 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6295 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6296 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6297
6298 set_code_cursor (cfg, code);
6299 return code;
6300 }
6301
6302 /*
6303 * mono_arch_emit_load_aotconst:
6304 *
6305 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6306 * TARGET from the mscorlib GOT in full-aot code.
6307 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6308 * EAX.
6309 */
6310 guint8*
6311 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6312 {
6313 /* Load the mscorlib got address */
6314 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (target_mgreg_t), 4);
6315 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6316 /* arch_emit_got_access () patches this */
6317 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6318
6319 return code;
6320 }
6321
6322 /* Can't put this into mini-x86.h */
6323 gpointer
6324 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6325
6326 GSList *
6327 mono_arch_get_trampolines (gboolean aot)
6328 {
6329 MonoTrampInfo *info;
6330 GSList *tramps = NULL;
6331
6332 mono_x86_get_signal_exception_trampoline (&info, aot);
6333
6334 tramps = g_slist_append (tramps, info);
6335
6336 return tramps;
6337 }
6338
6339 /* Soft Debug support */
6340 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6341
6342 /*
6343 * mono_arch_set_breakpoint:
6344 *
6345 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6346 * The location should contain code emitted by OP_SEQ_POINT.
6347 */
6348 void
6349 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6350 {
6351 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6352
6353 g_assert (code [0] == 0x90);
6354 x86_call_membase (code, X86_ECX, 0);
6355 }
6356
6357 /*
6358 * mono_arch_clear_breakpoint:
6359 *
6360 * Clear the breakpoint at IP.
6361 */
6362 void
6363 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6364 {
6365 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6366 int i;
6367
6368 for (i = 0; i < 2; ++i)
6369 x86_nop (code);
6370 }
6371
6372 /*
6373 * mono_arch_start_single_stepping:
6374 *
6375 * Start single stepping.
6376 */
6377 void
6378 mono_arch_start_single_stepping (void)
6379 {
6380 ss_trampoline = mini_get_single_step_trampoline ();
6381 }
6382
6383 /*
6384 * mono_arch_stop_single_stepping:
6385 *
6386 * Stop single stepping.
6387 */
6388 void
6389 mono_arch_stop_single_stepping (void)
6390 {
6391 ss_trampoline = NULL;
6392 }
6393
6394 /*
6395 * mono_arch_is_single_step_event:
6396 *
6397 * Return whenever the machine state in SIGCTX corresponds to a single
6398 * step event.
6399 */
6400 gboolean
6401 mono_arch_is_single_step_event (void *info, void *sigctx)
6402 {
6403 /* We use soft breakpoints */
6404 return FALSE;
6405 }
6406
6407 gboolean
6408 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6409 {
6410 /* We use soft breakpoints */
6411 return FALSE;
6412 }
6413
6414 #define BREAKPOINT_SIZE 2
6415
6416 /*
6417 * mono_arch_skip_breakpoint:
6418 *
6419 * See mini-amd64.c for docs.
6420 */
6421 void
6422 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6423 {
6424 g_assert_not_reached ();
6425 }
6426
6427 /*
6428 * mono_arch_skip_single_step:
6429 *
6430 * See mini-amd64.c for docs.
6431 */
6432 void
6433 mono_arch_skip_single_step (MonoContext *ctx)
6434 {
6435 g_assert_not_reached ();
6436 }
6437
6438 /*
6439 * mono_arch_get_seq_point_info:
6440 *
6441 * See mini-amd64.c for docs.
6442 */
6443 SeqPointInfo*
6444 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6445 {
6446 NOT_IMPLEMENTED;
6447 return NULL;
6448 }
6449
6450 #endif
6451
6452 gboolean
6453 mono_arch_opcode_supported (int opcode)
6454 {
6455 switch (opcode) {
6456 case OP_ATOMIC_ADD_I4:
6457 case OP_ATOMIC_EXCHANGE_I4:
6458 case OP_ATOMIC_CAS_I4:
6459 case OP_ATOMIC_LOAD_I1:
6460 case OP_ATOMIC_LOAD_I2:
6461 case OP_ATOMIC_LOAD_I4:
6462 case OP_ATOMIC_LOAD_U1:
6463 case OP_ATOMIC_LOAD_U2:
6464 case OP_ATOMIC_LOAD_U4:
6465 case OP_ATOMIC_LOAD_R4:
6466 case OP_ATOMIC_LOAD_R8:
6467 case OP_ATOMIC_STORE_I1:
6468 case OP_ATOMIC_STORE_I2:
6469 case OP_ATOMIC_STORE_I4:
6470 case OP_ATOMIC_STORE_U1:
6471 case OP_ATOMIC_STORE_U2:
6472 case OP_ATOMIC_STORE_U4:
6473 case OP_ATOMIC_STORE_R4:
6474 case OP_ATOMIC_STORE_R8:
6475 return TRUE;
6476 default:
6477 return FALSE;
6478 }
6479 }
6480
6481 CallInfo*
6482 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6483 {
6484 return get_call_info (mp, sig);
6485 }
6486
6487 gpointer
6488 mono_arch_load_function (MonoJitICallId jit_icall_id)
6489 {
6490 gpointer target = NULL;
6491 switch (jit_icall_id) {
6492 #undef MONO_AOT_ICALL
6493 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
6494 MONO_AOT_ICALL (mono_x86_start_gsharedvt_call)
6495 MONO_AOT_ICALL (mono_x86_throw_corlib_exception)
6496 MONO_AOT_ICALL (mono_x86_throw_exception)
6497 }
6498 return target;
6499 }
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