5 #ifndef __MONO_MINI_MIPS_H__
6 #define __MONO_MINI_MIPS_H__
9 #include <mono/arch/mips/mips-codegen.h>
10 #include <mono/utils/mono-context.h>
12 #if _MIPS_SIM == _ABIO32
13 /* o32 fully supported */
14 #elif _MIPS_SIM == _ABIN32
15 /* n32 under development */
16 #warning "MIPS using n32 - under development"
18 /* o64 not supported */
19 /* n64 not supported */
20 #error "MIPS unsupported ABI"
24 #define MONO_ARCH_CPU_SPEC mono_mips_desc
26 #define MONO_MAX_IREGS 32
27 #define MONO_MAX_FREGS 32
29 #define MONO_SAVED_GREGS 32
30 #define MONO_SAVED_FREGS 32
33 #if SIZEOF_REGISTER == 4
36 typedef gfloat mips_freg
;
38 #elif SIZEOF_REGISTER == 8
42 typedef gdouble mips_freg
;
45 #error Unknown REGISTER_SIZE
49 * at and t0 used internally
50 * v0, v1 aren't here for clarity reasons
51 * a0, a1, a2, a3 are for arguments
52 * Use t9 for indirect calls to match the ABI
55 #define MIPS_V_REGS ((1 << mips_v0) | \
57 #if _MIPS_SIM == _ABIO32
58 #define MIPS_T_REGS ((1 << mips_t0) | \
66 #elif _MIPS_SIM == _ABIN32
67 #define MIPS_T_REGS ((1 << mips_t0) | \
74 #define MIPS_S_REGS ((1 << mips_s0) | \
83 #if _MIPS_SIM == _ABIO32
84 #define MIPS_A_REGS ((1 << mips_a0) | \
88 #elif _MIPS_SIM == _ABIN32
89 #define MIPS_A_REGS ((1 << mips_a0) | \
99 #define mips_temp mips_t8
101 #define MONO_ARCH_CALLEE_REGS (MIPS_T_REGS | MIPS_V_REGS | MIPS_A_REGS)
102 #define MONO_ARCH_CALLEE_SAVED_REGS MIPS_S_REGS
103 #define MIPS_ARG_REGS MIPS_A_REGS
106 #define MIPS_FP_PAIR(reg) ((1 << (reg)) | (1 << ((reg)+1)))
108 /* Only put the even regs in */
109 #define MIPS_FP_PAIR(reg) (1 << (reg))
112 #if _MIPS_SIM == _ABIO32
113 #define MONO_ARCH_CALLEE_FREGS (MIPS_FP_PAIR(mips_f0) | \
114 MIPS_FP_PAIR(mips_f2) | \
115 MIPS_FP_PAIR(mips_f4) | \
116 MIPS_FP_PAIR(mips_f6) | \
117 MIPS_FP_PAIR(mips_f8) | \
118 MIPS_FP_PAIR(mips_f10) | \
119 MIPS_FP_PAIR(mips_f12) | \
120 MIPS_FP_PAIR(mips_f14) | \
121 MIPS_FP_PAIR(mips_f16) | \
122 MIPS_FP_PAIR(mips_f18))
124 #define MONO_ARCH_CALLEE_SAVED_FREGS (MIPS_FP_PAIR(mips_f20) | \
125 MIPS_FP_PAIR(mips_f22) | \
126 MIPS_FP_PAIR(mips_f24) | \
127 MIPS_FP_PAIR(mips_f26) | \
128 MIPS_FP_PAIR(mips_f28) | \
129 MIPS_FP_PAIR(mips_f30))
130 #elif _MIPS_SIM == _ABIN32
131 #define MONO_ARCH_CALLEE_FREGS (MIPS_FP_PAIR(mips_f0) | \
132 MIPS_FP_PAIR(mips_f1) | \
133 MIPS_FP_PAIR(mips_f2) | \
134 MIPS_FP_PAIR(mips_f3) | \
135 MIPS_FP_PAIR(mips_f4) | \
136 MIPS_FP_PAIR(mips_f5) | \
137 MIPS_FP_PAIR(mips_f6) | \
138 MIPS_FP_PAIR(mips_f7) | \
139 MIPS_FP_PAIR(mips_f8) | \
140 MIPS_FP_PAIR(mips_f9) | \
141 MIPS_FP_PAIR(mips_f10) | \
142 MIPS_FP_PAIR(mips_f11) | \
143 MIPS_FP_PAIR(mips_f12) | \
144 MIPS_FP_PAIR(mips_f13) | \
145 MIPS_FP_PAIR(mips_f14) | \
146 MIPS_FP_PAIR(mips_f15) | \
147 MIPS_FP_PAIR(mips_f16) | \
148 MIPS_FP_PAIR(mips_f17) | \
149 MIPS_FP_PAIR(mips_f18) | \
150 MIPS_FP_PAIR(mips_f19))
152 #define MONO_ARCH_CALLEE_SAVED_FREGS (MIPS_FP_PAIR(mips_f20) | \
153 MIPS_FP_PAIR(mips_f21) | \
154 MIPS_FP_PAIR(mips_f22) | \
155 MIPS_FP_PAIR(mips_f23) | \
156 MIPS_FP_PAIR(mips_f24) | \
157 MIPS_FP_PAIR(mips_f25) | \
158 MIPS_FP_PAIR(mips_f26) | \
159 MIPS_FP_PAIR(mips_f27) | \
160 MIPS_FP_PAIR(mips_f28) | \
161 MIPS_FP_PAIR(mips_f29) | \
162 MIPS_FP_PAIR(mips_f30) | \
163 MIPS_FP_PAIR(mips_f31))
166 #define mips_ftemp mips_f18
168 #define MONO_ARCH_USE_FPSTACK FALSE
170 /* Parameters used by the register allocator */
172 /* On Mips, for regpairs, the lower-numbered reg is most significant
173 * This is true in both big and little endian
176 #if G_BYTE_ORDER == G_LITTLE_ENDIAN
177 #define RET_REG1 mips_v0
178 #define RET_REG2 mips_v1
180 #define RET_REG1 mips_v1
181 #define RET_REG2 mips_v0
184 #define MONO_ARCH_INST_SREG2_MASK(ins) (0)
185 #define MONO_ARCH_INST_IS_REGPAIR(desc) ((desc) == 'V' || (desc) == 'l')
186 #define MONO_ARCH_INST_REGPAIR_REG2(desc,hreg1) (((desc) == 'l') ? ((hreg1) + 1) : (((desc) == 'V') ? RET_REG2 : -1))
187 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc == 'f') || (desc == 'g'))
189 // This define is called to get specific dest register as defined
190 // by md file (letter after "dest"). Overwise return -1
192 #define MONO_ARCH_INST_FIXED_REG(desc) (((desc) == '0') ? mips_zero : (((desc) == 'a') ? mips_at : ((((desc) == 'v')) ? mips_v0 : (((desc) == 'V') ? RET_REG1 : (((desc) == 'g') ? mips_f0 : -1)))))
194 #define MONO_ARCH_FRAME_ALIGNMENT 8
196 /* fixme: align to 16byte instead of 32byte (we align to 32byte to get
197 * reproduceable results for benchmarks */
198 #define MONO_ARCH_CODE_ALIGNMENT 32
200 void mips_patch (guint32
*code
, guint32 target
);
202 #define MIPS_LMF_MAGIC1 0xa5a5a5a5
203 #define MIPS_LMF_MAGIC2 0xc3c3c3c3
205 /* Registers saved in lmf->iregs */
206 #define MIPS_LMF_IREGMASK (0xffffffff & ~((1 << mips_zero) | (1 << mips_at) | MONO_ARCH_CALLEE_REGS))
209 gpointer previous_lmf
;
213 host_mgreg_t iregs
[MONO_SAVED_GREGS
];
214 mips_freg fregs
[MONO_SAVED_FREGS
];
218 typedef struct MonoCompileArch
{
222 guint local_alloc_offset
;
223 guint spillvar_offset
;
224 guint spillvar_offset_float
;
225 guint tracing_offset
;
228 gboolean omit_fp_computed
;
231 #if SIZEOF_REGISTER == 4
232 #define MONO_ARCH_EMULATE_FCONV_TO_I8 1
233 #define MONO_ARCH_EMULATE_LCONV_TO_R8 1
234 #define MONO_ARCH_EMULATE_LCONV_TO_R4 1
235 #define MONO_ARCH_EMULATE_LCONV_TO_R8_UN 1
236 #define MONO_ARCH_EMULATE_FREM 1
239 #define MONO_ARCH_EMULATE_FCONV_TO_U8 1
242 * mips backend misses some instructions that enable emitting of optimal
243 * code on other targets and, additionally, the register allocator gets
244 * confused by this optimization, failing to allocate all hw regs.
246 #if SIZEOF_REGISTER == 4
247 #define MONO_ARCH_NO_DIV_WITH_MUL
250 #if SIZEOF_REGISTER == 8
251 #define MONO_ARCH_NO_EMULATE_LONG_MUL_OPTS
254 #define MIPS_RET_ADDR_OFFSET (-sizeof (target_mgreg_t))
255 #define MIPS_FP_ADDR_OFFSET (-8)
256 #define MIPS_STACK_ALIGNMENT 16
257 #define MIPS_STACK_PARAM_OFFSET 16 /* from sp to first parameter */
258 #define MIPS_MINIMAL_STACK_SIZE (8 * sizeof (target_mgreg_t))
259 #define MIPS_EXTRA_STACK_SIZE 16 /* from last parameter to top of frame */
261 #if _MIPS_SIM == _ABIO32
262 #define MIPS_FIRST_ARG_REG mips_a0
263 #define MIPS_LAST_ARG_REG mips_a3
264 #define MIPS_FIRST_FPARG_REG mips_f12
265 #define MIPS_LAST_FPARG_REG mips_f14
266 #elif _MIPS_SIM == _ABIN32
267 #define MIPS_FIRST_ARG_REG mips_a0
268 #define MIPS_LAST_ARG_REG mips_t3
269 #define MIPS_FIRST_FPARG_REG mips_f12
270 #define MIPS_LAST_FPARG_REG mips_f19
273 #define MONO_ARCH_IMT_REG mips_t0
275 #define MONO_ARCH_VTABLE_REG mips_a0
276 #define MONO_ARCH_RGCTX_REG MONO_ARCH_IMT_REG
278 #define MONO_ARCH_HAVE_DECOMPOSE_OPTS 1
279 #define MONO_ARCH_HAVE_DECOMPOSE_LONG_OPTS 1
281 #define MONO_ARCH_HAVE_GENERALIZED_IMT_TRAMPOLINE 1
282 #define MONO_ARCH_SOFT_DEBUG_SUPPORTED 1
283 #define MONO_ARCH_HAVE_SETUP_RESUME_FROM_SIGNAL_HANDLER_CTX 1
284 #define MONO_ARCH_GSHARED_SUPPORTED 1
286 /* set the next to 0 once inssel-mips.brg is updated */
287 #define MIPS_PASS_STRUCTS_BY_VALUE 1
289 #define MONO_ARCH_USE_SIGACTION
290 #define MONO_ARCH_NEED_DIV_CHECK 1
291 #define MONO_ARCH_NO_IOV_CHECK 1
293 // Does the ABI have a volatile non-parameter register, so tailcall
294 // can pass context to generics or interfaces?
295 #define MONO_ARCH_HAVE_VOLATILE_NON_PARAM_REGISTER 0 // FIXME?
297 #define MIPS_NUM_REG_ARGS (MIPS_LAST_ARG_REG-MIPS_FIRST_ARG_REG+1)
298 #define MIPS_NUM_REG_FPARGS (MIPS_LAST_FPARG_REG-MIPS_FIRST_FPARG_REG+1)
302 unsigned long at
; /* assembler temp */
303 unsigned long v0
; /* return values */
305 unsigned long a0
; /* 4 - func arguments */
309 unsigned long t0
; /* 8 temporaries */
317 unsigned long s0
; /* 16 calle saved */
325 unsigned long t8
; /* 24 temps */
326 unsigned long t9
; /* 25 temp / pic call-through register */
327 unsigned long k0
; /* 26 kernel-reserved */
329 unsigned long gp
; /* 28 */
330 unsigned long sp
; /* stack pointer */
331 unsigned long fp
; /* frame pointer */
332 unsigned long ra
; /* return address */
333 } MonoMipsStackFrame
;
335 #define MONO_INIT_CONTEXT_FROM_FUNC(ctx,func) do { \
336 MONO_CONTEXT_SET_BP ((ctx), __builtin_frame_address (0)); \
337 MONO_CONTEXT_SET_SP ((ctx), __builtin_frame_address (0)); \
338 MONO_CONTEXT_SET_IP ((ctx), (func)); \
341 #define MONO_ARCH_INIT_TOP_LMF_ENTRY(lmf)
343 /* re-attaches with gdb - sometimes causes executable to hang */
344 #undef HAVE_BACKTRACE_SYMBOLS
346 #undef DEBUG_EXCEPTIONS
348 #define MONO_EMIT_NEW_MIPS_COND_EXC(cfg,cond,sr1,sr2,name) do { \
350 MONO_INST_NEW ((cfg), (inst), cond); \
351 inst->inst_p1 = (char*)name; \
354 MONO_ADD_INS ((cfg)->cbb, inst); \
357 #ifndef MONO_EMIT_NEW_COMPARE_EXC
358 #define MONO_EMIT_NEW_COMPARE_EXC(cfg, cmp_op, sreg1, sreg2, exc) do { \
359 switch (OP_MIPS_COND_EXC_##cmp_op) { \
360 case OP_MIPS_COND_EXC_EQ: \
361 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, sreg1, sreg2, exc); \
363 case OP_MIPS_COND_EXC_NE_UN: \
364 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, sreg1, sreg2, exc); \
366 case OP_MIPS_COND_EXC_GT: \
367 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
368 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
370 case OP_MIPS_COND_EXC_GT_UN: \
371 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
372 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
374 case OP_MIPS_COND_EXC_LE: \
375 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
376 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
378 case OP_MIPS_COND_EXC_LE_UN: \
379 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
380 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
382 case OP_MIPS_COND_EXC_LT: \
383 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg1, sreg2); \
384 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
386 case OP_MIPS_COND_EXC_LT_UN: \
387 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
388 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
391 g_warning ("unknown comparison %s\n", #cmp_op); \
392 g_assert_not_reached (); \
397 #ifndef MONO_EMIT_NEW_COMPARE_IMM_EXC
398 #define MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
401 cmp_reg = mips_zero; \
405 MONO_EMIT_NEW_ICONST (cfg, cmp_reg, (imm)); \
407 MONO_EMIT_NEW_COMPARE_EXC (cfg, cmp_op, sreg1, cmp_reg, exc); \
411 #ifndef MONO_EMIT_NEW_ICOMPARE_IMM_EXC
412 #define MONO_EMIT_NEW_ICOMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
413 MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc); \
424 guint8
*mips_emit_load_const (guint8
*code
, int dreg
, target_mgreg_t v
);
426 #endif /* __MONO_MINI_MIPS_H__ */