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Reorganize the scan-minor-copy/scan.h header files a bit. Move the nursery copying...
[mono-project.git] / mono / mini / mini-arm.c
blob762a178c195873d3931ea8aa52a4b4dd5c3fbfa7
1 /*
2 * mini-arm.c: ARM backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 *
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 */
12 #include "mini.h"
13 #include <string.h>
14
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
18
19 #include "mini-arm.h"
20 #include "cpu-arm.h"
21 #include "trace.h"
22 #include "ir-emit.h"
23 #include "debugger-agent.h"
24 #include "mini-gc.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
27
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
30 #endif
31
32 #ifdef ARM_FPU_VFP_HARD
33 #define ARM_FPU_VFP 1
34 #endif
35
36 #ifdef ARM_FPU_FPA
37 #define IS_FPA 1
38 #else
39 #define IS_FPA 0
40 #endif
41
42 #ifdef ARM_FPU_VFP
43 #define IS_VFP 1
44 #else
45 #define IS_VFP 0
46 #endif
47
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
50 #else
51 #define IS_SOFT_FLOAT 0
52 #endif
53
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
55
56 static gint lmf_tls_offset = -1;
57 static gint lmf_addr_tls_offset = -1;
58
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
63
64 static int v5_supported = 0;
65 static int v6_supported = 0;
66 static int v7_supported = 0;
67 static int thumb_supported = 0;
68 /*
69 * Whenever to use the ARM EABI
70 */
71 static int eabi_supported = 0;
72
73 /*
74 * Whenever we are on arm/darwin aka the iphone.
75 */
76 static int darwin = 0;
77 /*
78 * Whenever to use the iphone ABI extensions:
79 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
80 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
81 * This is required for debugging/profiling tools to work, but it has some overhead so it should
82 * only be turned on in debug builds.
83 */
84 static int iphone_abi = 0;
85
86 /*
87 * The FPU we are generating code for. This is NOT runtime configurable right now,
88 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
89 */
90 static MonoArmFPU arm_fpu;
91
92 static int i8_align;
93
94 static volatile int ss_trigger_var = 0;
95
96 static gpointer single_step_func_wrapper;
97 static gpointer breakpoint_func_wrapper;
98
99 /*
100 * The code generated for sequence points reads from this location, which is
101 * made read-only when single stepping is enabled.
102 */
103 static gpointer ss_trigger_page;
104
105 /* Enabled breakpoints read from this trigger page */
106 static gpointer bp_trigger_page;
107
108 /* Structure used by the sequence points in AOTed code */
109 typedef struct {
110 gpointer ss_trigger_page;
111 gpointer bp_trigger_page;
112 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
113 } SeqPointInfo;
114
115 /*
116 * TODO:
117 * floating point support: on ARM it is a mess, there are at least 3
118 * different setups, each of which binary incompat with the other.
119 * 1) FPA: old and ugly, but unfortunately what current distros use
120 * the double binary format has the two words swapped. 8 double registers.
121 * Implemented usually by kernel emulation.
122 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
123 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
124 * 3) VFP: the new and actually sensible and useful FP support. Implemented
125 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
126 *
127 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
128 */
129 int mono_exc_esp_offset = 0;
130
131 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
132 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
133 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
134
135 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
136 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
137 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
138
139 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
140 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
141 #define DEBUG_IMT 0
142
143 /* A variant of ARM_LDR_IMM which can handle large offsets */
144 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
145 if (arm_is_imm12 ((offset))) { \
146 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
147 } else { \
148 g_assert ((scratch_reg) != (basereg)); \
149 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
150 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
151 } \
152 } while (0)
153
154 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
155 if (arm_is_imm12 ((offset))) { \
156 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
157 } else { \
158 g_assert ((scratch_reg) != (basereg)); \
159 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
160 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
161 } \
162 } while (0)
163
164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165
166 const char*
167 mono_arch_regname (int reg)
168 {
169 static const char * rnames[] = {
170 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
171 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
172 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
173 "arm_pc"
174 };
175 if (reg >= 0 && reg < 16)
176 return rnames [reg];
177 return "unknown";
178 }
179
180 const char*
181 mono_arch_fregname (int reg)
182 {
183 static const char * rnames[] = {
184 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
185 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
186 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
187 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
188 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
189 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
190 "arm_f30", "arm_f31"
191 };
192 if (reg >= 0 && reg < 32)
193 return rnames [reg];
194 return "unknown";
195 }
196
197 #ifndef DISABLE_JIT
198
199 static guint8*
200 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
201 {
202 int imm8, rot_amount;
203 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
204 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
205 return code;
206 }
207 g_assert (dreg != sreg);
208 code = mono_arm_emit_load_imm (code, dreg, imm);
209 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
210 return code;
211 }
212
213 static guint8*
214 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
215 {
216 /* we can use r0-r3, since this is called only for incoming args on the stack */
217 if (size > sizeof (gpointer) * 4) {
218 guint8 *start_loop;
219 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
220 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
221 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
222 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
223 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
224 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
225 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
226 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
227 ARM_B_COND (code, ARMCOND_NE, 0);
228 arm_patch (code - 4, start_loop);
229 return code;
230 }
231 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
232 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
233 while (size >= 4) {
234 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
235 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
236 doffset += 4;
237 soffset += 4;
238 size -= 4;
239 }
240 } else if (size) {
241 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
242 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
243 doffset = soffset = 0;
244 while (size >= 4) {
245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
246 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
247 doffset += 4;
248 soffset += 4;
249 size -= 4;
250 }
251 }
252 g_assert (size == 0);
253 return code;
254 }
255
256 static guint8*
257 emit_call_reg (guint8 *code, int reg)
258 {
259 if (v5_supported) {
260 ARM_BLX_REG (code, reg);
261 } else {
262 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
263 if (thumb_supported)
264 ARM_BX (code, reg);
265 else
266 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
267 }
268 return code;
269 }
270
271 static guint8*
272 emit_call_seq (MonoCompile *cfg, guint8 *code)
273 {
274 if (cfg->method->dynamic) {
275 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
276 ARM_B (code, 0);
277 *(gpointer*)code = NULL;
278 code += 4;
279 code = emit_call_reg (code, ARMREG_IP);
280 } else {
281 ARM_BL (code, 0);
282 }
283 return code;
284 }
285
286 static guint8*
287 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
288 {
289 switch (ins->opcode) {
290 case OP_FCALL:
291 case OP_FCALL_REG:
292 case OP_FCALL_MEMBASE:
293 if (IS_FPA) {
294 if (ins->dreg != ARM_FPA_F0)
295 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
296 } else if (IS_VFP) {
297 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
298 ARM_FMSR (code, ins->dreg, ARMREG_R0);
299 ARM_CVTS (code, ins->dreg, ins->dreg);
300 } else {
301 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
302 }
303 }
304 break;
305 }
306
307 return code;
308 }
309
310 /*
311 * emit_save_lmf:
312 *
313 * Emit code to push an LMF structure on the LMF stack.
314 * On arm, this is intermixed with the initialization of other fields of the structure.
315 */
316 static guint8*
317 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
318 {
319 gboolean get_lmf_fast = FALSE;
320 int i;
321
322 #ifdef HAVE_AEABI_READ_TP
323 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
324
325 if (lmf_addr_tls_offset != -1) {
326 get_lmf_fast = TRUE;
327
328 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
329 (gpointer)"__aeabi_read_tp");
330 code = emit_call_seq (cfg, code);
331
332 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
333 get_lmf_fast = TRUE;
334 }
335 #endif
336 if (!get_lmf_fast) {
337 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
338 (gpointer)"mono_get_lmf_addr");
339 code = emit_call_seq (cfg, code);
340 }
341 /* we build the MonoLMF structure on the stack - see mini-arm.h */
342 /* lmf_offset is the offset from the previous stack pointer,
343 * alloc_size is the total stack space allocated, so the offset
344 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
345 * The pointer to the struct is put in r1 (new_lmf).
346 * ip is used as scratch
347 * The callee-saved registers are already in the MonoLMF structure
348 */
349 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
350 /* r0 is the result from mono_get_lmf_addr () */
351 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
352 /* new_lmf->previous_lmf = *lmf_addr */
353 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
354 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
355 /* *(lmf_addr) = r1 */
356 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
357 /* Skip method (only needed for trampoline LMF frames) */
358 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
359 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
360 /* save the current IP */
361 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
362 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
363
364 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
365 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
366
367 return code;
368 }
369
370 /*
371 * emit_save_lmf:
372 *
373 * Emit code to pop an LMF structure from the LMF stack.
374 */
375 static guint8*
376 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
377 {
378 int basereg, offset;
379
380 if (lmf_offset < 32) {
381 basereg = cfg->frame_reg;
382 offset = lmf_offset;
383 } else {
384 basereg = ARMREG_R2;
385 offset = 0;
386 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
387 }
388
389 /* ip = previous_lmf */
390 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
391 /* lr = lmf_addr */
392 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
393 /* *(lmf_addr) = previous_lmf */
394 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
395
396 return code;
397 }
398
399 #endif /* #ifndef DISABLE_JIT */
400
401 /*
402 * mono_arch_get_argument_info:
403 * @csig: a method signature
404 * @param_count: the number of parameters to consider
405 * @arg_info: an array to store the result infos
406 *
407 * Gathers information on parameters such as size, alignment and
408 * padding. arg_info should be large enought to hold param_count + 1 entries.
409 *
410 * Returns the size of the activation frame.
411 */
412 int
413 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
414 {
415 int k, frame_size = 0;
416 guint32 size, align, pad;
417 int offset = 8;
418
419 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
420 frame_size += sizeof (gpointer);
421 offset += 4;
422 }
423
424 arg_info [0].offset = offset;
425
426 if (csig->hasthis) {
427 frame_size += sizeof (gpointer);
428 offset += 4;
429 }
430
431 arg_info [0].size = frame_size;
432
433 for (k = 0; k < param_count; k++) {
434 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
435
436 /* ignore alignment for now */
437 align = 1;
438
439 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
440 arg_info [k].pad = pad;
441 frame_size += size;
442 arg_info [k + 1].pad = 0;
443 arg_info [k + 1].size = size;
444 offset += pad;
445 arg_info [k + 1].offset = offset;
446 offset += size;
447 }
448
449 align = MONO_ARCH_FRAME_ALIGNMENT;
450 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
451 arg_info [k].pad = pad;
452
453 return frame_size;
454 }
455
456 #define MAX_ARCH_DELEGATE_PARAMS 3
457
458 static gpointer
459 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
460 {
461 guint8 *code, *start;
462
463 if (has_target) {
464 start = code = mono_global_codeman_reserve (12);
465
466 /* Replace the this argument with the target */
467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
468 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
469 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
470
471 g_assert ((code - start) <= 12);
472
473 mono_arch_flush_icache (start, 12);
474 } else {
475 int size, i;
476
477 size = 8 + param_count * 4;
478 start = code = mono_global_codeman_reserve (size);
479
480 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
481 /* slide down the arguments */
482 for (i = 0; i < param_count; ++i) {
483 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
484 }
485 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
486
487 g_assert ((code - start) <= size);
488
489 mono_arch_flush_icache (start, size);
490 }
491
492 if (code_size)
493 *code_size = code - start;
494
495 return start;
496 }
497
498 /*
499 * mono_arch_get_delegate_invoke_impls:
500 *
501 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
502 * trampolines.
503 */
504 GSList*
505 mono_arch_get_delegate_invoke_impls (void)
506 {
507 GSList *res = NULL;
508 guint8 *code;
509 guint32 code_len;
510 int i;
511
512 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
513 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
514
515 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
516 code = get_delegate_invoke_impl (FALSE, i, &code_len);
517 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
518 }
519
520 return res;
521 }
522
523 gpointer
524 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
525 {
526 guint8 *code, *start;
527
528 /* FIXME: Support more cases */
529 if (MONO_TYPE_ISSTRUCT (sig->ret))
530 return NULL;
531
532 if (has_target) {
533 static guint8* cached = NULL;
534 mono_mini_arch_lock ();
535 if (cached) {
536 mono_mini_arch_unlock ();
537 return cached;
538 }
539
540 if (mono_aot_only)
541 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
542 else
543 start = get_delegate_invoke_impl (TRUE, 0, NULL);
544 cached = start;
545 mono_mini_arch_unlock ();
546 return cached;
547 } else {
548 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
549 int i;
550
551 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
552 return NULL;
553 for (i = 0; i < sig->param_count; ++i)
554 if (!mono_is_regsize_var (sig->params [i]))
555 return NULL;
556
557 mono_mini_arch_lock ();
558 code = cache [sig->param_count];
559 if (code) {
560 mono_mini_arch_unlock ();
561 return code;
562 }
563
564 if (mono_aot_only) {
565 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
566 start = mono_aot_get_trampoline (name);
567 g_free (name);
568 } else {
569 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
570 }
571 cache [sig->param_count] = start;
572 mono_mini_arch_unlock ();
573 return start;
574 }
575
576 return NULL;
577 }
578
579 gpointer
580 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
581 {
582 return (gpointer)regs [ARMREG_R0];
583 }
584
585 /*
586 * Initialize the cpu to execute managed code.
587 */
588 void
589 mono_arch_cpu_init (void)
590 {
591 #if defined(__ARM_EABI__)
592 eabi_supported = TRUE;
593 #endif
594 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
595 i8_align = 4;
596 #else
597 i8_align = __alignof__ (gint64);
598 #endif
599 }
600
601 static gpointer
602 create_function_wrapper (gpointer function)
603 {
604 guint8 *start, *code;
605
606 start = code = mono_global_codeman_reserve (96);
607
608 /*
609 * Construct the MonoContext structure on the stack.
610 */
611
612 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
613
614 /* save ip, lr and pc into their correspodings ctx.regs slots. */
615 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
616 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
617 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
618
619 /* save r0..r10 and fp */
620 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
621 ARM_STM (code, ARMREG_IP, 0x0fff);
622
623 /* now we can update fp. */
624 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
625
626 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
627 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
628 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
629 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
630
631 /* make ctx.eip hold the address of the call. */
632 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
633 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
634
635 /* r0 now points to the MonoContext */
636 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
637
638 /* call */
639 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
640 ARM_B (code, 0);
641 *(gpointer*)code = function;
642 code += 4;
643 ARM_BLX_REG (code, ARMREG_IP);
644
645 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
646 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
647 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
648 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
649
650 /* make ip point to the regs array, then restore everything, including pc. */
651 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
652 ARM_LDM (code, ARMREG_IP, 0xffff);
653
654 mono_arch_flush_icache (start, code - start);
655
656 return start;
657 }
658
659 /*
660 * Initialize architecture specific code.
661 */
662 void
663 mono_arch_init (void)
664 {
665 InitializeCriticalSection (&mini_arch_mutex);
666
667 if (mini_get_debug_options ()->soft_breakpoints) {
668 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
669 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
670 } else {
671 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
672 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
673 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
674 }
675
676 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
677 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
678 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
679
680 #ifdef ARM_FPU_FPA
681 arm_fpu = MONO_ARM_FPU_FPA;
682 #elif defined(ARM_FPU_VFP_HARD)
683 arm_fpu = MONO_ARM_FPU_VFP_HARD;
684 #elif defined(ARM_FPU_VFP)
685 arm_fpu = MONO_ARM_FPU_VFP;
686 #else
687 arm_fpu = MONO_ARM_FPU_NONE;
688 #endif
689 }
690
691 /*
692 * Cleanup architecture specific code.
693 */
694 void
695 mono_arch_cleanup (void)
696 {
697 }
698
699 /*
700 * This function returns the optimizations supported on this cpu.
701 */
702 guint32
703 mono_arch_cpu_optimizations (guint32 *exclude_mask)
704 {
705 guint32 opts = 0;
706 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
707 if (cpu_arch != NULL) {
708 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
709 if (strncmp (cpu_arch, "armv", 4) == 0) {
710 v5_supported = cpu_arch [4] >= '5';
711 v6_supported = cpu_arch [4] >= '6';
712 v7_supported = cpu_arch [4] >= '7';
713 }
714 } else {
715 #if __APPLE__
716 thumb_supported = TRUE;
717 v5_supported = TRUE;
718 darwin = TRUE;
719 iphone_abi = TRUE;
720 #else
721 char buf [512];
722 char *line;
723 FILE *file = fopen ("/proc/cpuinfo", "r");
724 if (file) {
725 while ((line = fgets (buf, 512, file))) {
726 if (strncmp (line, "Processor", 9) == 0) {
727 char *ver = strstr (line, "(v");
728 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
729 v5_supported = TRUE;
730 if (ver && (ver [2] == '6' || ver [2] == '7'))
731 v6_supported = TRUE;
732 if (ver && (ver [2] == '7'))
733 v7_supported = TRUE;
734 continue;
735 }
736 if (strncmp (line, "Features", 8) == 0) {
737 char *th = strstr (line, "thumb");
738 if (th) {
739 thumb_supported = TRUE;
740 if (v5_supported)
741 break;
742 }
743 continue;
744 }
745 }
746 fclose (file);
747 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
748 }
749 #endif
750 }
751
752 /* no arm-specific optimizations yet */
753 *exclude_mask = 0;
754 return opts;
755 }
756
757 /*
758 * This function test for all SIMD functions supported.
759 *
760 * Returns a bitmask corresponding to all supported versions.
761 *
762 */
763 guint32
764 mono_arch_cpu_enumerate_simd_versions (void)
765 {
766 /* SIMD is currently unimplemented */
767 return 0;
768 }
769
770
771 #ifndef DISABLE_JIT
772
773 static gboolean
774 is_regsize_var (MonoType *t) {
775 if (t->byref)
776 return TRUE;
777 t = mini_type_get_underlying_type (NULL, t);
778 switch (t->type) {
779 case MONO_TYPE_I4:
780 case MONO_TYPE_U4:
781 case MONO_TYPE_I:
782 case MONO_TYPE_U:
783 case MONO_TYPE_PTR:
784 case MONO_TYPE_FNPTR:
785 return TRUE;
786 case MONO_TYPE_OBJECT:
787 case MONO_TYPE_STRING:
788 case MONO_TYPE_CLASS:
789 case MONO_TYPE_SZARRAY:
790 case MONO_TYPE_ARRAY:
791 return TRUE;
792 case MONO_TYPE_GENERICINST:
793 if (!mono_type_generic_inst_is_valuetype (t))
794 return TRUE;
795 return FALSE;
796 case MONO_TYPE_VALUETYPE:
797 return FALSE;
798 }
799 return FALSE;
800 }
801
802 GList *
803 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
804 {
805 GList *vars = NULL;
806 int i;
807
808 for (i = 0; i < cfg->num_varinfo; i++) {
809 MonoInst *ins = cfg->varinfo [i];
810 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
811
812 /* unused vars */
813 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
814 continue;
815
816 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
817 continue;
818
819 /* we can only allocate 32 bit values */
820 if (is_regsize_var (ins->inst_vtype)) {
821 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
822 g_assert (i == vmv->idx);
823 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
824 }
825 }
826
827 return vars;
828 }
829
830 #define USE_EXTRA_TEMPS 0
831
832 GList *
833 mono_arch_get_global_int_regs (MonoCompile *cfg)
834 {
835 GList *regs = NULL;
836
837 mono_arch_compute_omit_fp (cfg);
838
839 /*
840 * FIXME: Interface calls might go through a static rgctx trampoline which
841 * sets V5, but it doesn't save it, so we need to save it ourselves, and
842 * avoid using it.
843 */
844 if (cfg->flags & MONO_CFG_HAS_CALLS)
845 cfg->uses_rgctx_reg = TRUE;
846
847 if (cfg->arch.omit_fp)
848 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
849 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
850 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
851 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
852 if (darwin)
853 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
854 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
855 else
856 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
857 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
858 /* V5 is reserved for passing the vtable/rgctx/IMT method */
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
860 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
861 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
862
863 return regs;
864 }
865
866 /*
867 * mono_arch_regalloc_cost:
868 *
869 * Return the cost, in number of memory references, of the action of
870 * allocating the variable VMV into a register during global register
871 * allocation.
872 */
873 guint32
874 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
875 {
876 /* FIXME: */
877 return 2;
878 }
879
880 #endif /* #ifndef DISABLE_JIT */
881
882 #ifndef __GNUC_PREREQ
883 #define __GNUC_PREREQ(maj, min) (0)
884 #endif
885
886 void
887 mono_arch_flush_icache (guint8 *code, gint size)
888 {
889 #ifdef MONO_CROSS_COMPILE
890 #elif __APPLE__
891 sys_icache_invalidate (code, size);
892 #elif __GNUC_PREREQ(4, 1)
893 __clear_cache (code, code + size);
894 #elif defined(PLATFORM_ANDROID)
895 const int syscall = 0xf0002;
896 __asm __volatile (
897 "mov r0, %0\n"
898 "mov r1, %1\n"
899 "mov r7, %2\n"
900 "mov r2, #0x0\n"
901 "svc 0x00000000\n"
902 :
903 : "r" (code), "r" (code + size), "r" (syscall)
904 : "r0", "r1", "r7", "r2"
905 );
906 #else
907 __asm __volatile ("mov r0, %0\n"
908 "mov r1, %1\n"
909 "mov r2, %2\n"
910 "swi 0x9f0002 @ sys_cacheflush"
911 : /* no outputs */
912 : "r" (code), "r" (code + size), "r" (0)
913 : "r0", "r1", "r3" );
914 #endif
915 }
916
917 typedef enum {
918 RegTypeNone,
919 RegTypeGeneral,
920 RegTypeIRegPair,
921 RegTypeBase,
922 RegTypeBaseGen,
923 RegTypeFP,
924 RegTypeStructByVal,
925 RegTypeStructByAddr
926 } ArgStorage;
927
928 typedef struct {
929 gint32 offset;
930 guint16 vtsize; /* in param area */
931 guint8 reg;
932 ArgStorage storage;
933 gint32 struct_size;
934 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
935 } ArgInfo;
936
937 typedef struct {
938 int nargs;
939 guint32 stack_usage;
940 gboolean vtype_retaddr;
941 /* The index of the vret arg in the argument list */
942 int vret_arg_index;
943 ArgInfo ret;
944 ArgInfo sig_cookie;
945 ArgInfo args [1];
946 } CallInfo;
947
948 #define DEBUG(a)
949
950 #ifndef __GNUC__
951 /*#define __alignof__(a) sizeof(a)*/
952 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
953 #endif
954
955 #define PARAM_REGS 4
956
957 static void inline
958 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
959 {
960 if (simple) {
961 if (*gr > ARMREG_R3) {
962 ainfo->offset = *stack_size;
963 ainfo->reg = ARMREG_SP; /* in the caller */
964 ainfo->storage = RegTypeBase;
965 *stack_size += 4;
966 } else {
967 ainfo->storage = RegTypeGeneral;
968 ainfo->reg = *gr;
969 }
970 } else {
971 gboolean split;
972
973 if (eabi_supported)
974 split = i8_align == 4;
975 else
976 split = TRUE;
977
978 if (*gr == ARMREG_R3 && split) {
979 /* first word in r3 and the second on the stack */
980 ainfo->offset = *stack_size;
981 ainfo->reg = ARMREG_SP; /* in the caller */
982 ainfo->storage = RegTypeBaseGen;
983 *stack_size += 4;
984 } else if (*gr >= ARMREG_R3) {
985 if (eabi_supported) {
986 /* darwin aligns longs to 4 byte only */
987 if (i8_align == 8) {
988 *stack_size += 7;
989 *stack_size &= ~7;
990 }
991 }
992 ainfo->offset = *stack_size;
993 ainfo->reg = ARMREG_SP; /* in the caller */
994 ainfo->storage = RegTypeBase;
995 *stack_size += 8;
996 } else {
997 if (eabi_supported) {
998 if (i8_align == 8 && ((*gr) & 1))
999 (*gr) ++;
1000 }
1001 ainfo->storage = RegTypeIRegPair;
1002 ainfo->reg = *gr;
1003 }
1004 (*gr) ++;
1005 }
1006 (*gr) ++;
1007 }
1008
1009 static CallInfo*
1010 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1011 {
1012 guint i, gr, pstart;
1013 int n = sig->hasthis + sig->param_count;
1014 MonoType *simpletype;
1015 guint32 stack_size = 0;
1016 CallInfo *cinfo;
1017 gboolean is_pinvoke = sig->pinvoke;
1018
1019 if (mp)
1020 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1021 else
1022 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1023
1024 cinfo->nargs = n;
1025 gr = ARMREG_R0;
1026
1027 /* FIXME: handle returning a struct */
1028 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1029 guint32 align;
1030
1031 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1032 cinfo->ret.storage = RegTypeStructByVal;
1033 } else {
1034 cinfo->vtype_retaddr = TRUE;
1035 }
1036 }
1037
1038 pstart = 0;
1039 n = 0;
1040 /*
1041 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1042 * the first argument, allowing 'this' to be always passed in the first arg reg.
1043 * Also do this if the first argument is a reference type, since virtual calls
1044 * are sometimes made using calli without sig->hasthis set, like in the delegate
1045 * invoke wrappers.
1046 */
1047 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1048 if (sig->hasthis) {
1049 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1050 } else {
1051 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1052 pstart = 1;
1053 }
1054 n ++;
1055 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1056 cinfo->vret_arg_index = 1;
1057 } else {
1058 /* this */
1059 if (sig->hasthis) {
1060 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1061 n ++;
1062 }
1063
1064 if (cinfo->vtype_retaddr)
1065 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1066 }
1067
1068 DEBUG(printf("params: %d\n", sig->param_count));
1069 for (i = pstart; i < sig->param_count; ++i) {
1070 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1071 /* Prevent implicit arguments and sig_cookie from
1072 being passed in registers */
1073 gr = ARMREG_R3 + 1;
1074 /* Emit the signature cookie just before the implicit arguments */
1075 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1076 }
1077 DEBUG(printf("param %d: ", i));
1078 if (sig->params [i]->byref) {
1079 DEBUG(printf("byref\n"));
1080 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1081 n++;
1082 continue;
1083 }
1084 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1085 switch (simpletype->type) {
1086 case MONO_TYPE_BOOLEAN:
1087 case MONO_TYPE_I1:
1088 case MONO_TYPE_U1:
1089 cinfo->args [n].size = 1;
1090 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1091 n++;
1092 break;
1093 case MONO_TYPE_CHAR:
1094 case MONO_TYPE_I2:
1095 case MONO_TYPE_U2:
1096 cinfo->args [n].size = 2;
1097 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1098 n++;
1099 break;
1100 case MONO_TYPE_I4:
1101 case MONO_TYPE_U4:
1102 cinfo->args [n].size = 4;
1103 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1104 n++;
1105 break;
1106 case MONO_TYPE_I:
1107 case MONO_TYPE_U:
1108 case MONO_TYPE_PTR:
1109 case MONO_TYPE_FNPTR:
1110 case MONO_TYPE_CLASS:
1111 case MONO_TYPE_OBJECT:
1112 case MONO_TYPE_STRING:
1113 case MONO_TYPE_SZARRAY:
1114 case MONO_TYPE_ARRAY:
1115 case MONO_TYPE_R4:
1116 cinfo->args [n].size = sizeof (gpointer);
1117 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1118 n++;
1119 break;
1120 case MONO_TYPE_GENERICINST:
1121 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1122 cinfo->args [n].size = sizeof (gpointer);
1123 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1124 n++;
1125 break;
1126 }
1127 /* Fall through */
1128 case MONO_TYPE_TYPEDBYREF:
1129 case MONO_TYPE_VALUETYPE: {
1130 gint size;
1131 int align_size;
1132 int nwords;
1133 guint32 align;
1134
1135 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1136 size = sizeof (MonoTypedRef);
1137 align = sizeof (gpointer);
1138 } else {
1139 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1140 if (is_pinvoke)
1141 size = mono_class_native_size (klass, &align);
1142 else
1143 size = mono_class_value_size (klass, &align);
1144 }
1145 DEBUG(printf ("load %d bytes struct\n",
1146 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1147 align_size = size;
1148 nwords = 0;
1149 align_size += (sizeof (gpointer) - 1);
1150 align_size &= ~(sizeof (gpointer) - 1);
1151 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1152 cinfo->args [n].storage = RegTypeStructByVal;
1153 cinfo->args [n].struct_size = size;
1154 /* FIXME: align stack_size if needed */
1155 if (eabi_supported) {
1156 if (align >= 8 && (gr & 1))
1157 gr ++;
1158 }
1159 if (gr > ARMREG_R3) {
1160 cinfo->args [n].size = 0;
1161 cinfo->args [n].vtsize = nwords;
1162 } else {
1163 int rest = ARMREG_R3 - gr + 1;
1164 int n_in_regs = rest >= nwords? nwords: rest;
1165
1166 cinfo->args [n].size = n_in_regs;
1167 cinfo->args [n].vtsize = nwords - n_in_regs;
1168 cinfo->args [n].reg = gr;
1169 gr += n_in_regs;
1170 nwords -= n_in_regs;
1171 }
1172 cinfo->args [n].offset = stack_size;
1173 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1174 stack_size += nwords * sizeof (gpointer);
1175 n++;
1176 break;
1177 }
1178 case MONO_TYPE_U8:
1179 case MONO_TYPE_I8:
1180 case MONO_TYPE_R8:
1181 cinfo->args [n].size = 8;
1182 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1183 n++;
1184 break;
1185 default:
1186 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1187 }
1188 }
1189
1190 /* Handle the case where there are no implicit arguments */
1191 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1192 /* Prevent implicit arguments and sig_cookie from
1193 being passed in registers */
1194 gr = ARMREG_R3 + 1;
1195 /* Emit the signature cookie just before the implicit arguments */
1196 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1197 }
1198
1199 {
1200 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1201 switch (simpletype->type) {
1202 case MONO_TYPE_BOOLEAN:
1203 case MONO_TYPE_I1:
1204 case MONO_TYPE_U1:
1205 case MONO_TYPE_I2:
1206 case MONO_TYPE_U2:
1207 case MONO_TYPE_CHAR:
1208 case MONO_TYPE_I4:
1209 case MONO_TYPE_U4:
1210 case MONO_TYPE_I:
1211 case MONO_TYPE_U:
1212 case MONO_TYPE_PTR:
1213 case MONO_TYPE_FNPTR:
1214 case MONO_TYPE_CLASS:
1215 case MONO_TYPE_OBJECT:
1216 case MONO_TYPE_SZARRAY:
1217 case MONO_TYPE_ARRAY:
1218 case MONO_TYPE_STRING:
1219 cinfo->ret.storage = RegTypeGeneral;
1220 cinfo->ret.reg = ARMREG_R0;
1221 break;
1222 case MONO_TYPE_U8:
1223 case MONO_TYPE_I8:
1224 cinfo->ret.storage = RegTypeIRegPair;
1225 cinfo->ret.reg = ARMREG_R0;
1226 break;
1227 case MONO_TYPE_R4:
1228 case MONO_TYPE_R8:
1229 cinfo->ret.storage = RegTypeFP;
1230 cinfo->ret.reg = ARMREG_R0;
1231 /* FIXME: cinfo->ret.reg = ???;
1232 cinfo->ret.storage = RegTypeFP;*/
1233 break;
1234 case MONO_TYPE_GENERICINST:
1235 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1236 cinfo->ret.storage = RegTypeGeneral;
1237 cinfo->ret.reg = ARMREG_R0;
1238 break;
1239 }
1240 /* Fall through */
1241 case MONO_TYPE_VALUETYPE:
1242 case MONO_TYPE_TYPEDBYREF:
1243 if (cinfo->ret.storage != RegTypeStructByVal)
1244 cinfo->ret.storage = RegTypeStructByAddr;
1245 break;
1246 case MONO_TYPE_VOID:
1247 break;
1248 default:
1249 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1250 }
1251 }
1252
1253 /* align stack size to 8 */
1254 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1255 stack_size = (stack_size + 7) & ~7;
1256
1257 cinfo->stack_usage = stack_size;
1258 return cinfo;
1259 }
1260
1261 #ifndef DISABLE_JIT
1262
1263 static gboolean
1264 debug_omit_fp (void)
1265 {
1266 #if 0
1267 return mono_debug_count ();
1268 #else
1269 return TRUE;
1270 #endif
1271 }
1272
1273 /**
1274 * mono_arch_compute_omit_fp:
1275 *
1276 * Determine whenever the frame pointer can be eliminated.
1277 */
1278 static void
1279 mono_arch_compute_omit_fp (MonoCompile *cfg)
1280 {
1281 MonoMethodSignature *sig;
1282 MonoMethodHeader *header;
1283 int i, locals_size;
1284 CallInfo *cinfo;
1285
1286 if (cfg->arch.omit_fp_computed)
1287 return;
1288
1289 header = cfg->header;
1290
1291 sig = mono_method_signature (cfg->method);
1292
1293 if (!cfg->arch.cinfo)
1294 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1295 cinfo = cfg->arch.cinfo;
1296
1297 /*
1298 * FIXME: Remove some of the restrictions.
1299 */
1300 cfg->arch.omit_fp = TRUE;
1301 cfg->arch.omit_fp_computed = TRUE;
1302
1303 if (cfg->disable_omit_fp)
1304 cfg->arch.omit_fp = FALSE;
1305 if (!debug_omit_fp ())
1306 cfg->arch.omit_fp = FALSE;
1307 /*
1308 if (cfg->method->save_lmf)
1309 cfg->arch.omit_fp = FALSE;
1310 */
1311 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1312 cfg->arch.omit_fp = FALSE;
1313 if (header->num_clauses)
1314 cfg->arch.omit_fp = FALSE;
1315 if (cfg->param_area)
1316 cfg->arch.omit_fp = FALSE;
1317 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1318 cfg->arch.omit_fp = FALSE;
1319 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1320 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1321 cfg->arch.omit_fp = FALSE;
1322 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1323 ArgInfo *ainfo = &cinfo->args [i];
1324
1325 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1326 /*
1327 * The stack offset can only be determined when the frame
1328 * size is known.
1329 */
1330 cfg->arch.omit_fp = FALSE;
1331 }
1332 }
1333
1334 locals_size = 0;
1335 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1336 MonoInst *ins = cfg->varinfo [i];
1337 int ialign;
1338
1339 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1340 }
1341 }
1342
1343 /*
1344 * Set var information according to the calling convention. arm version.
1345 * The locals var stuff should most likely be split in another method.
1346 */
1347 void
1348 mono_arch_allocate_vars (MonoCompile *cfg)
1349 {
1350 MonoMethodSignature *sig;
1351 MonoMethodHeader *header;
1352 MonoInst *ins;
1353 int i, offset, size, align, curinst;
1354 CallInfo *cinfo;
1355 guint32 ualign;
1356
1357 sig = mono_method_signature (cfg->method);
1358
1359 if (!cfg->arch.cinfo)
1360 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1361 cinfo = cfg->arch.cinfo;
1362
1363 mono_arch_compute_omit_fp (cfg);
1364
1365 if (cfg->arch.omit_fp)
1366 cfg->frame_reg = ARMREG_SP;
1367 else
1368 cfg->frame_reg = ARMREG_FP;
1369
1370 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1371
1372 /* allow room for the vararg method args: void* and long/double */
1373 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1374 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1375
1376 header = cfg->header;
1377
1378 /* See mono_arch_get_global_int_regs () */
1379 if (cfg->flags & MONO_CFG_HAS_CALLS)
1380 cfg->uses_rgctx_reg = TRUE;
1381
1382 if (cfg->frame_reg != ARMREG_SP)
1383 cfg->used_int_regs |= 1 << cfg->frame_reg;
1384
1385 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1386 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1387 cfg->used_int_regs |= (1 << ARMREG_V5);
1388
1389 offset = 0;
1390 curinst = 0;
1391 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1392 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1393 case MONO_TYPE_VOID:
1394 break;
1395 default:
1396 cfg->ret->opcode = OP_REGVAR;
1397 cfg->ret->inst_c0 = ARMREG_R0;
1398 break;
1399 }
1400 }
1401 /* local vars are at a positive offset from the stack pointer */
1402 /*
1403 * also note that if the function uses alloca, we use FP
1404 * to point at the local variables.
1405 */
1406 offset = 0; /* linkage area */
1407 /* align the offset to 16 bytes: not sure this is needed here */
1408 //offset += 8 - 1;
1409 //offset &= ~(8 - 1);
1410
1411 /* add parameter area size for called functions */
1412 offset += cfg->param_area;
1413 offset += 8 - 1;
1414 offset &= ~(8 - 1);
1415 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1416 offset += 8;
1417
1418 /* allow room to save the return value */
1419 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1420 offset += 8;
1421
1422 /* the MonoLMF structure is stored just below the stack pointer */
1423 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1424 if (cinfo->ret.storage == RegTypeStructByVal) {
1425 cfg->ret->opcode = OP_REGOFFSET;
1426 cfg->ret->inst_basereg = cfg->frame_reg;
1427 offset += sizeof (gpointer) - 1;
1428 offset &= ~(sizeof (gpointer) - 1);
1429 cfg->ret->inst_offset = - offset;
1430 } else {
1431 ins = cfg->vret_addr;
1432 offset += sizeof(gpointer) - 1;
1433 offset &= ~(sizeof(gpointer) - 1);
1434 ins->inst_offset = offset;
1435 ins->opcode = OP_REGOFFSET;
1436 ins->inst_basereg = cfg->frame_reg;
1437 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1438 printf ("vret_addr =");
1439 mono_print_ins (cfg->vret_addr);
1440 }
1441 }
1442 offset += sizeof(gpointer);
1443 }
1444
1445 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1446 if (cfg->arch.seq_point_info_var) {
1447 MonoInst *ins;
1448
1449 ins = cfg->arch.seq_point_info_var;
1450
1451 size = 4;
1452 align = 4;
1453 offset += align - 1;
1454 offset &= ~(align - 1);
1455 ins->opcode = OP_REGOFFSET;
1456 ins->inst_basereg = cfg->frame_reg;
1457 ins->inst_offset = offset;
1458 offset += size;
1459
1460 ins = cfg->arch.ss_trigger_page_var;
1461 size = 4;
1462 align = 4;
1463 offset += align - 1;
1464 offset &= ~(align - 1);
1465 ins->opcode = OP_REGOFFSET;
1466 ins->inst_basereg = cfg->frame_reg;
1467 ins->inst_offset = offset;
1468 offset += size;
1469 }
1470
1471 if (cfg->arch.seq_point_read_var) {
1472 MonoInst *ins;
1473
1474 ins = cfg->arch.seq_point_read_var;
1475
1476 size = 4;
1477 align = 4;
1478 offset += align - 1;
1479 offset &= ~(align - 1);
1480 ins->opcode = OP_REGOFFSET;
1481 ins->inst_basereg = cfg->frame_reg;
1482 ins->inst_offset = offset;
1483 offset += size;
1484
1485 ins = cfg->arch.seq_point_ss_method_var;
1486 size = 4;
1487 align = 4;
1488 offset += align - 1;
1489 offset &= ~(align - 1);
1490 ins->opcode = OP_REGOFFSET;
1491 ins->inst_basereg = cfg->frame_reg;
1492 ins->inst_offset = offset;
1493 offset += size;
1494
1495 ins = cfg->arch.seq_point_bp_method_var;
1496 size = 4;
1497 align = 4;
1498 offset += align - 1;
1499 offset &= ~(align - 1);
1500 ins->opcode = OP_REGOFFSET;
1501 ins->inst_basereg = cfg->frame_reg;
1502 ins->inst_offset = offset;
1503 offset += size;
1504 }
1505
1506 cfg->locals_min_stack_offset = offset;
1507
1508 curinst = cfg->locals_start;
1509 for (i = curinst; i < cfg->num_varinfo; ++i) {
1510 ins = cfg->varinfo [i];
1511 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1512 continue;
1513
1514 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1515 * pinvoke wrappers when they call functions returning structure */
1516 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1517 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1518 align = ualign;
1519 }
1520 else
1521 size = mono_type_size (ins->inst_vtype, &align);
1522
1523 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1524 * since it loads/stores misaligned words, which don't do the right thing.
1525 */
1526 if (align < 4 && size >= 4)
1527 align = 4;
1528 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1529 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1530 offset += align - 1;
1531 offset &= ~(align - 1);
1532 ins->opcode = OP_REGOFFSET;
1533 ins->inst_offset = offset;
1534 ins->inst_basereg = cfg->frame_reg;
1535 offset += size;
1536 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1537 }
1538
1539 cfg->locals_max_stack_offset = offset;
1540
1541 curinst = 0;
1542 if (sig->hasthis) {
1543 ins = cfg->args [curinst];
1544 if (ins->opcode != OP_REGVAR) {
1545 ins->opcode = OP_REGOFFSET;
1546 ins->inst_basereg = cfg->frame_reg;
1547 offset += sizeof (gpointer) - 1;
1548 offset &= ~(sizeof (gpointer) - 1);
1549 ins->inst_offset = offset;
1550 offset += sizeof (gpointer);
1551 }
1552 curinst++;
1553 }
1554
1555 if (sig->call_convention == MONO_CALL_VARARG) {
1556 size = 4;
1557 align = 4;
1558
1559 /* Allocate a local slot to hold the sig cookie address */
1560 offset += align - 1;
1561 offset &= ~(align - 1);
1562 cfg->sig_cookie = offset;
1563 offset += size;
1564 }
1565
1566 for (i = 0; i < sig->param_count; ++i) {
1567 ins = cfg->args [curinst];
1568
1569 if (ins->opcode != OP_REGVAR) {
1570 ins->opcode = OP_REGOFFSET;
1571 ins->inst_basereg = cfg->frame_reg;
1572 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1573 align = ualign;
1574 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1575 * since it loads/stores misaligned words, which don't do the right thing.
1576 */
1577 if (align < 4 && size >= 4)
1578 align = 4;
1579 /* The code in the prolog () stores words when storing vtypes received in a register */
1580 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1581 align = 4;
1582 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1583 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1584 offset += align - 1;
1585 offset &= ~(align - 1);
1586 ins->inst_offset = offset;
1587 offset += size;
1588 }
1589 curinst++;
1590 }
1591
1592 /* align the offset to 8 bytes */
1593 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1594 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1595 offset += 8 - 1;
1596 offset &= ~(8 - 1);
1597
1598 /* change sign? */
1599 cfg->stack_offset = offset;
1600 }
1601
1602 void
1603 mono_arch_create_vars (MonoCompile *cfg)
1604 {
1605 MonoMethodSignature *sig;
1606 CallInfo *cinfo;
1607
1608 sig = mono_method_signature (cfg->method);
1609
1610 if (!cfg->arch.cinfo)
1611 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1612 cinfo = cfg->arch.cinfo;
1613
1614 if (cinfo->ret.storage == RegTypeStructByVal)
1615 cfg->ret_var_is_local = TRUE;
1616
1617 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1618 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1619 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1620 printf ("vret_addr = ");
1621 mono_print_ins (cfg->vret_addr);
1622 }
1623 }
1624
1625 if (cfg->gen_seq_points) {
1626 if (cfg->soft_breakpoints) {
1627 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1628 ins->flags |= MONO_INST_VOLATILE;
1629 cfg->arch.seq_point_read_var = ins;
1630
1631 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1632 ins->flags |= MONO_INST_VOLATILE;
1633 cfg->arch.seq_point_ss_method_var = ins;
1634
1635 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1636 ins->flags |= MONO_INST_VOLATILE;
1637 cfg->arch.seq_point_bp_method_var = ins;
1638
1639 g_assert (!cfg->compile_aot);
1640 } else if (cfg->compile_aot) {
1641 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1642 ins->flags |= MONO_INST_VOLATILE;
1643 cfg->arch.seq_point_info_var = ins;
1644
1645 /* Allocate a separate variable for this to save 1 load per seq point */
1646 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1647 ins->flags |= MONO_INST_VOLATILE;
1648 cfg->arch.ss_trigger_page_var = ins;
1649 }
1650 }
1651 }
1652
1653 static void
1654 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1655 {
1656 MonoMethodSignature *tmp_sig;
1657 int sig_reg;
1658
1659 if (call->tail_call)
1660 NOT_IMPLEMENTED;
1661
1662 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1663
1664 /*
1665 * mono_ArgIterator_Setup assumes the signature cookie is
1666 * passed first and all the arguments which were before it are
1667 * passed on the stack after the signature. So compensate by
1668 * passing a different signature.
1669 */
1670 tmp_sig = mono_metadata_signature_dup (call->signature);
1671 tmp_sig->param_count -= call->signature->sentinelpos;
1672 tmp_sig->sentinelpos = 0;
1673 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1674
1675 sig_reg = mono_alloc_ireg (cfg);
1676 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1677
1678 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1679 }
1680
1681 #ifdef ENABLE_LLVM
1682 LLVMCallInfo*
1683 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1684 {
1685 int i, n;
1686 CallInfo *cinfo;
1687 ArgInfo *ainfo;
1688 LLVMCallInfo *linfo;
1689
1690 n = sig->param_count + sig->hasthis;
1691
1692 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1693
1694 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1695
1696 /*
1697 * LLVM always uses the native ABI while we use our own ABI, the
1698 * only difference is the handling of vtypes:
1699 * - we only pass/receive them in registers in some cases, and only
1700 * in 1 or 2 integer registers.
1701 */
1702 if (cinfo->vtype_retaddr) {
1703 /* Vtype returned using a hidden argument */
1704 linfo->ret.storage = LLVMArgVtypeRetAddr;
1705 linfo->vret_arg_index = cinfo->vret_arg_index;
1706 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1707 cfg->exception_message = g_strdup ("unknown ret conv");
1708 cfg->disable_llvm = TRUE;
1709 return linfo;
1710 }
1711
1712 for (i = 0; i < n; ++i) {
1713 ainfo = cinfo->args + i;
1714
1715 linfo->args [i].storage = LLVMArgNone;
1716
1717 switch (ainfo->storage) {
1718 case RegTypeGeneral:
1719 case RegTypeIRegPair:
1720 case RegTypeBase:
1721 linfo->args [i].storage = LLVMArgInIReg;
1722 break;
1723 case RegTypeStructByVal:
1724 // FIXME: Passing entirely on the stack or split reg/stack
1725 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1726 linfo->args [i].storage = LLVMArgVtypeInReg;
1727 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1728 if (ainfo->size == 2)
1729 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1730 else
1731 linfo->args [i].pair_storage [1] = LLVMArgNone;
1732 } else {
1733 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1734 cfg->disable_llvm = TRUE;
1735 }
1736 break;
1737 default:
1738 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1739 cfg->disable_llvm = TRUE;
1740 break;
1741 }
1742 }
1743
1744 return linfo;
1745 }
1746 #endif
1747
1748 void
1749 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1750 {
1751 MonoInst *in, *ins;
1752 MonoMethodSignature *sig;
1753 int i, n;
1754 CallInfo *cinfo;
1755
1756 sig = call->signature;
1757 n = sig->param_count + sig->hasthis;
1758
1759 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1760
1761 for (i = 0; i < n; ++i) {
1762 ArgInfo *ainfo = cinfo->args + i;
1763 MonoType *t;
1764
1765 if (i >= sig->hasthis)
1766 t = sig->params [i - sig->hasthis];
1767 else
1768 t = &mono_defaults.int_class->byval_arg;
1769 t = mini_type_get_underlying_type (NULL, t);
1770
1771 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1772 /* Emit the signature cookie just before the implicit arguments */
1773 emit_sig_cookie (cfg, call, cinfo);
1774 }
1775
1776 in = call->args [i];
1777
1778 switch (ainfo->storage) {
1779 case RegTypeGeneral:
1780 case RegTypeIRegPair:
1781 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1782 MONO_INST_NEW (cfg, ins, OP_MOVE);
1783 ins->dreg = mono_alloc_ireg (cfg);
1784 ins->sreg1 = in->dreg + 1;
1785 MONO_ADD_INS (cfg->cbb, ins);
1786 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1787
1788 MONO_INST_NEW (cfg, ins, OP_MOVE);
1789 ins->dreg = mono_alloc_ireg (cfg);
1790 ins->sreg1 = in->dreg + 2;
1791 MONO_ADD_INS (cfg->cbb, ins);
1792 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1793 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1794 if (ainfo->size == 4) {
1795 if (IS_SOFT_FLOAT) {
1796 /* mono_emit_call_args () have already done the r8->r4 conversion */
1797 /* The converted value is in an int vreg */
1798 MONO_INST_NEW (cfg, ins, OP_MOVE);
1799 ins->dreg = mono_alloc_ireg (cfg);
1800 ins->sreg1 = in->dreg;
1801 MONO_ADD_INS (cfg->cbb, ins);
1802 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1803 } else {
1804 int creg;
1805
1806 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1807 creg = mono_alloc_ireg (cfg);
1808 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1809 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1810 }
1811 } else {
1812 if (IS_SOFT_FLOAT) {
1813 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1814 ins->dreg = mono_alloc_ireg (cfg);
1815 ins->sreg1 = in->dreg;
1816 MONO_ADD_INS (cfg->cbb, ins);
1817 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1818
1819 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1820 ins->dreg = mono_alloc_ireg (cfg);
1821 ins->sreg1 = in->dreg;
1822 MONO_ADD_INS (cfg->cbb, ins);
1823 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1824 } else {
1825 int creg;
1826
1827 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1828 creg = mono_alloc_ireg (cfg);
1829 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1830 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1831 creg = mono_alloc_ireg (cfg);
1832 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1833 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1834 }
1835 }
1836 cfg->flags |= MONO_CFG_HAS_FPOUT;
1837 } else {
1838 MONO_INST_NEW (cfg, ins, OP_MOVE);
1839 ins->dreg = mono_alloc_ireg (cfg);
1840 ins->sreg1 = in->dreg;
1841 MONO_ADD_INS (cfg->cbb, ins);
1842
1843 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1844 }
1845 break;
1846 case RegTypeStructByAddr:
1847 NOT_IMPLEMENTED;
1848 #if 0
1849 /* FIXME: where si the data allocated? */
1850 arg->backend.reg3 = ainfo->reg;
1851 call->used_iregs |= 1 << ainfo->reg;
1852 g_assert_not_reached ();
1853 #endif
1854 break;
1855 case RegTypeStructByVal:
1856 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1857 ins->opcode = OP_OUTARG_VT;
1858 ins->sreg1 = in->dreg;
1859 ins->klass = in->klass;
1860 ins->inst_p0 = call;
1861 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1862 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1863 mono_call_inst_add_outarg_vt (cfg, call, ins);
1864 MONO_ADD_INS (cfg->cbb, ins);
1865 break;
1866 case RegTypeBase:
1867 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1868 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1869 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1870 if (t->type == MONO_TYPE_R8) {
1871 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1872 } else {
1873 if (IS_SOFT_FLOAT)
1874 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1875 else
1876 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1877 }
1878 } else {
1879 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1880 }
1881 break;
1882 case RegTypeBaseGen:
1883 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1884 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1885 MONO_INST_NEW (cfg, ins, OP_MOVE);
1886 ins->dreg = mono_alloc_ireg (cfg);
1887 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1888 MONO_ADD_INS (cfg->cbb, ins);
1889 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1890 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1891 int creg;
1892
1893 /* This should work for soft-float as well */
1894
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1896 creg = mono_alloc_ireg (cfg);
1897 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1898 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1899 creg = mono_alloc_ireg (cfg);
1900 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1901 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1902 cfg->flags |= MONO_CFG_HAS_FPOUT;
1903 } else {
1904 g_assert_not_reached ();
1905 }
1906 break;
1907 case RegTypeFP: {
1908 /* FIXME: */
1909 NOT_IMPLEMENTED;
1910 #if 0
1911 arg->backend.reg3 = ainfo->reg;
1912 /* FP args are passed in int regs */
1913 call->used_iregs |= 1 << ainfo->reg;
1914 if (ainfo->size == 8) {
1915 arg->opcode = OP_OUTARG_R8;
1916 call->used_iregs |= 1 << (ainfo->reg + 1);
1917 } else {
1918 arg->opcode = OP_OUTARG_R4;
1919 }
1920 #endif
1921 cfg->flags |= MONO_CFG_HAS_FPOUT;
1922 break;
1923 }
1924 default:
1925 g_assert_not_reached ();
1926 }
1927 }
1928
1929 /* Handle the case where there are no implicit arguments */
1930 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1931 emit_sig_cookie (cfg, call, cinfo);
1932
1933 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1934 MonoInst *vtarg;
1935
1936 if (cinfo->ret.storage == RegTypeStructByVal) {
1937 /* The JIT will transform this into a normal call */
1938 call->vret_in_reg = TRUE;
1939 } else {
1940 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1941 vtarg->sreg1 = call->vret_var->dreg;
1942 vtarg->dreg = mono_alloc_preg (cfg);
1943 MONO_ADD_INS (cfg->cbb, vtarg);
1944
1945 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1946 }
1947 }
1948
1949 call->stack_usage = cinfo->stack_usage;
1950
1951 g_free (cinfo);
1952 }
1953
1954 void
1955 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1956 {
1957 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1958 ArgInfo *ainfo = ins->inst_p1;
1959 int ovf_size = ainfo->vtsize;
1960 int doffset = ainfo->offset;
1961 int struct_size = ainfo->struct_size;
1962 int i, soffset, dreg, tmpreg;
1963
1964 soffset = 0;
1965 for (i = 0; i < ainfo->size; ++i) {
1966 dreg = mono_alloc_ireg (cfg);
1967 switch (struct_size) {
1968 case 1:
1969 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1970 break;
1971 case 2:
1972 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1973 break;
1974 case 3:
1975 tmpreg = mono_alloc_ireg (cfg);
1976 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1977 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1978 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1979 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1981 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1982 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1983 break;
1984 default:
1985 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1986 break;
1987 }
1988 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1989 soffset += sizeof (gpointer);
1990 struct_size -= sizeof (gpointer);
1991 }
1992 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1993 if (ovf_size != 0)
1994 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1995 }
1996
1997 void
1998 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1999 {
2000 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2001
2002 if (!ret->byref) {
2003 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2004 MonoInst *ins;
2005
2006 if (COMPILE_LLVM (cfg)) {
2007 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2008 } else {
2009 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2010 ins->sreg1 = val->dreg + 1;
2011 ins->sreg2 = val->dreg + 2;
2012 MONO_ADD_INS (cfg->cbb, ins);
2013 }
2014 return;
2015 }
2016 switch (arm_fpu) {
2017 case MONO_ARM_FPU_NONE:
2018 if (ret->type == MONO_TYPE_R8) {
2019 MonoInst *ins;
2020
2021 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2022 ins->dreg = cfg->ret->dreg;
2023 ins->sreg1 = val->dreg;
2024 MONO_ADD_INS (cfg->cbb, ins);
2025 return;
2026 }
2027 if (ret->type == MONO_TYPE_R4) {
2028 /* Already converted to an int in method_to_ir () */
2029 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2030 return;
2031 }
2032 break;
2033 case MONO_ARM_FPU_VFP:
2034 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2035 MonoInst *ins;
2036
2037 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2038 ins->dreg = cfg->ret->dreg;
2039 ins->sreg1 = val->dreg;
2040 MONO_ADD_INS (cfg->cbb, ins);
2041 return;
2042 }
2043 break;
2044 case MONO_ARM_FPU_FPA:
2045 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2046 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2047 return;
2048 }
2049 break;
2050 default:
2051 g_assert_not_reached ();
2052 }
2053 }
2054
2055 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2056 }
2057
2058 #endif /* #ifndef DISABLE_JIT */
2059
2060 gboolean
2061 mono_arch_is_inst_imm (gint64 imm)
2062 {
2063 return TRUE;
2064 }
2065
2066 #define DYN_CALL_STACK_ARGS 6
2067
2068 typedef struct {
2069 MonoMethodSignature *sig;
2070 CallInfo *cinfo;
2071 } ArchDynCallInfo;
2072
2073 typedef struct {
2074 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2075 mgreg_t res, res2;
2076 guint8 *ret;
2077 } DynCallArgs;
2078
2079 static gboolean
2080 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2081 {
2082 int i;
2083
2084 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2085 return FALSE;
2086
2087 switch (cinfo->ret.storage) {
2088 case RegTypeNone:
2089 case RegTypeGeneral:
2090 case RegTypeIRegPair:
2091 case RegTypeStructByAddr:
2092 break;
2093 case RegTypeFP:
2094 if (IS_FPA)
2095 return FALSE;
2096 else if (IS_VFP)
2097 break;
2098 else
2099 return FALSE;
2100 default:
2101 return FALSE;
2102 }
2103
2104 for (i = 0; i < cinfo->nargs; ++i) {
2105 switch (cinfo->args [i].storage) {
2106 case RegTypeGeneral:
2107 break;
2108 case RegTypeIRegPair:
2109 break;
2110 case RegTypeBase:
2111 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2112 return FALSE;
2113 break;
2114 case RegTypeStructByVal:
2115 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2116 return FALSE;
2117 break;
2118 default:
2119 return FALSE;
2120 }
2121 }
2122
2123 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2124 for (i = 0; i < sig->param_count; ++i) {
2125 MonoType *t = sig->params [i];
2126
2127 if (t->byref)
2128 continue;
2129
2130 switch (t->type) {
2131 case MONO_TYPE_R4:
2132 case MONO_TYPE_R8:
2133 if (IS_SOFT_FLOAT)
2134 return FALSE;
2135 else
2136 break;
2137 /*
2138 case MONO_TYPE_I8:
2139 case MONO_TYPE_U8:
2140 return FALSE;
2141 */
2142 default:
2143 break;
2144 }
2145 }
2146
2147 return TRUE;
2148 }
2149
2150 MonoDynCallInfo*
2151 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2152 {
2153 ArchDynCallInfo *info;
2154 CallInfo *cinfo;
2155
2156 cinfo = get_call_info (NULL, NULL, sig);
2157
2158 if (!dyn_call_supported (cinfo, sig)) {
2159 g_free (cinfo);
2160 return NULL;
2161 }
2162
2163 info = g_new0 (ArchDynCallInfo, 1);
2164 // FIXME: Preprocess the info to speed up start_dyn_call ()
2165 info->sig = sig;
2166 info->cinfo = cinfo;
2167
2168 return (MonoDynCallInfo*)info;
2169 }
2170
2171 void
2172 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2173 {
2174 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2175
2176 g_free (ainfo->cinfo);
2177 g_free (ainfo);
2178 }
2179
2180 void
2181 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2182 {
2183 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2184 DynCallArgs *p = (DynCallArgs*)buf;
2185 int arg_index, greg, i, j, pindex;
2186 MonoMethodSignature *sig = dinfo->sig;
2187
2188 g_assert (buf_len >= sizeof (DynCallArgs));
2189
2190 p->res = 0;
2191 p->ret = ret;
2192
2193 arg_index = 0;
2194 greg = 0;
2195 pindex = 0;
2196
2197 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2198 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2199 if (!sig->hasthis)
2200 pindex = 1;
2201 }
2202
2203 if (dinfo->cinfo->vtype_retaddr)
2204 p->regs [greg ++] = (mgreg_t)ret;
2205
2206 for (i = pindex; i < sig->param_count; i++) {
2207 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2208 gpointer *arg = args [arg_index ++];
2209 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2210 int slot = -1;
2211
2212 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2213 slot = ainfo->reg;
2214 else if (ainfo->storage == RegTypeBase)
2215 slot = PARAM_REGS + (ainfo->offset / 4);
2216 else
2217 g_assert_not_reached ();
2218
2219 if (t->byref) {
2220 p->regs [slot] = (mgreg_t)*arg;
2221 continue;
2222 }
2223
2224 switch (t->type) {
2225 case MONO_TYPE_STRING:
2226 case MONO_TYPE_CLASS:
2227 case MONO_TYPE_ARRAY:
2228 case MONO_TYPE_SZARRAY:
2229 case MONO_TYPE_OBJECT:
2230 case MONO_TYPE_PTR:
2231 case MONO_TYPE_I:
2232 case MONO_TYPE_U:
2233 p->regs [slot] = (mgreg_t)*arg;
2234 break;
2235 case MONO_TYPE_BOOLEAN:
2236 case MONO_TYPE_U1:
2237 p->regs [slot] = *(guint8*)arg;
2238 break;
2239 case MONO_TYPE_I1:
2240 p->regs [slot] = *(gint8*)arg;
2241 break;
2242 case MONO_TYPE_I2:
2243 p->regs [slot] = *(gint16*)arg;
2244 break;
2245 case MONO_TYPE_U2:
2246 case MONO_TYPE_CHAR:
2247 p->regs [slot] = *(guint16*)arg;
2248 break;
2249 case MONO_TYPE_I4:
2250 p->regs [slot] = *(gint32*)arg;
2251 break;
2252 case MONO_TYPE_U4:
2253 p->regs [slot] = *(guint32*)arg;
2254 break;
2255 case MONO_TYPE_I8:
2256 case MONO_TYPE_U8:
2257 p->regs [slot ++] = (mgreg_t)arg [0];
2258 p->regs [slot] = (mgreg_t)arg [1];
2259 break;
2260 case MONO_TYPE_R4:
2261 p->regs [slot] = *(mgreg_t*)arg;
2262 break;
2263 case MONO_TYPE_R8:
2264 p->regs [slot ++] = (mgreg_t)arg [0];
2265 p->regs [slot] = (mgreg_t)arg [1];
2266 break;
2267 case MONO_TYPE_GENERICINST:
2268 if (MONO_TYPE_IS_REFERENCE (t)) {
2269 p->regs [slot] = (mgreg_t)*arg;
2270 break;
2271 } else {
2272 /* Fall though */
2273 }
2274 case MONO_TYPE_VALUETYPE:
2275 g_assert (ainfo->storage == RegTypeStructByVal);
2276
2277 if (ainfo->size == 0)
2278 slot = PARAM_REGS + (ainfo->offset / 4);
2279 else
2280 slot = ainfo->reg;
2281
2282 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2283 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2284 break;
2285 default:
2286 g_assert_not_reached ();
2287 }
2288 }
2289 }
2290
2291 void
2292 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2293 {
2294 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2295 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2296 guint8 *ret = ((DynCallArgs*)buf)->ret;
2297 mgreg_t res = ((DynCallArgs*)buf)->res;
2298 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2299
2300 switch (mono_type_get_underlying_type (sig->ret)->type) {
2301 case MONO_TYPE_VOID:
2302 *(gpointer*)ret = NULL;
2303 break;
2304 case MONO_TYPE_STRING:
2305 case MONO_TYPE_CLASS:
2306 case MONO_TYPE_ARRAY:
2307 case MONO_TYPE_SZARRAY:
2308 case MONO_TYPE_OBJECT:
2309 case MONO_TYPE_I:
2310 case MONO_TYPE_U:
2311 case MONO_TYPE_PTR:
2312 *(gpointer*)ret = (gpointer)res;
2313 break;
2314 case MONO_TYPE_I1:
2315 *(gint8*)ret = res;
2316 break;
2317 case MONO_TYPE_U1:
2318 case MONO_TYPE_BOOLEAN:
2319 *(guint8*)ret = res;
2320 break;
2321 case MONO_TYPE_I2:
2322 *(gint16*)ret = res;
2323 break;
2324 case MONO_TYPE_U2:
2325 case MONO_TYPE_CHAR:
2326 *(guint16*)ret = res;
2327 break;
2328 case MONO_TYPE_I4:
2329 *(gint32*)ret = res;
2330 break;
2331 case MONO_TYPE_U4:
2332 *(guint32*)ret = res;
2333 break;
2334 case MONO_TYPE_I8:
2335 case MONO_TYPE_U8:
2336 /* This handles endianness as well */
2337 ((gint32*)ret) [0] = res;
2338 ((gint32*)ret) [1] = res2;
2339 break;
2340 case MONO_TYPE_GENERICINST:
2341 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2342 *(gpointer*)ret = (gpointer)res;
2343 break;
2344 } else {
2345 /* Fall though */
2346 }
2347 case MONO_TYPE_VALUETYPE:
2348 g_assert (ainfo->cinfo->vtype_retaddr);
2349 /* Nothing to do */
2350 break;
2351 case MONO_TYPE_R4:
2352 g_assert (IS_VFP);
2353 *(float*)ret = *(float*)&res;
2354 break;
2355 case MONO_TYPE_R8: {
2356 mgreg_t regs [2];
2357
2358 g_assert (IS_VFP);
2359 regs [0] = res;
2360 regs [1] = res2;
2361
2362 *(double*)ret = *(double*)&regs;
2363 break;
2364 }
2365 default:
2366 g_assert_not_reached ();
2367 }
2368 }
2369
2370 #ifndef DISABLE_JIT
2371
2372 /*
2373 * Allow tracing to work with this interface (with an optional argument)
2374 */
2375
2376 void*
2377 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2378 {
2379 guchar *code = p;
2380
2381 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2382 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2383 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2384 code = emit_call_reg (code, ARMREG_R2);
2385 return code;
2386 }
2387
2388 enum {
2389 SAVE_NONE,
2390 SAVE_STRUCT,
2391 SAVE_ONE,
2392 SAVE_TWO,
2393 SAVE_FP
2394 };
2395
2396 void*
2397 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2398 {
2399 guchar *code = p;
2400 int save_mode = SAVE_NONE;
2401 int offset;
2402 MonoMethod *method = cfg->method;
2403 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2404 int save_offset = cfg->param_area;
2405 save_offset += 7;
2406 save_offset &= ~7;
2407
2408 offset = code - cfg->native_code;
2409 /* we need about 16 instructions */
2410 if (offset > (cfg->code_size - 16 * 4)) {
2411 cfg->code_size *= 2;
2412 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2413 code = cfg->native_code + offset;
2414 }
2415 switch (rtype) {
2416 case MONO_TYPE_VOID:
2417 /* special case string .ctor icall */
2418 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2419 save_mode = SAVE_ONE;
2420 else
2421 save_mode = SAVE_NONE;
2422 break;
2423 case MONO_TYPE_I8:
2424 case MONO_TYPE_U8:
2425 save_mode = SAVE_TWO;
2426 break;
2427 case MONO_TYPE_R4:
2428 case MONO_TYPE_R8:
2429 save_mode = SAVE_FP;
2430 break;
2431 case MONO_TYPE_VALUETYPE:
2432 save_mode = SAVE_STRUCT;
2433 break;
2434 default:
2435 save_mode = SAVE_ONE;
2436 break;
2437 }
2438
2439 switch (save_mode) {
2440 case SAVE_TWO:
2441 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2442 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2443 if (enable_arguments) {
2444 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2445 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2446 }
2447 break;
2448 case SAVE_ONE:
2449 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2450 if (enable_arguments) {
2451 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2452 }
2453 break;
2454 case SAVE_FP:
2455 /* FIXME: what reg? */
2456 if (enable_arguments) {
2457 /* FIXME: what reg? */
2458 }
2459 break;
2460 case SAVE_STRUCT:
2461 if (enable_arguments) {
2462 /* FIXME: get the actual address */
2463 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2464 }
2465 break;
2466 case SAVE_NONE:
2467 default:
2468 break;
2469 }
2470
2471 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2472 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2473 code = emit_call_reg (code, ARMREG_IP);
2474
2475 switch (save_mode) {
2476 case SAVE_TWO:
2477 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2478 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2479 break;
2480 case SAVE_ONE:
2481 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2482 break;
2483 case SAVE_FP:
2484 /* FIXME */
2485 break;
2486 case SAVE_NONE:
2487 default:
2488 break;
2489 }
2490
2491 return code;
2492 }
2493
2494 /*
2495 * The immediate field for cond branches is big enough for all reasonable methods
2496 */
2497 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2498 if (0 && ins->inst_true_bb->native_offset) { \
2499 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2500 } else { \
2501 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2502 ARM_B_COND (code, (condcode), 0); \
2503 }
2504
2505 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2506
2507 /* emit an exception if condition is fail
2508 *
2509 * We assign the extra code used to throw the implicit exceptions
2510 * to cfg->bb_exit as far as the big branch handling is concerned
2511 */
2512 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2513 do { \
2514 mono_add_patch_info (cfg, code - cfg->native_code, \
2515 MONO_PATCH_INFO_EXC, exc_name); \
2516 ARM_BL_COND (code, (condcode), 0); \
2517 } while (0);
2518
2519 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2520
2521 void
2522 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2523 {
2524 }
2525
2526 void
2527 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2528 {
2529 MonoInst *ins, *n, *last_ins = NULL;
2530
2531 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2532 switch (ins->opcode) {
2533 case OP_MUL_IMM:
2534 case OP_IMUL_IMM:
2535 /* Already done by an arch-independent pass */
2536 break;
2537 case OP_LOAD_MEMBASE:
2538 case OP_LOADI4_MEMBASE:
2539 /*
2540 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2541 * OP_LOAD_MEMBASE offset(basereg), reg
2542 */
2543 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2544 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2545 ins->inst_basereg == last_ins->inst_destbasereg &&
2546 ins->inst_offset == last_ins->inst_offset) {
2547 if (ins->dreg == last_ins->sreg1) {
2548 MONO_DELETE_INS (bb, ins);
2549 continue;
2550 } else {
2551 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2552 ins->opcode = OP_MOVE;
2553 ins->sreg1 = last_ins->sreg1;
2554 }
2555
2556 /*
2557 * Note: reg1 must be different from the basereg in the second load
2558 * OP_LOAD_MEMBASE offset(basereg), reg1
2559 * OP_LOAD_MEMBASE offset(basereg), reg2
2560 * -->
2561 * OP_LOAD_MEMBASE offset(basereg), reg1
2562 * OP_MOVE reg1, reg2
2563 */
2564 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2565 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2566 ins->inst_basereg != last_ins->dreg &&
2567 ins->inst_basereg == last_ins->inst_basereg &&
2568 ins->inst_offset == last_ins->inst_offset) {
2569
2570 if (ins->dreg == last_ins->dreg) {
2571 MONO_DELETE_INS (bb, ins);
2572 continue;
2573 } else {
2574 ins->opcode = OP_MOVE;
2575 ins->sreg1 = last_ins->dreg;
2576 }
2577
2578 //g_assert_not_reached ();
2579
2580 #if 0
2581 /*
2582 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2583 * OP_LOAD_MEMBASE offset(basereg), reg
2584 * -->
2585 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2586 * OP_ICONST reg, imm
2587 */
2588 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2589 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2590 ins->inst_basereg == last_ins->inst_destbasereg &&
2591 ins->inst_offset == last_ins->inst_offset) {
2592 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2593 ins->opcode = OP_ICONST;
2594 ins->inst_c0 = last_ins->inst_imm;
2595 g_assert_not_reached (); // check this rule
2596 #endif
2597 }
2598 break;
2599 case OP_LOADU1_MEMBASE:
2600 case OP_LOADI1_MEMBASE:
2601 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2602 ins->inst_basereg == last_ins->inst_destbasereg &&
2603 ins->inst_offset == last_ins->inst_offset) {
2604 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2605 ins->sreg1 = last_ins->sreg1;
2606 }
2607 break;
2608 case OP_LOADU2_MEMBASE:
2609 case OP_LOADI2_MEMBASE:
2610 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2611 ins->inst_basereg == last_ins->inst_destbasereg &&
2612 ins->inst_offset == last_ins->inst_offset) {
2613 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2614 ins->sreg1 = last_ins->sreg1;
2615 }
2616 break;
2617 case OP_MOVE:
2618 ins->opcode = OP_MOVE;
2619 /*
2620 * OP_MOVE reg, reg
2621 */
2622 if (ins->dreg == ins->sreg1) {
2623 MONO_DELETE_INS (bb, ins);
2624 continue;
2625 }
2626 /*
2627 * OP_MOVE sreg, dreg
2628 * OP_MOVE dreg, sreg
2629 */
2630 if (last_ins && last_ins->opcode == OP_MOVE &&
2631 ins->sreg1 == last_ins->dreg &&
2632 ins->dreg == last_ins->sreg1) {
2633 MONO_DELETE_INS (bb, ins);
2634 continue;
2635 }
2636 break;
2637 }
2638 last_ins = ins;
2639 ins = ins->next;
2640 }
2641 bb->last_ins = last_ins;
2642 }
2643
2644 /*
2645 * the branch_cc_table should maintain the order of these
2646 * opcodes.
2647 case CEE_BEQ:
2648 case CEE_BGE:
2649 case CEE_BGT:
2650 case CEE_BLE:
2651 case CEE_BLT:
2652 case CEE_BNE_UN:
2653 case CEE_BGE_UN:
2654 case CEE_BGT_UN:
2655 case CEE_BLE_UN:
2656 case CEE_BLT_UN:
2657 */
2658 static const guchar
2659 branch_cc_table [] = {
2660 ARMCOND_EQ,
2661 ARMCOND_GE,
2662 ARMCOND_GT,
2663 ARMCOND_LE,
2664 ARMCOND_LT,
2665
2666 ARMCOND_NE,
2667 ARMCOND_HS,
2668 ARMCOND_HI,
2669 ARMCOND_LS,
2670 ARMCOND_LO
2671 };
2672
2673 #define ADD_NEW_INS(cfg,dest,op) do { \
2674 MONO_INST_NEW ((cfg), (dest), (op)); \
2675 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2676 } while (0)
2677
2678 static int
2679 map_to_reg_reg_op (int op)
2680 {
2681 switch (op) {
2682 case OP_ADD_IMM:
2683 return OP_IADD;
2684 case OP_SUB_IMM:
2685 return OP_ISUB;
2686 case OP_AND_IMM:
2687 return OP_IAND;
2688 case OP_COMPARE_IMM:
2689 return OP_COMPARE;
2690 case OP_ICOMPARE_IMM:
2691 return OP_ICOMPARE;
2692 case OP_ADDCC_IMM:
2693 return OP_ADDCC;
2694 case OP_ADC_IMM:
2695 return OP_ADC;
2696 case OP_SUBCC_IMM:
2697 return OP_SUBCC;
2698 case OP_SBB_IMM:
2699 return OP_SBB;
2700 case OP_OR_IMM:
2701 return OP_IOR;
2702 case OP_XOR_IMM:
2703 return OP_IXOR;
2704 case OP_LOAD_MEMBASE:
2705 return OP_LOAD_MEMINDEX;
2706 case OP_LOADI4_MEMBASE:
2707 return OP_LOADI4_MEMINDEX;
2708 case OP_LOADU4_MEMBASE:
2709 return OP_LOADU4_MEMINDEX;
2710 case OP_LOADU1_MEMBASE:
2711 return OP_LOADU1_MEMINDEX;
2712 case OP_LOADI2_MEMBASE:
2713 return OP_LOADI2_MEMINDEX;
2714 case OP_LOADU2_MEMBASE:
2715 return OP_LOADU2_MEMINDEX;
2716 case OP_LOADI1_MEMBASE:
2717 return OP_LOADI1_MEMINDEX;
2718 case OP_STOREI1_MEMBASE_REG:
2719 return OP_STOREI1_MEMINDEX;
2720 case OP_STOREI2_MEMBASE_REG:
2721 return OP_STOREI2_MEMINDEX;
2722 case OP_STOREI4_MEMBASE_REG:
2723 return OP_STOREI4_MEMINDEX;
2724 case OP_STORE_MEMBASE_REG:
2725 return OP_STORE_MEMINDEX;
2726 case OP_STORER4_MEMBASE_REG:
2727 return OP_STORER4_MEMINDEX;
2728 case OP_STORER8_MEMBASE_REG:
2729 return OP_STORER8_MEMINDEX;
2730 case OP_STORE_MEMBASE_IMM:
2731 return OP_STORE_MEMBASE_REG;
2732 case OP_STOREI1_MEMBASE_IMM:
2733 return OP_STOREI1_MEMBASE_REG;
2734 case OP_STOREI2_MEMBASE_IMM:
2735 return OP_STOREI2_MEMBASE_REG;
2736 case OP_STOREI4_MEMBASE_IMM:
2737 return OP_STOREI4_MEMBASE_REG;
2738 }
2739 g_assert_not_reached ();
2740 }
2741
2742 /*
2743 * Remove from the instruction list the instructions that can't be
2744 * represented with very simple instructions with no register
2745 * requirements.
2746 */
2747 void
2748 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2749 {
2750 MonoInst *ins, *temp, *last_ins = NULL;
2751 int rot_amount, imm8, low_imm;
2752
2753 MONO_BB_FOR_EACH_INS (bb, ins) {
2754 loop_start:
2755 switch (ins->opcode) {
2756 case OP_ADD_IMM:
2757 case OP_SUB_IMM:
2758 case OP_AND_IMM:
2759 case OP_COMPARE_IMM:
2760 case OP_ICOMPARE_IMM:
2761 case OP_ADDCC_IMM:
2762 case OP_ADC_IMM:
2763 case OP_SUBCC_IMM:
2764 case OP_SBB_IMM:
2765 case OP_OR_IMM:
2766 case OP_XOR_IMM:
2767 case OP_IADD_IMM:
2768 case OP_ISUB_IMM:
2769 case OP_IAND_IMM:
2770 case OP_IADC_IMM:
2771 case OP_ISBB_IMM:
2772 case OP_IOR_IMM:
2773 case OP_IXOR_IMM:
2774 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2775 ADD_NEW_INS (cfg, temp, OP_ICONST);
2776 temp->inst_c0 = ins->inst_imm;
2777 temp->dreg = mono_alloc_ireg (cfg);
2778 ins->sreg2 = temp->dreg;
2779 ins->opcode = mono_op_imm_to_op (ins->opcode);
2780 }
2781 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2782 goto loop_start;
2783 else
2784 break;
2785 case OP_MUL_IMM:
2786 case OP_IMUL_IMM:
2787 if (ins->inst_imm == 1) {
2788 ins->opcode = OP_MOVE;
2789 break;
2790 }
2791 if (ins->inst_imm == 0) {
2792 ins->opcode = OP_ICONST;
2793 ins->inst_c0 = 0;
2794 break;
2795 }
2796 imm8 = mono_is_power_of_two (ins->inst_imm);
2797 if (imm8 > 0) {
2798 ins->opcode = OP_SHL_IMM;
2799 ins->inst_imm = imm8;
2800 break;
2801 }
2802 ADD_NEW_INS (cfg, temp, OP_ICONST);
2803 temp->inst_c0 = ins->inst_imm;
2804 temp->dreg = mono_alloc_ireg (cfg);
2805 ins->sreg2 = temp->dreg;
2806 ins->opcode = OP_IMUL;
2807 break;
2808 case OP_SBB:
2809 case OP_ISBB:
2810 case OP_SUBCC:
2811 case OP_ISUBCC:
2812 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2813 /* ARM sets the C flag to 1 if there was _no_ overflow */
2814 ins->next->opcode = OP_COND_EXC_NC;
2815 break;
2816 case OP_LOCALLOC_IMM:
2817 ADD_NEW_INS (cfg, temp, OP_ICONST);
2818 temp->inst_c0 = ins->inst_imm;
2819 temp->dreg = mono_alloc_ireg (cfg);
2820 ins->sreg1 = temp->dreg;
2821 ins->opcode = OP_LOCALLOC;
2822 break;
2823 case OP_LOAD_MEMBASE:
2824 case OP_LOADI4_MEMBASE:
2825 case OP_LOADU4_MEMBASE:
2826 case OP_LOADU1_MEMBASE:
2827 /* we can do two things: load the immed in a register
2828 * and use an indexed load, or see if the immed can be
2829 * represented as an ad_imm + a load with a smaller offset
2830 * that fits. We just do the first for now, optimize later.
2831 */
2832 if (arm_is_imm12 (ins->inst_offset))
2833 break;
2834 ADD_NEW_INS (cfg, temp, OP_ICONST);
2835 temp->inst_c0 = ins->inst_offset;
2836 temp->dreg = mono_alloc_ireg (cfg);
2837 ins->sreg2 = temp->dreg;
2838 ins->opcode = map_to_reg_reg_op (ins->opcode);
2839 break;
2840 case OP_LOADI2_MEMBASE:
2841 case OP_LOADU2_MEMBASE:
2842 case OP_LOADI1_MEMBASE:
2843 if (arm_is_imm8 (ins->inst_offset))
2844 break;
2845 ADD_NEW_INS (cfg, temp, OP_ICONST);
2846 temp->inst_c0 = ins->inst_offset;
2847 temp->dreg = mono_alloc_ireg (cfg);
2848 ins->sreg2 = temp->dreg;
2849 ins->opcode = map_to_reg_reg_op (ins->opcode);
2850 break;
2851 case OP_LOADR4_MEMBASE:
2852 case OP_LOADR8_MEMBASE:
2853 if (arm_is_fpimm8 (ins->inst_offset))
2854 break;
2855 low_imm = ins->inst_offset & 0x1ff;
2856 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2857 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2858 temp->inst_imm = ins->inst_offset & ~0x1ff;
2859 temp->sreg1 = ins->inst_basereg;
2860 temp->dreg = mono_alloc_ireg (cfg);
2861 ins->inst_basereg = temp->dreg;
2862 ins->inst_offset = low_imm;
2863 } else {
2864 MonoInst *add_ins;
2865
2866 ADD_NEW_INS (cfg, temp, OP_ICONST);
2867 temp->inst_c0 = ins->inst_offset;
2868 temp->dreg = mono_alloc_ireg (cfg);
2869
2870 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2871 add_ins->sreg1 = ins->inst_basereg;
2872 add_ins->sreg2 = temp->dreg;
2873 add_ins->dreg = mono_alloc_ireg (cfg);
2874
2875 ins->inst_basereg = add_ins->dreg;
2876 ins->inst_offset = 0;
2877 }
2878 break;
2879 case OP_STORE_MEMBASE_REG:
2880 case OP_STOREI4_MEMBASE_REG:
2881 case OP_STOREI1_MEMBASE_REG:
2882 if (arm_is_imm12 (ins->inst_offset))
2883 break;
2884 ADD_NEW_INS (cfg, temp, OP_ICONST);
2885 temp->inst_c0 = ins->inst_offset;
2886 temp->dreg = mono_alloc_ireg (cfg);
2887 ins->sreg2 = temp->dreg;
2888 ins->opcode = map_to_reg_reg_op (ins->opcode);
2889 break;
2890 case OP_STOREI2_MEMBASE_REG:
2891 if (arm_is_imm8 (ins->inst_offset))
2892 break;
2893 ADD_NEW_INS (cfg, temp, OP_ICONST);
2894 temp->inst_c0 = ins->inst_offset;
2895 temp->dreg = mono_alloc_ireg (cfg);
2896 ins->sreg2 = temp->dreg;
2897 ins->opcode = map_to_reg_reg_op (ins->opcode);
2898 break;
2899 case OP_STORER4_MEMBASE_REG:
2900 case OP_STORER8_MEMBASE_REG:
2901 if (arm_is_fpimm8 (ins->inst_offset))
2902 break;
2903 low_imm = ins->inst_offset & 0x1ff;
2904 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2905 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2906 temp->inst_imm = ins->inst_offset & ~0x1ff;
2907 temp->sreg1 = ins->inst_destbasereg;
2908 temp->dreg = mono_alloc_ireg (cfg);
2909 ins->inst_destbasereg = temp->dreg;
2910 ins->inst_offset = low_imm;
2911 } else {
2912 MonoInst *add_ins;
2913
2914 ADD_NEW_INS (cfg, temp, OP_ICONST);
2915 temp->inst_c0 = ins->inst_offset;
2916 temp->dreg = mono_alloc_ireg (cfg);
2917
2918 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2919 add_ins->sreg1 = ins->inst_destbasereg;
2920 add_ins->sreg2 = temp->dreg;
2921 add_ins->dreg = mono_alloc_ireg (cfg);
2922
2923 ins->inst_destbasereg = add_ins->dreg;
2924 ins->inst_offset = 0;
2925 }
2926 break;
2927 case OP_STORE_MEMBASE_IMM:
2928 case OP_STOREI1_MEMBASE_IMM:
2929 case OP_STOREI2_MEMBASE_IMM:
2930 case OP_STOREI4_MEMBASE_IMM:
2931 ADD_NEW_INS (cfg, temp, OP_ICONST);
2932 temp->inst_c0 = ins->inst_imm;
2933 temp->dreg = mono_alloc_ireg (cfg);
2934 ins->sreg1 = temp->dreg;
2935 ins->opcode = map_to_reg_reg_op (ins->opcode);
2936 last_ins = temp;
2937 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2938 case OP_FCOMPARE: {
2939 gboolean swap = FALSE;
2940 int reg;
2941
2942 if (!ins->next) {
2943 /* Optimized away */
2944 NULLIFY_INS (ins);
2945 break;
2946 }
2947
2948 /* Some fp compares require swapped operands */
2949 switch (ins->next->opcode) {
2950 case OP_FBGT:
2951 ins->next->opcode = OP_FBLT;
2952 swap = TRUE;
2953 break;
2954 case OP_FBGT_UN:
2955 ins->next->opcode = OP_FBLT_UN;
2956 swap = TRUE;
2957 break;
2958 case OP_FBLE:
2959 ins->next->opcode = OP_FBGE;
2960 swap = TRUE;
2961 break;
2962 case OP_FBLE_UN:
2963 ins->next->opcode = OP_FBGE_UN;
2964 swap = TRUE;
2965 break;
2966 default:
2967 break;
2968 }
2969 if (swap) {
2970 reg = ins->sreg1;
2971 ins->sreg1 = ins->sreg2;
2972 ins->sreg2 = reg;
2973 }
2974 break;
2975 }
2976 }
2977
2978 last_ins = ins;
2979 }
2980 bb->last_ins = last_ins;
2981 bb->max_vreg = cfg->next_vreg;
2982 }
2983
2984 void
2985 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2986 {
2987 MonoInst *ins;
2988
2989 if (long_ins->opcode == OP_LNEG) {
2990 ins = long_ins;
2991 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2992 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2993 NULLIFY_INS (ins);
2994 }
2995 }
2996
2997 static guchar*
2998 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2999 {
3000 /* sreg is a float, dreg is an integer reg */
3001 if (IS_FPA)
3002 ARM_FPA_FIXZ (code, dreg, sreg);
3003 else if (IS_VFP) {
3004 if (is_signed)
3005 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3006 else
3007 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3008 ARM_FMRS (code, dreg, ARM_VFP_F0);
3009 }
3010 if (!is_signed) {
3011 if (size == 1)
3012 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3013 else if (size == 2) {
3014 ARM_SHL_IMM (code, dreg, dreg, 16);
3015 ARM_SHR_IMM (code, dreg, dreg, 16);
3016 }
3017 } else {
3018 if (size == 1) {
3019 ARM_SHL_IMM (code, dreg, dreg, 24);
3020 ARM_SAR_IMM (code, dreg, dreg, 24);
3021 } else if (size == 2) {
3022 ARM_SHL_IMM (code, dreg, dreg, 16);
3023 ARM_SAR_IMM (code, dreg, dreg, 16);
3024 }
3025 }
3026 return code;
3027 }
3028
3029 #endif /* #ifndef DISABLE_JIT */
3030
3031 typedef struct {
3032 guchar *code;
3033 const guchar *target;
3034 int absolute;
3035 int found;
3036 } PatchData;
3037
3038 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3039
3040 static int
3041 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3042 PatchData *pdata = (PatchData*)user_data;
3043 guchar *code = data;
3044 guint32 *thunks = data;
3045 guint32 *endthunks = (guint32*)(code + bsize);
3046 int count = 0;
3047 int difflow, diffhigh;
3048
3049 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3050 difflow = (char*)pdata->code - (char*)thunks;
3051 diffhigh = (char*)pdata->code - (char*)endthunks;
3052 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3053 return 0;
3054
3055 /*
3056 * The thunk is composed of 3 words:
3057 * load constant from thunks [2] into ARM_IP
3058 * bx to ARM_IP
3059 * address constant
3060 * Note that the LR register is already setup
3061 */
3062 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3063 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3064 while (thunks < endthunks) {
3065 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3066 if (thunks [2] == (guint32)pdata->target) {
3067 arm_patch (pdata->code, (guchar*)thunks);
3068 mono_arch_flush_icache (pdata->code, 4);
3069 pdata->found = 1;
3070 return 1;
3071 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3072 /* found a free slot instead: emit thunk */
3073 /* ARMREG_IP is fine to use since this can't be an IMT call
3074 * which is indirect
3075 */
3076 code = (guchar*)thunks;
3077 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3078 if (thumb_supported)
3079 ARM_BX (code, ARMREG_IP);
3080 else
3081 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3082 thunks [2] = (guint32)pdata->target;
3083 mono_arch_flush_icache ((guchar*)thunks, 12);
3084
3085 arm_patch (pdata->code, (guchar*)thunks);
3086 mono_arch_flush_icache (pdata->code, 4);
3087 pdata->found = 1;
3088 return 1;
3089 }
3090 /* skip 12 bytes, the size of the thunk */
3091 thunks += 3;
3092 count++;
3093 }
3094 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3095 }
3096 return 0;
3097 }
3098
3099 static void
3100 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3101 {
3102 PatchData pdata;
3103
3104 if (!domain)
3105 domain = mono_domain_get ();
3106
3107 pdata.code = code;
3108 pdata.target = target;
3109 pdata.absolute = absolute;
3110 pdata.found = 0;
3111
3112 if (dyn_code_mp) {
3113 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3114 }
3115
3116 if (pdata.found != 1) {
3117 mono_domain_lock (domain);
3118 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3119
3120 if (!pdata.found) {
3121 /* this uses the first available slot */
3122 pdata.found = 2;
3123 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3124 }
3125 mono_domain_unlock (domain);
3126 }
3127
3128 if (pdata.found != 1) {
3129 GHashTable *hash;
3130 GHashTableIter iter;
3131 MonoJitDynamicMethodInfo *ji;
3132
3133 /*
3134 * This might be a dynamic method, search its code manager. We can only
3135 * use the dynamic method containing CODE, since the others might be freed later.
3136 */
3137 pdata.found = 0;
3138
3139 mono_domain_lock (domain);
3140 hash = domain_jit_info (domain)->dynamic_code_hash;
3141 if (hash) {
3142 /* FIXME: Speed this up */
3143 g_hash_table_iter_init (&iter, hash);
3144 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3145 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3146 if (pdata.found == 1)
3147 break;
3148 }
3149 }
3150 mono_domain_unlock (domain);
3151 }
3152 if (pdata.found != 1)
3153 g_print ("thunk failed for %p from %p\n", target, code);
3154 g_assert (pdata.found == 1);
3155 }
3156
3157 static void
3158 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3159 {
3160 guint32 *code32 = (void*)code;
3161 guint32 ins = *code32;
3162 guint32 prim = (ins >> 25) & 7;
3163 guint32 tval = GPOINTER_TO_UINT (target);
3164
3165 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3166 if (prim == 5) { /* 101b */
3167 /* the diff starts 8 bytes from the branch opcode */
3168 gint diff = target - code - 8;
3169 gint tbits;
3170 gint tmask = 0xffffffff;
3171 if (tval & 1) { /* entering thumb mode */
3172 diff = target - 1 - code - 8;
3173 g_assert (thumb_supported);
3174 tbits = 0xf << 28; /* bl->blx bit pattern */
3175 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3176 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3177 if (diff & 2) {
3178 tbits |= 1 << 24;
3179 }
3180 tmask = ~(1 << 24); /* clear the link bit */
3181 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3182 } else {
3183 tbits = 0;
3184 }
3185 if (diff >= 0) {
3186 if (diff <= 33554431) {
3187 diff >>= 2;
3188 ins = (ins & 0xff000000) | diff;
3189 ins &= tmask;
3190 *code32 = ins | tbits;
3191 return;
3192 }
3193 } else {
3194 /* diff between 0 and -33554432 */
3195 if (diff >= -33554432) {
3196 diff >>= 2;
3197 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3198 ins &= tmask;
3199 *code32 = ins | tbits;
3200 return;
3201 }
3202 }
3203
3204 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3205 return;
3206 }
3207
3208 /*
3209 * The alternative call sequences looks like this:
3210 *
3211 * ldr ip, [pc] // loads the address constant
3212 * b 1f // jumps around the constant
3213 * address constant embedded in the code
3214 * 1f:
3215 * mov lr, pc
3216 * mov pc, ip
3217 *
3218 * There are two cases for patching:
3219 * a) at the end of method emission: in this case code points to the start
3220 * of the call sequence
3221 * b) during runtime patching of the call site: in this case code points
3222 * to the mov pc, ip instruction
3223 *
3224 * We have to handle also the thunk jump code sequence:
3225 *
3226 * ldr ip, [pc]
3227 * mov pc, ip
3228 * address constant // execution never reaches here
3229 */
3230 if ((ins & 0x0ffffff0) == 0x12fff10) {
3231 /* Branch and exchange: the address is constructed in a reg
3232 * We can patch BX when the code sequence is the following:
3233 * ldr ip, [pc, #0] ; 0x8
3234 * b 0xc
3235 * .word code_ptr
3236 * mov lr, pc
3237 * bx ips
3238 * */
3239 guint32 ccode [4];
3240 guint8 *emit = (guint8*)ccode;
3241 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3242 ARM_B (emit, 0);
3243 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3244 ARM_BX (emit, ARMREG_IP);
3245
3246 /*patching from magic trampoline*/
3247 if (ins == ccode [3]) {
3248 g_assert (code32 [-4] == ccode [0]);
3249 g_assert (code32 [-3] == ccode [1]);
3250 g_assert (code32 [-1] == ccode [2]);
3251 code32 [-2] = (guint32)target;
3252 return;
3253 }
3254 /*patching from JIT*/
3255 if (ins == ccode [0]) {
3256 g_assert (code32 [1] == ccode [1]);
3257 g_assert (code32 [3] == ccode [2]);
3258 g_assert (code32 [4] == ccode [3]);
3259 code32 [2] = (guint32)target;
3260 return;
3261 }
3262 g_assert_not_reached ();
3263 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3264 /*
3265 * ldr ip, [pc, #0]
3266 * b 0xc
3267 * .word code_ptr
3268 * blx ip
3269 */
3270 guint32 ccode [4];
3271 guint8 *emit = (guint8*)ccode;
3272 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3273 ARM_B (emit, 0);
3274 ARM_BLX_REG (emit, ARMREG_IP);
3275
3276 g_assert (code32 [-3] == ccode [0]);
3277 g_assert (code32 [-2] == ccode [1]);
3278 g_assert (code32 [0] == ccode [2]);
3279
3280 code32 [-1] = (guint32)target;
3281 } else {
3282 guint32 ccode [4];
3283 guint32 *tmp = ccode;
3284 guint8 *emit = (guint8*)tmp;
3285 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3286 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3287 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3288 ARM_BX (emit, ARMREG_IP);
3289 if (ins == ccode [2]) {
3290 g_assert_not_reached (); // should be -2 ...
3291 code32 [-1] = (guint32)target;
3292 return;
3293 }
3294 if (ins == ccode [0]) {
3295 /* handles both thunk jump code and the far call sequence */
3296 code32 [2] = (guint32)target;
3297 return;
3298 }
3299 g_assert_not_reached ();
3300 }
3301 // g_print ("patched with 0x%08x\n", ins);
3302 }
3303
3304 void
3305 arm_patch (guchar *code, const guchar *target)
3306 {
3307 arm_patch_general (NULL, code, target, NULL);
3308 }
3309
3310 /*
3311 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3312 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3313 * to be used with the emit macros.
3314 * Return -1 otherwise.
3315 */
3316 int
3317 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3318 {
3319 guint32 res, i;
3320 for (i = 0; i < 31; i+= 2) {
3321 res = (val << (32 - i)) | (val >> i);
3322 if (res & ~0xff)
3323 continue;
3324 *rot_amount = i? 32 - i: 0;
3325 return res;
3326 }
3327 return -1;
3328 }
3329
3330 /*
3331 * Emits in code a sequence of instructions that load the value 'val'
3332 * into the dreg register. Uses at most 4 instructions.
3333 */
3334 guint8*
3335 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3336 {
3337 int imm8, rot_amount;
3338 #if 0
3339 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3340 /* skip the constant pool */
3341 ARM_B (code, 0);
3342 *(int*)code = val;
3343 code += 4;
3344 return code;
3345 #endif
3346 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3347 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3348 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3349 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3350 } else {
3351 if (v7_supported) {
3352 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3353 if (val >> 16)
3354 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3355 return code;
3356 }
3357 if (val & 0xFF) {
3358 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3359 if (val & 0xFF00) {
3360 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3361 }
3362 if (val & 0xFF0000) {
3363 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3364 }
3365 if (val & 0xFF000000) {
3366 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3367 }
3368 } else if (val & 0xFF00) {
3369 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3370 if (val & 0xFF0000) {
3371 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3372 }
3373 if (val & 0xFF000000) {
3374 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3375 }
3376 } else if (val & 0xFF0000) {
3377 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3378 if (val & 0xFF000000) {
3379 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3380 }
3381 }
3382 //g_assert_not_reached ();
3383 }
3384 return code;
3385 }
3386
3387 gboolean
3388 mono_arm_thumb_supported (void)
3389 {
3390 return thumb_supported;
3391 }
3392
3393 #ifndef DISABLE_JIT
3394
3395 /*
3396 * emit_load_volatile_arguments:
3397 *
3398 * Load volatile arguments from the stack to the original input registers.
3399 * Required before a tail call.
3400 */
3401 static guint8*
3402 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3403 {
3404 MonoMethod *method = cfg->method;
3405 MonoMethodSignature *sig;
3406 MonoInst *inst;
3407 CallInfo *cinfo;
3408 guint32 i, pos;
3409
3410 /* FIXME: Generate intermediate code instead */
3411
3412 sig = mono_method_signature (method);
3413
3414 /* This is the opposite of the code in emit_prolog */
3415
3416 pos = 0;
3417
3418 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3419
3420 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3421 ArgInfo *ainfo = &cinfo->ret;
3422 inst = cfg->vret_addr;
3423 g_assert (arm_is_imm12 (inst->inst_offset));
3424 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3425 }
3426 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3427 ArgInfo *ainfo = cinfo->args + i;
3428 inst = cfg->args [pos];
3429
3430 if (cfg->verbose_level > 2)
3431 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3432 if (inst->opcode == OP_REGVAR) {
3433 if (ainfo->storage == RegTypeGeneral)
3434 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3435 else if (ainfo->storage == RegTypeFP) {
3436 g_assert_not_reached ();
3437 } else if (ainfo->storage == RegTypeBase) {
3438 // FIXME:
3439 NOT_IMPLEMENTED;
3440 /*
3441 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3442 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3443 } else {
3444 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3445 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3446 }
3447 */
3448 } else
3449 g_assert_not_reached ();
3450 } else {
3451 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3452 switch (ainfo->size) {
3453 case 1:
3454 case 2:
3455 // FIXME:
3456 NOT_IMPLEMENTED;
3457 break;
3458 case 8:
3459 g_assert (arm_is_imm12 (inst->inst_offset));
3460 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3461 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3462 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3463 break;
3464 default:
3465 if (arm_is_imm12 (inst->inst_offset)) {
3466 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3467 } else {
3468 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3469 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3470 }
3471 break;
3472 }
3473 } else if (ainfo->storage == RegTypeBaseGen) {
3474 // FIXME:
3475 NOT_IMPLEMENTED;
3476 } else if (ainfo->storage == RegTypeBase) {
3477 /* Nothing to do */
3478 } else if (ainfo->storage == RegTypeFP) {
3479 g_assert_not_reached ();
3480 } else if (ainfo->storage == RegTypeStructByVal) {
3481 int doffset = inst->inst_offset;
3482 int soffset = 0;
3483 int cur_reg;
3484 int size = 0;
3485 if (mono_class_from_mono_type (inst->inst_vtype))
3486 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3487 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3488 if (arm_is_imm12 (doffset)) {
3489 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3490 } else {
3491 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3492 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3493 }
3494 soffset += sizeof (gpointer);
3495 doffset += sizeof (gpointer);
3496 }
3497 if (ainfo->vtsize)
3498 // FIXME:
3499 NOT_IMPLEMENTED;
3500 } else if (ainfo->storage == RegTypeStructByAddr) {
3501 } else {
3502 // FIXME:
3503 NOT_IMPLEMENTED;
3504 }
3505 }
3506 pos ++;
3507 }
3508
3509 g_free (cinfo);
3510
3511 return code;
3512 }
3513
3514 void
3515 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3516 {
3517 MonoInst *ins;
3518 MonoCallInst *call;
3519 guint offset;
3520 guint8 *code = cfg->native_code + cfg->code_len;
3521 MonoInst *last_ins = NULL;
3522 guint last_offset = 0;
3523 int max_len, cpos;
3524 int imm8, rot_amount;
3525
3526 /* we don't align basic blocks of loops on arm */
3527
3528 if (cfg->verbose_level > 2)
3529 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3530
3531 cpos = bb->max_offset;
3532
3533 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3534 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3535 //g_assert (!mono_compile_aot);
3536 //cpos += 6;
3537 //if (bb->cil_code)
3538 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3539 /* this is not thread save, but good enough */
3540 /* fixme: howto handle overflows? */
3541 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3542 }
3543
3544 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3545 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3546 (gpointer)"mono_break");
3547 code = emit_call_seq (cfg, code);
3548 }
3549
3550 MONO_BB_FOR_EACH_INS (bb, ins) {
3551 offset = code - cfg->native_code;
3552
3553 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3554
3555 if (offset > (cfg->code_size - max_len - 16)) {
3556 cfg->code_size *= 2;
3557 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3558 code = cfg->native_code + offset;
3559 }
3560 // if (ins->cil_code)
3561 // g_print ("cil code\n");
3562 mono_debug_record_line_number (cfg, ins, offset);
3563
3564 switch (ins->opcode) {
3565 case OP_MEMORY_BARRIER:
3566 if (v6_supported) {
3567 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3568 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3569 }
3570 break;
3571 case OP_TLS_GET:
3572 #ifdef HAVE_AEABI_READ_TP
3573 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3574 (gpointer)"__aeabi_read_tp");
3575 code = emit_call_seq (cfg, code);
3576
3577 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3578 #else
3579 g_assert_not_reached ();
3580 #endif
3581 break;
3582 /*case OP_BIGMUL:
3583 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3584 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3585 break;
3586 case OP_BIGMUL_UN:
3587 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3588 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3589 break;*/
3590 case OP_STOREI1_MEMBASE_IMM:
3591 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3592 g_assert (arm_is_imm12 (ins->inst_offset));
3593 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3594 break;
3595 case OP_STOREI2_MEMBASE_IMM:
3596 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3597 g_assert (arm_is_imm8 (ins->inst_offset));
3598 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3599 break;
3600 case OP_STORE_MEMBASE_IMM:
3601 case OP_STOREI4_MEMBASE_IMM:
3602 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3603 g_assert (arm_is_imm12 (ins->inst_offset));
3604 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3605 break;
3606 case OP_STOREI1_MEMBASE_REG:
3607 g_assert (arm_is_imm12 (ins->inst_offset));
3608 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3609 break;
3610 case OP_STOREI2_MEMBASE_REG:
3611 g_assert (arm_is_imm8 (ins->inst_offset));
3612 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3613 break;
3614 case OP_STORE_MEMBASE_REG:
3615 case OP_STOREI4_MEMBASE_REG:
3616 /* this case is special, since it happens for spill code after lowering has been called */
3617 if (arm_is_imm12 (ins->inst_offset)) {
3618 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3619 } else {
3620 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3621 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3622 }
3623 break;
3624 case OP_STOREI1_MEMINDEX:
3625 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3626 break;
3627 case OP_STOREI2_MEMINDEX:
3628 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3629 break;
3630 case OP_STORE_MEMINDEX:
3631 case OP_STOREI4_MEMINDEX:
3632 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3633 break;
3634 case OP_LOADU4_MEM:
3635 g_assert_not_reached ();
3636 break;
3637 case OP_LOAD_MEMINDEX:
3638 case OP_LOADI4_MEMINDEX:
3639 case OP_LOADU4_MEMINDEX:
3640 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3641 break;
3642 case OP_LOADI1_MEMINDEX:
3643 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3644 break;
3645 case OP_LOADU1_MEMINDEX:
3646 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3647 break;
3648 case OP_LOADI2_MEMINDEX:
3649 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3650 break;
3651 case OP_LOADU2_MEMINDEX:
3652 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3653 break;
3654 case OP_LOAD_MEMBASE:
3655 case OP_LOADI4_MEMBASE:
3656 case OP_LOADU4_MEMBASE:
3657 /* this case is special, since it happens for spill code after lowering has been called */
3658 if (arm_is_imm12 (ins->inst_offset)) {
3659 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3660 } else {
3661 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3662 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3663 }
3664 break;
3665 case OP_LOADI1_MEMBASE:
3666 g_assert (arm_is_imm8 (ins->inst_offset));
3667 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3668 break;
3669 case OP_LOADU1_MEMBASE:
3670 g_assert (arm_is_imm12 (ins->inst_offset));
3671 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3672 break;
3673 case OP_LOADU2_MEMBASE:
3674 g_assert (arm_is_imm8 (ins->inst_offset));
3675 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3676 break;
3677 case OP_LOADI2_MEMBASE:
3678 g_assert (arm_is_imm8 (ins->inst_offset));
3679 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3680 break;
3681 case OP_ICONV_TO_I1:
3682 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3683 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3684 break;
3685 case OP_ICONV_TO_I2:
3686 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3687 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3688 break;
3689 case OP_ICONV_TO_U1:
3690 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3691 break;
3692 case OP_ICONV_TO_U2:
3693 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3694 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3695 break;
3696 case OP_COMPARE:
3697 case OP_ICOMPARE:
3698 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3699 break;
3700 case OP_COMPARE_IMM:
3701 case OP_ICOMPARE_IMM:
3702 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3703 g_assert (imm8 >= 0);
3704 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3705 break;
3706 case OP_BREAK:
3707 /*
3708 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3709 * So instead of emitting a trap, we emit a call a C function and place a
3710 * breakpoint there.
3711 */
3712 //*(int*)code = 0xef9f0001;
3713 //code += 4;
3714 //ARM_DBRK (code);
3715 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3716 (gpointer)"mono_break");
3717 code = emit_call_seq (cfg, code);
3718 break;
3719 case OP_RELAXED_NOP:
3720 ARM_NOP (code);
3721 break;
3722 case OP_NOP:
3723 case OP_DUMMY_USE:
3724 case OP_DUMMY_STORE:
3725 case OP_NOT_REACHED:
3726 case OP_NOT_NULL:
3727 break;
3728 case OP_SEQ_POINT: {
3729 int i;
3730 MonoInst *info_var = cfg->arch.seq_point_info_var;
3731 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3732 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3733 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3734 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3735 MonoInst *var;
3736 int dreg = ARMREG_LR;
3737
3738 if (cfg->soft_breakpoints) {
3739 g_assert (!cfg->compile_aot);
3740 }
3741
3742 /*
3743 * For AOT, we use one got slot per method, which will point to a
3744 * SeqPointInfo structure, containing all the information required
3745 * by the code below.
3746 */
3747 if (cfg->compile_aot) {
3748 g_assert (info_var);
3749 g_assert (info_var->opcode == OP_REGOFFSET);
3750 g_assert (arm_is_imm12 (info_var->inst_offset));
3751 }
3752
3753 if (!cfg->soft_breakpoints) {
3754 /*
3755 * Read from the single stepping trigger page. This will cause a
3756 * SIGSEGV when single stepping is enabled.
3757 * We do this _before_ the breakpoint, so single stepping after
3758 * a breakpoint is hit will step to the next IL offset.
3759 */
3760 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3761 }
3762
3763 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3764 if (cfg->soft_breakpoints) {
3765 /* Load the address of the sequence point trigger variable. */
3766 var = ss_read_var;
3767 g_assert (var);
3768 g_assert (var->opcode == OP_REGOFFSET);
3769 g_assert (arm_is_imm12 (var->inst_offset));
3770 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3771
3772 /* Read the value and check whether it is non-zero. */
3773 ARM_LDR_IMM (code, dreg, dreg, 0);
3774 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3775
3776 /* Load the address of the sequence point method. */
3777 var = ss_method_var;
3778 g_assert (var);
3779 g_assert (var->opcode == OP_REGOFFSET);
3780 g_assert (arm_is_imm12 (var->inst_offset));
3781 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3782
3783 /* Call it conditionally. */
3784 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3785 } else {
3786 if (cfg->compile_aot) {
3787 /* Load the trigger page addr from the variable initialized in the prolog */
3788 var = ss_trigger_page_var;
3789 g_assert (var);
3790 g_assert (var->opcode == OP_REGOFFSET);
3791 g_assert (arm_is_imm12 (var->inst_offset));
3792 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3793 } else {
3794 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3795 ARM_B (code, 0);
3796 *(int*)code = (int)ss_trigger_page;
3797 code += 4;
3798 }
3799 ARM_LDR_IMM (code, dreg, dreg, 0);
3800 }
3801 }
3802
3803 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3804
3805 if (cfg->soft_breakpoints) {
3806 /* Load the address of the breakpoint method into ip. */
3807 var = bp_method_var;
3808 g_assert (var);
3809 g_assert (var->opcode == OP_REGOFFSET);
3810 g_assert (arm_is_imm12 (var->inst_offset));
3811 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3812
3813 /*
3814 * A placeholder for a possible breakpoint inserted by
3815 * mono_arch_set_breakpoint ().
3816 */
3817 ARM_NOP (code);
3818 } else if (cfg->compile_aot) {
3819 guint32 offset = code - cfg->native_code;
3820 guint32 val;
3821
3822 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3823 /* Add the offset */
3824 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3825 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3826 if (val & 0xFF00)
3827 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3828 if (val & 0xFF0000)
3829 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3830 g_assert (!(val & 0xFF000000));
3831 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3832 ARM_LDR_IMM (code, dreg, dreg, 0);
3833
3834 /* What is faster, a branch or a load ? */
3835 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3836 /* The breakpoint instruction */
3837 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3838 } else {
3839 /*
3840 * A placeholder for a possible breakpoint inserted by
3841 * mono_arch_set_breakpoint ().
3842 */
3843 for (i = 0; i < 4; ++i)
3844 ARM_NOP (code);
3845 }
3846 break;
3847 }
3848 case OP_ADDCC:
3849 case OP_IADDCC:
3850 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3851 break;
3852 case OP_IADD:
3853 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3854 break;
3855 case OP_ADC:
3856 case OP_IADC:
3857 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3858 break;
3859 case OP_ADDCC_IMM:
3860 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3861 g_assert (imm8 >= 0);
3862 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3863 break;
3864 case OP_ADD_IMM:
3865 case OP_IADD_IMM:
3866 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3867 g_assert (imm8 >= 0);
3868 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3869 break;
3870 case OP_ADC_IMM:
3871 case OP_IADC_IMM:
3872 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3873 g_assert (imm8 >= 0);
3874 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3875 break;
3876 case OP_IADD_OVF:
3877 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3878 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3879 break;
3880 case OP_IADD_OVF_UN:
3881 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3882 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3883 break;
3884 case OP_ISUB_OVF:
3885 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3886 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3887 break;
3888 case OP_ISUB_OVF_UN:
3889 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3890 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3891 break;
3892 case OP_ADD_OVF_CARRY:
3893 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3894 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3895 break;
3896 case OP_ADD_OVF_UN_CARRY:
3897 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3898 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3899 break;
3900 case OP_SUB_OVF_CARRY:
3901 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3903 break;
3904 case OP_SUB_OVF_UN_CARRY:
3905 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3907 break;
3908 case OP_SUBCC:
3909 case OP_ISUBCC:
3910 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3911 break;
3912 case OP_SUBCC_IMM:
3913 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3914 g_assert (imm8 >= 0);
3915 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3916 break;
3917 case OP_ISUB:
3918 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3919 break;
3920 case OP_SBB:
3921 case OP_ISBB:
3922 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3923 break;
3924 case OP_SUB_IMM:
3925 case OP_ISUB_IMM:
3926 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3927 g_assert (imm8 >= 0);
3928 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3929 break;
3930 case OP_SBB_IMM:
3931 case OP_ISBB_IMM:
3932 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3933 g_assert (imm8 >= 0);
3934 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3935 break;
3936 case OP_ARM_RSBS_IMM:
3937 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3938 g_assert (imm8 >= 0);
3939 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3940 break;
3941 case OP_ARM_RSC_IMM:
3942 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3943 g_assert (imm8 >= 0);
3944 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3945 break;
3946 case OP_IAND:
3947 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3948 break;
3949 case OP_AND_IMM:
3950 case OP_IAND_IMM:
3951 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3952 g_assert (imm8 >= 0);
3953 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3954 break;
3955 case OP_IDIV:
3956 case OP_IDIV_UN:
3957 case OP_DIV_IMM:
3958 case OP_IREM:
3959 case OP_IREM_UN:
3960 case OP_REM_IMM:
3961 /* crappy ARM arch doesn't have a DIV instruction */
3962 g_assert_not_reached ();
3963 case OP_IOR:
3964 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3965 break;
3966 case OP_OR_IMM:
3967 case OP_IOR_IMM:
3968 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3969 g_assert (imm8 >= 0);
3970 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3971 break;
3972 case OP_IXOR:
3973 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3974 break;
3975 case OP_XOR_IMM:
3976 case OP_IXOR_IMM:
3977 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3978 g_assert (imm8 >= 0);
3979 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3980 break;
3981 case OP_ISHL:
3982 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3983 break;
3984 case OP_SHL_IMM:
3985 case OP_ISHL_IMM:
3986 if (ins->inst_imm)
3987 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3988 else if (ins->dreg != ins->sreg1)
3989 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3990 break;
3991 case OP_ISHR:
3992 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3993 break;
3994 case OP_SHR_IMM:
3995 case OP_ISHR_IMM:
3996 if (ins->inst_imm)
3997 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3998 else if (ins->dreg != ins->sreg1)
3999 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4000 break;
4001 case OP_SHR_UN_IMM:
4002 case OP_ISHR_UN_IMM:
4003 if (ins->inst_imm)
4004 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4005 else if (ins->dreg != ins->sreg1)
4006 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4007 break;
4008 case OP_ISHR_UN:
4009 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4010 break;
4011 case OP_INOT:
4012 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4013 break;
4014 case OP_INEG:
4015 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4016 break;
4017 case OP_IMUL:
4018 if (ins->dreg == ins->sreg2)
4019 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4020 else
4021 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4022 break;
4023 case OP_MUL_IMM:
4024 g_assert_not_reached ();
4025 break;
4026 case OP_IMUL_OVF:
4027 /* FIXME: handle ovf/ sreg2 != dreg */
4028 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4029 /* FIXME: MUL doesn't set the C/O flags on ARM */
4030 break;
4031 case OP_IMUL_OVF_UN:
4032 /* FIXME: handle ovf/ sreg2 != dreg */
4033 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4034 /* FIXME: MUL doesn't set the C/O flags on ARM */
4035 break;
4036 case OP_ICONST:
4037 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4038 break;
4039 case OP_AOTCONST:
4040 /* Load the GOT offset */
4041 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4042 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4043 ARM_B (code, 0);
4044 *(gpointer*)code = NULL;
4045 code += 4;
4046 /* Load the value from the GOT */
4047 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4048 break;
4049 case OP_ICONV_TO_I4:
4050 case OP_ICONV_TO_U4:
4051 case OP_MOVE:
4052 if (ins->dreg != ins->sreg1)
4053 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4054 break;
4055 case OP_SETLRET: {
4056 int saved = ins->sreg2;
4057 if (ins->sreg2 == ARM_LSW_REG) {
4058 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4059 saved = ARMREG_LR;
4060 }
4061 if (ins->sreg1 != ARM_LSW_REG)
4062 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4063 if (saved != ARM_MSW_REG)
4064 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4065 break;
4066 }
4067 case OP_FMOVE:
4068 if (IS_FPA)
4069 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4070 else if (IS_VFP)
4071 ARM_CPYD (code, ins->dreg, ins->sreg1);
4072 break;
4073 case OP_FCONV_TO_R4:
4074 if (IS_FPA)
4075 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4076 else if (IS_VFP) {
4077 ARM_CVTD (code, ins->dreg, ins->sreg1);
4078 ARM_CVTS (code, ins->dreg, ins->dreg);
4079 }
4080 break;
4081 case OP_JMP:
4082 /*
4083 * Keep in sync with mono_arch_emit_epilog
4084 */
4085 g_assert (!cfg->method->save_lmf);
4086
4087 code = emit_load_volatile_arguments (cfg, code);
4088
4089 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4090 if (iphone_abi) {
4091 if (cfg->used_int_regs)
4092 ARM_POP (code, cfg->used_int_regs);
4093 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4094 } else {
4095 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4096 }
4097 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4098 if (cfg->compile_aot) {
4099 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4100 ARM_B (code, 0);
4101 *(gpointer*)code = NULL;
4102 code += 4;
4103 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4104 } else {
4105 ARM_B (code, 0);
4106 }
4107 break;
4108 case OP_CHECK_THIS:
4109 /* ensure ins->sreg1 is not NULL */
4110 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4111 break;
4112 case OP_ARGLIST: {
4113 g_assert (cfg->sig_cookie < 128);
4114 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4115 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4116 break;
4117 }
4118 case OP_FCALL:
4119 case OP_LCALL:
4120 case OP_VCALL:
4121 case OP_VCALL2:
4122 case OP_VOIDCALL:
4123 case OP_CALL:
4124 call = (MonoCallInst*)ins;
4125 if (ins->flags & MONO_INST_HAS_METHOD)
4126 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4127 else
4128 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4129 code = emit_call_seq (cfg, code);
4130 ins->flags |= MONO_INST_GC_CALLSITE;
4131 ins->backend.pc_offset = code - cfg->native_code;
4132 code = emit_move_return_value (cfg, ins, code);
4133 break;
4134 case OP_FCALL_REG:
4135 case OP_LCALL_REG:
4136 case OP_VCALL_REG:
4137 case OP_VCALL2_REG:
4138 case OP_VOIDCALL_REG:
4139 case OP_CALL_REG:
4140 code = emit_call_reg (code, ins->sreg1);
4141 ins->flags |= MONO_INST_GC_CALLSITE;
4142 ins->backend.pc_offset = code - cfg->native_code;
4143 code = emit_move_return_value (cfg, ins, code);
4144 break;
4145 case OP_FCALL_MEMBASE:
4146 case OP_LCALL_MEMBASE:
4147 case OP_VCALL_MEMBASE:
4148 case OP_VCALL2_MEMBASE:
4149 case OP_VOIDCALL_MEMBASE:
4150 case OP_CALL_MEMBASE:
4151 g_assert (arm_is_imm12 (ins->inst_offset));
4152 g_assert (ins->sreg1 != ARMREG_LR);
4153 call = (MonoCallInst*)ins;
4154 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4155 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4156 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4157 /*
4158 * We can't embed the method in the code stream in PIC code, or
4159 * in gshared code.
4160 * Instead, we put it in V5 in code emitted by
4161 * mono_arch_emit_imt_argument (), and embed NULL here to
4162 * signal the IMT thunk that the value is in V5.
4163 */
4164 if (call->dynamic_imt_arg)
4165 *((gpointer*)code) = NULL;
4166 else
4167 *((gpointer*)code) = (gpointer)call->method;
4168 code += 4;
4169 } else {
4170 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4171 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4172 }
4173 ins->flags |= MONO_INST_GC_CALLSITE;
4174 ins->backend.pc_offset = code - cfg->native_code;
4175 code = emit_move_return_value (cfg, ins, code);
4176 break;
4177 case OP_LOCALLOC: {
4178 /* keep alignment */
4179 int alloca_waste = cfg->param_area;
4180 alloca_waste += 7;
4181 alloca_waste &= ~7;
4182 /* round the size to 8 bytes */
4183 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4184 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4185 if (alloca_waste)
4186 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4187 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4188 /* memzero the area: dreg holds the size, sp is the pointer */
4189 if (ins->flags & MONO_INST_INIT) {
4190 guint8 *start_loop, *branch_to_cond;
4191 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4192 branch_to_cond = code;
4193 ARM_B (code, 0);
4194 start_loop = code;
4195 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4196 arm_patch (branch_to_cond, code);
4197 /* decrement by 4 and set flags */
4198 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4199 ARM_B_COND (code, ARMCOND_GE, 0);
4200 arm_patch (code - 4, start_loop);
4201 }
4202 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4203 break;
4204 }
4205 case OP_DYN_CALL: {
4206 int i;
4207 MonoInst *var = cfg->dyn_call_var;
4208
4209 g_assert (var->opcode == OP_REGOFFSET);
4210 g_assert (arm_is_imm12 (var->inst_offset));
4211
4212 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4213 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4214 /* ip = ftn */
4215 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4216
4217 /* Save args buffer */
4218 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4219
4220 /* Set stack slots using R0 as scratch reg */
4221 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4222 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4223 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4224 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4225 }
4226
4227 /* Set argument registers */
4228 for (i = 0; i < PARAM_REGS; ++i)
4229 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4230
4231 /* Make the call */
4232 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4233 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4234
4235 /* Save result */
4236 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4237 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4238 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4239 break;
4240 }
4241 case OP_THROW: {
4242 if (ins->sreg1 != ARMREG_R0)
4243 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4244 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4245 (gpointer)"mono_arch_throw_exception");
4246 code = emit_call_seq (cfg, code);
4247 break;
4248 }
4249 case OP_RETHROW: {
4250 if (ins->sreg1 != ARMREG_R0)
4251 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4252 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4253 (gpointer)"mono_arch_rethrow_exception");
4254 code = emit_call_seq (cfg, code);
4255 break;
4256 }
4257 case OP_START_HANDLER: {
4258 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4259 int i, rot_amount;
4260
4261 /* Reserve a param area, see filter-stack.exe */
4262 if (cfg->param_area) {
4263 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4264 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4265 } else {
4266 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4267 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4268 }
4269 }
4270
4271 if (arm_is_imm12 (spvar->inst_offset)) {
4272 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4273 } else {
4274 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4275 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4276 }
4277 break;
4278 }
4279 case OP_ENDFILTER: {
4280 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4281 int i, rot_amount;
4282
4283 /* Free the param area */
4284 if (cfg->param_area) {
4285 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4286 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4287 } else {
4288 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4289 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4290 }
4291 }
4292
4293 if (ins->sreg1 != ARMREG_R0)
4294 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4295 if (arm_is_imm12 (spvar->inst_offset)) {
4296 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4297 } else {
4298 g_assert (ARMREG_IP != spvar->inst_basereg);
4299 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4300 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4301 }
4302 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4303 break;
4304 }
4305 case OP_ENDFINALLY: {
4306 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4307 int i, rot_amount;
4308
4309 /* Free the param area */
4310 if (cfg->param_area) {
4311 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4312 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4313 } else {
4314 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4315 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4316 }
4317 }
4318
4319 if (arm_is_imm12 (spvar->inst_offset)) {
4320 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4321 } else {
4322 g_assert (ARMREG_IP != spvar->inst_basereg);
4323 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4324 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4325 }
4326 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4327 break;
4328 }
4329 case OP_CALL_HANDLER:
4330 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4331 ARM_BL (code, 0);
4332 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4333 break;
4334 case OP_LABEL:
4335 ins->inst_c0 = code - cfg->native_code;
4336 break;
4337 case OP_BR:
4338 /*if (ins->inst_target_bb->native_offset) {
4339 ARM_B (code, 0);
4340 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4341 } else*/ {
4342 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4343 ARM_B (code, 0);
4344 }
4345 break;
4346 case OP_BR_REG:
4347 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4348 break;
4349 case OP_SWITCH:
4350 /*
4351 * In the normal case we have:
4352 * ldr pc, [pc, ins->sreg1 << 2]
4353 * nop
4354 * If aot, we have:
4355 * ldr lr, [pc, ins->sreg1 << 2]
4356 * add pc, pc, lr
4357 * After follows the data.
4358 * FIXME: add aot support.
4359 */
4360 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4361 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4362 if (offset + max_len > (cfg->code_size - 16)) {
4363 cfg->code_size += max_len;
4364 cfg->code_size *= 2;
4365 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4366 code = cfg->native_code + offset;
4367 }
4368 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4369 ARM_NOP (code);
4370 code += 4 * GPOINTER_TO_INT (ins->klass);
4371 break;
4372 case OP_CEQ:
4373 case OP_ICEQ:
4374 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4376 break;
4377 case OP_CLT:
4378 case OP_ICLT:
4379 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4380 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4381 break;
4382 case OP_CLT_UN:
4383 case OP_ICLT_UN:
4384 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4385 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4386 break;
4387 case OP_CGT:
4388 case OP_ICGT:
4389 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4390 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4391 break;
4392 case OP_CGT_UN:
4393 case OP_ICGT_UN:
4394 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4395 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4396 break;
4397 case OP_COND_EXC_EQ:
4398 case OP_COND_EXC_NE_UN:
4399 case OP_COND_EXC_LT:
4400 case OP_COND_EXC_LT_UN:
4401 case OP_COND_EXC_GT:
4402 case OP_COND_EXC_GT_UN:
4403 case OP_COND_EXC_GE:
4404 case OP_COND_EXC_GE_UN:
4405 case OP_COND_EXC_LE:
4406 case OP_COND_EXC_LE_UN:
4407 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4408 break;
4409 case OP_COND_EXC_IEQ:
4410 case OP_COND_EXC_INE_UN:
4411 case OP_COND_EXC_ILT:
4412 case OP_COND_EXC_ILT_UN:
4413 case OP_COND_EXC_IGT:
4414 case OP_COND_EXC_IGT_UN:
4415 case OP_COND_EXC_IGE:
4416 case OP_COND_EXC_IGE_UN:
4417 case OP_COND_EXC_ILE:
4418 case OP_COND_EXC_ILE_UN:
4419 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4420 break;
4421 case OP_COND_EXC_C:
4422 case OP_COND_EXC_IC:
4423 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4424 break;
4425 case OP_COND_EXC_OV:
4426 case OP_COND_EXC_IOV:
4427 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4428 break;
4429 case OP_COND_EXC_NC:
4430 case OP_COND_EXC_INC:
4431 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4432 break;
4433 case OP_COND_EXC_NO:
4434 case OP_COND_EXC_INO:
4435 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4436 break;
4437 case OP_IBEQ:
4438 case OP_IBNE_UN:
4439 case OP_IBLT:
4440 case OP_IBLT_UN:
4441 case OP_IBGT:
4442 case OP_IBGT_UN:
4443 case OP_IBGE:
4444 case OP_IBGE_UN:
4445 case OP_IBLE:
4446 case OP_IBLE_UN:
4447 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4448 break;
4449
4450 /* floating point opcodes */
4451 #ifdef ARM_FPU_FPA
4452 case OP_R8CONST:
4453 if (cfg->compile_aot) {
4454 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4455 ARM_B (code, 1);
4456 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4457 code += 4;
4458 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4459 code += 4;
4460 } else {
4461 /* FIXME: we can optimize the imm load by dealing with part of
4462 * the displacement in LDFD (aligning to 512).
4463 */
4464 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4465 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4466 }
4467 break;
4468 case OP_R4CONST:
4469 if (cfg->compile_aot) {
4470 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4471 ARM_B (code, 0);
4472 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4473 code += 4;
4474 } else {
4475 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4476 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4477 }
4478 break;
4479 case OP_STORER8_MEMBASE_REG:
4480 /* This is generated by the local regalloc pass which runs after the lowering pass */
4481 if (!arm_is_fpimm8 (ins->inst_offset)) {
4482 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4483 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4484 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4485 } else {
4486 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4487 }
4488 break;
4489 case OP_LOADR8_MEMBASE:
4490 /* This is generated by the local regalloc pass which runs after the lowering pass */
4491 if (!arm_is_fpimm8 (ins->inst_offset)) {
4492 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4493 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4494 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4495 } else {
4496 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4497 }
4498 break;
4499 case OP_STORER4_MEMBASE_REG:
4500 g_assert (arm_is_fpimm8 (ins->inst_offset));
4501 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4502 break;
4503 case OP_LOADR4_MEMBASE:
4504 g_assert (arm_is_fpimm8 (ins->inst_offset));
4505 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4506 break;
4507 case OP_ICONV_TO_R_UN: {
4508 int tmpreg;
4509 tmpreg = ins->dreg == 0? 1: 0;
4510 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4511 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4512 ARM_B_COND (code, ARMCOND_GE, 8);
4513 /* save the temp register */
4514 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4515 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4516 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4517 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4518 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4519 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4520 /* skip the constant pool */
4521 ARM_B (code, 8);
4522 code += 4;
4523 *(int*)code = 0x41f00000;
4524 code += 4;
4525 *(int*)code = 0;
4526 code += 4;
4527 /* FIXME: adjust:
4528 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4529 * adfltd fdest, fdest, ftemp
4530 */
4531 break;
4532 }
4533 case OP_ICONV_TO_R4:
4534 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4535 break;
4536 case OP_ICONV_TO_R8:
4537 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4538 break;
4539
4540 #elif defined(ARM_FPU_VFP)
4541
4542 case OP_R8CONST:
4543 if (cfg->compile_aot) {
4544 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4545 ARM_B (code, 1);
4546 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4547 code += 4;
4548 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4549 code += 4;
4550 } else {
4551 /* FIXME: we can optimize the imm load by dealing with part of
4552 * the displacement in LDFD (aligning to 512).
4553 */
4554 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4555 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4556 }
4557 break;
4558 case OP_R4CONST:
4559 if (cfg->compile_aot) {
4560 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4561 ARM_B (code, 0);
4562 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4563 code += 4;
4564 ARM_CVTS (code, ins->dreg, ins->dreg);
4565 } else {
4566 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4567 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4568 ARM_CVTS (code, ins->dreg, ins->dreg);
4569 }
4570 break;
4571 case OP_STORER8_MEMBASE_REG:
4572 /* This is generated by the local regalloc pass which runs after the lowering pass */
4573 if (!arm_is_fpimm8 (ins->inst_offset)) {
4574 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4575 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4576 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4577 } else {
4578 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4579 }
4580 break;
4581 case OP_LOADR8_MEMBASE:
4582 /* This is generated by the local regalloc pass which runs after the lowering pass */
4583 if (!arm_is_fpimm8 (ins->inst_offset)) {
4584 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4585 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4586 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4587 } else {
4588 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4589 }
4590 break;
4591 case OP_STORER4_MEMBASE_REG:
4592 g_assert (arm_is_fpimm8 (ins->inst_offset));
4593 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4594 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4595 break;
4596 case OP_LOADR4_MEMBASE:
4597 g_assert (arm_is_fpimm8 (ins->inst_offset));
4598 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4599 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4600 break;
4601 case OP_ICONV_TO_R_UN: {
4602 g_assert_not_reached ();
4603 break;
4604 }
4605 case OP_ICONV_TO_R4:
4606 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4607 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4608 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4609 break;
4610 case OP_ICONV_TO_R8:
4611 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4612 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4613 break;
4614
4615 case OP_SETFRET:
4616 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4617 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4618 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4619 } else {
4620 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4621 }
4622 break;
4623
4624 #endif
4625
4626 case OP_FCONV_TO_I1:
4627 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4628 break;
4629 case OP_FCONV_TO_U1:
4630 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4631 break;
4632 case OP_FCONV_TO_I2:
4633 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4634 break;
4635 case OP_FCONV_TO_U2:
4636 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4637 break;
4638 case OP_FCONV_TO_I4:
4639 case OP_FCONV_TO_I:
4640 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4641 break;
4642 case OP_FCONV_TO_U4:
4643 case OP_FCONV_TO_U:
4644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4645 break;
4646 case OP_FCONV_TO_I8:
4647 case OP_FCONV_TO_U8:
4648 g_assert_not_reached ();
4649 /* Implemented as helper calls */
4650 break;
4651 case OP_LCONV_TO_R_UN:
4652 g_assert_not_reached ();
4653 /* Implemented as helper calls */
4654 break;
4655 case OP_LCONV_TO_OVF_I4_2: {
4656 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4657 /*
4658 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4659 */
4660
4661 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4662 high_bit_not_set = code;
4663 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4664
4665 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4666 valid_negative = code;
4667 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4668 invalid_negative = code;
4669 ARM_B_COND (code, ARMCOND_AL, 0);
4670
4671 arm_patch (high_bit_not_set, code);
4672
4673 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4674 valid_positive = code;
4675 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4676
4677 arm_patch (invalid_negative, code);
4678 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4679
4680 arm_patch (valid_negative, code);
4681 arm_patch (valid_positive, code);
4682
4683 if (ins->dreg != ins->sreg1)
4684 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4685 break;
4686 }
4687 #ifdef ARM_FPU_FPA
4688 case OP_FADD:
4689 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4690 break;
4691 case OP_FSUB:
4692 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4693 break;
4694 case OP_FMUL:
4695 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4696 break;
4697 case OP_FDIV:
4698 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 break;
4700 case OP_FNEG:
4701 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4702 break;
4703 #elif defined(ARM_FPU_VFP)
4704 case OP_FADD:
4705 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 break;
4707 case OP_FSUB:
4708 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 break;
4710 case OP_FMUL:
4711 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4712 break;
4713 case OP_FDIV:
4714 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 break;
4716 case OP_FNEG:
4717 ARM_NEGD (code, ins->dreg, ins->sreg1);
4718 break;
4719 #endif
4720 case OP_FREM:
4721 /* emulated */
4722 g_assert_not_reached ();
4723 break;
4724 case OP_FCOMPARE:
4725 if (IS_FPA) {
4726 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4727 } else if (IS_VFP) {
4728 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4729 ARM_FMSTAT (code);
4730 }
4731 break;
4732 case OP_FCEQ:
4733 if (IS_FPA) {
4734 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4735 } else if (IS_VFP) {
4736 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4737 ARM_FMSTAT (code);
4738 }
4739 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4740 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4741 break;
4742 case OP_FCLT:
4743 if (IS_FPA) {
4744 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4745 } else {
4746 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4747 ARM_FMSTAT (code);
4748 }
4749 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4751 break;
4752 case OP_FCLT_UN:
4753 if (IS_FPA) {
4754 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4755 } else if (IS_VFP) {
4756 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4757 ARM_FMSTAT (code);
4758 }
4759 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4760 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4761 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4762 break;
4763 case OP_FCGT:
4764 /* swapped */
4765 if (IS_FPA) {
4766 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4767 } else if (IS_VFP) {
4768 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4769 ARM_FMSTAT (code);
4770 }
4771 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4772 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4773 break;
4774 case OP_FCGT_UN:
4775 /* swapped */
4776 if (IS_FPA) {
4777 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4778 } else if (IS_VFP) {
4779 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4780 ARM_FMSTAT (code);
4781 }
4782 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4783 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4784 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4785 break;
4786 /* ARM FPA flags table:
4787 * N Less than ARMCOND_MI
4788 * Z Equal ARMCOND_EQ
4789 * C Greater Than or Equal ARMCOND_CS
4790 * V Unordered ARMCOND_VS
4791 */
4792 case OP_FBEQ:
4793 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4794 break;
4795 case OP_FBNE_UN:
4796 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4797 break;
4798 case OP_FBLT:
4799 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4800 break;
4801 case OP_FBLT_UN:
4802 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4803 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4804 break;
4805 case OP_FBGT:
4806 case OP_FBGT_UN:
4807 case OP_FBLE:
4808 case OP_FBLE_UN:
4809 g_assert_not_reached ();
4810 break;
4811 case OP_FBGE:
4812 if (IS_VFP) {
4813 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4814 } else {
4815 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4817 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4818 }
4819 break;
4820 case OP_FBGE_UN:
4821 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4822 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4823 break;
4824
4825 case OP_CKFINITE: {
4826 if (IS_FPA) {
4827 if (ins->dreg != ins->sreg1)
4828 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4829 } else if (IS_VFP) {
4830 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4831 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4832 ARM_B (code, 1);
4833 *(guint32*)code = 0xffffffff;
4834 code += 4;
4835 *(guint32*)code = 0x7fefffff;
4836 code += 4;
4837 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4838 ARM_FMSTAT (code);
4839 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4840 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4841 ARM_FMSTAT (code);
4842 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4843 ARM_CPYD (code, ins->dreg, ins->sreg1);
4844 }
4845 break;
4846 }
4847
4848 case OP_GC_LIVENESS_DEF:
4849 case OP_GC_LIVENESS_USE:
4850 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4851 ins->backend.pc_offset = code - cfg->native_code;
4852 break;
4853 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4854 ins->backend.pc_offset = code - cfg->native_code;
4855 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4856 break;
4857
4858 default:
4859 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4860 g_assert_not_reached ();
4861 }
4862
4863 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4864 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4865 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4866 g_assert_not_reached ();
4867 }
4868
4869 cpos += max_len;
4870
4871 last_ins = ins;
4872 last_offset = offset;
4873 }
4874
4875 cfg->code_len = code - cfg->native_code;
4876 }
4877
4878 #endif /* DISABLE_JIT */
4879
4880 #ifdef HAVE_AEABI_READ_TP
4881 void __aeabi_read_tp (void);
4882 #endif
4883
4884 void
4885 mono_arch_register_lowlevel_calls (void)
4886 {
4887 /* The signature doesn't matter */
4888 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4889 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4890
4891 #ifndef MONO_CROSS_COMPILE
4892 #ifdef HAVE_AEABI_READ_TP
4893 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4894 #endif
4895 #endif
4896 }
4897
4898 #define patch_lis_ori(ip,val) do {\
4899 guint16 *__lis_ori = (guint16*)(ip); \
4900 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4901 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4902 } while (0)
4903
4904 void
4905 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4906 {
4907 MonoJumpInfo *patch_info;
4908 gboolean compile_aot = !run_cctors;
4909
4910 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4911 unsigned char *ip = patch_info->ip.i + code;
4912 const unsigned char *target;
4913
4914 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4915 gpointer *jt = (gpointer*)(ip + 8);
4916 int i;
4917 /* jt is the inlined jump table, 2 instructions after ip
4918 * In the normal case we store the absolute addresses,
4919 * otherwise the displacements.
4920 */
4921 for (i = 0; i < patch_info->data.table->table_size; i++)
4922 jt [i] = code + (int)patch_info->data.table->table [i];
4923 continue;
4924 }
4925 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4926
4927 if (compile_aot) {
4928 switch (patch_info->type) {
4929 case MONO_PATCH_INFO_BB:
4930 case MONO_PATCH_INFO_LABEL:
4931 break;
4932 default:
4933 /* No need to patch these */
4934 continue;
4935 }
4936 }
4937
4938 switch (patch_info->type) {
4939 case MONO_PATCH_INFO_IP:
4940 g_assert_not_reached ();
4941 patch_lis_ori (ip, ip);
4942 continue;
4943 case MONO_PATCH_INFO_METHOD_REL:
4944 g_assert_not_reached ();
4945 *((gpointer *)(ip)) = code + patch_info->data.offset;
4946 continue;
4947 case MONO_PATCH_INFO_METHODCONST:
4948 case MONO_PATCH_INFO_CLASS:
4949 case MONO_PATCH_INFO_IMAGE:
4950 case MONO_PATCH_INFO_FIELD:
4951 case MONO_PATCH_INFO_VTABLE:
4952 case MONO_PATCH_INFO_IID:
4953 case MONO_PATCH_INFO_SFLDA:
4954 case MONO_PATCH_INFO_LDSTR:
4955 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4956 case MONO_PATCH_INFO_LDTOKEN:
4957 g_assert_not_reached ();
4958 /* from OP_AOTCONST : lis + ori */
4959 patch_lis_ori (ip, target);
4960 continue;
4961 case MONO_PATCH_INFO_R4:
4962 case MONO_PATCH_INFO_R8:
4963 g_assert_not_reached ();
4964 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4965 continue;
4966 case MONO_PATCH_INFO_EXC_NAME:
4967 g_assert_not_reached ();
4968 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4969 continue;
4970 case MONO_PATCH_INFO_NONE:
4971 case MONO_PATCH_INFO_BB_OVF:
4972 case MONO_PATCH_INFO_EXC_OVF:
4973 /* everything is dealt with at epilog output time */
4974 continue;
4975 default:
4976 break;
4977 }
4978 arm_patch_general (domain, ip, target, dyn_code_mp);
4979 }
4980 }
4981
4982 #ifndef DISABLE_JIT
4983
4984 /*
4985 * Stack frame layout:
4986 *
4987 * ------------------- fp
4988 * MonoLMF structure or saved registers
4989 * -------------------
4990 * locals
4991 * -------------------
4992 * spilled regs
4993 * -------------------
4994 * optional 8 bytes for tracing
4995 * -------------------
4996 * param area size is cfg->param_area
4997 * ------------------- sp
4998 */
4999 guint8 *
5000 mono_arch_emit_prolog (MonoCompile *cfg)
5001 {
5002 MonoMethod *method = cfg->method;
5003 MonoBasicBlock *bb;
5004 MonoMethodSignature *sig;
5005 MonoInst *inst;
5006 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5007 guint8 *code;
5008 CallInfo *cinfo;
5009 int tracing = 0;
5010 int lmf_offset = 0;
5011 int prev_sp_offset, reg_offset;
5012
5013 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5014 tracing = 1;
5015
5016 sig = mono_method_signature (method);
5017 cfg->code_size = 256 + sig->param_count * 64;
5018 code = cfg->native_code = g_malloc (cfg->code_size);
5019
5020 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5021
5022 alloc_size = cfg->stack_offset;
5023 pos = 0;
5024 prev_sp_offset = 0;
5025
5026 if (!method->save_lmf) {
5027 if (iphone_abi) {
5028 /*
5029 * The iphone uses R7 as the frame pointer, and it points at the saved
5030 * r7+lr:
5031 * <lr>
5032 * r7 -> <r7>
5033 * <rest of frame>
5034 * We can't use r7 as a frame pointer since it points into the middle of
5035 * the frame, so we keep using our own frame pointer.
5036 * FIXME: Optimize this.
5037 */
5038 g_assert (darwin);
5039 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5040 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5041 prev_sp_offset += 8; /* r7 and lr */
5042 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5043 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5044
5045 /* No need to push LR again */
5046 if (cfg->used_int_regs)
5047 ARM_PUSH (code, cfg->used_int_regs);
5048 } else {
5049 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5050 prev_sp_offset += 4;
5051 }
5052 for (i = 0; i < 16; ++i) {
5053 if (cfg->used_int_regs & (1 << i))
5054 prev_sp_offset += 4;
5055 }
5056 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5057 reg_offset = 0;
5058 for (i = 0; i < 16; ++i) {
5059 if ((cfg->used_int_regs & (1 << i))) {
5060 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5061 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5062 reg_offset += 4;
5063 }
5064 }
5065 if (iphone_abi) {
5066 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5067 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5068 } else {
5069 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5070 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5071 }
5072 } else {
5073 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5074 ARM_PUSH (code, 0x5ff0);
5075 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5076 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5077 reg_offset = 0;
5078 for (i = 0; i < 16; ++i) {
5079 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5080 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5081 reg_offset += 4;
5082 }
5083 }
5084 pos += sizeof (MonoLMF) - prev_sp_offset;
5085 lmf_offset = pos;
5086 }
5087 alloc_size += pos;
5088 orig_alloc_size = alloc_size;
5089 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5090 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5091 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5092 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5093 }
5094
5095 /* the stack used in the pushed regs */
5096 if (prev_sp_offset & 4)
5097 alloc_size += 4;
5098 cfg->stack_usage = alloc_size;
5099 if (alloc_size) {
5100 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5101 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5102 } else {
5103 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5104 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5105 }
5106 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5107 }
5108 if (cfg->frame_reg != ARMREG_SP) {
5109 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5110 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5111 }
5112 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5113 prev_sp_offset += alloc_size;
5114
5115 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5116 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5117
5118 /* compute max_offset in order to use short forward jumps
5119 * we could skip do it on arm because the immediate displacement
5120 * for jumps is large enough, it may be useful later for constant pools
5121 */
5122 max_offset = 0;
5123 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5124 MonoInst *ins = bb->code;
5125 bb->max_offset = max_offset;
5126
5127 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5128 max_offset += 6;
5129
5130 MONO_BB_FOR_EACH_INS (bb, ins)
5131 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5132 }
5133
5134 /* store runtime generic context */
5135 if (cfg->rgctx_var) {
5136 MonoInst *ins = cfg->rgctx_var;
5137
5138 g_assert (ins->opcode == OP_REGOFFSET);
5139
5140 if (arm_is_imm12 (ins->inst_offset)) {
5141 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5142 } else {
5143 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5144 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5145 }
5146 }
5147
5148 /* load arguments allocated to register from the stack */
5149 pos = 0;
5150
5151 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5152
5153 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5154 ArgInfo *ainfo = &cinfo->ret;
5155 inst = cfg->vret_addr;
5156 g_assert (arm_is_imm12 (inst->inst_offset));
5157 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5158 }
5159
5160 if (sig->call_convention == MONO_CALL_VARARG) {
5161 ArgInfo *cookie = &cinfo->sig_cookie;
5162
5163 /* Save the sig cookie address */
5164 g_assert (cookie->storage == RegTypeBase);
5165
5166 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5167 g_assert (arm_is_imm12 (cfg->sig_cookie));
5168 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5169 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5170 }
5171
5172 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5173 ArgInfo *ainfo = cinfo->args + i;
5174 inst = cfg->args [pos];
5175
5176 if (cfg->verbose_level > 2)
5177 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5178 if (inst->opcode == OP_REGVAR) {
5179 if (ainfo->storage == RegTypeGeneral)
5180 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5181 else if (ainfo->storage == RegTypeFP) {
5182 g_assert_not_reached ();
5183 } else if (ainfo->storage == RegTypeBase) {
5184 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5185 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5186 } else {
5187 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5188 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5189 }
5190 } else
5191 g_assert_not_reached ();
5192
5193 if (cfg->verbose_level > 2)
5194 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5195 } else {
5196 /* the argument should be put on the stack: FIXME handle size != word */
5197 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5198 switch (ainfo->size) {
5199 case 1:
5200 if (arm_is_imm12 (inst->inst_offset))
5201 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5202 else {
5203 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5204 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5205 }
5206 break;
5207 case 2:
5208 if (arm_is_imm8 (inst->inst_offset)) {
5209 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5210 } else {
5211 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5212 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5213 }
5214 break;
5215 case 8:
5216 if (arm_is_imm12 (inst->inst_offset)) {
5217 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5218 } else {
5219 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5220 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5221 }
5222 if (arm_is_imm12 (inst->inst_offset + 4)) {
5223 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5224 } else {
5225 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5226 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5227 }
5228 break;
5229 default:
5230 if (arm_is_imm12 (inst->inst_offset)) {
5231 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5232 } else {
5233 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5234 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5235 }
5236 break;
5237 }
5238 } else if (ainfo->storage == RegTypeBaseGen) {
5239 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5240 g_assert (arm_is_imm12 (inst->inst_offset));
5241 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5242 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5243 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5244 } else if (ainfo->storage == RegTypeBase) {
5245 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5246 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5247 } else {
5248 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5249 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5250 }
5251
5252 switch (ainfo->size) {
5253 case 1:
5254 if (arm_is_imm8 (inst->inst_offset)) {
5255 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5256 } else {
5257 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5258 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5259 }
5260 break;
5261 case 2:
5262 if (arm_is_imm8 (inst->inst_offset)) {
5263 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5264 } else {
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5266 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5267 }
5268 break;
5269 case 8:
5270 if (arm_is_imm12 (inst->inst_offset)) {
5271 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5272 } else {
5273 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5274 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5275 }
5276 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5277 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5278 } else {
5279 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5280 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5281 }
5282 if (arm_is_imm12 (inst->inst_offset + 4)) {
5283 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5284 } else {
5285 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5286 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5287 }
5288 break;
5289 default:
5290 if (arm_is_imm12 (inst->inst_offset)) {
5291 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5292 } else {
5293 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5294 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5295 }
5296 break;
5297 }
5298 } else if (ainfo->storage == RegTypeFP) {
5299 g_assert_not_reached ();
5300 } else if (ainfo->storage == RegTypeStructByVal) {
5301 int doffset = inst->inst_offset;
5302 int soffset = 0;
5303 int cur_reg;
5304 int size = 0;
5305 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5306 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5307 if (arm_is_imm12 (doffset)) {
5308 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5309 } else {
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5311 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5312 }
5313 soffset += sizeof (gpointer);
5314 doffset += sizeof (gpointer);
5315 }
5316 if (ainfo->vtsize) {
5317 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5318 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5319 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5320 }
5321 } else if (ainfo->storage == RegTypeStructByAddr) {
5322 g_assert_not_reached ();
5323 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5324 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5325 } else
5326 g_assert_not_reached ();
5327 }
5328 pos++;
5329 }
5330
5331 if (method->save_lmf)
5332 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5333
5334 if (tracing)
5335 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5336
5337 if (cfg->arch.seq_point_info_var) {
5338 MonoInst *ins = cfg->arch.seq_point_info_var;
5339
5340 /* Initialize the variable from a GOT slot */
5341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5342 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5343 ARM_B (code, 0);
5344 *(gpointer*)code = NULL;
5345 code += 4;
5346 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5347
5348 g_assert (ins->opcode == OP_REGOFFSET);
5349
5350 if (arm_is_imm12 (ins->inst_offset)) {
5351 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5352 } else {
5353 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5354 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5355 }
5356 }
5357
5358 /* Initialize ss_trigger_page_var */
5359 if (!cfg->soft_breakpoints) {
5360 MonoInst *info_var = cfg->arch.seq_point_info_var;
5361 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5362 int dreg = ARMREG_LR;
5363
5364 if (info_var) {
5365 g_assert (info_var->opcode == OP_REGOFFSET);
5366 g_assert (arm_is_imm12 (info_var->inst_offset));
5367
5368 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5369 /* Load the trigger page addr */
5370 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5371 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5372 }
5373 }
5374
5375 if (cfg->arch.seq_point_read_var) {
5376 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5377 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5378 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5379
5380 g_assert (read_ins->opcode == OP_REGOFFSET);
5381 g_assert (arm_is_imm12 (read_ins->inst_offset));
5382 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5383 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5384 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5385 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5386
5387 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5388 ARM_B (code, 2);
5389 *(volatile int **)code = &ss_trigger_var;
5390 code += 4;
5391 *(gpointer*)code = single_step_func_wrapper;
5392 code += 4;
5393 *(gpointer*)code = breakpoint_func_wrapper;
5394 code += 4;
5395
5396 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5397 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5398 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5399 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5400 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5401 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5402 }
5403
5404 cfg->code_len = code - cfg->native_code;
5405 g_assert (cfg->code_len < cfg->code_size);
5406 g_free (cinfo);
5407
5408 return code;
5409 }
5410
5411 void
5412 mono_arch_emit_epilog (MonoCompile *cfg)
5413 {
5414 MonoMethod *method = cfg->method;
5415 int pos, i, rot_amount;
5416 int max_epilog_size = 16 + 20*4;
5417 guint8 *code;
5418 CallInfo *cinfo;
5419
5420 if (cfg->method->save_lmf)
5421 max_epilog_size += 128;
5422
5423 if (mono_jit_trace_calls != NULL)
5424 max_epilog_size += 50;
5425
5426 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5427 max_epilog_size += 50;
5428
5429 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5430 cfg->code_size *= 2;
5431 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5432 cfg->stat_code_reallocs++;
5433 }
5434
5435 /*
5436 * Keep in sync with OP_JMP
5437 */
5438 code = cfg->native_code + cfg->code_len;
5439
5440 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5441 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5442 }
5443 pos = 0;
5444
5445 /* Load returned vtypes into registers if needed */
5446 cinfo = cfg->arch.cinfo;
5447 if (cinfo->ret.storage == RegTypeStructByVal) {
5448 MonoInst *ins = cfg->ret;
5449
5450 if (arm_is_imm12 (ins->inst_offset)) {
5451 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5452 } else {
5453 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5454 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5455 }
5456 }
5457
5458 if (method->save_lmf) {
5459 int lmf_offset, reg, sp_adj, regmask;
5460 /* all but r0-r3, sp and pc */
5461 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5462 lmf_offset = pos;
5463
5464 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5465
5466 /* This points to r4 inside MonoLMF->iregs */
5467 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5468 reg = ARMREG_R4;
5469 regmask = 0x9ff0; /* restore lr to pc */
5470 /* Skip caller saved registers not used by the method */
5471 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5472 regmask &= ~(1 << reg);
5473 sp_adj += 4;
5474 reg ++;
5475 }
5476 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5477 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5478 /* restore iregs */
5479 ARM_POP (code, regmask);
5480 } else {
5481 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5482 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5483 } else {
5484 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5485 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5486 }
5487
5488 if (iphone_abi) {
5489 /* Restore saved gregs */
5490 if (cfg->used_int_regs)
5491 ARM_POP (code, cfg->used_int_regs);
5492 /* Restore saved r7, restore LR to PC */
5493 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5494 } else {
5495 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5496 }
5497 }
5498
5499 cfg->code_len = code - cfg->native_code;
5500
5501 g_assert (cfg->code_len < cfg->code_size);
5502
5503 }
5504
5505 /* remove once throw_exception_by_name is eliminated */
5506 static int
5507 exception_id_by_name (const char *name)
5508 {
5509 if (strcmp (name, "IndexOutOfRangeException") == 0)
5510 return MONO_EXC_INDEX_OUT_OF_RANGE;
5511 if (strcmp (name, "OverflowException") == 0)
5512 return MONO_EXC_OVERFLOW;
5513 if (strcmp (name, "ArithmeticException") == 0)
5514 return MONO_EXC_ARITHMETIC;
5515 if (strcmp (name, "DivideByZeroException") == 0)
5516 return MONO_EXC_DIVIDE_BY_ZERO;
5517 if (strcmp (name, "InvalidCastException") == 0)
5518 return MONO_EXC_INVALID_CAST;
5519 if (strcmp (name, "NullReferenceException") == 0)
5520 return MONO_EXC_NULL_REF;
5521 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5522 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5523 if (strcmp (name, "ArgumentException") == 0)
5524 return MONO_EXC_ARGUMENT;
5525 g_error ("Unknown intrinsic exception %s\n", name);
5526 return -1;
5527 }
5528
5529 void
5530 mono_arch_emit_exceptions (MonoCompile *cfg)
5531 {
5532 MonoJumpInfo *patch_info;
5533 int i;
5534 guint8 *code;
5535 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5536 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5537 int max_epilog_size = 50;
5538
5539 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5540 exc_throw_pos [i] = NULL;
5541 exc_throw_found [i] = 0;
5542 }
5543
5544 /* count the number of exception infos */
5545
5546 /*
5547 * make sure we have enough space for exceptions
5548 */
5549 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5550 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5551 i = exception_id_by_name (patch_info->data.target);
5552 if (!exc_throw_found [i]) {
5553 max_epilog_size += 32;
5554 exc_throw_found [i] = TRUE;
5555 }
5556 }
5557 }
5558
5559 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5560 cfg->code_size *= 2;
5561 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5562 cfg->stat_code_reallocs++;
5563 }
5564
5565 code = cfg->native_code + cfg->code_len;
5566
5567 /* add code to raise exceptions */
5568 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5569 switch (patch_info->type) {
5570 case MONO_PATCH_INFO_EXC: {
5571 MonoClass *exc_class;
5572 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5573
5574 i = exception_id_by_name (patch_info->data.target);
5575 if (exc_throw_pos [i]) {
5576 arm_patch (ip, exc_throw_pos [i]);
5577 patch_info->type = MONO_PATCH_INFO_NONE;
5578 break;
5579 } else {
5580 exc_throw_pos [i] = code;
5581 }
5582 arm_patch (ip, code);
5583
5584 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5585 g_assert (exc_class);
5586
5587 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5588 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5589 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5590 patch_info->data.name = "mono_arch_throw_corlib_exception";
5591 patch_info->ip.i = code - cfg->native_code;
5592 ARM_BL (code, 0);
5593 *(guint32*)(gpointer)code = exc_class->type_token;
5594 code += 4;
5595 break;
5596 }
5597 default:
5598 /* do nothing */
5599 break;
5600 }
5601 }
5602
5603 cfg->code_len = code - cfg->native_code;
5604
5605 g_assert (cfg->code_len < cfg->code_size);
5606
5607 }
5608
5609 #endif /* #ifndef DISABLE_JIT */
5610
5611 void
5612 mono_arch_finish_init (void)
5613 {
5614 lmf_tls_offset = mono_get_lmf_tls_offset ();
5615 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5616 }
5617
5618 void
5619 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5620 {
5621 }
5622
5623 MonoInst*
5624 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5625 {
5626 /* FIXME: */
5627 return NULL;
5628 }
5629
5630 gboolean
5631 mono_arch_print_tree (MonoInst *tree, int arity)
5632 {
5633 return 0;
5634 }
5635
5636 MonoInst*
5637 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5638 {
5639 return mono_get_domain_intrinsic (cfg);
5640 }
5641
5642 guint32
5643 mono_arch_get_patch_offset (guint8 *code)
5644 {
5645 /* OP_AOTCONST */
5646 return 8;
5647 }
5648
5649 void
5650 mono_arch_flush_register_windows (void)
5651 {
5652 }
5653
5654 #ifdef MONO_ARCH_HAVE_IMT
5655
5656 #ifndef DISABLE_JIT
5657
5658 void
5659 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5660 {
5661 if (cfg->compile_aot) {
5662 int method_reg = mono_alloc_ireg (cfg);
5663 MonoInst *ins;
5664
5665 call->dynamic_imt_arg = TRUE;
5666
5667 if (imt_arg) {
5668 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5669 } else {
5670 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5671 ins->dreg = method_reg;
5672 ins->inst_p0 = call->method;
5673 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5674 MONO_ADD_INS (cfg->cbb, ins);
5675
5676 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5677 }
5678 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5679
5680 /* Always pass in a register for simplicity */
5681 call->dynamic_imt_arg = TRUE;
5682
5683 cfg->uses_rgctx_reg = TRUE;
5684
5685 if (imt_arg) {
5686 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5687 } else {
5688 MonoInst *ins;
5689 int method_reg = mono_alloc_preg (cfg);
5690
5691 MONO_INST_NEW (cfg, ins, OP_PCONST);
5692 ins->inst_p0 = call->method;
5693 ins->dreg = method_reg;
5694 MONO_ADD_INS (cfg->cbb, ins);
5695
5696 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5697 }
5698 }
5699 }
5700
5701 #endif /* DISABLE_JIT */
5702
5703 MonoMethod*
5704 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5705 {
5706 guint32 *code_ptr = (guint32*)code;
5707 code_ptr -= 2;
5708
5709 if (mono_use_llvm)
5710 /* Passed in V5 */
5711 return (MonoMethod*)regs [ARMREG_V5];
5712
5713 /* The IMT value is stored in the code stream right after the LDC instruction. */
5714 if (!IS_LDR_PC (code_ptr [0])) {
5715 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5716 g_assert (IS_LDR_PC (code_ptr [0]));
5717 }
5718 if (code_ptr [1] == 0)
5719 /* This is AOTed code, the IMT method is in V5 */
5720 return (MonoMethod*)regs [ARMREG_V5];
5721 else
5722 return (MonoMethod*) code_ptr [1];
5723 }
5724
5725 MonoVTable*
5726 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5727 {
5728 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5729 }
5730
5731 #define ENABLE_WRONG_METHOD_CHECK 0
5732 #define BASE_SIZE (6 * 4)
5733 #define BSEARCH_ENTRY_SIZE (4 * 4)
5734 #define CMP_SIZE (3 * 4)
5735 #define BRANCH_SIZE (1 * 4)
5736 #define CALL_SIZE (2 * 4)
5737 #define WMC_SIZE (5 * 4)
5738 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5739
5740 static arminstr_t *
5741 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5742 {
5743 guint32 delta = DISTANCE (target, code);
5744 delta -= 8;
5745 g_assert (delta >= 0 && delta <= 0xFFF);
5746 *target = *target | delta;
5747 *code = value;
5748 return code + 1;
5749 }
5750
5751 gpointer
5752 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5753 gpointer fail_tramp)
5754 {
5755 int size, i, extra_space = 0;
5756 arminstr_t *code, *start, *vtable_target = NULL;
5757 gboolean large_offsets = FALSE;
5758 guint32 **constant_pool_starts;
5759
5760 size = BASE_SIZE;
5761 constant_pool_starts = g_new0 (guint32*, count);
5762
5763 for (i = 0; i < count; ++i) {
5764 MonoIMTCheckItem *item = imt_entries [i];
5765 if (item->is_equals) {
5766 gboolean fail_case = !item->check_target_idx && fail_tramp;
5767
5768 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5769 item->chunk_size += 32;
5770 large_offsets = TRUE;
5771 }
5772
5773 if (item->check_target_idx || fail_case) {
5774 if (!item->compare_done || fail_case)
5775 item->chunk_size += CMP_SIZE;
5776 item->chunk_size += BRANCH_SIZE;
5777 } else {
5778 #if ENABLE_WRONG_METHOD_CHECK
5779 item->chunk_size += WMC_SIZE;
5780 #endif
5781 }
5782 if (fail_case) {
5783 item->chunk_size += 16;
5784 large_offsets = TRUE;
5785 }
5786 item->chunk_size += CALL_SIZE;
5787 } else {
5788 item->chunk_size += BSEARCH_ENTRY_SIZE;
5789 imt_entries [item->check_target_idx]->compare_done = TRUE;
5790 }
5791 size += item->chunk_size;
5792 }
5793
5794 if (large_offsets)
5795 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5796
5797 if (fail_tramp)
5798 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5799 else
5800 code = mono_domain_code_reserve (domain, size);
5801 start = code;
5802
5803 #if DEBUG_IMT
5804 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5805 for (i = 0; i < count; ++i) {
5806 MonoIMTCheckItem *item = imt_entries [i];
5807 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5808 }
5809 #endif
5810
5811 if (large_offsets)
5812 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5813 else
5814 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5815 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5816 vtable_target = code;
5817 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5818
5819 if (mono_use_llvm) {
5820 /* LLVM always passes the IMT method in R5 */
5821 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5822 } else {
5823 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5824 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5825 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5826 }
5827
5828 for (i = 0; i < count; ++i) {
5829 MonoIMTCheckItem *item = imt_entries [i];
5830 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5831 gint32 vtable_offset;
5832
5833 item->code_target = (guint8*)code;
5834
5835 if (item->is_equals) {
5836 gboolean fail_case = !item->check_target_idx && fail_tramp;
5837
5838 if (item->check_target_idx || fail_case) {
5839 if (!item->compare_done || fail_case) {
5840 imt_method = code;
5841 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5842 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5843 }
5844 item->jmp_code = (guint8*)code;
5845 ARM_B_COND (code, ARMCOND_NE, 0);
5846 } else {
5847 /*Enable the commented code to assert on wrong method*/
5848 #if ENABLE_WRONG_METHOD_CHECK
5849 imt_method = code;
5850 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5851 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5852 ARM_B_COND (code, ARMCOND_NE, 1);
5853
5854 ARM_DBRK (code);
5855 #endif
5856 }
5857
5858 if (item->has_target_code) {
5859 target_code_ins = code;
5860 /* Load target address */
5861 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5862 /* Save it to the fourth slot */
5863 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5864 /* Restore registers and branch */
5865 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5866
5867 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5868 } else {
5869 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5870 if (!arm_is_imm12 (vtable_offset)) {
5871 /*
5872 * We need to branch to a computed address but we don't have
5873 * a free register to store it, since IP must contain the
5874 * vtable address. So we push the two values to the stack, and
5875 * load them both using LDM.
5876 */
5877 /* Compute target address */
5878 vtable_offset_ins = code;
5879 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5880 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5881 /* Save it to the fourth slot */
5882 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5883 /* Restore registers and branch */
5884 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5885
5886 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5887 } else {
5888 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5889 if (large_offsets)
5890 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5891 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5892 }
5893 }
5894
5895 if (fail_case) {
5896 arm_patch (item->jmp_code, (guchar*)code);
5897
5898 target_code_ins = code;
5899 /* Load target address */
5900 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5901 /* Save it to the fourth slot */
5902 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5903 /* Restore registers and branch */
5904 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5905
5906 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5907 item->jmp_code = NULL;
5908 }
5909
5910 if (imt_method)
5911 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5912
5913 /*must emit after unconditional branch*/
5914 if (vtable_target) {
5915 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5916 item->chunk_size += 4;
5917 vtable_target = NULL;
5918 }
5919
5920 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5921 constant_pool_starts [i] = code;
5922 if (extra_space) {
5923 code += extra_space;
5924 extra_space = 0;
5925 }
5926 } else {
5927 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5928 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5929
5930 item->jmp_code = (guint8*)code;
5931 ARM_B_COND (code, ARMCOND_GE, 0);
5932 ++extra_space;
5933 }
5934 }
5935
5936 for (i = 0; i < count; ++i) {
5937 MonoIMTCheckItem *item = imt_entries [i];
5938 if (item->jmp_code) {
5939 if (item->check_target_idx)
5940 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5941 }
5942 if (i > 0 && item->is_equals) {
5943 int j;
5944 arminstr_t *space_start = constant_pool_starts [i];
5945 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5946 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5947 }
5948 }
5949 }
5950
5951 #if DEBUG_IMT
5952 {
5953 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5954 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5955 g_free (buff);
5956 }
5957 #endif
5958
5959 g_free (constant_pool_starts);
5960
5961 mono_arch_flush_icache ((guint8*)start, size);
5962 mono_stats.imt_thunks_size += code - start;
5963
5964 g_assert (DISTANCE (start, code) <= size);
5965 return start;
5966 }
5967
5968 #endif
5969
5970 mgreg_t
5971 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5972 {
5973 return ctx->regs [reg];
5974 }
5975
5976 void
5977 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5978 {
5979 ctx->regs [reg] = val;
5980 }
5981
5982 /*
5983 * mono_arch_get_trampolines:
5984 *
5985 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5986 * for AOT.
5987 */
5988 GSList *
5989 mono_arch_get_trampolines (gboolean aot)
5990 {
5991 return mono_arm_get_exception_trampolines (aot);
5992 }
5993
5994 /*
5995 * mono_arch_set_breakpoint:
5996 *
5997 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5998 * The location should contain code emitted by OP_SEQ_POINT.
5999 */
6000 void
6001 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6002 {
6003 guint8 *code = ip;
6004 guint32 native_offset = ip - (guint8*)ji->code_start;
6005 MonoDebugOptions *opt = mini_get_debug_options ();
6006
6007 if (opt->soft_breakpoints) {
6008 g_assert (!ji->from_aot);
6009 code += 4;
6010 ARM_BLX_REG (code, ARMREG_LR);
6011 mono_arch_flush_icache (code - 4, 4);
6012 } else if (ji->from_aot) {
6013 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6014
6015 g_assert (native_offset % 4 == 0);
6016 g_assert (info->bp_addrs [native_offset / 4] == 0);
6017 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6018 } else {
6019 int dreg = ARMREG_LR;
6020
6021 /* Read from another trigger page */
6022 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6023 ARM_B (code, 0);
6024 *(int*)code = (int)bp_trigger_page;
6025 code += 4;
6026 ARM_LDR_IMM (code, dreg, dreg, 0);
6027
6028 mono_arch_flush_icache (code - 16, 16);
6029
6030 #if 0
6031 /* This is currently implemented by emitting an SWI instruction, which
6032 * qemu/linux seems to convert to a SIGILL.
6033 */
6034 *(int*)code = (0xef << 24) | 8;
6035 code += 4;
6036 mono_arch_flush_icache (code - 4, 4);
6037 #endif
6038 }
6039 }
6040
6041 /*
6042 * mono_arch_clear_breakpoint:
6043 *
6044 * Clear the breakpoint at IP.
6045 */
6046 void
6047 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6048 {
6049 MonoDebugOptions *opt = mini_get_debug_options ();
6050 guint8 *code = ip;
6051 int i;
6052
6053 if (opt->soft_breakpoints) {
6054 g_assert (!ji->from_aot);
6055 code += 4;
6056 ARM_NOP (code);
6057 mono_arch_flush_icache (code - 4, 4);
6058 } else if (ji->from_aot) {
6059 guint32 native_offset = ip - (guint8*)ji->code_start;
6060 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6061
6062 g_assert (native_offset % 4 == 0);
6063 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6064 info->bp_addrs [native_offset / 4] = 0;
6065 } else {
6066 for (i = 0; i < 4; ++i)
6067 ARM_NOP (code);
6068
6069 mono_arch_flush_icache (ip, code - ip);
6070 }
6071 }
6072
6073 /*
6074 * mono_arch_start_single_stepping:
6075 *
6076 * Start single stepping.
6077 */
6078 void
6079 mono_arch_start_single_stepping (void)
6080 {
6081 if (ss_trigger_page)
6082 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6083 else
6084 ss_trigger_var = 1;
6085 }
6086
6087 /*
6088 * mono_arch_stop_single_stepping:
6089 *
6090 * Stop single stepping.
6091 */
6092 void
6093 mono_arch_stop_single_stepping (void)
6094 {
6095 if (ss_trigger_page)
6096 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6097 else
6098 ss_trigger_var = 0;
6099 }
6100
6101 #if __APPLE__
6102 #define DBG_SIGNAL SIGBUS
6103 #else
6104 #define DBG_SIGNAL SIGSEGV
6105 #endif
6106
6107 /*
6108 * mono_arch_is_single_step_event:
6109 *
6110 * Return whenever the machine state in SIGCTX corresponds to a single
6111 * step event.
6112 */
6113 gboolean
6114 mono_arch_is_single_step_event (void *info, void *sigctx)
6115 {
6116 siginfo_t *sinfo = info;
6117
6118 if (!ss_trigger_page)
6119 return FALSE;
6120
6121 /* Sometimes the address is off by 4 */
6122 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6123 return TRUE;
6124 else
6125 return FALSE;
6126 }
6127
6128 /*
6129 * mono_arch_is_breakpoint_event:
6130 *
6131 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6132 */
6133 gboolean
6134 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6135 {
6136 siginfo_t *sinfo = info;
6137
6138 if (!ss_trigger_page)
6139 return FALSE;
6140
6141 if (sinfo->si_signo == DBG_SIGNAL) {
6142 /* Sometimes the address is off by 4 */
6143 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6144 return TRUE;
6145 else
6146 return FALSE;
6147 } else {
6148 return FALSE;
6149 }
6150 }
6151
6152 /*
6153 * mono_arch_skip_breakpoint:
6154 *
6155 * See mini-amd64.c for docs.
6156 */
6157 void
6158 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6159 {
6160 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6161 }
6162
6163 /*
6164 * mono_arch_skip_single_step:
6165 *
6166 * See mini-amd64.c for docs.
6167 */
6168 void
6169 mono_arch_skip_single_step (MonoContext *ctx)
6170 {
6171 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6172 }
6173
6174 /*
6175 * mono_arch_get_seq_point_info:
6176 *
6177 * See mini-amd64.c for docs.
6178 */
6179 gpointer
6180 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6181 {
6182 SeqPointInfo *info;
6183 MonoJitInfo *ji;
6184
6185 // FIXME: Add a free function
6186
6187 mono_domain_lock (domain);
6188 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6189 code);
6190 mono_domain_unlock (domain);
6191
6192 if (!info) {
6193 ji = mono_jit_info_table_find (domain, (char*)code);
6194 g_assert (ji);
6195
6196 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6197
6198 info->ss_trigger_page = ss_trigger_page;
6199 info->bp_trigger_page = bp_trigger_page;
6200
6201 mono_domain_lock (domain);
6202 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6203 code, info);
6204 mono_domain_unlock (domain);
6205 }
6206
6207 return info;
6208 }
6209
6210 /*
6211 * mono_arch_set_target:
6212 *
6213 * Set the target architecture the JIT backend should generate code for, in the form
6214 * of a GNU target triplet. Only used in AOT mode.
6215 */
6216 void
6217 mono_arch_set_target (char *mtriple)
6218 {
6219 /* The GNU target triple format is not very well documented */
6220 if (strstr (mtriple, "armv7")) {
6221 v6_supported = TRUE;
6222 v7_supported = TRUE;
6223 }
6224 if (strstr (mtriple, "armv6")) {
6225 v6_supported = TRUE;
6226 }
6227 if (strstr (mtriple, "darwin")) {
6228 v5_supported = TRUE;
6229 thumb_supported = TRUE;
6230 darwin = TRUE;
6231 iphone_abi = TRUE;
6232 }
6233 if (strstr (mtriple, "gnueabi"))
6234 eabi_supported = TRUE;
6235 }
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