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Merge pull request #1861 from saper/home-override
[mono-project.git] / mono / mini / mini-x86.c
blob53e5d6fbbd100281e84f66b44ab3ee564b0ac1b2
1 /*
2 * mini-x86.c: x86 backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 * Patrik Torstensson
8 *
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
12 */
13 #include "mini.h"
14 #include <string.h>
15 #include <math.h>
16 #ifdef HAVE_UNISTD_H
17 #include <unistd.h>
18 #endif
19
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
33
34 #include "trace.h"
35 #include "mini-x86.h"
36 #include "cpu-x86.h"
37 #include "ir-emit.h"
38 #include "mini-gc.h"
39
40 #ifndef TARGET_WIN32
41 #ifdef MONO_XEN_OPT
42 static gboolean optimize_for_xen = TRUE;
43 #else
44 #define optimize_for_xen 0
45 #endif
46 #endif
47
48 /* This mutex protects architecture specific caches */
49 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
50 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
51 static mono_mutex_t mini_arch_mutex;
52
53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54
55 #define ARGS_OFFSET 8
56
57 #ifdef TARGET_WIN32
58 /* Under windows, the default pinvoke calling convention is stdcall */
59 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #else
61 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
62 #endif
63
64 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
65
66 MonoBreakpointInfo
67 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68
69 static guint8*
70 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71
72 #ifdef __native_client_codegen__
73
74 /* Default alignment for Native Client is 32-byte. */
75 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76
77 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
78 /* Check that alignment doesn't cross an alignment boundary. */
79 guint8 *
80 mono_arch_nacl_pad (guint8 *code, int pad)
81 {
82 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83
84 if (pad == 0) return code;
85 /* assertion: alignment cannot cross a block boundary */
86 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
87 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
88 while (pad >= kMaxPadding) {
89 x86_padding (code, kMaxPadding);
90 pad -= kMaxPadding;
91 }
92 if (pad != 0) x86_padding (code, pad);
93 return code;
94 }
95
96 guint8 *
97 mono_arch_nacl_skip_nops (guint8 *code)
98 {
99 x86_skip_nops (code);
100 return code;
101 }
102
103 #endif /* __native_client_codegen__ */
104
105 /*
106 * The code generated for sequence points reads from this location, which is
107 * made read-only when single stepping is enabled.
108 */
109 static gpointer ss_trigger_page;
110
111 /* Enabled breakpoints read from this trigger page */
112 static gpointer bp_trigger_page;
113
114 const char*
115 mono_arch_regname (int reg)
116 {
117 switch (reg) {
118 case X86_EAX: return "%eax";
119 case X86_EBX: return "%ebx";
120 case X86_ECX: return "%ecx";
121 case X86_EDX: return "%edx";
122 case X86_ESP: return "%esp";
123 case X86_EBP: return "%ebp";
124 case X86_EDI: return "%edi";
125 case X86_ESI: return "%esi";
126 }
127 return "unknown";
128 }
129
130 const char*
131 mono_arch_fregname (int reg)
132 {
133 switch (reg) {
134 case 0:
135 return "%fr0";
136 case 1:
137 return "%fr1";
138 case 2:
139 return "%fr2";
140 case 3:
141 return "%fr3";
142 case 4:
143 return "%fr4";
144 case 5:
145 return "%fr5";
146 case 6:
147 return "%fr6";
148 case 7:
149 return "%fr7";
150 default:
151 return "unknown";
152 }
153 }
154
155 const char *
156 mono_arch_xregname (int reg)
157 {
158 switch (reg) {
159 case 0:
160 return "%xmm0";
161 case 1:
162 return "%xmm1";
163 case 2:
164 return "%xmm2";
165 case 3:
166 return "%xmm3";
167 case 4:
168 return "%xmm4";
169 case 5:
170 return "%xmm5";
171 case 6:
172 return "%xmm6";
173 case 7:
174 return "%xmm7";
175 default:
176 return "unknown";
177 }
178 }
179
180 void
181 mono_x86_patch (unsigned char* code, gpointer target)
182 {
183 x86_patch (code, (unsigned char*)target);
184 }
185
186 typedef enum {
187 ArgInIReg,
188 ArgInFloatSSEReg,
189 ArgInDoubleSSEReg,
190 ArgOnStack,
191 ArgValuetypeInReg,
192 ArgOnFloatFpStack,
193 ArgOnDoubleFpStack,
194 /* gsharedvt argument passed by addr */
195 ArgGSharedVt,
196 ArgNone
197 } ArgStorage;
198
199 typedef struct {
200 gint16 offset;
201 gint8 reg;
202 ArgStorage storage;
203 int nslots;
204 gboolean is_pair;
205
206 /* Only if storage == ArgValuetypeInReg */
207 ArgStorage pair_storage [2];
208 gint8 pair_regs [2];
209 } ArgInfo;
210
211 typedef struct {
212 int nargs;
213 guint32 stack_usage;
214 guint32 reg_usage;
215 guint32 freg_usage;
216 gboolean need_stack_align;
217 guint32 stack_align_amount;
218 gboolean vtype_retaddr;
219 /* The index of the vret arg in the argument list */
220 int vret_arg_index;
221 int vret_arg_offset;
222 /* Argument space popped by the callee */
223 int callee_stack_pop;
224 ArgInfo ret;
225 ArgInfo sig_cookie;
226 ArgInfo args [1];
227 } CallInfo;
228
229 #define FLOAT_PARAM_REGS 0
230
231 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232
233 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 {
235 if (!sig->pinvoke)
236 return NULL;
237
238 switch (sig->call_convention) {
239 case MONO_CALL_THISCALL:
240 return thiscall_param_regs;
241 default:
242 return NULL;
243 }
244 }
245
246 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
247 #define SMALL_STRUCTS_IN_REGS
248 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
249 #endif
250
251 static void inline
252 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 {
254 ainfo->offset = *stack_size;
255
256 if (!param_regs || param_regs [*gr] == X86_NREG) {
257 ainfo->storage = ArgOnStack;
258 ainfo->nslots = 1;
259 (*stack_size) += sizeof (gpointer);
260 }
261 else {
262 ainfo->storage = ArgInIReg;
263 ainfo->reg = param_regs [*gr];
264 (*gr) ++;
265 }
266 }
267
268 static void inline
269 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 {
271 ainfo->offset = *stack_size;
272
273 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274
275 ainfo->storage = ArgOnStack;
276 (*stack_size) += sizeof (gpointer) * 2;
277 ainfo->nslots = 2;
278 }
279
280 static void inline
281 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 {
283 ainfo->offset = *stack_size;
284
285 if (*gr >= FLOAT_PARAM_REGS) {
286 ainfo->storage = ArgOnStack;
287 (*stack_size) += is_double ? 8 : 4;
288 ainfo->nslots = is_double ? 2 : 1;
289 }
290 else {
291 /* A double register */
292 if (is_double)
293 ainfo->storage = ArgInDoubleSSEReg;
294 else
295 ainfo->storage = ArgInFloatSSEReg;
296 ainfo->reg = *gr;
297 (*gr) += 1;
298 }
299 }
300
301
302 static void
303 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 gboolean is_return,
305 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 {
307 guint32 size;
308 MonoClass *klass;
309
310 klass = mono_class_from_mono_type (type);
311 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312
313 #ifdef SMALL_STRUCTS_IN_REGS
314 if (sig->pinvoke && is_return) {
315 MonoMarshalType *info;
316
317 /*
318 * the exact rules are not very well documented, the code below seems to work with the
319 * code generated by gcc 3.3.3 -mno-cygwin.
320 */
321 info = mono_marshal_load_type_info (klass);
322 g_assert (info);
323
324 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325
326 /* Special case structs with only a float member */
327 if (info->num_fields == 1) {
328 int ftype = mini_type_get_underlying_type (gsctx, info->fields [0].field->type)->type;
329 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
330 ainfo->storage = ArgValuetypeInReg;
331 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
332 return;
333 }
334 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
335 ainfo->storage = ArgValuetypeInReg;
336 ainfo->pair_storage [0] = ArgOnFloatFpStack;
337 return;
338 }
339 }
340 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
341 ainfo->storage = ArgValuetypeInReg;
342 ainfo->pair_storage [0] = ArgInIReg;
343 ainfo->pair_regs [0] = return_regs [0];
344 if (info->native_size > 4) {
345 ainfo->pair_storage [1] = ArgInIReg;
346 ainfo->pair_regs [1] = return_regs [1];
347 }
348 return;
349 }
350 }
351 #endif
352
353 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
354 g_assert (size <= 4);
355 ainfo->storage = ArgValuetypeInReg;
356 ainfo->reg = param_regs [*gr];
357 (*gr)++;
358 return;
359 }
360
361 ainfo->offset = *stack_size;
362 ainfo->storage = ArgOnStack;
363 *stack_size += ALIGN_TO (size, sizeof (gpointer));
364 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
365 }
366
367 /*
368 * get_call_info:
369 *
370 * Obtain information about a call according to the calling convention.
371 * For x86 ELF, see the "System V Application Binary Interface Intel386
372 * Architecture Processor Supplment, Fourth Edition" document for more
373 * information.
374 * For x86 win32, see ???.
375 */
376 static CallInfo*
377 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 {
379 guint32 i, gr, fr, pstart;
380 const guint32 *param_regs;
381 MonoType *ret_type;
382 int n = sig->hasthis + sig->param_count;
383 guint32 stack_size = 0;
384 gboolean is_pinvoke = sig->pinvoke;
385
386 gr = 0;
387 fr = 0;
388 cinfo->nargs = n;
389
390 param_regs = callconv_param_regs(sig);
391
392 /* return value */
393 {
394 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
395 switch (ret_type->type) {
396 case MONO_TYPE_I1:
397 case MONO_TYPE_U1:
398 case MONO_TYPE_I2:
399 case MONO_TYPE_U2:
400 case MONO_TYPE_I4:
401 case MONO_TYPE_U4:
402 case MONO_TYPE_I:
403 case MONO_TYPE_U:
404 case MONO_TYPE_PTR:
405 case MONO_TYPE_FNPTR:
406 case MONO_TYPE_CLASS:
407 case MONO_TYPE_OBJECT:
408 case MONO_TYPE_SZARRAY:
409 case MONO_TYPE_ARRAY:
410 case MONO_TYPE_STRING:
411 cinfo->ret.storage = ArgInIReg;
412 cinfo->ret.reg = X86_EAX;
413 break;
414 case MONO_TYPE_U8:
415 case MONO_TYPE_I8:
416 cinfo->ret.storage = ArgInIReg;
417 cinfo->ret.reg = X86_EAX;
418 cinfo->ret.is_pair = TRUE;
419 break;
420 case MONO_TYPE_R4:
421 cinfo->ret.storage = ArgOnFloatFpStack;
422 break;
423 case MONO_TYPE_R8:
424 cinfo->ret.storage = ArgOnDoubleFpStack;
425 break;
426 case MONO_TYPE_GENERICINST:
427 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
428 cinfo->ret.storage = ArgInIReg;
429 cinfo->ret.reg = X86_EAX;
430 break;
431 }
432 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
433 cinfo->ret.storage = ArgOnStack;
434 cinfo->vtype_retaddr = TRUE;
435 break;
436 }
437 /* Fall through */
438 case MONO_TYPE_VALUETYPE:
439 case MONO_TYPE_TYPEDBYREF: {
440 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
441
442 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
443 if (cinfo->ret.storage == ArgOnStack) {
444 cinfo->vtype_retaddr = TRUE;
445 /* The caller passes the address where the value is stored */
446 }
447 break;
448 }
449 case MONO_TYPE_VAR:
450 case MONO_TYPE_MVAR:
451 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
452 cinfo->ret.storage = ArgOnStack;
453 cinfo->vtype_retaddr = TRUE;
454 break;
455 case MONO_TYPE_VOID:
456 cinfo->ret.storage = ArgNone;
457 break;
458 default:
459 g_error ("Can't handle as return value 0x%x", ret_type->type);
460 }
461 }
462
463 pstart = 0;
464 /*
465 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
466 * the first argument, allowing 'this' to be always passed in the first arg reg.
467 * Also do this if the first argument is a reference type, since virtual calls
468 * are sometimes made using calli without sig->hasthis set, like in the delegate
469 * invoke wrappers.
470 */
471 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
472 if (sig->hasthis) {
473 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
474 } else {
475 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
476 pstart = 1;
477 }
478 cinfo->vret_arg_offset = stack_size;
479 add_general (&gr, NULL, &stack_size, &cinfo->ret);
480 cinfo->vret_arg_index = 1;
481 } else {
482 /* this */
483 if (sig->hasthis)
484 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
485
486 if (cinfo->vtype_retaddr)
487 add_general (&gr, NULL, &stack_size, &cinfo->ret);
488 }
489
490 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
491 fr = FLOAT_PARAM_REGS;
492
493 /* Emit the signature cookie just before the implicit arguments */
494 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
495 }
496
497 for (i = pstart; i < sig->param_count; ++i) {
498 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
499 MonoType *ptype;
500
501 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
502 /* We allways pass the sig cookie on the stack for simplicity */
503 /*
504 * Prevent implicit arguments + the sig cookie from being passed
505 * in registers.
506 */
507 fr = FLOAT_PARAM_REGS;
508
509 /* Emit the signature cookie just before the implicit arguments */
510 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
511 }
512
513 if (sig->params [i]->byref) {
514 add_general (&gr, param_regs, &stack_size, ainfo);
515 continue;
516 }
517 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
518 switch (ptype->type) {
519 case MONO_TYPE_I1:
520 case MONO_TYPE_U1:
521 add_general (&gr, param_regs, &stack_size, ainfo);
522 break;
523 case MONO_TYPE_I2:
524 case MONO_TYPE_U2:
525 add_general (&gr, param_regs, &stack_size, ainfo);
526 break;
527 case MONO_TYPE_I4:
528 case MONO_TYPE_U4:
529 add_general (&gr, param_regs, &stack_size, ainfo);
530 break;
531 case MONO_TYPE_I:
532 case MONO_TYPE_U:
533 case MONO_TYPE_PTR:
534 case MONO_TYPE_FNPTR:
535 case MONO_TYPE_CLASS:
536 case MONO_TYPE_OBJECT:
537 case MONO_TYPE_STRING:
538 case MONO_TYPE_SZARRAY:
539 case MONO_TYPE_ARRAY:
540 add_general (&gr, param_regs, &stack_size, ainfo);
541 break;
542 case MONO_TYPE_GENERICINST:
543 if (!mono_type_generic_inst_is_valuetype (ptype)) {
544 add_general (&gr, param_regs, &stack_size, ainfo);
545 break;
546 }
547 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
548 /* gsharedvt arguments are passed by ref */
549 add_general (&gr, param_regs, &stack_size, ainfo);
550 g_assert (ainfo->storage == ArgOnStack);
551 ainfo->storage = ArgGSharedVt;
552 break;
553 }
554 /* Fall through */
555 case MONO_TYPE_VALUETYPE:
556 case MONO_TYPE_TYPEDBYREF:
557 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
558 break;
559 case MONO_TYPE_U8:
560 case MONO_TYPE_I8:
561 add_general_pair (&gr, param_regs, &stack_size, ainfo);
562 break;
563 case MONO_TYPE_R4:
564 add_float (&fr, &stack_size, ainfo, FALSE);
565 break;
566 case MONO_TYPE_R8:
567 add_float (&fr, &stack_size, ainfo, TRUE);
568 break;
569 case MONO_TYPE_VAR:
570 case MONO_TYPE_MVAR:
571 /* gsharedvt arguments are passed by ref */
572 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
573 add_general (&gr, param_regs, &stack_size, ainfo);
574 g_assert (ainfo->storage == ArgOnStack);
575 ainfo->storage = ArgGSharedVt;
576 break;
577 default:
578 g_error ("unexpected type 0x%x", ptype->type);
579 g_assert_not_reached ();
580 }
581 }
582
583 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
584 fr = FLOAT_PARAM_REGS;
585
586 /* Emit the signature cookie just before the implicit arguments */
587 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
588 }
589
590 if (cinfo->vtype_retaddr) {
591 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
592 cinfo->callee_stack_pop = 4;
593 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
594 /* Have to compensate for the stack space popped by the native callee */
595 cinfo->callee_stack_pop = stack_size;
596 }
597
598 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
599 cinfo->need_stack_align = TRUE;
600 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
601 stack_size += cinfo->stack_align_amount;
602 }
603
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
607 return cinfo;
608 }
609
610 static CallInfo*
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
612 {
613 int n = sig->hasthis + sig->param_count;
614 CallInfo *cinfo;
615
616 if (mp)
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
618 else
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
620
621 return get_call_info_internal (gsctx, cinfo, sig);
622 }
623
624 /*
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
629 *
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
632 *
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
637 */
638 int
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
640 {
641 int len, k, args_size = 0;
642 int size, pad;
643 guint32 align;
644 int offset = 8;
645 CallInfo *cinfo;
646
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
651
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
653
654 arg_info [0].offset = offset;
655
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
658 offset += 4;
659 }
660
661 if (csig->hasthis) {
662 args_size += sizeof (gpointer);
663 offset += 4;
664 }
665
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
669 offset += 4;
670 }
671
672 arg_info [0].size = args_size;
673
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
676
677 /* ignore alignment for now */
678 align = 1;
679
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
682 args_size += size;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
685 offset += pad;
686 arg_info [k + 1].offset = offset;
687 offset += size;
688
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
692 offset += 4;
693 }
694 }
695
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
698 else
699 align = 4;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
702
703 return args_size;
704 }
705
706 gboolean
707 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
708 {
709 MonoType *callee_ret;
710 CallInfo *c1, *c2;
711 gboolean res;
712
713 if (cfg->compile_aot && !cfg->full_aot)
714 /* OP_TAILCALL doesn't work with AOT */
715 return FALSE;
716
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
719 /*
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
722 */
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
727 res = FALSE;
728
729 g_free (c1);
730 g_free (c2);
731
732 return res;
733 }
734
735 /*
736 * Initialize the cpu to execute managed code.
737 */
738 void
739 mono_arch_cpu_init (void)
740 {
741 /* spec compliance requires running with double precision */
742 #ifndef _MSC_VER
743 guint16 fpcw;
744
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
750 #else
751 _control87 (_PC_53, MCW_PC);
752 #endif
753 }
754
755 /*
756 * Initialize architecture specific code.
757 */
758 void
759 mono_arch_init (void)
760 {
761 mono_mutex_init_recursive (&mini_arch_mutex);
762
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
766
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(ENABLE_GSHAREDVT)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
771 #endif
772 }
773
774 /*
775 * Cleanup architecture specific code.
776 */
777 void
778 mono_arch_cleanup (void)
779 {
780 if (ss_trigger_page)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
782 if (bp_trigger_page)
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 mono_mutex_destroy (&mini_arch_mutex);
785 }
786
787 /*
788 * This function returns the optimizations supported on this cpu.
789 */
790 guint32
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
792 {
793 #if !defined(__native_client__)
794 guint32 opts = 0;
795
796 *exclude_mask = 0;
797
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
800
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
803 else
804 *exclude_mask |= MONO_OPT_FCMOV;
805 } else {
806 *exclude_mask |= MONO_OPT_CMOV;
807 }
808
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
811 else
812 *exclude_mask |= MONO_OPT_SSE2;
813
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
818 #endif
819
820 return opts;
821 #else
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
823 #endif
824 }
825
826 /*
827 * This function test for all SSE functions supported.
828 *
829 * Returns a bitmask corresponding to all supported versions.
830 *
831 */
832 guint32
833 mono_arch_cpu_enumerate_simd_versions (void)
834 {
835 guint32 sse_opts = 0;
836
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
839
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
842
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
845
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
848
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
851
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
854
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
857
858 return sse_opts;
859 }
860
861 /*
862 * Determine whenever the trap whose info is in SIGINFO is caused by
863 * integer overflow.
864 */
865 gboolean
866 mono_arch_is_int_overflow (void *sigctx, void *info)
867 {
868 MonoContext ctx;
869 guint8* ip;
870
871 mono_sigctx_to_monoctx (sigctx, &ctx);
872
873 ip = (guint8*)ctx.eip;
874
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
876 gint32 reg;
877
878 /* idiv REG */
879 switch (x86_modrm_rm (ip [1])) {
880 case X86_EAX:
881 reg = ctx.eax;
882 break;
883 case X86_ECX:
884 reg = ctx.ecx;
885 break;
886 case X86_EDX:
887 reg = ctx.edx;
888 break;
889 case X86_EBX:
890 reg = ctx.ebx;
891 break;
892 case X86_ESI:
893 reg = ctx.esi;
894 break;
895 case X86_EDI:
896 reg = ctx.edi;
897 break;
898 default:
899 g_assert_not_reached ();
900 reg = -1;
901 }
902
903 if (reg == -1)
904 return TRUE;
905 }
906
907 return FALSE;
908 }
909
910 GList *
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
912 {
913 GList *vars = NULL;
914 int i;
915
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
919
920 /* unused vars */
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
922 continue;
923
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
926 continue;
927
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
934 }
935 }
936
937 vars = mono_varlist_sort (cfg, vars, 0);
938
939 return vars;
940 }
941
942 GList *
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
944 {
945 GList *regs = NULL;
946
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
951
952 return regs;
953 }
954
955 /*
956 * mono_arch_regalloc_cost:
957 *
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
960 * allocation.
961 */
962 guint32
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
964 {
965 MonoInst *ins = cfg->varinfo [vmv->idx];
966
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
970 else
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
973 }
974
975 static void
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
977 {
978 static int inited = FALSE;
979 static int count = 0;
980
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
983 return;
984 }
985
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
988
989 if (flag)
990 return;
991
992 if (!inited) {
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
994 inited = TRUE;
995 }
996 ++count;
997
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
999 }
1000
1001 static gboolean
1002 needs_stack_frame (MonoCompile *cfg)
1003 {
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1007
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1010 return TRUE;
1011 #endif
1012
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1015
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1018
1019 if (cfg->disable_omit_fp)
1020 result = TRUE;
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1022 result = TRUE;
1023 else if (cfg->method->save_lmf)
1024 result = TRUE;
1025 else if (cfg->stack_offset)
1026 result = TRUE;
1027 else if (cfg->param_area)
1028 result = TRUE;
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1030 result = TRUE;
1031 else if (header->num_clauses)
1032 result = TRUE;
1033 else if (sig->param_count + sig->hasthis)
1034 result = TRUE;
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1036 result = TRUE;
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1039 result = TRUE;
1040
1041 set_needs_stack_frame (cfg, result);
1042
1043 return cfg->arch.need_stack_frame;
1044 }
1045
1046 /*
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1049 */
1050 void
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1052 {
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1055 MonoInst *inst;
1056 guint32 locals_stack_size, locals_stack_align;
1057 int i, offset;
1058 gint32 *offsets;
1059 CallInfo *cinfo;
1060
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1063
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1065
1066 cfg->frame_reg = X86_EBP;
1067 offset = 0;
1068
1069 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1070 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1071 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1072 }
1073
1074 /* Reserve space to save LMF and caller saved registers */
1075
1076 if (cfg->method->save_lmf) {
1077 /* The LMF var is allocated normally */
1078 } else {
1079 if (cfg->used_int_regs & (1 << X86_EBX)) {
1080 offset += 4;
1081 }
1082
1083 if (cfg->used_int_regs & (1 << X86_EDI)) {
1084 offset += 4;
1085 }
1086
1087 if (cfg->used_int_regs & (1 << X86_ESI)) {
1088 offset += 4;
1089 }
1090 }
1091
1092 switch (cinfo->ret.storage) {
1093 case ArgValuetypeInReg:
1094 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1095 offset += 8;
1096 cfg->ret->opcode = OP_REGOFFSET;
1097 cfg->ret->inst_basereg = X86_EBP;
1098 cfg->ret->inst_offset = - offset;
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 /* Allocate locals */
1105 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1106 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1107 char *mname = mono_method_full_name (cfg->method, TRUE);
1108 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1109 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1110 g_free (mname);
1111 return;
1112 }
1113 if (locals_stack_align) {
1114 int prev_offset = offset;
1115
1116 offset += (locals_stack_align - 1);
1117 offset &= ~(locals_stack_align - 1);
1118
1119 while (prev_offset < offset) {
1120 prev_offset += 4;
1121 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1122 }
1123 }
1124 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1125 cfg->locals_max_stack_offset = - offset;
1126 /*
1127 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1128 * have locals larger than 8 bytes we need to make sure that
1129 * they have the appropriate offset.
1130 */
1131 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1132 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1133 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1134 if (offsets [i] != -1) {
1135 MonoInst *inst = cfg->varinfo [i];
1136 inst->opcode = OP_REGOFFSET;
1137 inst->inst_basereg = X86_EBP;
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1140 }
1141 }
1142 offset += locals_stack_size;
1143
1144
1145 /*
1146 * Allocate arguments+return value
1147 */
1148
1149 switch (cinfo->ret.storage) {
1150 case ArgOnStack:
1151 if (cfg->vret_addr) {
1152 /*
1153 * In the new IR, the cfg->vret_addr variable represents the
1154 * vtype return value.
1155 */
1156 cfg->vret_addr->opcode = OP_REGOFFSET;
1157 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1158 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1160 printf ("vret_addr =");
1161 mono_print_ins (cfg->vret_addr);
1162 }
1163 } else {
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1167 }
1168 break;
1169 case ArgValuetypeInReg:
1170 break;
1171 case ArgInIReg:
1172 cfg->ret->opcode = OP_REGVAR;
1173 cfg->ret->inst_c0 = cinfo->ret.reg;
1174 cfg->ret->dreg = cinfo->ret.reg;
1175 break;
1176 case ArgNone:
1177 case ArgOnFloatFpStack:
1178 case ArgOnDoubleFpStack:
1179 break;
1180 default:
1181 g_assert_not_reached ();
1182 }
1183
1184 if (sig->call_convention == MONO_CALL_VARARG) {
1185 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1186 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1187 }
1188
1189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1190 ArgInfo *ainfo = &cinfo->args [i];
1191 inst = cfg->args [i];
1192 if (inst->opcode != OP_REGVAR) {
1193 inst->opcode = OP_REGOFFSET;
1194 inst->inst_basereg = X86_EBP;
1195 }
1196 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1197 }
1198
1199 cfg->stack_offset = offset;
1200 }
1201
1202 void
1203 mono_arch_create_vars (MonoCompile *cfg)
1204 {
1205 MonoType *sig_ret;
1206 MonoMethodSignature *sig;
1207 CallInfo *cinfo;
1208
1209 sig = mono_method_signature (cfg->method);
1210
1211 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1212 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1213
1214 if (cinfo->ret.storage == ArgValuetypeInReg)
1215 cfg->ret_var_is_local = TRUE;
1216 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1217 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1218 }
1219
1220 if (cfg->method->save_lmf) {
1221 cfg->create_lmf_var = TRUE;
1222 cfg->lmf_ir = TRUE;
1223 #ifndef HOST_WIN32
1224 cfg->lmf_ir_mono_lmf = TRUE;
1225 #endif
1226 }
1227
1228 cfg->arch_eh_jit_info = 1;
1229 }
1230
1231 /*
1232 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1233 * so we try to do it just once when we have multiple fp arguments in a row.
1234 * We don't use this mechanism generally because for int arguments the generated code
1235 * is slightly bigger and new generation cpus optimize away the dependency chains
1236 * created by push instructions on the esp value.
1237 * fp_arg_setup is the first argument in the execution sequence where the esp register
1238 * is modified.
1239 */
1240 static G_GNUC_UNUSED int
1241 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1242 {
1243 int fp_space = 0;
1244 MonoType *t;
1245
1246 for (; start_arg < sig->param_count; ++start_arg) {
1247 t = mini_replace_type (sig->params [start_arg]);
1248 if (!t->byref && t->type == MONO_TYPE_R8) {
1249 fp_space += sizeof (double);
1250 *fp_arg_setup = start_arg;
1251 } else {
1252 break;
1253 }
1254 }
1255 return fp_space;
1256 }
1257
1258 static void
1259 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1260 {
1261 MonoMethodSignature *tmp_sig;
1262 int sig_reg;
1263
1264 /*
1265 * mono_ArgIterator_Setup assumes the signature cookie is
1266 * passed first and all the arguments which were before it are
1267 * passed on the stack after the signature. So compensate by
1268 * passing a different signature.
1269 */
1270 tmp_sig = mono_metadata_signature_dup (call->signature);
1271 tmp_sig->param_count -= call->signature->sentinelpos;
1272 tmp_sig->sentinelpos = 0;
1273 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1274
1275 if (cfg->compile_aot) {
1276 sig_reg = mono_alloc_ireg (cfg);
1277 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1279 } else {
1280 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1281 }
1282 }
1283
1284 #ifdef ENABLE_LLVM
1285 LLVMCallInfo*
1286 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1287 {
1288 int i, n;
1289 CallInfo *cinfo;
1290 ArgInfo *ainfo;
1291 LLVMCallInfo *linfo;
1292 MonoType *t, *sig_ret;
1293
1294 n = sig->param_count + sig->hasthis;
1295
1296 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1297 sig_ret = sig->ret;
1298
1299 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1300
1301 /*
1302 * LLVM always uses the native ABI while we use our own ABI, the
1303 * only difference is the handling of vtypes:
1304 * - we only pass/receive them in registers in some cases, and only
1305 * in 1 or 2 integer registers.
1306 */
1307 if (cinfo->ret.storage == ArgValuetypeInReg) {
1308 if (sig->pinvoke) {
1309 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1310 cfg->disable_llvm = TRUE;
1311 return linfo;
1312 }
1313
1314 cfg->exception_message = g_strdup ("vtype ret in call");
1315 cfg->disable_llvm = TRUE;
1316 /*
1317 linfo->ret.storage = LLVMArgVtypeInReg;
1318 for (j = 0; j < 2; ++j)
1319 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1320 */
1321 }
1322
1323 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1324 /* Vtype returned using a hidden argument */
1325 linfo->ret.storage = LLVMArgVtypeRetAddr;
1326 linfo->vret_arg_index = cinfo->vret_arg_index;
1327 }
1328
1329 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1330 // FIXME:
1331 cfg->exception_message = g_strdup ("vtype ret in call");
1332 cfg->disable_llvm = TRUE;
1333 }
1334
1335 for (i = 0; i < n; ++i) {
1336 ainfo = cinfo->args + i;
1337
1338 if (i >= sig->hasthis)
1339 t = sig->params [i - sig->hasthis];
1340 else
1341 t = &mono_defaults.int_class->byval_arg;
1342
1343 linfo->args [i].storage = LLVMArgNone;
1344
1345 switch (ainfo->storage) {
1346 case ArgInIReg:
1347 linfo->args [i].storage = LLVMArgInIReg;
1348 break;
1349 case ArgInDoubleSSEReg:
1350 case ArgInFloatSSEReg:
1351 linfo->args [i].storage = LLVMArgInFPReg;
1352 break;
1353 case ArgOnStack:
1354 if (mini_type_is_vtype (cfg, t)) {
1355 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1356 /* LLVM seems to allocate argument space for empty structures too */
1357 linfo->args [i].storage = LLVMArgNone;
1358 else
1359 linfo->args [i].storage = LLVMArgVtypeByVal;
1360 } else {
1361 linfo->args [i].storage = LLVMArgInIReg;
1362 if (t->byref) {
1363 if (t->type == MONO_TYPE_R4)
1364 linfo->args [i].storage = LLVMArgInFPReg;
1365 else if (t->type == MONO_TYPE_R8)
1366 linfo->args [i].storage = LLVMArgInFPReg;
1367 }
1368 }
1369 break;
1370 case ArgValuetypeInReg:
1371 if (sig->pinvoke) {
1372 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1373 cfg->disable_llvm = TRUE;
1374 return linfo;
1375 }
1376
1377 cfg->exception_message = g_strdup ("vtype arg");
1378 cfg->disable_llvm = TRUE;
1379 /*
1380 linfo->args [i].storage = LLVMArgVtypeInReg;
1381 for (j = 0; j < 2; ++j)
1382 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1383 */
1384 break;
1385 case ArgGSharedVt:
1386 linfo->args [i].storage = LLVMArgGSharedVt;
1387 break;
1388 default:
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1391 break;
1392 }
1393 }
1394
1395 return linfo;
1396 }
1397 #endif
1398
1399 static void
1400 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1401 {
1402 if (cfg->compute_gc_maps) {
1403 MonoInst *def;
1404
1405 /* Needs checking if the feature will be enabled again */
1406 g_assert_not_reached ();
1407
1408 /* On x86, the offsets are from the sp value before the start of the call sequence */
1409 if (t == NULL)
1410 t = &mono_defaults.int_class->byval_arg;
1411 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 }
1413 }
1414
1415 void
1416 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1417 {
1418 MonoType *sig_ret;
1419 MonoInst *arg, *in;
1420 MonoMethodSignature *sig;
1421 int i, j, n;
1422 CallInfo *cinfo;
1423 int sentinelpos = 0, sp_offset = 0;
1424
1425 sig = call->signature;
1426 n = sig->param_count + sig->hasthis;
1427 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1428
1429 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1430 call->call_info = cinfo;
1431
1432 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1433 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1434
1435 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1436 if (cinfo->ret.storage == ArgValuetypeInReg) {
1437 /*
1438 * Tell the JIT to use a more efficient calling convention: call using
1439 * OP_CALL, compute the result location after the call, and save the
1440 * result there.
1441 */
1442 call->vret_in_reg = TRUE;
1443 #if defined(__APPLE__)
1444 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1445 call->vret_in_reg_fp = TRUE;
1446 #endif
1447 if (call->vret_var)
1448 NULLIFY_INS (call->vret_var);
1449 }
1450 }
1451
1452 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1453
1454 /* Handle the case where there are no implicit arguments */
1455 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1456 emit_sig_cookie (cfg, call, cinfo);
1457 sp_offset = cinfo->sig_cookie.offset;
1458 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1459 }
1460
1461 /* Arguments are pushed in the reverse order */
1462 for (i = n - 1; i >= 0; i --) {
1463 ArgInfo *ainfo = cinfo->args + i;
1464 MonoType *orig_type, *t;
1465 int argsize;
1466
1467 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1468 MonoInst *vtarg;
1469
1470 /* Push the vret arg before the first argument */
1471 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1472 vtarg->type = STACK_MP;
1473 vtarg->inst_destbasereg = X86_ESP;
1474 vtarg->sreg1 = call->vret_var->dreg;
1475 vtarg->inst_offset = cinfo->ret.offset;
1476 MONO_ADD_INS (cfg->cbb, vtarg);
1477 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1478 }
1479
1480 if (i >= sig->hasthis)
1481 t = sig->params [i - sig->hasthis];
1482 else
1483 t = &mono_defaults.int_class->byval_arg;
1484 orig_type = t;
1485 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1486
1487 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1488
1489 in = call->args [i];
1490 arg->cil_code = in->cil_code;
1491 arg->sreg1 = in->dreg;
1492 arg->type = in->type;
1493
1494 g_assert (in->dreg != -1);
1495
1496 if (ainfo->storage == ArgGSharedVt) {
1497 arg->opcode = OP_OUTARG_VT;
1498 arg->sreg1 = in->dreg;
1499 arg->klass = in->klass;
1500 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1501 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1502 sp_offset += 4;
1503 MONO_ADD_INS (cfg->cbb, arg);
1504 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1505 guint32 align;
1506 guint32 size;
1507
1508 g_assert (in->klass);
1509
1510 if (t->type == MONO_TYPE_TYPEDBYREF) {
1511 size = sizeof (MonoTypedRef);
1512 align = sizeof (gpointer);
1513 }
1514 else {
1515 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1516 }
1517
1518 if (size > 0) {
1519 arg->opcode = OP_OUTARG_VT;
1520 arg->sreg1 = in->dreg;
1521 arg->klass = in->klass;
1522 arg->backend.size = size;
1523 arg->inst_p0 = call;
1524 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1525 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1526
1527 MONO_ADD_INS (cfg->cbb, arg);
1528 if (ainfo->storage != ArgValuetypeInReg) {
1529 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1530 }
1531 }
1532 } else {
1533 switch (ainfo->storage) {
1534 case ArgOnStack:
1535 if (!t->byref) {
1536 if (t->type == MONO_TYPE_R4) {
1537 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 argsize = 4;
1539 } else if (t->type == MONO_TYPE_R8) {
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1541 argsize = 8;
1542 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1544 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1545 argsize = 4;
1546 } else {
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1548 argsize = 4;
1549 }
1550 } else {
1551 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 argsize = 4;
1553 }
1554 break;
1555 case ArgInIReg:
1556 arg->opcode = OP_MOVE;
1557 arg->dreg = ainfo->reg;
1558 MONO_ADD_INS (cfg->cbb, arg);
1559 argsize = 0;
1560 break;
1561 default:
1562 g_assert_not_reached ();
1563 }
1564
1565 if (cfg->compute_gc_maps) {
1566 if (argsize == 4) {
1567 /* FIXME: The == STACK_OBJ check might be fragile ? */
1568 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1569 /* this */
1570 if (call->need_unbox_trampoline)
1571 /* The unbox trampoline transforms this into a managed pointer */
1572 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1573 else
1574 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1575 } else {
1576 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1577 }
1578 } else {
1579 /* i8/r8 */
1580 for (j = 0; j < argsize; j += 4)
1581 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 }
1583 }
1584 }
1585
1586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1587 /* Emit the signature cookie just before the implicit arguments */
1588 emit_sig_cookie (cfg, call, cinfo);
1589 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1590 }
1591 }
1592
1593 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1594 MonoInst *vtarg;
1595
1596 if (cinfo->ret.storage == ArgValuetypeInReg) {
1597 /* Already done */
1598 }
1599 else if (cinfo->ret.storage == ArgInIReg) {
1600 NOT_IMPLEMENTED;
1601 /* The return address is passed in a register */
1602 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1603 vtarg->sreg1 = call->inst.dreg;
1604 vtarg->dreg = mono_alloc_ireg (cfg);
1605 MONO_ADD_INS (cfg->cbb, vtarg);
1606
1607 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1608 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1609 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1610 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1611 }
1612 }
1613
1614 call->stack_usage = cinfo->stack_usage;
1615 call->stack_align_amount = cinfo->stack_align_amount;
1616 }
1617
1618 void
1619 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1620 {
1621 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1622 ArgInfo *ainfo = ins->inst_p1;
1623 int size = ins->backend.size;
1624
1625 if (ainfo->storage == ArgValuetypeInReg) {
1626 int dreg = mono_alloc_ireg (cfg);
1627 switch (size) {
1628 case 1:
1629 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1630 break;
1631 case 2:
1632 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1633 break;
1634 case 4:
1635 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1636 break;
1637 case 3: /* FIXME */
1638 default:
1639 g_assert_not_reached ();
1640 }
1641 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1642 }
1643 else {
1644 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1645 /* Pass by addr */
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1647 } else if (size <= 4) {
1648 int dreg = mono_alloc_ireg (cfg);
1649 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1650 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1651 } else if (size <= 20) {
1652 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1653 } else {
1654 // FIXME: Code growth
1655 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1656 }
1657 }
1658 }
1659
1660 void
1661 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1662 {
1663 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1664
1665 if (!ret->byref) {
1666 if (ret->type == MONO_TYPE_R4) {
1667 if (COMPILE_LLVM (cfg))
1668 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1669 /* Nothing to do */
1670 return;
1671 } else if (ret->type == MONO_TYPE_R8) {
1672 if (COMPILE_LLVM (cfg))
1673 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1674 /* Nothing to do */
1675 return;
1676 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1677 if (COMPILE_LLVM (cfg))
1678 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1679 else {
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1681 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1682 }
1683 return;
1684 }
1685 }
1686
1687 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1688 }
1689
1690 /*
1691 * Allow tracing to work with this interface (with an optional argument)
1692 */
1693 void*
1694 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1695 {
1696 guchar *code = p;
1697
1698 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1699 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1700
1701 /* if some args are passed in registers, we need to save them here */
1702 x86_push_reg (code, X86_EBP);
1703
1704 if (cfg->compile_aot) {
1705 x86_push_imm (code, cfg->method);
1706 x86_mov_reg_imm (code, X86_EAX, func);
1707 x86_call_reg (code, X86_EAX);
1708 } else {
1709 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1710 x86_push_imm (code, cfg->method);
1711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1712 x86_call_code (code, 0);
1713 }
1714 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1715
1716 return code;
1717 }
1718
1719 enum {
1720 SAVE_NONE,
1721 SAVE_STRUCT,
1722 SAVE_EAX,
1723 SAVE_EAX_EDX,
1724 SAVE_FP
1725 };
1726
1727 void*
1728 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1729 {
1730 guchar *code = p;
1731 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1732 MonoMethod *method = cfg->method;
1733 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1734
1735 switch (ret_type->type) {
1736 case MONO_TYPE_VOID:
1737 /* special case string .ctor icall */
1738 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1739 save_mode = SAVE_EAX;
1740 stack_usage = enable_arguments ? 8 : 4;
1741 } else
1742 save_mode = SAVE_NONE;
1743 break;
1744 case MONO_TYPE_I8:
1745 case MONO_TYPE_U8:
1746 save_mode = SAVE_EAX_EDX;
1747 stack_usage = enable_arguments ? 16 : 8;
1748 break;
1749 case MONO_TYPE_R4:
1750 case MONO_TYPE_R8:
1751 save_mode = SAVE_FP;
1752 stack_usage = enable_arguments ? 16 : 8;
1753 break;
1754 case MONO_TYPE_GENERICINST:
1755 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1756 save_mode = SAVE_EAX;
1757 stack_usage = enable_arguments ? 8 : 4;
1758 break;
1759 }
1760 /* Fall through */
1761 case MONO_TYPE_VALUETYPE:
1762 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1763 save_mode = SAVE_STRUCT;
1764 stack_usage = enable_arguments ? 4 : 0;
1765 break;
1766 default:
1767 save_mode = SAVE_EAX;
1768 stack_usage = enable_arguments ? 8 : 4;
1769 break;
1770 }
1771
1772 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1773
1774 switch (save_mode) {
1775 case SAVE_EAX_EDX:
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1778 if (enable_arguments) {
1779 x86_push_reg (code, X86_EDX);
1780 x86_push_reg (code, X86_EAX);
1781 arg_size = 8;
1782 }
1783 break;
1784 case SAVE_EAX:
1785 x86_push_reg (code, X86_EAX);
1786 if (enable_arguments) {
1787 x86_push_reg (code, X86_EAX);
1788 arg_size = 4;
1789 }
1790 break;
1791 case SAVE_FP:
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1794 if (enable_arguments) {
1795 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1796 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 arg_size = 8;
1798 }
1799 break;
1800 case SAVE_STRUCT:
1801 if (enable_arguments) {
1802 x86_push_membase (code, X86_EBP, 8);
1803 arg_size = 4;
1804 }
1805 break;
1806 case SAVE_NONE:
1807 default:
1808 break;
1809 }
1810
1811 if (cfg->compile_aot) {
1812 x86_push_imm (code, method);
1813 x86_mov_reg_imm (code, X86_EAX, func);
1814 x86_call_reg (code, X86_EAX);
1815 } else {
1816 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1817 x86_push_imm (code, method);
1818 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1819 x86_call_code (code, 0);
1820 }
1821
1822 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1823
1824 switch (save_mode) {
1825 case SAVE_EAX_EDX:
1826 x86_pop_reg (code, X86_EAX);
1827 x86_pop_reg (code, X86_EDX);
1828 break;
1829 case SAVE_EAX:
1830 x86_pop_reg (code, X86_EAX);
1831 break;
1832 case SAVE_FP:
1833 x86_fld_membase (code, X86_ESP, 0, TRUE);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1835 break;
1836 case SAVE_NONE:
1837 default:
1838 break;
1839 }
1840
1841 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842
1843 return code;
1844 }
1845
1846 #define EMIT_COND_BRANCH(ins,cond,sign) \
1847 if (ins->inst_true_bb->native_offset) { \
1848 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1849 } else { \
1850 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1851 if ((cfg->opt & MONO_OPT_BRANCH) && \
1852 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1853 x86_branch8 (code, cond, 0, sign); \
1854 else \
1855 x86_branch32 (code, cond, 0, sign); \
1856 }
1857
1858 /*
1859 * Emit an exception if condition is fail and
1860 * if possible do a directly branch to target
1861 */
1862 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1863 do { \
1864 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1865 if (tins == NULL) { \
1866 mono_add_patch_info (cfg, code - cfg->native_code, \
1867 MONO_PATCH_INFO_EXC, exc_name); \
1868 x86_branch32 (code, cond, 0, signed); \
1869 } else { \
1870 EMIT_COND_BRANCH (tins, cond, signed); \
1871 } \
1872 } while (0);
1873
1874 #define EMIT_FPCOMPARE(code) do { \
1875 x86_fcompp (code); \
1876 x86_fnstsw (code); \
1877 } while (0);
1878
1879
1880 static guint8*
1881 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1882 {
1883 gboolean needs_paddings = TRUE;
1884 guint32 pad_size;
1885 MonoJumpInfo *jinfo = NULL;
1886
1887 if (cfg->abs_patches) {
1888 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1889 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1890 needs_paddings = FALSE;
1891 }
1892
1893 if (cfg->compile_aot)
1894 needs_paddings = FALSE;
1895 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1896 This is required for code patching to be safe on SMP machines.
1897 */
1898 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1899 #ifndef __native_client_codegen__
1900 if (needs_paddings && pad_size)
1901 x86_padding (code, 4 - pad_size);
1902 #endif
1903
1904 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1905 x86_call_code (code, 0);
1906
1907 return code;
1908 }
1909
1910 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1911
1912 /*
1913 * mono_peephole_pass_1:
1914 *
1915 * Perform peephole opts which should/can be performed before local regalloc
1916 */
1917 void
1918 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1919 {
1920 MonoInst *ins, *n;
1921
1922 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1923 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1924
1925 switch (ins->opcode) {
1926 case OP_IADD_IMM:
1927 case OP_ADD_IMM:
1928 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1929 /*
1930 * X86_LEA is like ADD, but doesn't have the
1931 * sreg1==dreg restriction.
1932 */
1933 ins->opcode = OP_X86_LEA_MEMBASE;
1934 ins->inst_basereg = ins->sreg1;
1935 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1936 ins->opcode = OP_X86_INC_REG;
1937 break;
1938 case OP_SUB_IMM:
1939 case OP_ISUB_IMM:
1940 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1941 ins->opcode = OP_X86_LEA_MEMBASE;
1942 ins->inst_basereg = ins->sreg1;
1943 ins->inst_imm = -ins->inst_imm;
1944 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1945 ins->opcode = OP_X86_DEC_REG;
1946 break;
1947 case OP_COMPARE_IMM:
1948 case OP_ICOMPARE_IMM:
1949 /* OP_COMPARE_IMM (reg, 0)
1950 * -->
1951 * OP_X86_TEST_NULL (reg)
1952 */
1953 if (!ins->inst_imm)
1954 ins->opcode = OP_X86_TEST_NULL;
1955 break;
1956 case OP_X86_COMPARE_MEMBASE_IMM:
1957 /*
1958 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1959 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1960 * -->
1961 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1962 * OP_COMPARE_IMM reg, imm
1963 *
1964 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1965 */
1966 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1967 ins->inst_basereg == last_ins->inst_destbasereg &&
1968 ins->inst_offset == last_ins->inst_offset) {
1969 ins->opcode = OP_COMPARE_IMM;
1970 ins->sreg1 = last_ins->sreg1;
1971
1972 /* check if we can remove cmp reg,0 with test null */
1973 if (!ins->inst_imm)
1974 ins->opcode = OP_X86_TEST_NULL;
1975 }
1976
1977 break;
1978 case OP_X86_PUSH_MEMBASE:
1979 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1980 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1981 ins->inst_basereg == last_ins->inst_destbasereg &&
1982 ins->inst_offset == last_ins->inst_offset) {
1983 ins->opcode = OP_X86_PUSH;
1984 ins->sreg1 = last_ins->sreg1;
1985 }
1986 break;
1987 }
1988
1989 mono_peephole_ins (bb, ins);
1990 }
1991 }
1992
1993 void
1994 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1995 {
1996 MonoInst *ins, *n;
1997
1998 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1999 switch (ins->opcode) {
2000 case OP_ICONST:
2001 /* reg = 0 -> XOR (reg, reg) */
2002 /* XOR sets cflags on x86, so we cant do it always */
2003 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2004 MonoInst *ins2;
2005
2006 ins->opcode = OP_IXOR;
2007 ins->sreg1 = ins->dreg;
2008 ins->sreg2 = ins->dreg;
2009
2010 /*
2011 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2012 * since it takes 3 bytes instead of 7.
2013 */
2014 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2015 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STORE_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2018 }
2019 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2020 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2021 ins2->sreg1 = ins->dreg;
2022 }
2023 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2024 /* Continue iteration */
2025 }
2026 else
2027 break;
2028 }
2029 }
2030 break;
2031 case OP_IADD_IMM:
2032 case OP_ADD_IMM:
2033 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2034 ins->opcode = OP_X86_INC_REG;
2035 break;
2036 case OP_ISUB_IMM:
2037 case OP_SUB_IMM:
2038 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2039 ins->opcode = OP_X86_DEC_REG;
2040 break;
2041 }
2042
2043 mono_peephole_ins (bb, ins);
2044 }
2045 }
2046
2047 /*
2048 * mono_arch_lowering_pass:
2049 *
2050 * Converts complex opcodes into simpler ones so that each IR instruction
2051 * corresponds to one machine instruction.
2052 */
2053 void
2054 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2055 {
2056 MonoInst *ins, *next;
2057
2058 /*
2059 * FIXME: Need to add more instructions, but the current machine
2060 * description can't model some parts of the composite instructions like
2061 * cdq.
2062 */
2063 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2064 switch (ins->opcode) {
2065 case OP_IREM_IMM:
2066 case OP_IDIV_IMM:
2067 case OP_IDIV_UN_IMM:
2068 case OP_IREM_UN_IMM:
2069 /*
2070 * Keep the cases where we could generated optimized code, otherwise convert
2071 * to the non-imm variant.
2072 */
2073 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2074 break;
2075 mono_decompose_op_imm (cfg, bb, ins);
2076 break;
2077 default:
2078 break;
2079 }
2080 }
2081
2082 bb->max_vreg = cfg->next_vreg;
2083 }
2084
2085 static const int
2086 branch_cc_table [] = {
2087 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2089 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2090 };
2091
2092 /* Maps CMP_... constants to X86_CC_... constants */
2093 static const int
2094 cc_table [] = {
2095 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2096 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2097 };
2098
2099 static const int
2100 cc_signed_table [] = {
2101 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2102 FALSE, FALSE, FALSE, FALSE
2103 };
2104
2105 static unsigned char*
2106 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2107 {
2108 #define XMM_TEMP_REG 0
2109 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2110 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2111 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2112 /* optimize by assigning a local var for this use so we avoid
2113 * the stack manipulations */
2114 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2115 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2116 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2117 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2118 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2119 if (size == 1)
2120 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2121 else if (size == 2)
2122 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2123 return code;
2124 }
2125 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2126 x86_fnstcw_membase(code, X86_ESP, 0);
2127 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2128 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2129 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2130 x86_fldcw_membase (code, X86_ESP, 2);
2131 if (size == 8) {
2132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2133 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2134 x86_pop_reg (code, dreg);
2135 /* FIXME: need the high register
2136 * x86_pop_reg (code, dreg_high);
2137 */
2138 } else {
2139 x86_push_reg (code, X86_EAX); // SP = SP - 4
2140 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2141 x86_pop_reg (code, dreg);
2142 }
2143 x86_fldcw_membase (code, X86_ESP, 0);
2144 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2145
2146 if (size == 1)
2147 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2148 else if (size == 2)
2149 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2150 return code;
2151 }
2152
2153 static unsigned char*
2154 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2155 {
2156 int sreg = tree->sreg1;
2157 int need_touch = FALSE;
2158
2159 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2160 need_touch = TRUE;
2161 #endif
2162
2163 if (need_touch) {
2164 guint8* br[5];
2165
2166 /*
2167 * Under Windows:
2168 * If requested stack size is larger than one page,
2169 * perform stack-touch operation
2170 */
2171 /*
2172 * Generate stack probe code.
2173 * Under Windows, it is necessary to allocate one page at a time,
2174 * "touching" stack after each successful sub-allocation. This is
2175 * because of the way stack growth is implemented - there is a
2176 * guard page before the lowest stack page that is currently commited.
2177 * Stack normally grows sequentially so OS traps access to the
2178 * guard page and commits more pages when needed.
2179 */
2180 x86_test_reg_imm (code, sreg, ~0xFFF);
2181 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2182
2183 br[2] = code; /* loop */
2184 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2185 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2186
2187 /*
2188 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2189 * that follows only initializes the last part of the area.
2190 */
2191 /* Same as the init code below with size==0x1000 */
2192 if (tree->flags & MONO_INST_INIT) {
2193 x86_push_reg (code, X86_EAX);
2194 x86_push_reg (code, X86_ECX);
2195 x86_push_reg (code, X86_EDI);
2196 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2197 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2198 if (cfg->param_area)
2199 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2200 else
2201 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2202 x86_cld (code);
2203 x86_prefix (code, X86_REP_PREFIX);
2204 x86_stosl (code);
2205 x86_pop_reg (code, X86_EDI);
2206 x86_pop_reg (code, X86_ECX);
2207 x86_pop_reg (code, X86_EAX);
2208 }
2209
2210 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2211 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2212 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2213 x86_patch (br[3], br[2]);
2214 x86_test_reg_reg (code, sreg, sreg);
2215 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2216 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2217
2218 br[1] = code; x86_jump8 (code, 0);
2219
2220 x86_patch (br[0], code);
2221 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2222 x86_patch (br[1], code);
2223 x86_patch (br[4], code);
2224 }
2225 else
2226 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2227
2228 if (tree->flags & MONO_INST_INIT) {
2229 int offset = 0;
2230 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2231 x86_push_reg (code, X86_EAX);
2232 offset += 4;
2233 }
2234 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2235 x86_push_reg (code, X86_ECX);
2236 offset += 4;
2237 }
2238 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2239 x86_push_reg (code, X86_EDI);
2240 offset += 4;
2241 }
2242
2243 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2244 if (sreg != X86_ECX)
2245 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2246 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2247
2248 if (cfg->param_area)
2249 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2250 else
2251 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2252 x86_cld (code);
2253 x86_prefix (code, X86_REP_PREFIX);
2254 x86_stosl (code);
2255
2256 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2257 x86_pop_reg (code, X86_EDI);
2258 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2259 x86_pop_reg (code, X86_ECX);
2260 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2261 x86_pop_reg (code, X86_EAX);
2262 }
2263 return code;
2264 }
2265
2266
2267 static guint8*
2268 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2269 {
2270 /* Move return value to the target register */
2271 switch (ins->opcode) {
2272 case OP_CALL:
2273 case OP_CALL_REG:
2274 case OP_CALL_MEMBASE:
2275 if (ins->dreg != X86_EAX)
2276 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2277 break;
2278 default:
2279 break;
2280 }
2281
2282 return code;
2283 }
2284
2285 #ifdef __APPLE__
2286 static int tls_gs_offset;
2287 #endif
2288
2289 gboolean
2290 mono_x86_have_tls_get (void)
2291 {
2292 #ifdef TARGET_MACH
2293 static gboolean have_tls_get = FALSE;
2294 static gboolean inited = FALSE;
2295 guint32 *ins;
2296
2297 if (inited)
2298 return have_tls_get;
2299
2300 ins = (guint32*)pthread_getspecific;
2301 /*
2302 * We're looking for these two instructions:
2303 *
2304 * mov 0x4(%esp),%eax
2305 * mov %gs:[offset](,%eax,4),%eax
2306 */
2307 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2308 tls_gs_offset = ins [2];
2309
2310 inited = TRUE;
2311
2312 return have_tls_get;
2313 #elif defined(TARGET_ANDROID)
2314 return FALSE;
2315 #else
2316 return TRUE;
2317 #endif
2318 }
2319
2320 static guint8*
2321 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2322 {
2323 #if defined(__APPLE__)
2324 x86_prefix (code, X86_GS_PREFIX);
2325 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2326 #elif defined(TARGET_WIN32)
2327 g_assert_not_reached ();
2328 #else
2329 x86_prefix (code, X86_GS_PREFIX);
2330 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2331 #endif
2332 return code;
2333 }
2334
2335 /*
2336 * mono_x86_emit_tls_get:
2337 * @code: buffer to store code to
2338 * @dreg: hard register where to place the result
2339 * @tls_offset: offset info
2340 *
2341 * mono_x86_emit_tls_get emits in @code the native code that puts in
2342 * the dreg register the item in the thread local storage identified
2343 * by tls_offset.
2344 *
2345 * Returns: a pointer to the end of the stored code
2346 */
2347 guint8*
2348 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2349 {
2350 #if defined(__APPLE__)
2351 x86_prefix (code, X86_GS_PREFIX);
2352 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2353 #elif defined(TARGET_WIN32)
2354 /*
2355 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2356 * Journal and/or a disassembly of the TlsGet () function.
2357 */
2358 x86_prefix (code, X86_FS_PREFIX);
2359 x86_mov_reg_mem (code, dreg, 0x18, 4);
2360 if (tls_offset < 64) {
2361 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2362 } else {
2363 guint8 *buf [16];
2364
2365 g_assert (tls_offset < 0x440);
2366 /* Load TEB->TlsExpansionSlots */
2367 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2368 x86_test_reg_reg (code, dreg, dreg);
2369 buf [0] = code;
2370 x86_branch (code, X86_CC_EQ, code, TRUE);
2371 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2372 x86_patch (buf [0], code);
2373 }
2374 #else
2375 if (optimize_for_xen) {
2376 x86_prefix (code, X86_GS_PREFIX);
2377 x86_mov_reg_mem (code, dreg, 0, 4);
2378 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2379 } else {
2380 x86_prefix (code, X86_GS_PREFIX);
2381 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2382 }
2383 #endif
2384 return code;
2385 }
2386
2387 static guint8*
2388 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2389 {
2390 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2391 #if defined(__APPLE__) || defined(__linux__)
2392 if (dreg != offset_reg)
2393 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2394 x86_prefix (code, X86_GS_PREFIX);
2395 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2396 #else
2397 g_assert_not_reached ();
2398 #endif
2399 return code;
2400 }
2401
2402 guint8*
2403 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2404 {
2405 return emit_tls_get_reg (code, dreg, offset_reg);
2406 }
2407
2408 static guint8*
2409 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2410 {
2411 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2412 #ifdef HOST_WIN32
2413 g_assert_not_reached ();
2414 #elif defined(__APPLE__) || defined(__linux__)
2415 x86_prefix (code, X86_GS_PREFIX);
2416 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2417 #else
2418 g_assert_not_reached ();
2419 #endif
2420 return code;
2421 }
2422
2423 /*
2424 * mono_arch_translate_tls_offset:
2425 *
2426 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2427 */
2428 int
2429 mono_arch_translate_tls_offset (int offset)
2430 {
2431 #ifdef __APPLE__
2432 return tls_gs_offset + (offset * 4);
2433 #else
2434 return offset;
2435 #endif
2436 }
2437
2438 /*
2439 * emit_setup_lmf:
2440 *
2441 * Emit code to initialize an LMF structure at LMF_OFFSET.
2442 */
2443 static guint8*
2444 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2445 {
2446 /* save all caller saved regs */
2447 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2448 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2450 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2451 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2452 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2454
2455 /* save the current IP */
2456 if (cfg->compile_aot) {
2457 /* This pushes the current ip */
2458 x86_call_imm (code, 0);
2459 x86_pop_reg (code, X86_EAX);
2460 } else {
2461 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2462 x86_mov_reg_imm (code, X86_EAX, 0);
2463 }
2464 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2465
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2475
2476 return code;
2477 }
2478
2479 #define REAL_PRINT_REG(text,reg) \
2480 mono_assert (reg >= 0); \
2481 x86_push_reg (code, X86_EAX); \
2482 x86_push_reg (code, X86_EDX); \
2483 x86_push_reg (code, X86_ECX); \
2484 x86_push_reg (code, reg); \
2485 x86_push_imm (code, reg); \
2486 x86_push_imm (code, text " %d %p\n"); \
2487 x86_mov_reg_imm (code, X86_EAX, printf); \
2488 x86_call_reg (code, X86_EAX); \
2489 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2490 x86_pop_reg (code, X86_ECX); \
2491 x86_pop_reg (code, X86_EDX); \
2492 x86_pop_reg (code, X86_EAX);
2493
2494 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2495 #ifdef __native__client_codegen__
2496 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2497 #endif
2498
2499 /* benchmark and set based on cpu */
2500 #define LOOP_ALIGNMENT 8
2501 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2502
2503 #ifndef DISABLE_JIT
2504 void
2505 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2506 {
2507 MonoInst *ins;
2508 MonoCallInst *call;
2509 guint offset;
2510 guint8 *code = cfg->native_code + cfg->code_len;
2511 int max_len, cpos;
2512
2513 if (cfg->opt & MONO_OPT_LOOP) {
2514 int pad, align = LOOP_ALIGNMENT;
2515 /* set alignment depending on cpu */
2516 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2517 pad = align - pad;
2518 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2519 x86_padding (code, pad);
2520 cfg->code_len += pad;
2521 bb->native_offset = cfg->code_len;
2522 }
2523 }
2524 #ifdef __native_client_codegen__
2525 {
2526 /* For Native Client, all indirect call/jump targets must be */
2527 /* 32-byte aligned. Exception handler blocks are jumped to */
2528 /* indirectly as well. */
2529 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2530 (bb->flags & BB_EXCEPTION_HANDLER);
2531
2532 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2533 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2534 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2535 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2536 cfg->code_len += pad;
2537 bb->native_offset = cfg->code_len;
2538 }
2539 }
2540 #endif /* __native_client_codegen__ */
2541 if (cfg->verbose_level > 2)
2542 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2543
2544 cpos = bb->max_offset;
2545
2546 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2547 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2548 g_assert (!cfg->compile_aot);
2549 cpos += 6;
2550
2551 cov->data [bb->dfn].cil_code = bb->cil_code;
2552 /* this is not thread save, but good enough */
2553 x86_inc_mem (code, &cov->data [bb->dfn].count);
2554 }
2555
2556 offset = code - cfg->native_code;
2557
2558 mono_debug_open_block (cfg, bb, offset);
2559
2560 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2561 x86_breakpoint (code);
2562
2563 MONO_BB_FOR_EACH_INS (bb, ins) {
2564 offset = code - cfg->native_code;
2565
2566 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2567
2568 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2569
2570 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2571 cfg->code_size *= 2;
2572 cfg->native_code = mono_realloc_native_code(cfg);
2573 code = cfg->native_code + offset;
2574 cfg->stat_code_reallocs++;
2575 }
2576
2577 if (cfg->debug_info)
2578 mono_debug_record_line_number (cfg, ins, offset);
2579
2580 switch (ins->opcode) {
2581 case OP_BIGMUL:
2582 x86_mul_reg (code, ins->sreg2, TRUE);
2583 break;
2584 case OP_BIGMUL_UN:
2585 x86_mul_reg (code, ins->sreg2, FALSE);
2586 break;
2587 case OP_X86_SETEQ_MEMBASE:
2588 case OP_X86_SETNE_MEMBASE:
2589 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2590 ins->inst_basereg, ins->inst_offset, TRUE);
2591 break;
2592 case OP_STOREI1_MEMBASE_IMM:
2593 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2594 break;
2595 case OP_STOREI2_MEMBASE_IMM:
2596 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2597 break;
2598 case OP_STORE_MEMBASE_IMM:
2599 case OP_STOREI4_MEMBASE_IMM:
2600 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2601 break;
2602 case OP_STOREI1_MEMBASE_REG:
2603 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2604 break;
2605 case OP_STOREI2_MEMBASE_REG:
2606 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2607 break;
2608 case OP_STORE_MEMBASE_REG:
2609 case OP_STOREI4_MEMBASE_REG:
2610 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2611 break;
2612 case OP_STORE_MEM_IMM:
2613 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2614 break;
2615 case OP_LOADU4_MEM:
2616 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2617 break;
2618 case OP_LOAD_MEM:
2619 case OP_LOADI4_MEM:
2620 /* These are created by the cprop pass so they use inst_imm as the source */
2621 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2622 break;
2623 case OP_LOADU1_MEM:
2624 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2625 break;
2626 case OP_LOADU2_MEM:
2627 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2628 break;
2629 case OP_LOAD_MEMBASE:
2630 case OP_LOADI4_MEMBASE:
2631 case OP_LOADU4_MEMBASE:
2632 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2633 break;
2634 case OP_LOADU1_MEMBASE:
2635 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2636 break;
2637 case OP_LOADI1_MEMBASE:
2638 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2639 break;
2640 case OP_LOADU2_MEMBASE:
2641 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2642 break;
2643 case OP_LOADI2_MEMBASE:
2644 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2645 break;
2646 case OP_ICONV_TO_I1:
2647 case OP_SEXT_I1:
2648 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2649 break;
2650 case OP_ICONV_TO_I2:
2651 case OP_SEXT_I2:
2652 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2653 break;
2654 case OP_ICONV_TO_U1:
2655 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2656 break;
2657 case OP_ICONV_TO_U2:
2658 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2659 break;
2660 case OP_COMPARE:
2661 case OP_ICOMPARE:
2662 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2663 break;
2664 case OP_COMPARE_IMM:
2665 case OP_ICOMPARE_IMM:
2666 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2667 break;
2668 case OP_X86_COMPARE_MEMBASE_REG:
2669 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2670 break;
2671 case OP_X86_COMPARE_MEMBASE_IMM:
2672 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2673 break;
2674 case OP_X86_COMPARE_MEMBASE8_IMM:
2675 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2676 break;
2677 case OP_X86_COMPARE_REG_MEMBASE:
2678 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 break;
2680 case OP_X86_COMPARE_MEM_IMM:
2681 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2682 break;
2683 case OP_X86_TEST_NULL:
2684 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2685 break;
2686 case OP_X86_ADD_MEMBASE_IMM:
2687 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2688 break;
2689 case OP_X86_ADD_REG_MEMBASE:
2690 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2691 break;
2692 case OP_X86_SUB_MEMBASE_IMM:
2693 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2694 break;
2695 case OP_X86_SUB_REG_MEMBASE:
2696 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2697 break;
2698 case OP_X86_AND_MEMBASE_IMM:
2699 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2700 break;
2701 case OP_X86_OR_MEMBASE_IMM:
2702 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2703 break;
2704 case OP_X86_XOR_MEMBASE_IMM:
2705 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2706 break;
2707 case OP_X86_ADD_MEMBASE_REG:
2708 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2709 break;
2710 case OP_X86_SUB_MEMBASE_REG:
2711 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2712 break;
2713 case OP_X86_AND_MEMBASE_REG:
2714 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2715 break;
2716 case OP_X86_OR_MEMBASE_REG:
2717 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2718 break;
2719 case OP_X86_XOR_MEMBASE_REG:
2720 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2721 break;
2722 case OP_X86_INC_MEMBASE:
2723 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2724 break;
2725 case OP_X86_INC_REG:
2726 x86_inc_reg (code, ins->dreg);
2727 break;
2728 case OP_X86_DEC_MEMBASE:
2729 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2730 break;
2731 case OP_X86_DEC_REG:
2732 x86_dec_reg (code, ins->dreg);
2733 break;
2734 case OP_X86_MUL_REG_MEMBASE:
2735 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2736 break;
2737 case OP_X86_AND_REG_MEMBASE:
2738 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2739 break;
2740 case OP_X86_OR_REG_MEMBASE:
2741 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2742 break;
2743 case OP_X86_XOR_REG_MEMBASE:
2744 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2745 break;
2746 case OP_BREAK:
2747 x86_breakpoint (code);
2748 break;
2749 case OP_RELAXED_NOP:
2750 x86_prefix (code, X86_REP_PREFIX);
2751 x86_nop (code);
2752 break;
2753 case OP_HARD_NOP:
2754 x86_nop (code);
2755 break;
2756 case OP_NOP:
2757 case OP_DUMMY_USE:
2758 case OP_DUMMY_STORE:
2759 case OP_DUMMY_ICONST:
2760 case OP_DUMMY_R8CONST:
2761 case OP_NOT_REACHED:
2762 case OP_NOT_NULL:
2763 break;
2764 case OP_IL_SEQ_POINT:
2765 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2766 break;
2767 case OP_SEQ_POINT: {
2768 int i;
2769
2770 if (cfg->compile_aot)
2771 NOT_IMPLEMENTED;
2772
2773 /*
2774 * Read from the single stepping trigger page. This will cause a
2775 * SIGSEGV when single stepping is enabled.
2776 * We do this _before_ the breakpoint, so single stepping after
2777 * a breakpoint is hit will step to the next IL offset.
2778 */
2779 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2780 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2781
2782 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2783
2784 /*
2785 * A placeholder for a possible breakpoint inserted by
2786 * mono_arch_set_breakpoint ().
2787 */
2788 for (i = 0; i < 6; ++i)
2789 x86_nop (code);
2790 /*
2791 * Add an additional nop so skipping the bp doesn't cause the ip to point
2792 * to another IL offset.
2793 */
2794 x86_nop (code);
2795 break;
2796 }
2797 case OP_ADDCC:
2798 case OP_IADDCC:
2799 case OP_IADD:
2800 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2801 break;
2802 case OP_ADC:
2803 case OP_IADC:
2804 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2805 break;
2806 case OP_ADDCC_IMM:
2807 case OP_ADD_IMM:
2808 case OP_IADD_IMM:
2809 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2810 break;
2811 case OP_ADC_IMM:
2812 case OP_IADC_IMM:
2813 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2814 break;
2815 case OP_SUBCC:
2816 case OP_ISUBCC:
2817 case OP_ISUB:
2818 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2819 break;
2820 case OP_SBB:
2821 case OP_ISBB:
2822 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2823 break;
2824 case OP_SUBCC_IMM:
2825 case OP_SUB_IMM:
2826 case OP_ISUB_IMM:
2827 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2828 break;
2829 case OP_SBB_IMM:
2830 case OP_ISBB_IMM:
2831 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2832 break;
2833 case OP_IAND:
2834 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2835 break;
2836 case OP_AND_IMM:
2837 case OP_IAND_IMM:
2838 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2839 break;
2840 case OP_IDIV:
2841 case OP_IREM:
2842 #if defined( __native_client_codegen__ )
2843 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2844 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2845 #endif
2846 /*
2847 * The code is the same for div/rem, the allocator will allocate dreg
2848 * to RAX/RDX as appropriate.
2849 */
2850 if (ins->sreg2 == X86_EDX) {
2851 /* cdq clobbers this */
2852 x86_push_reg (code, ins->sreg2);
2853 x86_cdq (code);
2854 x86_div_membase (code, X86_ESP, 0, TRUE);
2855 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2856 } else {
2857 x86_cdq (code);
2858 x86_div_reg (code, ins->sreg2, TRUE);
2859 }
2860 break;
2861 case OP_IDIV_UN:
2862 case OP_IREM_UN:
2863 #if defined( __native_client_codegen__ )
2864 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2865 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2866 #endif
2867 if (ins->sreg2 == X86_EDX) {
2868 x86_push_reg (code, ins->sreg2);
2869 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2870 x86_div_membase (code, X86_ESP, 0, FALSE);
2871 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2872 } else {
2873 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2874 x86_div_reg (code, ins->sreg2, FALSE);
2875 }
2876 break;
2877 case OP_DIV_IMM:
2878 #if defined( __native_client_codegen__ )
2879 if (ins->inst_imm == 0) {
2880 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2881 x86_jump32 (code, 0);
2882 break;
2883 }
2884 #endif
2885 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2886 x86_cdq (code);
2887 x86_div_reg (code, ins->sreg2, TRUE);
2888 break;
2889 case OP_IREM_IMM: {
2890 int power = mono_is_power_of_two (ins->inst_imm);
2891
2892 g_assert (ins->sreg1 == X86_EAX);
2893 g_assert (ins->dreg == X86_EAX);
2894 g_assert (power >= 0);
2895
2896 if (power == 1) {
2897 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2898 x86_cdq (code);
2899 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2900 /*
2901 * If the divident is >= 0, this does not nothing. If it is positive, it
2902 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2903 */
2904 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2905 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2906 } else if (power == 0) {
2907 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2908 } else {
2909 /* Based on gcc code */
2910
2911 /* Add compensation for negative dividents */
2912 x86_cdq (code);
2913 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2914 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2915 /* Compute remainder */
2916 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2917 /* Remove compensation */
2918 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2919 }
2920 break;
2921 }
2922 case OP_IOR:
2923 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2924 break;
2925 case OP_OR_IMM:
2926 case OP_IOR_IMM:
2927 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2928 break;
2929 case OP_IXOR:
2930 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2931 break;
2932 case OP_XOR_IMM:
2933 case OP_IXOR_IMM:
2934 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2935 break;
2936 case OP_ISHL:
2937 g_assert (ins->sreg2 == X86_ECX);
2938 x86_shift_reg (code, X86_SHL, ins->dreg);
2939 break;
2940 case OP_ISHR:
2941 g_assert (ins->sreg2 == X86_ECX);
2942 x86_shift_reg (code, X86_SAR, ins->dreg);
2943 break;
2944 case OP_SHR_IMM:
2945 case OP_ISHR_IMM:
2946 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2947 break;
2948 case OP_SHR_UN_IMM:
2949 case OP_ISHR_UN_IMM:
2950 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2951 break;
2952 case OP_ISHR_UN:
2953 g_assert (ins->sreg2 == X86_ECX);
2954 x86_shift_reg (code, X86_SHR, ins->dreg);
2955 break;
2956 case OP_SHL_IMM:
2957 case OP_ISHL_IMM:
2958 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2959 break;
2960 case OP_LSHL: {
2961 guint8 *jump_to_end;
2962
2963 /* handle shifts below 32 bits */
2964 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2965 x86_shift_reg (code, X86_SHL, ins->sreg1);
2966
2967 x86_test_reg_imm (code, X86_ECX, 32);
2968 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2969
2970 /* handle shift over 32 bit */
2971 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2972 x86_clear_reg (code, ins->sreg1);
2973
2974 x86_patch (jump_to_end, code);
2975 }
2976 break;
2977 case OP_LSHR: {
2978 guint8 *jump_to_end;
2979
2980 /* handle shifts below 32 bits */
2981 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2982 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2983
2984 x86_test_reg_imm (code, X86_ECX, 32);
2985 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2986
2987 /* handle shifts over 31 bits */
2988 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2989 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2990
2991 x86_patch (jump_to_end, code);
2992 }
2993 break;
2994 case OP_LSHR_UN: {
2995 guint8 *jump_to_end;
2996
2997 /* handle shifts below 32 bits */
2998 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2999 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3000
3001 x86_test_reg_imm (code, X86_ECX, 32);
3002 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3003
3004 /* handle shifts over 31 bits */
3005 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3006 x86_clear_reg (code, ins->backend.reg3);
3007
3008 x86_patch (jump_to_end, code);
3009 }
3010 break;
3011 case OP_LSHL_IMM:
3012 if (ins->inst_imm >= 32) {
3013 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3014 x86_clear_reg (code, ins->sreg1);
3015 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3016 } else {
3017 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3018 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3019 }
3020 break;
3021 case OP_LSHR_IMM:
3022 if (ins->inst_imm >= 32) {
3023 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3024 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3025 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3026 } else {
3027 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3028 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3029 }
3030 break;
3031 case OP_LSHR_UN_IMM:
3032 if (ins->inst_imm >= 32) {
3033 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3034 x86_clear_reg (code, ins->backend.reg3);
3035 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3036 } else {
3037 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3038 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3039 }
3040 break;
3041 case OP_INOT:
3042 x86_not_reg (code, ins->sreg1);
3043 break;
3044 case OP_INEG:
3045 x86_neg_reg (code, ins->sreg1);
3046 break;
3047
3048 case OP_IMUL:
3049 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3050 break;
3051 case OP_MUL_IMM:
3052 case OP_IMUL_IMM:
3053 switch (ins->inst_imm) {
3054 case 2:
3055 /* MOV r1, r2 */
3056 /* ADD r1, r1 */
3057 if (ins->dreg != ins->sreg1)
3058 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3059 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3060 break;
3061 case 3:
3062 /* LEA r1, [r2 + r2*2] */
3063 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3064 break;
3065 case 5:
3066 /* LEA r1, [r2 + r2*4] */
3067 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3068 break;
3069 case 6:
3070 /* LEA r1, [r2 + r2*2] */
3071 /* ADD r1, r1 */
3072 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3073 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3074 break;
3075 case 9:
3076 /* LEA r1, [r2 + r2*8] */
3077 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3078 break;
3079 case 10:
3080 /* LEA r1, [r2 + r2*4] */
3081 /* ADD r1, r1 */
3082 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3083 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3084 break;
3085 case 12:
3086 /* LEA r1, [r2 + r2*2] */
3087 /* SHL r1, 2 */
3088 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3089 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3090 break;
3091 case 25:
3092 /* LEA r1, [r2 + r2*4] */
3093 /* LEA r1, [r1 + r1*4] */
3094 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3095 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3096 break;
3097 case 100:
3098 /* LEA r1, [r2 + r2*4] */
3099 /* SHL r1, 2 */
3100 /* LEA r1, [r1 + r1*4] */
3101 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3102 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3103 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3104 break;
3105 default:
3106 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3107 break;
3108 }
3109 break;
3110 case OP_IMUL_OVF:
3111 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3112 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3113 break;
3114 case OP_IMUL_OVF_UN: {
3115 /* the mul operation and the exception check should most likely be split */
3116 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3117 /*g_assert (ins->sreg2 == X86_EAX);
3118 g_assert (ins->dreg == X86_EAX);*/
3119 if (ins->sreg2 == X86_EAX) {
3120 non_eax_reg = ins->sreg1;
3121 } else if (ins->sreg1 == X86_EAX) {
3122 non_eax_reg = ins->sreg2;
3123 } else {
3124 /* no need to save since we're going to store to it anyway */
3125 if (ins->dreg != X86_EAX) {
3126 saved_eax = TRUE;
3127 x86_push_reg (code, X86_EAX);
3128 }
3129 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3130 non_eax_reg = ins->sreg2;
3131 }
3132 if (ins->dreg == X86_EDX) {
3133 if (!saved_eax) {
3134 saved_eax = TRUE;
3135 x86_push_reg (code, X86_EAX);
3136 }
3137 } else if (ins->dreg != X86_EAX) {
3138 saved_edx = TRUE;
3139 x86_push_reg (code, X86_EDX);
3140 }
3141 x86_mul_reg (code, non_eax_reg, FALSE);
3142 /* save before the check since pop and mov don't change the flags */
3143 if (ins->dreg != X86_EAX)
3144 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3145 if (saved_edx)
3146 x86_pop_reg (code, X86_EDX);
3147 if (saved_eax)
3148 x86_pop_reg (code, X86_EAX);
3149 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3150 break;
3151 }
3152 case OP_ICONST:
3153 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3154 break;
3155 case OP_AOTCONST:
3156 g_assert_not_reached ();
3157 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3158 x86_mov_reg_imm (code, ins->dreg, 0);
3159 break;
3160 case OP_JUMP_TABLE:
3161 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3162 x86_mov_reg_imm (code, ins->dreg, 0);
3163 break;
3164 case OP_LOAD_GOTADDR:
3165 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3166 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3167 break;
3168 case OP_GOT_ENTRY:
3169 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3170 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3171 break;
3172 case OP_X86_PUSH_GOT_ENTRY:
3173 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3174 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3175 break;
3176 case OP_MOVE:
3177 if (ins->dreg != ins->sreg1)
3178 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3179 break;
3180 case OP_TAILCALL: {
3181 MonoCallInst *call = (MonoCallInst*)ins;
3182 int pos = 0, i;
3183
3184 ins->flags |= MONO_INST_GC_CALLSITE;
3185 ins->backend.pc_offset = code - cfg->native_code;
3186
3187 /* reset offset to make max_len work */
3188 offset = code - cfg->native_code;
3189
3190 g_assert (!cfg->method->save_lmf);
3191
3192 /* restore callee saved registers */
3193 for (i = 0; i < X86_NREG; ++i)
3194 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3195 pos -= 4;
3196 if (cfg->used_int_regs & (1 << X86_ESI)) {
3197 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3198 pos += 4;
3199 }
3200 if (cfg->used_int_regs & (1 << X86_EDI)) {
3201 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3202 pos += 4;
3203 }
3204 if (cfg->used_int_regs & (1 << X86_EBX)) {
3205 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3206 pos += 4;
3207 }
3208
3209 /* Copy arguments on the stack to our argument area */
3210 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3211 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3212 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3213 }
3214
3215 /* restore ESP/EBP */
3216 x86_leave (code);
3217 offset = code - cfg->native_code;
3218 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3219 x86_jump32 (code, 0);
3220
3221 ins->flags |= MONO_INST_GC_CALLSITE;
3222 cfg->disable_aot = TRUE;
3223 break;
3224 }
3225 case OP_CHECK_THIS:
3226 /* ensure ins->sreg1 is not NULL
3227 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3228 * cmp DWORD PTR [eax], 0
3229 */
3230 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3231 break;
3232 case OP_ARGLIST: {
3233 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3234 x86_push_reg (code, hreg);
3235 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3236 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3237 x86_pop_reg (code, hreg);
3238 break;
3239 }
3240 case OP_FCALL:
3241 case OP_LCALL:
3242 case OP_VCALL:
3243 case OP_VCALL2:
3244 case OP_VOIDCALL:
3245 case OP_CALL:
3246 case OP_FCALL_REG:
3247 case OP_LCALL_REG:
3248 case OP_VCALL_REG:
3249 case OP_VCALL2_REG:
3250 case OP_VOIDCALL_REG:
3251 case OP_CALL_REG:
3252 case OP_FCALL_MEMBASE:
3253 case OP_LCALL_MEMBASE:
3254 case OP_VCALL_MEMBASE:
3255 case OP_VCALL2_MEMBASE:
3256 case OP_VOIDCALL_MEMBASE:
3257 case OP_CALL_MEMBASE: {
3258 CallInfo *cinfo;
3259
3260 call = (MonoCallInst*)ins;
3261 cinfo = (CallInfo*)call->call_info;
3262
3263 switch (ins->opcode) {
3264 case OP_FCALL:
3265 case OP_LCALL:
3266 case OP_VCALL:
3267 case OP_VCALL2:
3268 case OP_VOIDCALL:
3269 case OP_CALL:
3270 if (ins->flags & MONO_INST_HAS_METHOD)
3271 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3272 else
3273 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3274 break;
3275 case OP_FCALL_REG:
3276 case OP_LCALL_REG:
3277 case OP_VCALL_REG:
3278 case OP_VCALL2_REG:
3279 case OP_VOIDCALL_REG:
3280 case OP_CALL_REG:
3281 x86_call_reg (code, ins->sreg1);
3282 break;
3283 case OP_FCALL_MEMBASE:
3284 case OP_LCALL_MEMBASE:
3285 case OP_VCALL_MEMBASE:
3286 case OP_VCALL2_MEMBASE:
3287 case OP_VOIDCALL_MEMBASE:
3288 case OP_CALL_MEMBASE:
3289 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3290 break;
3291 default:
3292 g_assert_not_reached ();
3293 break;
3294 }
3295 ins->flags |= MONO_INST_GC_CALLSITE;
3296 ins->backend.pc_offset = code - cfg->native_code;
3297 if (cinfo->callee_stack_pop) {
3298 /* Have to compensate for the stack space popped by the callee */
3299 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3300 }
3301 code = emit_move_return_value (cfg, ins, code);
3302 break;
3303 }
3304 case OP_X86_LEA:
3305 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3306 break;
3307 case OP_X86_LEA_MEMBASE:
3308 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3309 break;
3310 case OP_X86_XCHG:
3311 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3312 break;
3313 case OP_LOCALLOC:
3314 /* keep alignment */
3315 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3316 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3317 code = mono_emit_stack_alloc (cfg, code, ins);
3318 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3319 if (cfg->param_area)
3320 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3321 break;
3322 case OP_LOCALLOC_IMM: {
3323 guint32 size = ins->inst_imm;
3324 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3325
3326 if (ins->flags & MONO_INST_INIT) {
3327 /* FIXME: Optimize this */
3328 x86_mov_reg_imm (code, ins->dreg, size);
3329 ins->sreg1 = ins->dreg;
3330
3331 code = mono_emit_stack_alloc (cfg, code, ins);
3332 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3333 } else {
3334 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3335 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3336 }
3337 if (cfg->param_area)
3338 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3339 break;
3340 }
3341 case OP_THROW: {
3342 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3343 x86_push_reg (code, ins->sreg1);
3344 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3345 (gpointer)"mono_arch_throw_exception");
3346 ins->flags |= MONO_INST_GC_CALLSITE;
3347 ins->backend.pc_offset = code - cfg->native_code;
3348 break;
3349 }
3350 case OP_RETHROW: {
3351 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3352 x86_push_reg (code, ins->sreg1);
3353 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3354 (gpointer)"mono_arch_rethrow_exception");
3355 ins->flags |= MONO_INST_GC_CALLSITE;
3356 ins->backend.pc_offset = code - cfg->native_code;
3357 break;
3358 }
3359 case OP_CALL_HANDLER:
3360 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3361 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3362 x86_call_imm (code, 0);
3363 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3364 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3365 break;
3366 case OP_START_HANDLER: {
3367 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3368 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3369 if (cfg->param_area)
3370 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3371 break;
3372 }
3373 case OP_ENDFINALLY: {
3374 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3375 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3376 x86_ret (code);
3377 break;
3378 }
3379 case OP_ENDFILTER: {
3380 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3381 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3382 /* The local allocator will put the result into EAX */
3383 x86_ret (code);
3384 break;
3385 }
3386 case OP_GET_EX_OBJ:
3387 if (ins->dreg != X86_EAX)
3388 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3389 break;
3390
3391 case OP_LABEL:
3392 ins->inst_c0 = code - cfg->native_code;
3393 break;
3394 case OP_BR:
3395 if (ins->inst_target_bb->native_offset) {
3396 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3397 } else {
3398 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3399 if ((cfg->opt & MONO_OPT_BRANCH) &&
3400 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3401 x86_jump8 (code, 0);
3402 else
3403 x86_jump32 (code, 0);
3404 }
3405 break;
3406 case OP_BR_REG:
3407 x86_jump_reg (code, ins->sreg1);
3408 break;
3409 case OP_ICNEQ:
3410 case OP_ICGE:
3411 case OP_ICLE:
3412 case OP_ICGE_UN:
3413 case OP_ICLE_UN:
3414
3415 case OP_CEQ:
3416 case OP_CLT:
3417 case OP_CLT_UN:
3418 case OP_CGT:
3419 case OP_CGT_UN:
3420 case OP_CNE:
3421 case OP_ICEQ:
3422 case OP_ICLT:
3423 case OP_ICLT_UN:
3424 case OP_ICGT:
3425 case OP_ICGT_UN:
3426 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3427 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3428 break;
3429 case OP_COND_EXC_EQ:
3430 case OP_COND_EXC_NE_UN:
3431 case OP_COND_EXC_LT:
3432 case OP_COND_EXC_LT_UN:
3433 case OP_COND_EXC_GT:
3434 case OP_COND_EXC_GT_UN:
3435 case OP_COND_EXC_GE:
3436 case OP_COND_EXC_GE_UN:
3437 case OP_COND_EXC_LE:
3438 case OP_COND_EXC_LE_UN:
3439 case OP_COND_EXC_IEQ:
3440 case OP_COND_EXC_INE_UN:
3441 case OP_COND_EXC_ILT:
3442 case OP_COND_EXC_ILT_UN:
3443 case OP_COND_EXC_IGT:
3444 case OP_COND_EXC_IGT_UN:
3445 case OP_COND_EXC_IGE:
3446 case OP_COND_EXC_IGE_UN:
3447 case OP_COND_EXC_ILE:
3448 case OP_COND_EXC_ILE_UN:
3449 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3450 break;
3451 case OP_COND_EXC_OV:
3452 case OP_COND_EXC_NO:
3453 case OP_COND_EXC_C:
3454 case OP_COND_EXC_NC:
3455 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3456 break;
3457 case OP_COND_EXC_IOV:
3458 case OP_COND_EXC_INO:
3459 case OP_COND_EXC_IC:
3460 case OP_COND_EXC_INC:
3461 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3462 break;
3463 case OP_IBEQ:
3464 case OP_IBNE_UN:
3465 case OP_IBLT:
3466 case OP_IBLT_UN:
3467 case OP_IBGT:
3468 case OP_IBGT_UN:
3469 case OP_IBGE:
3470 case OP_IBGE_UN:
3471 case OP_IBLE:
3472 case OP_IBLE_UN:
3473 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3474 break;
3475
3476 case OP_CMOV_IEQ:
3477 case OP_CMOV_IGE:
3478 case OP_CMOV_IGT:
3479 case OP_CMOV_ILE:
3480 case OP_CMOV_ILT:
3481 case OP_CMOV_INE_UN:
3482 case OP_CMOV_IGE_UN:
3483 case OP_CMOV_IGT_UN:
3484 case OP_CMOV_ILE_UN:
3485 case OP_CMOV_ILT_UN:
3486 g_assert (ins->dreg == ins->sreg1);
3487 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3488 break;
3489
3490 /* floating point opcodes */
3491 case OP_R8CONST: {
3492 double d = *(double *)ins->inst_p0;
3493
3494 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3495 x86_fldz (code);
3496 } else if (d == 1.0) {
3497 x86_fld1 (code);
3498 } else {
3499 if (cfg->compile_aot) {
3500 guint32 *val = (guint32*)&d;
3501 x86_push_imm (code, val [1]);
3502 x86_push_imm (code, val [0]);
3503 x86_fld_membase (code, X86_ESP, 0, TRUE);
3504 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3505 }
3506 else {
3507 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3508 x86_fld (code, NULL, TRUE);
3509 }
3510 }
3511 break;
3512 }
3513 case OP_R4CONST: {
3514 float f = *(float *)ins->inst_p0;
3515
3516 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3517 x86_fldz (code);
3518 } else if (f == 1.0) {
3519 x86_fld1 (code);
3520 } else {
3521 if (cfg->compile_aot) {
3522 guint32 val = *(guint32*)&f;
3523 x86_push_imm (code, val);
3524 x86_fld_membase (code, X86_ESP, 0, FALSE);
3525 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3526 }
3527 else {
3528 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3529 x86_fld (code, NULL, FALSE);
3530 }
3531 }
3532 break;
3533 }
3534 case OP_STORER8_MEMBASE_REG:
3535 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3536 break;
3537 case OP_LOADR8_MEMBASE:
3538 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3539 break;
3540 case OP_STORER4_MEMBASE_REG:
3541 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3542 break;
3543 case OP_LOADR4_MEMBASE:
3544 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3545 break;
3546 case OP_ICONV_TO_R4:
3547 x86_push_reg (code, ins->sreg1);
3548 x86_fild_membase (code, X86_ESP, 0, FALSE);
3549 /* Change precision */
3550 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3551 x86_fld_membase (code, X86_ESP, 0, FALSE);
3552 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3553 break;
3554 case OP_ICONV_TO_R8:
3555 x86_push_reg (code, ins->sreg1);
3556 x86_fild_membase (code, X86_ESP, 0, FALSE);
3557 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3558 break;
3559 case OP_ICONV_TO_R_UN:
3560 x86_push_imm (code, 0);
3561 x86_push_reg (code, ins->sreg1);
3562 x86_fild_membase (code, X86_ESP, 0, TRUE);
3563 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3564 break;
3565 case OP_X86_FP_LOAD_I8:
3566 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3567 break;
3568 case OP_X86_FP_LOAD_I4:
3569 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3570 break;
3571 case OP_FCONV_TO_R4:
3572 /* Change precision */
3573 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3574 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3575 x86_fld_membase (code, X86_ESP, 0, FALSE);
3576 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3577 break;
3578 case OP_FCONV_TO_I1:
3579 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3580 break;
3581 case OP_FCONV_TO_U1:
3582 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3583 break;
3584 case OP_FCONV_TO_I2:
3585 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3586 break;
3587 case OP_FCONV_TO_U2:
3588 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3589 break;
3590 case OP_FCONV_TO_I4:
3591 case OP_FCONV_TO_I:
3592 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3593 break;
3594 case OP_FCONV_TO_I8:
3595 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3596 x86_fnstcw_membase(code, X86_ESP, 0);
3597 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3598 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3599 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3600 x86_fldcw_membase (code, X86_ESP, 2);
3601 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3602 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3603 x86_pop_reg (code, ins->dreg);
3604 x86_pop_reg (code, ins->backend.reg3);
3605 x86_fldcw_membase (code, X86_ESP, 0);
3606 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3607 break;
3608 case OP_LCONV_TO_R8_2:
3609 x86_push_reg (code, ins->sreg2);
3610 x86_push_reg (code, ins->sreg1);
3611 x86_fild_membase (code, X86_ESP, 0, TRUE);
3612 /* Change precision */
3613 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3614 x86_fld_membase (code, X86_ESP, 0, TRUE);
3615 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3616 break;
3617 case OP_LCONV_TO_R4_2:
3618 x86_push_reg (code, ins->sreg2);
3619 x86_push_reg (code, ins->sreg1);
3620 x86_fild_membase (code, X86_ESP, 0, TRUE);
3621 /* Change precision */
3622 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3623 x86_fld_membase (code, X86_ESP, 0, FALSE);
3624 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3625 break;
3626 case OP_LCONV_TO_R_UN_2: {
3627 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3628 guint8 *br;
3629
3630 /* load 64bit integer to FP stack */
3631 x86_push_reg (code, ins->sreg2);
3632 x86_push_reg (code, ins->sreg1);
3633 x86_fild_membase (code, X86_ESP, 0, TRUE);
3634
3635 /* test if lreg is negative */
3636 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3637 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3638
3639 /* add correction constant mn */
3640 if (cfg->compile_aot) {
3641 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3642 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3643 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3644 x86_fld80_membase (code, X86_ESP, 2);
3645 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3646 } else {
3647 x86_fld80_mem (code, mn);
3648 }
3649 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3650
3651 x86_patch (br, code);
3652
3653 /* Change precision */
3654 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3655 x86_fld_membase (code, X86_ESP, 0, TRUE);
3656
3657 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3658
3659 break;
3660 }
3661 case OP_LCONV_TO_OVF_I:
3662 case OP_LCONV_TO_OVF_I4_2: {
3663 guint8 *br [3], *label [1];
3664 MonoInst *tins;
3665
3666 /*
3667 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3668 */
3669 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3670
3671 /* If the low word top bit is set, see if we are negative */
3672 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3673 /* We are not negative (no top bit set, check for our top word to be zero */
3674 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3675 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3676 label [0] = code;
3677
3678 /* throw exception */
3679 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3680 if (tins) {
3681 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3682 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3683 x86_jump8 (code, 0);
3684 else
3685 x86_jump32 (code, 0);
3686 } else {
3687 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3688 x86_jump32 (code, 0);
3689 }
3690
3691
3692 x86_patch (br [0], code);
3693 /* our top bit is set, check that top word is 0xfffffff */
3694 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3695
3696 x86_patch (br [1], code);
3697 /* nope, emit exception */
3698 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3699 x86_patch (br [2], label [0]);
3700
3701 if (ins->dreg != ins->sreg1)
3702 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3703 break;
3704 }
3705 case OP_FMOVE:
3706 /* Not needed on the fp stack */
3707 break;
3708 case OP_MOVE_F_TO_I4:
3709 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3710 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3711 break;
3712 case OP_MOVE_I4_TO_F:
3713 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3714 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3715 break;
3716 case OP_FADD:
3717 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3718 break;
3719 case OP_FSUB:
3720 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3721 break;
3722 case OP_FMUL:
3723 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3724 break;
3725 case OP_FDIV:
3726 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3727 break;
3728 case OP_FNEG:
3729 x86_fchs (code);
3730 break;
3731 case OP_SIN:
3732 x86_fsin (code);
3733 x86_fldz (code);
3734 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3735 break;
3736 case OP_COS:
3737 x86_fcos (code);
3738 x86_fldz (code);
3739 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3740 break;
3741 case OP_ABS:
3742 x86_fabs (code);
3743 break;
3744 case OP_TAN: {
3745 /*
3746 * it really doesn't make sense to inline all this code,
3747 * it's here just to show that things may not be as simple
3748 * as they appear.
3749 */
3750 guchar *check_pos, *end_tan, *pop_jump;
3751 x86_push_reg (code, X86_EAX);
3752 x86_fptan (code);
3753 x86_fnstsw (code);
3754 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3755 check_pos = code;
3756 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3757 x86_fstp (code, 0); /* pop the 1.0 */
3758 end_tan = code;
3759 x86_jump8 (code, 0);
3760 x86_fldpi (code);
3761 x86_fp_op (code, X86_FADD, 0);
3762 x86_fxch (code, 1);
3763 x86_fprem1 (code);
3764 x86_fstsw (code);
3765 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3766 pop_jump = code;
3767 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3768 x86_fstp (code, 1);
3769 x86_fptan (code);
3770 x86_patch (pop_jump, code);
3771 x86_fstp (code, 0); /* pop the 1.0 */
3772 x86_patch (check_pos, code);
3773 x86_patch (end_tan, code);
3774 x86_fldz (code);
3775 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3776 x86_pop_reg (code, X86_EAX);
3777 break;
3778 }
3779 case OP_ATAN:
3780 x86_fld1 (code);
3781 x86_fpatan (code);
3782 x86_fldz (code);
3783 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3784 break;
3785 case OP_SQRT:
3786 x86_fsqrt (code);
3787 break;
3788 case OP_ROUND:
3789 x86_frndint (code);
3790 break;
3791 case OP_IMIN:
3792 g_assert (cfg->opt & MONO_OPT_CMOV);
3793 g_assert (ins->dreg == ins->sreg1);
3794 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3795 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3796 break;
3797 case OP_IMIN_UN:
3798 g_assert (cfg->opt & MONO_OPT_CMOV);
3799 g_assert (ins->dreg == ins->sreg1);
3800 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3801 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3802 break;
3803 case OP_IMAX:
3804 g_assert (cfg->opt & MONO_OPT_CMOV);
3805 g_assert (ins->dreg == ins->sreg1);
3806 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3807 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3808 break;
3809 case OP_IMAX_UN:
3810 g_assert (cfg->opt & MONO_OPT_CMOV);
3811 g_assert (ins->dreg == ins->sreg1);
3812 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3813 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3814 break;
3815 case OP_X86_FPOP:
3816 x86_fstp (code, 0);
3817 break;
3818 case OP_X86_FXCH:
3819 x86_fxch (code, ins->inst_imm);
3820 break;
3821 case OP_FREM: {
3822 guint8 *l1, *l2;
3823
3824 x86_push_reg (code, X86_EAX);
3825 /* we need to exchange ST(0) with ST(1) */
3826 x86_fxch (code, 1);
3827
3828 /* this requires a loop, because fprem somtimes
3829 * returns a partial remainder */
3830 l1 = code;
3831 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3832 /* x86_fprem1 (code); */
3833 x86_fprem (code);
3834 x86_fnstsw (code);
3835 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3836 l2 = code;
3837 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3838 x86_patch (l2, l1);
3839
3840 /* pop result */
3841 x86_fstp (code, 1);
3842
3843 x86_pop_reg (code, X86_EAX);
3844 break;
3845 }
3846 case OP_FCOMPARE:
3847 if (cfg->opt & MONO_OPT_FCMOV) {
3848 x86_fcomip (code, 1);
3849 x86_fstp (code, 0);
3850 break;
3851 }
3852 /* this overwrites EAX */
3853 EMIT_FPCOMPARE(code);
3854 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3855 break;
3856 case OP_FCEQ:
3857 case OP_FCNEQ:
3858 if (cfg->opt & MONO_OPT_FCMOV) {
3859 /* zeroing the register at the start results in
3860 * shorter and faster code (we can also remove the widening op)
3861 */
3862 guchar *unordered_check;
3863 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3864 x86_fcomip (code, 1);
3865 x86_fstp (code, 0);
3866 unordered_check = code;
3867 x86_branch8 (code, X86_CC_P, 0, FALSE);
3868 if (ins->opcode == OP_FCEQ) {
3869 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3870 x86_patch (unordered_check, code);
3871 } else {
3872 guchar *jump_to_end;
3873 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3874 jump_to_end = code;
3875 x86_jump8 (code, 0);
3876 x86_patch (unordered_check, code);
3877 x86_inc_reg (code, ins->dreg);
3878 x86_patch (jump_to_end, code);
3879 }
3880
3881 break;
3882 }
3883 if (ins->dreg != X86_EAX)
3884 x86_push_reg (code, X86_EAX);
3885
3886 EMIT_FPCOMPARE(code);
3887 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3888 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3889 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3890 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3891
3892 if (ins->dreg != X86_EAX)
3893 x86_pop_reg (code, X86_EAX);
3894 break;
3895 case OP_FCLT:
3896 case OP_FCLT_UN:
3897 if (cfg->opt & MONO_OPT_FCMOV) {
3898 /* zeroing the register at the start results in
3899 * shorter and faster code (we can also remove the widening op)
3900 */
3901 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3902 x86_fcomip (code, 1);
3903 x86_fstp (code, 0);
3904 if (ins->opcode == OP_FCLT_UN) {
3905 guchar *unordered_check = code;
3906 guchar *jump_to_end;
3907 x86_branch8 (code, X86_CC_P, 0, FALSE);
3908 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3909 jump_to_end = code;
3910 x86_jump8 (code, 0);
3911 x86_patch (unordered_check, code);
3912 x86_inc_reg (code, ins->dreg);
3913 x86_patch (jump_to_end, code);
3914 } else {
3915 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3916 }
3917 break;
3918 }
3919 if (ins->dreg != X86_EAX)
3920 x86_push_reg (code, X86_EAX);
3921
3922 EMIT_FPCOMPARE(code);
3923 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3924 if (ins->opcode == OP_FCLT_UN) {
3925 guchar *is_not_zero_check, *end_jump;
3926 is_not_zero_check = code;
3927 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3928 end_jump = code;
3929 x86_jump8 (code, 0);
3930 x86_patch (is_not_zero_check, code);
3931 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3932
3933 x86_patch (end_jump, code);
3934 }
3935 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3936 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3937
3938 if (ins->dreg != X86_EAX)
3939 x86_pop_reg (code, X86_EAX);
3940 break;
3941 case OP_FCLE: {
3942 guchar *unordered_check;
3943 guchar *jump_to_end;
3944 if (cfg->opt & MONO_OPT_FCMOV) {
3945 /* zeroing the register at the start results in
3946 * shorter and faster code (we can also remove the widening op)
3947 */
3948 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3949 x86_fcomip (code, 1);
3950 x86_fstp (code, 0);
3951 unordered_check = code;
3952 x86_branch8 (code, X86_CC_P, 0, FALSE);
3953 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3954 x86_patch (unordered_check, code);
3955 break;
3956 }
3957 if (ins->dreg != X86_EAX)
3958 x86_push_reg (code, X86_EAX);
3959
3960 EMIT_FPCOMPARE(code);
3961 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3962 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3963 unordered_check = code;
3964 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3965
3966 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3967 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3968 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3969 jump_to_end = code;
3970 x86_jump8 (code, 0);
3971 x86_patch (unordered_check, code);
3972 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3973 x86_patch (jump_to_end, code);
3974
3975 if (ins->dreg != X86_EAX)
3976 x86_pop_reg (code, X86_EAX);
3977 break;
3978 }
3979 case OP_FCGT:
3980 case OP_FCGT_UN:
3981 if (cfg->opt & MONO_OPT_FCMOV) {
3982 /* zeroing the register at the start results in
3983 * shorter and faster code (we can also remove the widening op)
3984 */
3985 guchar *unordered_check;
3986 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3987 x86_fcomip (code, 1);
3988 x86_fstp (code, 0);
3989 if (ins->opcode == OP_FCGT) {
3990 unordered_check = code;
3991 x86_branch8 (code, X86_CC_P, 0, FALSE);
3992 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3993 x86_patch (unordered_check, code);
3994 } else {
3995 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3996 }
3997 break;
3998 }
3999 if (ins->dreg != X86_EAX)
4000 x86_push_reg (code, X86_EAX);
4001
4002 EMIT_FPCOMPARE(code);
4003 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4004 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4005 if (ins->opcode == OP_FCGT_UN) {
4006 guchar *is_not_zero_check, *end_jump;
4007 is_not_zero_check = code;
4008 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4009 end_jump = code;
4010 x86_jump8 (code, 0);
4011 x86_patch (is_not_zero_check, code);
4012 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4013
4014 x86_patch (end_jump, code);
4015 }
4016 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4017 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4018
4019 if (ins->dreg != X86_EAX)
4020 x86_pop_reg (code, X86_EAX);
4021 break;
4022 case OP_FCGE: {
4023 guchar *unordered_check;
4024 guchar *jump_to_end;
4025 if (cfg->opt & MONO_OPT_FCMOV) {
4026 /* zeroing the register at the start results in
4027 * shorter and faster code (we can also remove the widening op)
4028 */
4029 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4030 x86_fcomip (code, 1);
4031 x86_fstp (code, 0);
4032 unordered_check = code;
4033 x86_branch8 (code, X86_CC_P, 0, FALSE);
4034 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4035 x86_patch (unordered_check, code);
4036 break;
4037 }
4038 if (ins->dreg != X86_EAX)
4039 x86_push_reg (code, X86_EAX);
4040
4041 EMIT_FPCOMPARE(code);
4042 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4043 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4044 unordered_check = code;
4045 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4046
4047 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4048 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4049 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4050 jump_to_end = code;
4051 x86_jump8 (code, 0);
4052 x86_patch (unordered_check, code);
4053 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4054 x86_patch (jump_to_end, code);
4055
4056 if (ins->dreg != X86_EAX)
4057 x86_pop_reg (code, X86_EAX);
4058 break;
4059 }
4060 case OP_FBEQ:
4061 if (cfg->opt & MONO_OPT_FCMOV) {
4062 guchar *jump = code;
4063 x86_branch8 (code, X86_CC_P, 0, TRUE);
4064 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4065 x86_patch (jump, code);
4066 break;
4067 }
4068 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4069 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4070 break;
4071 case OP_FBNE_UN:
4072 /* Branch if C013 != 100 */
4073 if (cfg->opt & MONO_OPT_FCMOV) {
4074 /* branch if !ZF or (PF|CF) */
4075 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4076 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4077 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4078 break;
4079 }
4080 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4081 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4082 break;
4083 case OP_FBLT:
4084 if (cfg->opt & MONO_OPT_FCMOV) {
4085 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4086 break;
4087 }
4088 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4089 break;
4090 case OP_FBLT_UN:
4091 if (cfg->opt & MONO_OPT_FCMOV) {
4092 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4093 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4094 break;
4095 }
4096 if (ins->opcode == OP_FBLT_UN) {
4097 guchar *is_not_zero_check, *end_jump;
4098 is_not_zero_check = code;
4099 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4100 end_jump = code;
4101 x86_jump8 (code, 0);
4102 x86_patch (is_not_zero_check, code);
4103 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4104
4105 x86_patch (end_jump, code);
4106 }
4107 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4108 break;
4109 case OP_FBGT:
4110 case OP_FBGT_UN:
4111 if (cfg->opt & MONO_OPT_FCMOV) {
4112 if (ins->opcode == OP_FBGT) {
4113 guchar *br1;
4114
4115 /* skip branch if C1=1 */
4116 br1 = code;
4117 x86_branch8 (code, X86_CC_P, 0, FALSE);
4118 /* branch if (C0 | C3) = 1 */
4119 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4120 x86_patch (br1, code);
4121 } else {
4122 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4123 }
4124 break;
4125 }
4126 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4127 if (ins->opcode == OP_FBGT_UN) {
4128 guchar *is_not_zero_check, *end_jump;
4129 is_not_zero_check = code;
4130 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4131 end_jump = code;
4132 x86_jump8 (code, 0);
4133 x86_patch (is_not_zero_check, code);
4134 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4135
4136 x86_patch (end_jump, code);
4137 }
4138 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4139 break;
4140 case OP_FBGE:
4141 /* Branch if C013 == 100 or 001 */
4142 if (cfg->opt & MONO_OPT_FCMOV) {
4143 guchar *br1;
4144
4145 /* skip branch if C1=1 */
4146 br1 = code;
4147 x86_branch8 (code, X86_CC_P, 0, FALSE);
4148 /* branch if (C0 | C3) = 1 */
4149 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4150 x86_patch (br1, code);
4151 break;
4152 }
4153 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4154 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4155 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4156 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4157 break;
4158 case OP_FBGE_UN:
4159 /* Branch if C013 == 000 */
4160 if (cfg->opt & MONO_OPT_FCMOV) {
4161 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4162 break;
4163 }
4164 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4165 break;
4166 case OP_FBLE:
4167 /* Branch if C013=000 or 100 */
4168 if (cfg->opt & MONO_OPT_FCMOV) {
4169 guchar *br1;
4170
4171 /* skip branch if C1=1 */
4172 br1 = code;
4173 x86_branch8 (code, X86_CC_P, 0, FALSE);
4174 /* branch if C0=0 */
4175 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4176 x86_patch (br1, code);
4177 break;
4178 }
4179 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4180 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4181 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4182 break;
4183 case OP_FBLE_UN:
4184 /* Branch if C013 != 001 */
4185 if (cfg->opt & MONO_OPT_FCMOV) {
4186 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4187 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4188 break;
4189 }
4190 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4191 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4192 break;
4193 case OP_CKFINITE: {
4194 guchar *br1;
4195 x86_push_reg (code, X86_EAX);
4196 x86_fxam (code);
4197 x86_fnstsw (code);
4198 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4199 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4200 x86_pop_reg (code, X86_EAX);
4201
4202 /* Have to clean up the fp stack before throwing the exception */
4203 br1 = code;
4204 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4205
4206 x86_fstp (code, 0);
4207 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4208
4209 x86_patch (br1, code);
4210 break;
4211 }
4212 case OP_TLS_GET: {
4213 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4214 break;
4215 }
4216 case OP_TLS_GET_REG: {
4217 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4218 break;
4219 }
4220 case OP_TLS_SET: {
4221 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4222 break;
4223 }
4224 case OP_TLS_SET_REG: {
4225 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4226 break;
4227 }
4228 case OP_MEMORY_BARRIER: {
4229 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4230 x86_prefix (code, X86_LOCK_PREFIX);
4231 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4232 }
4233 break;
4234 }
4235 case OP_ATOMIC_ADD_I4: {
4236 int dreg = ins->dreg;
4237
4238 g_assert (cfg->has_atomic_add_i4);
4239
4240 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4241 if (ins->sreg2 == dreg) {
4242 if (dreg == X86_EBX) {
4243 dreg = X86_EDI;
4244 if (ins->inst_basereg == X86_EDI)
4245 dreg = X86_ESI;
4246 } else {
4247 dreg = X86_EBX;
4248 if (ins->inst_basereg == X86_EBX)
4249 dreg = X86_EDI;
4250 }
4251 } else if (ins->inst_basereg == dreg) {
4252 if (dreg == X86_EBX) {
4253 dreg = X86_EDI;
4254 if (ins->sreg2 == X86_EDI)
4255 dreg = X86_ESI;
4256 } else {
4257 dreg = X86_EBX;
4258 if (ins->sreg2 == X86_EBX)
4259 dreg = X86_EDI;
4260 }
4261 }
4262
4263 if (dreg != ins->dreg) {
4264 x86_push_reg (code, dreg);
4265 }
4266
4267 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4268 x86_prefix (code, X86_LOCK_PREFIX);
4269 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4270 /* dreg contains the old value, add with sreg2 value */
4271 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4272
4273 if (ins->dreg != dreg) {
4274 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4275 x86_pop_reg (code, dreg);
4276 }
4277
4278 break;
4279 }
4280 case OP_ATOMIC_EXCHANGE_I4: {
4281 guchar *br[2];
4282 int sreg2 = ins->sreg2;
4283 int breg = ins->inst_basereg;
4284
4285 g_assert (cfg->has_atomic_exchange_i4);
4286
4287 /* cmpxchg uses eax as comperand, need to make sure we can use it
4288 * hack to overcome limits in x86 reg allocator
4289 * (req: dreg == eax and sreg2 != eax and breg != eax)
4290 */
4291 g_assert (ins->dreg == X86_EAX);
4292
4293 /* We need the EAX reg for the cmpxchg */
4294 if (ins->sreg2 == X86_EAX) {
4295 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4296 x86_push_reg (code, sreg2);
4297 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4298 }
4299
4300 if (breg == X86_EAX) {
4301 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4302 x86_push_reg (code, breg);
4303 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4304 }
4305
4306 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4307
4308 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4309 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4310 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4311 x86_patch (br [1], br [0]);
4312
4313 if (breg != ins->inst_basereg)
4314 x86_pop_reg (code, breg);
4315
4316 if (ins->sreg2 != sreg2)
4317 x86_pop_reg (code, sreg2);
4318
4319 break;
4320 }
4321 case OP_ATOMIC_CAS_I4: {
4322 g_assert (ins->dreg == X86_EAX);
4323 g_assert (ins->sreg3 == X86_EAX);
4324 g_assert (ins->sreg1 != X86_EAX);
4325 g_assert (ins->sreg1 != ins->sreg2);
4326
4327 x86_prefix (code, X86_LOCK_PREFIX);
4328 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4329 break;
4330 }
4331 case OP_ATOMIC_LOAD_I1: {
4332 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4333 break;
4334 }
4335 case OP_ATOMIC_LOAD_U1: {
4336 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4337 break;
4338 }
4339 case OP_ATOMIC_LOAD_I2: {
4340 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4341 break;
4342 }
4343 case OP_ATOMIC_LOAD_U2: {
4344 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4345 break;
4346 }
4347 case OP_ATOMIC_LOAD_I4:
4348 case OP_ATOMIC_LOAD_U4: {
4349 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4350 break;
4351 }
4352 case OP_ATOMIC_LOAD_R4:
4353 case OP_ATOMIC_LOAD_R8: {
4354 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4355 break;
4356 }
4357 case OP_ATOMIC_STORE_I1:
4358 case OP_ATOMIC_STORE_U1:
4359 case OP_ATOMIC_STORE_I2:
4360 case OP_ATOMIC_STORE_U2:
4361 case OP_ATOMIC_STORE_I4:
4362 case OP_ATOMIC_STORE_U4: {
4363 int size;
4364
4365 switch (ins->opcode) {
4366 case OP_ATOMIC_STORE_I1:
4367 case OP_ATOMIC_STORE_U1:
4368 size = 1;
4369 break;
4370 case OP_ATOMIC_STORE_I2:
4371 case OP_ATOMIC_STORE_U2:
4372 size = 2;
4373 break;
4374 case OP_ATOMIC_STORE_I4:
4375 case OP_ATOMIC_STORE_U4:
4376 size = 4;
4377 break;
4378 }
4379
4380 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4381
4382 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4383 x86_mfence (code);
4384 break;
4385 }
4386 case OP_ATOMIC_STORE_R4:
4387 case OP_ATOMIC_STORE_R8: {
4388 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4389
4390 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4391 x86_mfence (code);
4392 break;
4393 }
4394 case OP_CARD_TABLE_WBARRIER: {
4395 int ptr = ins->sreg1;
4396 int value = ins->sreg2;
4397 guchar *br = NULL;
4398 int nursery_shift, card_table_shift;
4399 gpointer card_table_mask;
4400 size_t nursery_size;
4401 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4402 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4403 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4404
4405 /*
4406 * We need one register we can clobber, we choose EDX and make sreg1
4407 * fixed EAX to work around limitations in the local register allocator.
4408 * sreg2 might get allocated to EDX, but that is not a problem since
4409 * we use it before clobbering EDX.
4410 */
4411 g_assert (ins->sreg1 == X86_EAX);
4412
4413 /*
4414 * This is the code we produce:
4415 *
4416 * edx = value
4417 * edx >>= nursery_shift
4418 * cmp edx, (nursery_start >> nursery_shift)
4419 * jne done
4420 * edx = ptr
4421 * edx >>= card_table_shift
4422 * card_table[edx] = 1
4423 * done:
4424 */
4425
4426 if (card_table_nursery_check) {
4427 if (value != X86_EDX)
4428 x86_mov_reg_reg (code, X86_EDX, value, 4);
4429 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4430 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4431 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4432 }
4433 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4434 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4435 if (card_table_mask)
4436 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4437 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4438 if (card_table_nursery_check)
4439 x86_patch (br, code);
4440 break;
4441 }
4442 #ifdef MONO_ARCH_SIMD_INTRINSICS
4443 case OP_ADDPS:
4444 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4445 break;
4446 case OP_DIVPS:
4447 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4448 break;
4449 case OP_MULPS:
4450 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4451 break;
4452 case OP_SUBPS:
4453 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4454 break;
4455 case OP_MAXPS:
4456 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4457 break;
4458 case OP_MINPS:
4459 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4460 break;
4461 case OP_COMPPS:
4462 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4463 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4464 break;
4465 case OP_ANDPS:
4466 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4467 break;
4468 case OP_ANDNPS:
4469 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4470 break;
4471 case OP_ORPS:
4472 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4473 break;
4474 case OP_XORPS:
4475 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4476 break;
4477 case OP_SQRTPS:
4478 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4479 break;
4480 case OP_RSQRTPS:
4481 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4482 break;
4483 case OP_RCPPS:
4484 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4485 break;
4486 case OP_ADDSUBPS:
4487 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4488 break;
4489 case OP_HADDPS:
4490 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4491 break;
4492 case OP_HSUBPS:
4493 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4494 break;
4495 case OP_DUPPS_HIGH:
4496 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4497 break;
4498 case OP_DUPPS_LOW:
4499 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4500 break;
4501
4502 case OP_PSHUFLEW_HIGH:
4503 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4504 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4505 break;
4506 case OP_PSHUFLEW_LOW:
4507 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4508 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4509 break;
4510 case OP_PSHUFLED:
4511 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4512 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4513 break;
4514 case OP_SHUFPS:
4515 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4516 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4517 break;
4518 case OP_SHUFPD:
4519 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4520 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4521 break;
4522
4523 case OP_ADDPD:
4524 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4525 break;
4526 case OP_DIVPD:
4527 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4528 break;
4529 case OP_MULPD:
4530 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4531 break;
4532 case OP_SUBPD:
4533 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4534 break;
4535 case OP_MAXPD:
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4537 break;
4538 case OP_MINPD:
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4540 break;
4541 case OP_COMPPD:
4542 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4543 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4544 break;
4545 case OP_ANDPD:
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4547 break;
4548 case OP_ANDNPD:
4549 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4550 break;
4551 case OP_ORPD:
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4553 break;
4554 case OP_XORPD:
4555 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4556 break;
4557 case OP_SQRTPD:
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4559 break;
4560 case OP_ADDSUBPD:
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4562 break;
4563 case OP_HADDPD:
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4565 break;
4566 case OP_HSUBPD:
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4568 break;
4569 case OP_DUPPD:
4570 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4571 break;
4572
4573 case OP_EXTRACT_MASK:
4574 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4575 break;
4576
4577 case OP_PAND:
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4579 break;
4580 case OP_POR:
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4582 break;
4583 case OP_PXOR:
4584 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4585 break;
4586
4587 case OP_PADDB:
4588 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4589 break;
4590 case OP_PADDW:
4591 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4592 break;
4593 case OP_PADDD:
4594 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4595 break;
4596 case OP_PADDQ:
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4598 break;
4599
4600 case OP_PSUBB:
4601 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4602 break;
4603 case OP_PSUBW:
4604 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4605 break;
4606 case OP_PSUBD:
4607 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4608 break;
4609 case OP_PSUBQ:
4610 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4611 break;
4612
4613 case OP_PMAXB_UN:
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4615 break;
4616 case OP_PMAXW_UN:
4617 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4618 break;
4619 case OP_PMAXD_UN:
4620 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4621 break;
4622
4623 case OP_PMAXB:
4624 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4625 break;
4626 case OP_PMAXW:
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4628 break;
4629 case OP_PMAXD:
4630 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4631 break;
4632
4633 case OP_PAVGB_UN:
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4635 break;
4636 case OP_PAVGW_UN:
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4638 break;
4639
4640 case OP_PMINB_UN:
4641 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4642 break;
4643 case OP_PMINW_UN:
4644 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4645 break;
4646 case OP_PMIND_UN:
4647 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4648 break;
4649
4650 case OP_PMINB:
4651 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4652 break;
4653 case OP_PMINW:
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4655 break;
4656 case OP_PMIND:
4657 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4658 break;
4659
4660 case OP_PCMPEQB:
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4662 break;
4663 case OP_PCMPEQW:
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4665 break;
4666 case OP_PCMPEQD:
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4668 break;
4669 case OP_PCMPEQQ:
4670 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4671 break;
4672
4673 case OP_PCMPGTB:
4674 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4675 break;
4676 case OP_PCMPGTW:
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4678 break;
4679 case OP_PCMPGTD:
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4681 break;
4682 case OP_PCMPGTQ:
4683 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4684 break;
4685
4686 case OP_PSUM_ABS_DIFF:
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4688 break;
4689
4690 case OP_UNPACK_LOWB:
4691 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4692 break;
4693 case OP_UNPACK_LOWW:
4694 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4695 break;
4696 case OP_UNPACK_LOWD:
4697 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4698 break;
4699 case OP_UNPACK_LOWQ:
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4701 break;
4702 case OP_UNPACK_LOWPS:
4703 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4704 break;
4705 case OP_UNPACK_LOWPD:
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4707 break;
4708
4709 case OP_UNPACK_HIGHB:
4710 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4711 break;
4712 case OP_UNPACK_HIGHW:
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4714 break;
4715 case OP_UNPACK_HIGHD:
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4717 break;
4718 case OP_UNPACK_HIGHQ:
4719 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4720 break;
4721 case OP_UNPACK_HIGHPS:
4722 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4723 break;
4724 case OP_UNPACK_HIGHPD:
4725 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4726 break;
4727
4728 case OP_PACKW:
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4730 break;
4731 case OP_PACKD:
4732 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4733 break;
4734 case OP_PACKW_UN:
4735 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4736 break;
4737 case OP_PACKD_UN:
4738 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4739 break;
4740
4741 case OP_PADDB_SAT_UN:
4742 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4743 break;
4744 case OP_PSUBB_SAT_UN:
4745 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4746 break;
4747 case OP_PADDW_SAT_UN:
4748 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4749 break;
4750 case OP_PSUBW_SAT_UN:
4751 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4752 break;
4753
4754 case OP_PADDB_SAT:
4755 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4756 break;
4757 case OP_PSUBB_SAT:
4758 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4759 break;
4760 case OP_PADDW_SAT:
4761 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4762 break;
4763 case OP_PSUBW_SAT:
4764 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4765 break;
4766
4767 case OP_PMULW:
4768 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4769 break;
4770 case OP_PMULD:
4771 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4772 break;
4773 case OP_PMULQ:
4774 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4775 break;
4776 case OP_PMULW_HIGH_UN:
4777 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4778 break;
4779 case OP_PMULW_HIGH:
4780 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4781 break;
4782
4783 case OP_PSHRW:
4784 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4785 break;
4786 case OP_PSHRW_REG:
4787 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4788 break;
4789
4790 case OP_PSARW:
4791 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4792 break;
4793 case OP_PSARW_REG:
4794 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4795 break;
4796
4797 case OP_PSHLW:
4798 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4799 break;
4800 case OP_PSHLW_REG:
4801 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4802 break;
4803
4804 case OP_PSHRD:
4805 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4806 break;
4807 case OP_PSHRD_REG:
4808 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4809 break;
4810
4811 case OP_PSARD:
4812 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4813 break;
4814 case OP_PSARD_REG:
4815 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4816 break;
4817
4818 case OP_PSHLD:
4819 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4820 break;
4821 case OP_PSHLD_REG:
4822 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4823 break;
4824
4825 case OP_PSHRQ:
4826 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4827 break;
4828 case OP_PSHRQ_REG:
4829 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4830 break;
4831
4832 case OP_PSHLQ:
4833 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4834 break;
4835 case OP_PSHLQ_REG:
4836 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4837 break;
4838
4839 case OP_ICONV_TO_X:
4840 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4841 break;
4842 case OP_EXTRACT_I4:
4843 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4844 break;
4845 case OP_EXTRACT_I1:
4846 case OP_EXTRACT_U1:
4847 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4848 if (ins->inst_c0)
4849 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4850 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4851 break;
4852 case OP_EXTRACT_I2:
4853 case OP_EXTRACT_U2:
4854 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4855 if (ins->inst_c0)
4856 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4857 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4858 break;
4859 case OP_EXTRACT_R8:
4860 if (ins->inst_c0)
4861 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4862 else
4863 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4864 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4865 break;
4866
4867 case OP_INSERT_I2:
4868 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4869 break;
4870 case OP_EXTRACTX_U2:
4871 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4872 break;
4873 case OP_INSERTX_U1_SLOW:
4874 /*sreg1 is the extracted ireg (scratch)
4875 /sreg2 is the to be inserted ireg (scratch)
4876 /dreg is the xreg to receive the value*/
4877
4878 /*clear the bits from the extracted word*/
4879 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4880 /*shift the value to insert if needed*/
4881 if (ins->inst_c0 & 1)
4882 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4883 /*join them together*/
4884 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4885 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4886 break;
4887 case OP_INSERTX_I4_SLOW:
4888 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4889 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4890 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4891 break;
4892
4893 case OP_INSERTX_R4_SLOW:
4894 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4895 /*TODO if inst_c0 == 0 use movss*/
4896 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4897 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4898 break;
4899 case OP_INSERTX_R8_SLOW:
4900 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4901 if (cfg->verbose_level)
4902 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4903 if (ins->inst_c0)
4904 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4905 else
4906 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4907 break;
4908
4909 case OP_STOREX_MEMBASE_REG:
4910 case OP_STOREX_MEMBASE:
4911 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4912 break;
4913 case OP_LOADX_MEMBASE:
4914 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4915 break;
4916 case OP_LOADX_ALIGNED_MEMBASE:
4917 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4918 break;
4919 case OP_STOREX_ALIGNED_MEMBASE_REG:
4920 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4921 break;
4922 case OP_STOREX_NTA_MEMBASE_REG:
4923 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4924 break;
4925 case OP_PREFETCH_MEMBASE:
4926 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4927
4928 break;
4929 case OP_XMOVE:
4930 /*FIXME the peephole pass should have killed this*/
4931 if (ins->dreg != ins->sreg1)
4932 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4933 break;
4934 case OP_XZERO:
4935 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4936 break;
4937
4938 case OP_FCONV_TO_R8_X:
4939 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4940 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4941 break;
4942
4943 case OP_XCONV_R8_TO_I4:
4944 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4945 switch (ins->backend.source_opcode) {
4946 case OP_FCONV_TO_I1:
4947 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4948 break;
4949 case OP_FCONV_TO_U1:
4950 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4951 break;
4952 case OP_FCONV_TO_I2:
4953 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4954 break;
4955 case OP_FCONV_TO_U2:
4956 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4957 break;
4958 }
4959 break;
4960
4961 case OP_EXPAND_I1:
4962 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4963 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4964 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4965 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4966 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4967 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4968 break;
4969 case OP_EXPAND_I2:
4970 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4971 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4972 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4973 break;
4974 case OP_EXPAND_I4:
4975 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4976 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4977 break;
4978 case OP_EXPAND_R4:
4979 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4980 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4981 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4982 break;
4983 case OP_EXPAND_R8:
4984 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4985 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4986 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4987 break;
4988
4989 case OP_CVTDQ2PD:
4990 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4991 break;
4992 case OP_CVTDQ2PS:
4993 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4994 break;
4995 case OP_CVTPD2DQ:
4996 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4997 break;
4998 case OP_CVTPD2PS:
4999 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5000 break;
5001 case OP_CVTPS2DQ:
5002 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5003 break;
5004 case OP_CVTPS2PD:
5005 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5006 break;
5007 case OP_CVTTPD2DQ:
5008 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5009 break;
5010 case OP_CVTTPS2DQ:
5011 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5012 break;
5013
5014 #endif
5015 case OP_LIVERANGE_START: {
5016 if (cfg->verbose_level > 1)
5017 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5018 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5019 break;
5020 }
5021 case OP_LIVERANGE_END: {
5022 if (cfg->verbose_level > 1)
5023 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5024 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5025 break;
5026 }
5027 case OP_GC_SAFE_POINT: {
5028 const char *polling_func = NULL;
5029 int compare_val = 0;
5030 guint8 *br [1];
5031
5032 #if defined (USE_COOP_GC)
5033 polling_func = "mono_threads_state_poll";
5034 compare_val = 1;
5035 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
5036 polling_func = "mono_nacl_gc";
5037 compare_val = 0xFFFFFFFF;
5038 #endif
5039 if (!polling_func)
5040 break;
5041
5042 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5043 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5044 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5045 x86_patch (br [0], code);
5046
5047 break;
5048 }
5049 case OP_GC_LIVENESS_DEF:
5050 case OP_GC_LIVENESS_USE:
5051 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5052 ins->backend.pc_offset = code - cfg->native_code;
5053 break;
5054 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5055 ins->backend.pc_offset = code - cfg->native_code;
5056 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5057 break;
5058 case OP_GET_SP:
5059 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5060 break;
5061 case OP_SET_SP:
5062 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5063 break;
5064 default:
5065 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5066 g_assert_not_reached ();
5067 }
5068
5069 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5070 #ifndef __native_client_codegen__
5071 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5072 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5073 g_assert_not_reached ();
5074 #endif /* __native_client_codegen__ */
5075 }
5076
5077 cpos += max_len;
5078 }
5079
5080 cfg->code_len = code - cfg->native_code;
5081 }
5082
5083 #endif /* DISABLE_JIT */
5084
5085 void
5086 mono_arch_register_lowlevel_calls (void)
5087 {
5088 }
5089
5090 void
5091 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5092 {
5093 unsigned char *ip = ji->ip.i + code;
5094
5095 switch (ji->type) {
5096 case MONO_PATCH_INFO_IP:
5097 *((gconstpointer *)(ip)) = target;
5098 break;
5099 case MONO_PATCH_INFO_CLASS_INIT: {
5100 guint8 *code = ip;
5101 /* Might already been changed to a nop */
5102 x86_call_code (code, 0);
5103 x86_patch (ip, (unsigned char*)target);
5104 break;
5105 }
5106 case MONO_PATCH_INFO_ABS:
5107 case MONO_PATCH_INFO_METHOD:
5108 case MONO_PATCH_INFO_METHOD_JUMP:
5109 case MONO_PATCH_INFO_INTERNAL_METHOD:
5110 case MONO_PATCH_INFO_BB:
5111 case MONO_PATCH_INFO_LABEL:
5112 case MONO_PATCH_INFO_RGCTX_FETCH:
5113 case MONO_PATCH_INFO_MONITOR_ENTER:
5114 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5115 case MONO_PATCH_INFO_MONITOR_EXIT:
5116 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5117 #if defined(__native_client_codegen__) && defined(__native_client__)
5118 if (nacl_is_code_address (code)) {
5119 /* For tail calls, code is patched after being installed */
5120 /* but not through the normal "patch callsite" method. */
5121 unsigned char buf[kNaClAlignment];
5122 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5123 unsigned char *_target = target;
5124 int ret;
5125 /* All patch targets modified in x86_patch */
5126 /* are IP relative. */
5127 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5128 memcpy (buf, aligned_code, kNaClAlignment);
5129 /* Patch a temp buffer of bundle size, */
5130 /* then install to actual location. */
5131 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5132 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5133 g_assert (ret == 0);
5134 }
5135 else {
5136 x86_patch (ip, (unsigned char*)target);
5137 }
5138 #else
5139 x86_patch (ip, (unsigned char*)target);
5140 #endif
5141 break;
5142 case MONO_PATCH_INFO_NONE:
5143 break;
5144 case MONO_PATCH_INFO_R4:
5145 case MONO_PATCH_INFO_R8: {
5146 guint32 offset = mono_arch_get_patch_offset (ip);
5147 *((gconstpointer *)(ip + offset)) = target;
5148 break;
5149 }
5150 default: {
5151 guint32 offset = mono_arch_get_patch_offset (ip);
5152 #if !defined(__native_client__)
5153 *((gconstpointer *)(ip + offset)) = target;
5154 #else
5155 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5156 #endif
5157 break;
5158 }
5159 }
5160 }
5161
5162 static G_GNUC_UNUSED void
5163 stack_unaligned (MonoMethod *m, gpointer caller)
5164 {
5165 printf ("%s\n", mono_method_full_name (m, TRUE));
5166 g_assert_not_reached ();
5167 }
5168
5169 guint8 *
5170 mono_arch_emit_prolog (MonoCompile *cfg)
5171 {
5172 MonoMethod *method = cfg->method;
5173 MonoBasicBlock *bb;
5174 MonoMethodSignature *sig;
5175 MonoInst *inst;
5176 int alloc_size, pos, max_offset, i, cfa_offset;
5177 guint8 *code;
5178 gboolean need_stack_frame;
5179 #ifdef __native_client_codegen__
5180 guint alignment_check;
5181 #endif
5182
5183 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5184
5185 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5186 cfg->code_size += 512;
5187
5188 #if defined(__default_codegen__)
5189 code = cfg->native_code = g_malloc (cfg->code_size);
5190 #elif defined(__native_client_codegen__)
5191 /* native_code_alloc is not 32-byte aligned, native_code is. */
5192 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5193 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5194
5195 /* Align native_code to next nearest kNaclAlignment byte. */
5196 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5197 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5198
5199 code = cfg->native_code;
5200
5201 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5202 g_assert(alignment_check == 0);
5203 #endif
5204
5205 #if 0
5206 {
5207 guint8 *br [16];
5208
5209 /* Check that the stack is aligned on osx */
5210 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5211 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5212 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5213 br [0] = code;
5214 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5215 x86_push_membase (code, X86_ESP, 0);
5216 x86_push_imm (code, cfg->method);
5217 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5218 x86_call_reg (code, X86_EAX);
5219 x86_patch (br [0], code);
5220 }
5221 #endif
5222
5223 /* Offset between RSP and the CFA */
5224 cfa_offset = 0;
5225
5226 // CFA = sp + 4
5227 cfa_offset = sizeof (gpointer);
5228 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5229 // IP saved at CFA - 4
5230 /* There is no IP reg on x86 */
5231 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5232 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5233
5234 need_stack_frame = needs_stack_frame (cfg);
5235
5236 if (need_stack_frame) {
5237 x86_push_reg (code, X86_EBP);
5238 cfa_offset += sizeof (gpointer);
5239 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5240 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5241 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5242 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5243 /* These are handled automatically by the stack marking code */
5244 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5245 } else {
5246 cfg->frame_reg = X86_ESP;
5247 }
5248
5249 cfg->stack_offset += cfg->param_area;
5250 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5251
5252 alloc_size = cfg->stack_offset;
5253 pos = 0;
5254
5255 if (!method->save_lmf) {
5256 if (cfg->used_int_regs & (1 << X86_EBX)) {
5257 x86_push_reg (code, X86_EBX);
5258 pos += 4;
5259 cfa_offset += sizeof (gpointer);
5260 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5261 /* These are handled automatically by the stack marking code */
5262 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5263 }
5264
5265 if (cfg->used_int_regs & (1 << X86_EDI)) {
5266 x86_push_reg (code, X86_EDI);
5267 pos += 4;
5268 cfa_offset += sizeof (gpointer);
5269 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5270 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5271 }
5272
5273 if (cfg->used_int_regs & (1 << X86_ESI)) {
5274 x86_push_reg (code, X86_ESI);
5275 pos += 4;
5276 cfa_offset += sizeof (gpointer);
5277 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5278 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5279 }
5280 }
5281
5282 alloc_size -= pos;
5283
5284 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5285 if (mono_do_x86_stack_align && need_stack_frame) {
5286 int tot = alloc_size + pos + 4; /* ret ip */
5287 if (need_stack_frame)
5288 tot += 4; /* ebp */
5289 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5290 if (tot) {
5291 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5292 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5293 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5294 }
5295 }
5296
5297 cfg->arch.sp_fp_offset = alloc_size + pos;
5298
5299 if (alloc_size) {
5300 /* See mono_emit_stack_alloc */
5301 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5302 guint32 remaining_size = alloc_size;
5303 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5304 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5305 guint32 offset = code - cfg->native_code;
5306 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5307 while (required_code_size >= (cfg->code_size - offset))
5308 cfg->code_size *= 2;
5309 cfg->native_code = mono_realloc_native_code(cfg);
5310 code = cfg->native_code + offset;
5311 cfg->stat_code_reallocs++;
5312 }
5313 while (remaining_size >= 0x1000) {
5314 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5315 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5316 remaining_size -= 0x1000;
5317 }
5318 if (remaining_size)
5319 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5320 #else
5321 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5322 #endif
5323
5324 g_assert (need_stack_frame);
5325 }
5326
5327 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5328 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5329 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5330 }
5331
5332 #if DEBUG_STACK_ALIGNMENT
5333 /* check the stack is aligned */
5334 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5335 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5336 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5337 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5338 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5339 x86_breakpoint (code);
5340 }
5341 #endif
5342
5343 /* compute max_offset in order to use short forward jumps */
5344 max_offset = 0;
5345 if (cfg->opt & MONO_OPT_BRANCH) {
5346 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5347 MonoInst *ins;
5348 bb->max_offset = max_offset;
5349
5350 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5351 max_offset += 6;
5352 /* max alignment for loops */
5353 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5354 max_offset += LOOP_ALIGNMENT;
5355 #ifdef __native_client_codegen__
5356 /* max alignment for native client */
5357 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5358 max_offset += kNaClAlignment;
5359 #endif
5360 MONO_BB_FOR_EACH_INS (bb, ins) {
5361 if (ins->opcode == OP_LABEL)
5362 ins->inst_c1 = max_offset;
5363 #ifdef __native_client_codegen__
5364 switch (ins->opcode)
5365 {
5366 case OP_FCALL:
5367 case OP_LCALL:
5368 case OP_VCALL:
5369 case OP_VCALL2:
5370 case OP_VOIDCALL:
5371 case OP_CALL:
5372 case OP_FCALL_REG:
5373 case OP_LCALL_REG:
5374 case OP_VCALL_REG:
5375 case OP_VCALL2_REG:
5376 case OP_VOIDCALL_REG:
5377 case OP_CALL_REG:
5378 case OP_FCALL_MEMBASE:
5379 case OP_LCALL_MEMBASE:
5380 case OP_VCALL_MEMBASE:
5381 case OP_VCALL2_MEMBASE:
5382 case OP_VOIDCALL_MEMBASE:
5383 case OP_CALL_MEMBASE:
5384 max_offset += kNaClAlignment;
5385 break;
5386 default:
5387 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5388 break;
5389 }
5390 #endif /* __native_client_codegen__ */
5391 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5392 }
5393 }
5394 }
5395
5396 /* store runtime generic context */
5397 if (cfg->rgctx_var) {
5398 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5399
5400 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5401 }
5402
5403 if (method->save_lmf)
5404 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5405
5406 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5407 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5408
5409 /* load arguments allocated to register from the stack */
5410 sig = mono_method_signature (method);
5411 pos = 0;
5412
5413 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5414 inst = cfg->args [pos];
5415 if (inst->opcode == OP_REGVAR) {
5416 g_assert (need_stack_frame);
5417 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5418 if (cfg->verbose_level > 2)
5419 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5420 }
5421 pos++;
5422 }
5423
5424 cfg->code_len = code - cfg->native_code;
5425
5426 g_assert (cfg->code_len < cfg->code_size);
5427
5428 return code;
5429 }
5430
5431 void
5432 mono_arch_emit_epilog (MonoCompile *cfg)
5433 {
5434 MonoMethod *method = cfg->method;
5435 MonoMethodSignature *sig = mono_method_signature (method);
5436 int i, quad, pos;
5437 guint32 stack_to_pop;
5438 guint8 *code;
5439 int max_epilog_size = 16;
5440 CallInfo *cinfo;
5441 gboolean need_stack_frame = needs_stack_frame (cfg);
5442
5443 if (cfg->method->save_lmf)
5444 max_epilog_size += 128;
5445
5446 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5447 cfg->code_size *= 2;
5448 cfg->native_code = mono_realloc_native_code(cfg);
5449 cfg->stat_code_reallocs++;
5450 }
5451
5452 code = cfg->native_code + cfg->code_len;
5453
5454 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5455 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5456
5457 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5458 pos = 0;
5459
5460 if (method->save_lmf) {
5461 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5462 guint8 *patch;
5463 gboolean supported = FALSE;
5464
5465 if (cfg->compile_aot) {
5466 #if defined(__APPLE__) || defined(__linux__)
5467 supported = TRUE;
5468 #endif
5469 } else if (mono_get_jit_tls_offset () != -1) {
5470 supported = TRUE;
5471 }
5472
5473 /* check if we need to restore protection of the stack after a stack overflow */
5474 if (supported) {
5475 if (cfg->compile_aot) {
5476 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5477
5478 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5479 } else {
5480 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5481 }
5482
5483 /* we load the value in a separate instruction: this mechanism may be
5484 * used later as a safer way to do thread interruption
5485 */
5486 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5487 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5488 patch = code;
5489 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5490 /* note that the call trampoline will preserve eax/edx */
5491 x86_call_reg (code, X86_ECX);
5492 x86_patch (patch, code);
5493 } else {
5494 /* FIXME: maybe save the jit tls in the prolog */
5495 }
5496
5497 /* restore caller saved regs */
5498 if (cfg->used_int_regs & (1 << X86_EBX)) {
5499 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5500 }
5501
5502 if (cfg->used_int_regs & (1 << X86_EDI)) {
5503 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5504 }
5505 if (cfg->used_int_regs & (1 << X86_ESI)) {
5506 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5507 }
5508
5509 /* EBP is restored by LEAVE */
5510 } else {
5511 for (i = 0; i < X86_NREG; ++i) {
5512 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5513 pos -= 4;
5514 }
5515 }
5516
5517 if (pos) {
5518 g_assert (need_stack_frame);
5519 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5520 }
5521
5522 if (pos) {
5523 g_assert (need_stack_frame);
5524 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5525 }
5526
5527 if (cfg->used_int_regs & (1 << X86_ESI)) {
5528 x86_pop_reg (code, X86_ESI);
5529 }
5530 if (cfg->used_int_regs & (1 << X86_EDI)) {
5531 x86_pop_reg (code, X86_EDI);
5532 }
5533 if (cfg->used_int_regs & (1 << X86_EBX)) {
5534 x86_pop_reg (code, X86_EBX);
5535 }
5536 }
5537
5538 /* Load returned vtypes into registers if needed */
5539 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5540 if (cinfo->ret.storage == ArgValuetypeInReg) {
5541 for (quad = 0; quad < 2; quad ++) {
5542 switch (cinfo->ret.pair_storage [quad]) {
5543 case ArgInIReg:
5544 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5545 break;
5546 case ArgOnFloatFpStack:
5547 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5548 break;
5549 case ArgOnDoubleFpStack:
5550 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5551 break;
5552 case ArgNone:
5553 break;
5554 default:
5555 g_assert_not_reached ();
5556 }
5557 }
5558 }
5559
5560 if (need_stack_frame)
5561 x86_leave (code);
5562
5563 if (CALLCONV_IS_STDCALL (sig)) {
5564 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5565
5566 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5567 } else if (cinfo->callee_stack_pop)
5568 stack_to_pop = cinfo->callee_stack_pop;
5569 else
5570 stack_to_pop = 0;
5571
5572 if (stack_to_pop) {
5573 g_assert (need_stack_frame);
5574 x86_ret_imm (code, stack_to_pop);
5575 } else {
5576 x86_ret (code);
5577 }
5578
5579 cfg->code_len = code - cfg->native_code;
5580
5581 g_assert (cfg->code_len < cfg->code_size);
5582 }
5583
5584 void
5585 mono_arch_emit_exceptions (MonoCompile *cfg)
5586 {
5587 MonoJumpInfo *patch_info;
5588 int nthrows, i;
5589 guint8 *code;
5590 MonoClass *exc_classes [16];
5591 guint8 *exc_throw_start [16], *exc_throw_end [16];
5592 guint32 code_size;
5593 int exc_count = 0;
5594
5595 /* Compute needed space */
5596 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5597 if (patch_info->type == MONO_PATCH_INFO_EXC)
5598 exc_count++;
5599 }
5600
5601 /*
5602 * make sure we have enough space for exceptions
5603 * 16 is the size of two push_imm instructions and a call
5604 */
5605 if (cfg->compile_aot)
5606 code_size = exc_count * 32;
5607 else
5608 code_size = exc_count * 16;
5609
5610 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5611 cfg->code_size *= 2;
5612 cfg->native_code = mono_realloc_native_code(cfg);
5613 cfg->stat_code_reallocs++;
5614 }
5615
5616 code = cfg->native_code + cfg->code_len;
5617
5618 nthrows = 0;
5619 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5620 switch (patch_info->type) {
5621 case MONO_PATCH_INFO_EXC: {
5622 MonoClass *exc_class;
5623 guint8 *buf, *buf2;
5624 guint32 throw_ip;
5625
5626 x86_patch (patch_info->ip.i + cfg->native_code, code);
5627
5628 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5629 g_assert (exc_class);
5630 throw_ip = patch_info->ip.i;
5631
5632 /* Find a throw sequence for the same exception class */
5633 for (i = 0; i < nthrows; ++i)
5634 if (exc_classes [i] == exc_class)
5635 break;
5636 if (i < nthrows) {
5637 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5638 x86_jump_code (code, exc_throw_start [i]);
5639 patch_info->type = MONO_PATCH_INFO_NONE;
5640 }
5641 else {
5642 guint32 size;
5643
5644 /* Compute size of code following the push <OFFSET> */
5645 #if defined(__default_codegen__)
5646 size = 5 + 5;
5647 #elif defined(__native_client_codegen__)
5648 code = mono_nacl_align (code);
5649 size = kNaClAlignment;
5650 #endif
5651 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5652
5653 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5654 /* Use the shorter form */
5655 buf = buf2 = code;
5656 x86_push_imm (code, 0);
5657 }
5658 else {
5659 buf = code;
5660 x86_push_imm (code, 0xf0f0f0f0);
5661 buf2 = code;
5662 }
5663
5664 if (nthrows < 16) {
5665 exc_classes [nthrows] = exc_class;
5666 exc_throw_start [nthrows] = code;
5667 }
5668
5669 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5670 patch_info->data.name = "mono_arch_throw_corlib_exception";
5671 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5672 patch_info->ip.i = code - cfg->native_code;
5673 x86_call_code (code, 0);
5674 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5675 while (buf < buf2)
5676 x86_nop (buf);
5677
5678 if (nthrows < 16) {
5679 exc_throw_end [nthrows] = code;
5680 nthrows ++;
5681 }
5682 }
5683 break;
5684 }
5685 default:
5686 /* do nothing */
5687 break;
5688 }
5689 }
5690
5691 cfg->code_len = code - cfg->native_code;
5692
5693 g_assert (cfg->code_len < cfg->code_size);
5694 }
5695
5696 void
5697 mono_arch_flush_icache (guint8 *code, gint size)
5698 {
5699 /* not needed */
5700 }
5701
5702 void
5703 mono_arch_flush_register_windows (void)
5704 {
5705 }
5706
5707 gboolean
5708 mono_arch_is_inst_imm (gint64 imm)
5709 {
5710 return TRUE;
5711 }
5712
5713 void
5714 mono_arch_finish_init (void)
5715 {
5716 if (!g_getenv ("MONO_NO_TLS")) {
5717 #ifndef TARGET_WIN32
5718 #if MONO_XEN_OPT
5719 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5720 #endif
5721 #endif
5722 }
5723 }
5724
5725 void
5726 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5727 {
5728 }
5729
5730 // Linear handler, the bsearch head compare is shorter
5731 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5732 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5733 // x86_patch(ins,target)
5734 //[1 + 5] x86_jump_mem(inst,mem)
5735
5736 #define CMP_SIZE 6
5737 #if defined(__default_codegen__)
5738 #define BR_SMALL_SIZE 2
5739 #define BR_LARGE_SIZE 5
5740 #elif defined(__native_client_codegen__)
5741 /* I suspect the size calculation below is actually incorrect. */
5742 /* TODO: fix the calculation that uses these sizes. */
5743 #define BR_SMALL_SIZE 16
5744 #define BR_LARGE_SIZE 12
5745 #endif /*__native_client_codegen__*/
5746 #define JUMP_IMM_SIZE 6
5747 #define ENABLE_WRONG_METHOD_CHECK 0
5748 #define DEBUG_IMT 0
5749
5750 static int
5751 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5752 {
5753 int i, distance = 0;
5754 for (i = start; i < target; ++i)
5755 distance += imt_entries [i]->chunk_size;
5756 return distance;
5757 }
5758
5759 /*
5760 * LOCKING: called with the domain lock held
5761 */
5762 gpointer
5763 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5764 gpointer fail_tramp)
5765 {
5766 int i;
5767 int size = 0;
5768 guint8 *code, *start;
5769
5770 for (i = 0; i < count; ++i) {
5771 MonoIMTCheckItem *item = imt_entries [i];
5772 if (item->is_equals) {
5773 if (item->check_target_idx) {
5774 if (!item->compare_done)
5775 item->chunk_size += CMP_SIZE;
5776 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5777 } else {
5778 if (fail_tramp) {
5779 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5780 } else {
5781 item->chunk_size += JUMP_IMM_SIZE;
5782 #if ENABLE_WRONG_METHOD_CHECK
5783 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5784 #endif
5785 }
5786 }
5787 } else {
5788 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5789 imt_entries [item->check_target_idx]->compare_done = TRUE;
5790 }
5791 size += item->chunk_size;
5792 }
5793 #if defined(__native_client__) && defined(__native_client_codegen__)
5794 /* In Native Client, we don't re-use thunks, allocate from the */
5795 /* normal code manager paths. */
5796 size = NACL_BUNDLE_ALIGN_UP (size);
5797 code = mono_domain_code_reserve (domain, size);
5798 #else
5799 if (fail_tramp)
5800 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5801 else
5802 code = mono_domain_code_reserve (domain, size);
5803 #endif
5804 start = code;
5805 for (i = 0; i < count; ++i) {
5806 MonoIMTCheckItem *item = imt_entries [i];
5807 item->code_target = code;
5808 if (item->is_equals) {
5809 if (item->check_target_idx) {
5810 if (!item->compare_done)
5811 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5812 item->jmp_code = code;
5813 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5814 if (item->has_target_code)
5815 x86_jump_code (code, item->value.target_code);
5816 else
5817 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5818 } else {
5819 if (fail_tramp) {
5820 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5821 item->jmp_code = code;
5822 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5823 if (item->has_target_code)
5824 x86_jump_code (code, item->value.target_code);
5825 else
5826 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5827 x86_patch (item->jmp_code, code);
5828 x86_jump_code (code, fail_tramp);
5829 item->jmp_code = NULL;
5830 } else {
5831 /* enable the commented code to assert on wrong method */
5832 #if ENABLE_WRONG_METHOD_CHECK
5833 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5834 item->jmp_code = code;
5835 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5836 #endif
5837 if (item->has_target_code)
5838 x86_jump_code (code, item->value.target_code);
5839 else
5840 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5841 #if ENABLE_WRONG_METHOD_CHECK
5842 x86_patch (item->jmp_code, code);
5843 x86_breakpoint (code);
5844 item->jmp_code = NULL;
5845 #endif
5846 }
5847 }
5848 } else {
5849 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5850 item->jmp_code = code;
5851 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5852 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5853 else
5854 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5855 }
5856 }
5857 /* patch the branches to get to the target items */
5858 for (i = 0; i < count; ++i) {
5859 MonoIMTCheckItem *item = imt_entries [i];
5860 if (item->jmp_code) {
5861 if (item->check_target_idx) {
5862 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5863 }
5864 }
5865 }
5866
5867 if (!fail_tramp)
5868 mono_stats.imt_thunks_size += code - start;
5869 g_assert (code - start <= size);
5870
5871 #if DEBUG_IMT
5872 {
5873 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5874 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5875 g_free (buff);
5876 }
5877 #endif
5878 if (mono_jit_map_is_enabled ()) {
5879 char *buff;
5880 if (vtable)
5881 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5882 else
5883 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5884 mono_emit_jit_tramp (start, code - start, buff);
5885 g_free (buff);
5886 }
5887
5888 nacl_domain_code_validate (domain, &start, size, &code);
5889 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5890
5891 return start;
5892 }
5893
5894 MonoMethod*
5895 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5896 {
5897 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5898 }
5899
5900 MonoVTable*
5901 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5902 {
5903 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5904 }
5905
5906 GSList*
5907 mono_arch_get_cie_program (void)
5908 {
5909 GSList *l = NULL;
5910
5911 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5912 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5913
5914 return l;
5915 }
5916
5917 MonoInst*
5918 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5919 {
5920 MonoInst *ins = NULL;
5921 int opcode = 0;
5922
5923 if (cmethod->klass == mono_defaults.math_class) {
5924 if (strcmp (cmethod->name, "Sin") == 0) {
5925 opcode = OP_SIN;
5926 } else if (strcmp (cmethod->name, "Cos") == 0) {
5927 opcode = OP_COS;
5928 } else if (strcmp (cmethod->name, "Tan") == 0) {
5929 opcode = OP_TAN;
5930 } else if (strcmp (cmethod->name, "Atan") == 0) {
5931 opcode = OP_ATAN;
5932 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5933 opcode = OP_SQRT;
5934 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5935 opcode = OP_ABS;
5936 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5937 opcode = OP_ROUND;
5938 }
5939
5940 if (opcode && fsig->param_count == 1) {
5941 MONO_INST_NEW (cfg, ins, opcode);
5942 ins->type = STACK_R8;
5943 ins->dreg = mono_alloc_freg (cfg);
5944 ins->sreg1 = args [0]->dreg;
5945 MONO_ADD_INS (cfg->cbb, ins);
5946 }
5947
5948 if (cfg->opt & MONO_OPT_CMOV) {
5949 opcode = 0;
5950
5951 if (strcmp (cmethod->name, "Min") == 0) {
5952 if (fsig->params [0]->type == MONO_TYPE_I4)
5953 opcode = OP_IMIN;
5954 } else if (strcmp (cmethod->name, "Max") == 0) {
5955 if (fsig->params [0]->type == MONO_TYPE_I4)
5956 opcode = OP_IMAX;
5957 }
5958
5959 if (opcode && fsig->param_count == 2) {
5960 MONO_INST_NEW (cfg, ins, opcode);
5961 ins->type = STACK_I4;
5962 ins->dreg = mono_alloc_ireg (cfg);
5963 ins->sreg1 = args [0]->dreg;
5964 ins->sreg2 = args [1]->dreg;
5965 MONO_ADD_INS (cfg->cbb, ins);
5966 }
5967 }
5968
5969 #if 0
5970 /* OP_FREM is not IEEE compatible */
5971 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5972 MONO_INST_NEW (cfg, ins, OP_FREM);
5973 ins->inst_i0 = args [0];
5974 ins->inst_i1 = args [1];
5975 }
5976 #endif
5977 }
5978
5979 return ins;
5980 }
5981
5982 gboolean
5983 mono_arch_print_tree (MonoInst *tree, int arity)
5984 {
5985 return 0;
5986 }
5987
5988 guint32
5989 mono_arch_get_patch_offset (guint8 *code)
5990 {
5991 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5992 return 2;
5993 else if (code [0] == 0xba)
5994 return 1;
5995 else if (code [0] == 0x68)
5996 /* push IMM */
5997 return 1;
5998 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5999 /* push <OFFSET>(<REG>) */
6000 return 2;
6001 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6002 /* call *<OFFSET>(<REG>) */
6003 return 2;
6004 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6005 /* fldl <ADDR> */
6006 return 2;
6007 else if ((code [0] == 0x58) && (code [1] == 0x05))
6008 /* pop %eax; add <OFFSET>, %eax */
6009 return 2;
6010 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6011 /* pop <REG>; add <OFFSET>, <REG> */
6012 return 3;
6013 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6014 /* mov <REG>, imm */
6015 return 1;
6016 else {
6017 g_assert_not_reached ();
6018 return -1;
6019 }
6020 }
6021
6022 /**
6023 * mono_breakpoint_clean_code:
6024 *
6025 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6026 * breakpoints in the original code, they are removed in the copy.
6027 *
6028 * Returns TRUE if no sw breakpoint was present.
6029 */
6030 gboolean
6031 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6032 {
6033 /*
6034 * If method_start is non-NULL we need to perform bound checks, since we access memory
6035 * at code - offset we could go before the start of the method and end up in a different
6036 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6037 * instead.
6038 */
6039 if (!method_start || code - offset >= method_start) {
6040 memcpy (buf, code - offset, size);
6041 } else {
6042 int diff = code - method_start;
6043 memset (buf, 0, size);
6044 memcpy (buf + offset - diff, method_start, diff + size - offset);
6045 }
6046 return TRUE;
6047 }
6048
6049 /*
6050 * mono_x86_get_this_arg_offset:
6051 *
6052 * Return the offset of the stack location where this is passed during a virtual
6053 * call.
6054 */
6055 guint32
6056 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6057 {
6058 return 0;
6059 }
6060
6061 gpointer
6062 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6063 {
6064 guint32 esp = regs [X86_ESP];
6065 gpointer res;
6066 int offset;
6067
6068 offset = 0;
6069
6070 /*
6071 * The stack looks like:
6072 * <other args>
6073 * <this=delegate>
6074 */
6075 res = ((MonoObject**)esp) [0];
6076 return res;
6077 }
6078
6079 #define MAX_ARCH_DELEGATE_PARAMS 10
6080
6081 static gpointer
6082 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6083 {
6084 guint8 *code, *start;
6085 int code_reserve = 64;
6086
6087 /*
6088 * The stack contains:
6089 * <delegate>
6090 * <return addr>
6091 */
6092
6093 if (has_target) {
6094 start = code = mono_global_codeman_reserve (code_reserve);
6095
6096 /* Replace the this argument with the target */
6097 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6098 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6099 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6100 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6101
6102 g_assert ((code - start) < code_reserve);
6103 } else {
6104 int i = 0;
6105 /* 8 for mov_reg and jump, plus 8 for each parameter */
6106 #ifdef __native_client_codegen__
6107 /* TODO: calculate this size correctly */
6108 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6109 #else
6110 code_reserve = 8 + (param_count * 8);
6111 #endif /* __native_client_codegen__ */
6112 /*
6113 * The stack contains:
6114 * <args in reverse order>
6115 * <delegate>
6116 * <return addr>
6117 *
6118 * and we need:
6119 * <args in reverse order>
6120 * <return addr>
6121 *
6122 * without unbalancing the stack.
6123 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6124 * and leaving original spot of first arg as placeholder in stack so
6125 * when callee pops stack everything works.
6126 */
6127
6128 start = code = mono_global_codeman_reserve (code_reserve);
6129
6130 /* store delegate for access to method_ptr */
6131 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6132
6133 /* move args up */
6134 for (i = 0; i < param_count; ++i) {
6135 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6136 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6137 }
6138
6139 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6140
6141 g_assert ((code - start) < code_reserve);
6142 }
6143
6144 nacl_global_codeman_validate (&start, code_reserve, &code);
6145
6146 if (code_len)
6147 *code_len = code - start;
6148
6149 if (mono_jit_map_is_enabled ()) {
6150 char *buff;
6151 if (has_target)
6152 buff = (char*)"delegate_invoke_has_target";
6153 else
6154 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6155 mono_emit_jit_tramp (start, code - start, buff);
6156 if (!has_target)
6157 g_free (buff);
6158 }
6159 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6160
6161 return start;
6162 }
6163
6164 GSList*
6165 mono_arch_get_delegate_invoke_impls (void)
6166 {
6167 GSList *res = NULL;
6168 guint8 *code;
6169 guint32 code_len;
6170 int i;
6171 char *tramp_name;
6172
6173 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6174 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6175
6176 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6177 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6178 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6179 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6180 g_free (tramp_name);
6181 }
6182
6183 return res;
6184 }
6185
6186 gpointer
6187 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6188 {
6189 guint8 *code, *start;
6190
6191 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6192 return NULL;
6193
6194 /* FIXME: Support more cases */
6195 if (MONO_TYPE_ISSTRUCT (sig->ret))
6196 return NULL;
6197
6198 /*
6199 * The stack contains:
6200 * <delegate>
6201 * <return addr>
6202 */
6203
6204 if (has_target) {
6205 static guint8* cached = NULL;
6206 if (cached)
6207 return cached;
6208
6209 if (mono_aot_only)
6210 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6211 else
6212 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6213
6214 mono_memory_barrier ();
6215
6216 cached = start;
6217 } else {
6218 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6219 int i = 0;
6220
6221 for (i = 0; i < sig->param_count; ++i)
6222 if (!mono_is_regsize_var (sig->params [i]))
6223 return NULL;
6224
6225 code = cache [sig->param_count];
6226 if (code)
6227 return code;
6228
6229 if (mono_aot_only) {
6230 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6231 start = mono_aot_get_trampoline (name);
6232 g_free (name);
6233 } else {
6234 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6235 }
6236
6237 mono_memory_barrier ();
6238
6239 cache [sig->param_count] = start;
6240 }
6241
6242 return start;
6243 }
6244
6245 gpointer
6246 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6247 {
6248 guint8 *code, *start;
6249 int size = 24;
6250
6251 /*
6252 * The stack contains:
6253 * <delegate>
6254 * <return addr>
6255 */
6256 start = code = mono_global_codeman_reserve (size);
6257
6258 /* Replace the this argument with the target */
6259 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6260 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6261 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6262
6263 if (load_imt_reg) {
6264 /* Load the IMT reg */
6265 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6266 }
6267
6268 /* Load the vtable */
6269 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6270 x86_jump_membase (code, X86_EAX, offset);
6271 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6272
6273 return start;
6274 }
6275
6276 mgreg_t
6277 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6278 {
6279 switch (reg) {
6280 case X86_EAX: return ctx->eax;
6281 case X86_EBX: return ctx->ebx;
6282 case X86_ECX: return ctx->ecx;
6283 case X86_EDX: return ctx->edx;
6284 case X86_ESP: return ctx->esp;
6285 case X86_EBP: return ctx->ebp;
6286 case X86_ESI: return ctx->esi;
6287 case X86_EDI: return ctx->edi;
6288 default:
6289 g_assert_not_reached ();
6290 return 0;
6291 }
6292 }
6293
6294 void
6295 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6296 {
6297 switch (reg) {
6298 case X86_EAX:
6299 ctx->eax = val;
6300 break;
6301 case X86_EBX:
6302 ctx->ebx = val;
6303 break;
6304 case X86_ECX:
6305 ctx->ecx = val;
6306 break;
6307 case X86_EDX:
6308 ctx->edx = val;
6309 break;
6310 case X86_ESP:
6311 ctx->esp = val;
6312 break;
6313 case X86_EBP:
6314 ctx->ebp = val;
6315 break;
6316 case X86_ESI:
6317 ctx->esi = val;
6318 break;
6319 case X86_EDI:
6320 ctx->edi = val;
6321 break;
6322 default:
6323 g_assert_not_reached ();
6324 }
6325 }
6326
6327 #ifdef MONO_ARCH_SIMD_INTRINSICS
6328
6329 static MonoInst*
6330 get_float_to_x_spill_area (MonoCompile *cfg)
6331 {
6332 if (!cfg->fconv_to_r8_x_var) {
6333 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6334 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6335 }
6336 return cfg->fconv_to_r8_x_var;
6337 }
6338
6339 /*
6340 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6341 */
6342 void
6343 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6344 {
6345 MonoInst *fconv;
6346 int dreg, src_opcode;
6347
6348 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6349 return;
6350
6351 switch (src_opcode = ins->opcode) {
6352 case OP_FCONV_TO_I1:
6353 case OP_FCONV_TO_U1:
6354 case OP_FCONV_TO_I2:
6355 case OP_FCONV_TO_U2:
6356 case OP_FCONV_TO_I4:
6357 case OP_FCONV_TO_I:
6358 break;
6359 default:
6360 return;
6361 }
6362
6363 /* dreg is the IREG and sreg1 is the FREG */
6364 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6365 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6366 fconv->sreg1 = ins->sreg1;
6367 fconv->dreg = mono_alloc_ireg (cfg);
6368 fconv->type = STACK_VTYPE;
6369 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6370
6371 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6372
6373 dreg = ins->dreg;
6374 NULLIFY_INS (ins);
6375 ins->opcode = OP_XCONV_R8_TO_I4;
6376
6377 ins->klass = mono_defaults.int32_class;
6378 ins->sreg1 = fconv->dreg;
6379 ins->dreg = dreg;
6380 ins->type = STACK_I4;
6381 ins->backend.source_opcode = src_opcode;
6382 }
6383
6384 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6385
6386 void
6387 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6388 {
6389 MonoInst *ins;
6390 int vreg;
6391
6392 if (long_ins->opcode == OP_LNEG) {
6393 ins = long_ins;
6394 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6395 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6396 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6397 NULLIFY_INS (ins);
6398 return;
6399 }
6400
6401 #ifdef MONO_ARCH_SIMD_INTRINSICS
6402
6403 if (!(cfg->opt & MONO_OPT_SIMD))
6404 return;
6405
6406 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6407 switch (long_ins->opcode) {
6408 case OP_EXTRACT_I8:
6409 vreg = long_ins->sreg1;
6410
6411 if (long_ins->inst_c0) {
6412 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6413 ins->klass = long_ins->klass;
6414 ins->sreg1 = long_ins->sreg1;
6415 ins->inst_c0 = 2;
6416 ins->type = STACK_VTYPE;
6417 ins->dreg = vreg = alloc_ireg (cfg);
6418 MONO_ADD_INS (cfg->cbb, ins);
6419 }
6420
6421 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6422 ins->klass = mono_defaults.int32_class;
6423 ins->sreg1 = vreg;
6424 ins->type = STACK_I4;
6425 ins->dreg = long_ins->dreg + 1;
6426 MONO_ADD_INS (cfg->cbb, ins);
6427
6428 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6429 ins->klass = long_ins->klass;
6430 ins->sreg1 = long_ins->sreg1;
6431 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6432 ins->type = STACK_VTYPE;
6433 ins->dreg = vreg = alloc_ireg (cfg);
6434 MONO_ADD_INS (cfg->cbb, ins);
6435
6436 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6437 ins->klass = mono_defaults.int32_class;
6438 ins->sreg1 = vreg;
6439 ins->type = STACK_I4;
6440 ins->dreg = long_ins->dreg + 2;
6441 MONO_ADD_INS (cfg->cbb, ins);
6442
6443 long_ins->opcode = OP_NOP;
6444 break;
6445 case OP_INSERTX_I8_SLOW:
6446 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6447 ins->dreg = long_ins->dreg;
6448 ins->sreg1 = long_ins->dreg;
6449 ins->sreg2 = long_ins->sreg2 + 1;
6450 ins->inst_c0 = long_ins->inst_c0 * 2;
6451 MONO_ADD_INS (cfg->cbb, ins);
6452
6453 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6454 ins->dreg = long_ins->dreg;
6455 ins->sreg1 = long_ins->dreg;
6456 ins->sreg2 = long_ins->sreg2 + 2;
6457 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6458 MONO_ADD_INS (cfg->cbb, ins);
6459
6460 long_ins->opcode = OP_NOP;
6461 break;
6462 case OP_EXPAND_I8:
6463 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6464 ins->dreg = long_ins->dreg;
6465 ins->sreg1 = long_ins->sreg1 + 1;
6466 ins->klass = long_ins->klass;
6467 ins->type = STACK_VTYPE;
6468 MONO_ADD_INS (cfg->cbb, ins);
6469
6470 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6471 ins->dreg = long_ins->dreg;
6472 ins->sreg1 = long_ins->dreg;
6473 ins->sreg2 = long_ins->sreg1 + 2;
6474 ins->inst_c0 = 1;
6475 ins->klass = long_ins->klass;
6476 ins->type = STACK_VTYPE;
6477 MONO_ADD_INS (cfg->cbb, ins);
6478
6479 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6480 ins->dreg = long_ins->dreg;
6481 ins->sreg1 = long_ins->dreg;;
6482 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6483 ins->klass = long_ins->klass;
6484 ins->type = STACK_VTYPE;
6485 MONO_ADD_INS (cfg->cbb, ins);
6486
6487 long_ins->opcode = OP_NOP;
6488 break;
6489 }
6490 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6491 }
6492
6493 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6494 gpointer
6495 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6496 {
6497 int offset;
6498 gpointer *sp, old_value;
6499 char *bp;
6500
6501 offset = clause->exvar_offset;
6502
6503 /*Load the spvar*/
6504 bp = MONO_CONTEXT_GET_BP (ctx);
6505 sp = *(gpointer*)(bp + offset);
6506
6507 old_value = *sp;
6508 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6509 return old_value;
6510
6511 *sp = new_value;
6512
6513 return old_value;
6514 }
6515
6516 /*
6517 * mono_aot_emit_load_got_addr:
6518 *
6519 * Emit code to load the got address.
6520 * On x86, the result is placed into EBX.
6521 */
6522 guint8*
6523 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6524 {
6525 x86_call_imm (code, 0);
6526 /*
6527 * The patch needs to point to the pop, since the GOT offset needs
6528 * to be added to that address.
6529 */
6530 if (cfg)
6531 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6532 else
6533 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6534 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6535 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6536
6537 return code;
6538 }
6539
6540 static guint8*
6541 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6542 {
6543 if (cfg)
6544 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6545 else
6546 g_assert_not_reached ();
6547 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6548 return code;
6549 }
6550
6551 /*
6552 * mono_arch_emit_load_aotconst:
6553 *
6554 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6555 * TARGET from the mscorlib GOT in full-aot code.
6556 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6557 * EAX.
6558 */
6559 guint8*
6560 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6561 {
6562 /* Load the mscorlib got address */
6563 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6564 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6565 /* arch_emit_got_access () patches this */
6566 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6567
6568 return code;
6569 }
6570
6571 /* Can't put this into mini-x86.h */
6572 gpointer
6573 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6574
6575 GSList *
6576 mono_arch_get_trampolines (gboolean aot)
6577 {
6578 MonoTrampInfo *info;
6579 GSList *tramps = NULL;
6580
6581 mono_x86_get_signal_exception_trampoline (&info, aot);
6582
6583 tramps = g_slist_append (tramps, info);
6584
6585 return tramps;
6586 }
6587
6588
6589 #if __APPLE__
6590 #define DBG_SIGNAL SIGBUS
6591 #else
6592 #define DBG_SIGNAL SIGSEGV
6593 #endif
6594
6595 /* Soft Debug support */
6596 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6597
6598 /*
6599 * mono_arch_set_breakpoint:
6600 *
6601 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6602 * The location should contain code emitted by OP_SEQ_POINT.
6603 */
6604 void
6605 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6606 {
6607 guint8 *code = ip;
6608
6609 /*
6610 * In production, we will use int3 (has to fix the size in the md
6611 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6612 * instead.
6613 */
6614 g_assert (code [0] == 0x90);
6615 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6616 }
6617
6618 /*
6619 * mono_arch_clear_breakpoint:
6620 *
6621 * Clear the breakpoint at IP.
6622 */
6623 void
6624 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6625 {
6626 guint8 *code = ip;
6627 int i;
6628
6629 for (i = 0; i < 6; ++i)
6630 x86_nop (code);
6631 }
6632
6633 /*
6634 * mono_arch_start_single_stepping:
6635 *
6636 * Start single stepping.
6637 */
6638 void
6639 mono_arch_start_single_stepping (void)
6640 {
6641 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6642 }
6643
6644 /*
6645 * mono_arch_stop_single_stepping:
6646 *
6647 * Stop single stepping.
6648 */
6649 void
6650 mono_arch_stop_single_stepping (void)
6651 {
6652 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6653 }
6654
6655 /*
6656 * mono_arch_is_single_step_event:
6657 *
6658 * Return whenever the machine state in SIGCTX corresponds to a single
6659 * step event.
6660 */
6661 gboolean
6662 mono_arch_is_single_step_event (void *info, void *sigctx)
6663 {
6664 #ifdef TARGET_WIN32
6665 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6666
6667 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6668 return TRUE;
6669 else
6670 return FALSE;
6671 #else
6672 siginfo_t* sinfo = (siginfo_t*) info;
6673 /* Sometimes the address is off by 4 */
6674 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6675 return TRUE;
6676 else
6677 return FALSE;
6678 #endif
6679 }
6680
6681 gboolean
6682 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6683 {
6684 #ifdef TARGET_WIN32
6685 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6686 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6687 return TRUE;
6688 else
6689 return FALSE;
6690 #else
6691 siginfo_t* sinfo = (siginfo_t*)info;
6692 /* Sometimes the address is off by 4 */
6693 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6694 return TRUE;
6695 else
6696 return FALSE;
6697 #endif
6698 }
6699
6700 #define BREAKPOINT_SIZE 6
6701
6702 /*
6703 * mono_arch_skip_breakpoint:
6704 *
6705 * See mini-amd64.c for docs.
6706 */
6707 void
6708 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6709 {
6710 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6711 }
6712
6713 /*
6714 * mono_arch_skip_single_step:
6715 *
6716 * See mini-amd64.c for docs.
6717 */
6718 void
6719 mono_arch_skip_single_step (MonoContext *ctx)
6720 {
6721 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6722 }
6723
6724 /*
6725 * mono_arch_get_seq_point_info:
6726 *
6727 * See mini-amd64.c for docs.
6728 */
6729 gpointer
6730 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6731 {
6732 NOT_IMPLEMENTED;
6733 return NULL;
6734 }
6735
6736 void
6737 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6738 {
6739 ext->lmf.previous_lmf = (gsize)prev_lmf;
6740 /* Mark that this is a MonoLMFExt */
6741 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6742 ext->lmf.ebp = (gssize)ext;
6743 }
6744
6745 #endif
6746
6747 gboolean
6748 mono_arch_opcode_supported (int opcode)
6749 {
6750 switch (opcode) {
6751 case OP_ATOMIC_ADD_I4:
6752 case OP_ATOMIC_EXCHANGE_I4:
6753 case OP_ATOMIC_CAS_I4:
6754 case OP_ATOMIC_LOAD_I1:
6755 case OP_ATOMIC_LOAD_I2:
6756 case OP_ATOMIC_LOAD_I4:
6757 case OP_ATOMIC_LOAD_U1:
6758 case OP_ATOMIC_LOAD_U2:
6759 case OP_ATOMIC_LOAD_U4:
6760 case OP_ATOMIC_LOAD_R4:
6761 case OP_ATOMIC_LOAD_R8:
6762 case OP_ATOMIC_STORE_I1:
6763 case OP_ATOMIC_STORE_I2:
6764 case OP_ATOMIC_STORE_I4:
6765 case OP_ATOMIC_STORE_U1:
6766 case OP_ATOMIC_STORE_U2:
6767 case OP_ATOMIC_STORE_U4:
6768 case OP_ATOMIC_STORE_R4:
6769 case OP_ATOMIC_STORE_R8:
6770 return TRUE;
6771 default:
6772 return FALSE;
6773 }
6774 }
6775
6776 #if defined(ENABLE_GSHAREDVT)
6777
6778 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6779
6780 #endif /* !MONOTOUCH */
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