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1 # Copyright 2003-2011 Novell, Inc (http://www.novell.com)
2 # Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
3 # Licensed under the MIT license. See LICENSE file in the project root for full license information.
4 # arm cpu description file
5 # this file is read by genmdesc to pruduce a table with all the relevant information
6 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
7 # and other parts of the arch-dependent part of mini.
8 #
9 # An opcode name is followed by a colon and optional specifiers.
10 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
11 # Here is a description of the specifiers valid for this file and their possible values.
12 #
13 # dest:register describes the destination register of an instruction
14 # src1:register describes the first source register of an instruction
15 # src2:register describes the second source register of an instruction
16 #
17 # register may have the following values:
18 # i integer register
19 # a r0 register (first argument/result reg)
20 # b base register (used in address references)
21 # f floating point register
22 # g floating point register returned in r0:r1 for soft-float mode
23 #
24 # len:number describe the maximun length in bytes of the instruction
25 # number is a positive integer
26 #
27 # cost:number describe how many cycles are needed to complete the instruction (unused)
28 #
29 # clob:spec describe if the instruction clobbers registers or has special needs
30 #
31 # spec can be one of the following characters:
32 # c clobbers caller-save registers
33 # r 'reserves' the destination register until a later instruction unreserves it
34 # used mostly to set output registers in function calls
35 #
36 # flags:spec describe if the instruction uses or sets the flags (unused)
37 #
38 # spec can be one of the following chars:
39 # s sets the flags
40 # u uses the flags
41 # m uses and modifies the flags
42 #
43 # res:spec describe what units are used in the processor (unused)
44 #
45 # delay: describe delay slots (unused)
46 #
47 # the required specifiers are: len, clob (if registers are clobbered), the registers
48 # specifiers if the registers are actually used, flags (when scheduling is implemented).
49 #
50 # See the code in mini-x86.c for more details on how the specifiers are used.
51 #
52 nop: len:4
53 relaxed_nop: len:4
54 break: len:4
55 br: len:16
56 switch: src1:i len:12
57 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
58 # since the corresponding sigctx structures are not well defined.
59 seq_point: len:52 clob:c
60 il_seq_point: len:0
62 throw: src1:i len:24
63 rethrow: src1:i len:20
64 start_handler: len:20
65 endfinally: len:32
66 call_handler: len:16 clob:c
67 endfilter: src1:i len:16
68 get_ex_obj: dest:i len:16
70 ckfinite: dest:f src1:f len:112
71 ceq: dest:i len:12
72 cgt: dest:i len:12
73 cgt_un: dest:i len:12
74 clt: dest:i len:12
75 clt_un: dest:i len:12
76 localloc: dest:i src1:i len:60
77 compare: src1:i src2:i len:4
78 compare_imm: src1:i len:12
79 fcompare: src1:f src2:f len:12
80 rcompare: src1:f src2:f len:12
81 arglist: src1:i len:12
82 setlret: src1:i src2:i len:12
83 check_this: src1:b len:4
84 call: dest:a clob:c len:20
85 call_reg: dest:a src1:i len:8 clob:c
86 call_membase: dest:a src1:b len:30 clob:c
87 voidcall: len:20 clob:c
88 voidcall_reg: src1:i len:8 clob:c
89 voidcall_membase: src1:b len:24 clob:c
90 fcall: dest:g len:28 clob:c
91 fcall_reg: dest:g src1:i len:16 clob:c
92 fcall_membase: dest:g src1:b len:30 clob:c
93 rcall: dest:g len:28 clob:c
94 rcall_reg: dest:g src1:i len:16 clob:c
95 rcall_membase: dest:g src1:b len:30 clob:c
96 lcall: dest:l len:20 clob:c
97 lcall_reg: dest:l src1:i len:8 clob:c
98 lcall_membase: dest:l src1:b len:24 clob:c
99 vcall: len:64 clob:c
100 vcall_reg: src1:i len:64 clob:c
101 vcall_membase: src1:b len:70 clob:c
103 tailcall: len:255 clob:c # FIXME len
104 tailcall_membase: src1:b len:255 clob:c # FIXME len
105 tailcall_reg: src1:b len:255 clob:c # FIXME len
107 # tailcall_parameter models the size of moving one parameter,
108 # so that the required size of a branch around a tailcall can
109 # be accurately estimated; something like:
110 # void f1(volatile long *a)
111 # {
112 # a[large] = a[another large]
113 # }
114 #
115 # In current implementation with 4K limit this is typically
116 # two full instructions, howevever raising the limit some
117 # can lead two instructions and two thumb instructions.
118 # FIXME A fixed size sequence to move parameters would moot this.
119 tailcall_parameter: len:12
121 iconst: dest:i len:16
122 r4const: dest:f len:24
123 r8const: dest:f len:20
124 label: len:0
125 store_membase_imm: dest:b len:20
126 store_membase_reg: dest:b src1:i len:20
127 storei1_membase_imm: dest:b len:20
128 storei1_membase_reg: dest:b src1:i len:12
129 storei2_membase_imm: dest:b len:20
130 storei2_membase_reg: dest:b src1:i len:12
131 storei4_membase_imm: dest:b len:20
132 storei4_membase_reg: dest:b src1:i len:20
133 storei8_membase_imm: dest:b
134 storei8_membase_reg: dest:b src1:i
135 storer4_membase_reg: dest:b src1:f len:60
136 storer8_membase_reg: dest:b src1:f len:24
137 store_memindex: dest:b src1:i src2:i len:4
138 storei1_memindex: dest:b src1:i src2:i len:4
139 storei2_memindex: dest:b src1:i src2:i len:4
140 storei4_memindex: dest:b src1:i src2:i len:4
141 load_membase: dest:i src1:b len:20
142 loadi1_membase: dest:i src1:b len:4
143 loadu1_membase: dest:i src1:b len:4
144 loadi2_membase: dest:i src1:b len:4
145 loadu2_membase: dest:i src1:b len:4
146 loadi4_membase: dest:i src1:b len:4
147 loadu4_membase: dest:i src1:b len:4
148 loadi8_membase: dest:i src1:b
149 loadr4_membase: dest:f src1:b len:56
150 loadr8_membase: dest:f src1:b len:24
151 load_memindex: dest:i src1:b src2:i len:4
152 loadi1_memindex: dest:i src1:b src2:i len:4
153 loadu1_memindex: dest:i src1:b src2:i len:4
154 loadi2_memindex: dest:i src1:b src2:i len:4
155 loadu2_memindex: dest:i src1:b src2:i len:4
156 loadi4_memindex: dest:i src1:b src2:i len:4
157 loadu4_memindex: dest:i src1:b src2:i len:4
158 loadu4_mem: dest:i len:8
159 move: dest:i src1:i len:4
160 fmove: dest:f src1:f len:4
161 move_f_to_i4: dest:i src1:f len:28
162 move_i4_to_f: dest:f src1:i len:8
163 add_imm: dest:i src1:i len:12
164 sub_imm: dest:i src1:i len:12
165 mul_imm: dest:i src1:i len:12
166 and_imm: dest:i src1:i len:12
167 or_imm: dest:i src1:i len:12
168 xor_imm: dest:i src1:i len:12
169 shl_imm: dest:i src1:i len:8
170 shr_imm: dest:i src1:i len:8
171 shr_un_imm: dest:i src1:i len:8
172 cond_exc_eq: len:8
173 cond_exc_ne_un: len:8
174 cond_exc_lt: len:8
175 cond_exc_lt_un: len:8
176 cond_exc_gt: len:8
177 cond_exc_gt_un: len:8
178 cond_exc_ge: len:8
179 cond_exc_ge_un: len:8
180 cond_exc_le: len:8
181 cond_exc_le_un: len:8
182 cond_exc_ov: len:12
183 cond_exc_no: len:8
184 cond_exc_c: len:12
185 cond_exc_nc: len:8
186 #float_beq: src1:f src2:f len:20
187 #float_bne_un: src1:f src2:f len:20
188 #float_blt: src1:f src2:f len:20
189 #float_blt_un: src1:f src2:f len:20
190 #float_bgt: src1:f src2:f len:20
191 #float_bgt_un: src1:f src2:f len:20
192 #float_bge: src1:f src2:f len:20
193 #float_bge_un: src1:f src2:f len:20
194 #float_ble: src1:f src2:f len:20
195 #float_ble_un: src1:f src2:f len:20
196 float_add: dest:f src1:f src2:f len:4
197 float_sub: dest:f src1:f src2:f len:4
198 float_mul: dest:f src1:f src2:f len:4
199 float_div: dest:f src1:f src2:f len:4
200 float_div_un: dest:f src1:f src2:f len:4
201 float_rem: dest:f src1:f src2:f len:16
202 float_rem_un: dest:f src1:f src2:f len:16
203 float_neg: dest:f src1:f len:4
204 float_not: dest:f src1:f len:4
205 float_conv_to_i1: dest:i src1:f len:88
206 float_conv_to_i2: dest:i src1:f len:88
207 float_conv_to_i4: dest:i src1:f len:88
208 float_conv_to_i8: dest:l src1:f len:88
209 float_conv_to_r4: dest:f src1:f len:8
210 float_conv_to_u4: dest:i src1:f len:88
211 float_conv_to_u8: dest:l src1:f len:88
212 float_conv_to_u2: dest:i src1:f len:88
213 float_conv_to_u1: dest:i src1:f len:88
214 float_conv_to_i: dest:i src1:f len:40
215 float_ceq: dest:i src1:f src2:f len:16
216 float_cgt: dest:i src1:f src2:f len:16
217 float_cgt_un: dest:i src1:f src2:f len:20
218 float_clt: dest:i src1:f src2:f len:16
219 float_clt_un: dest:i src1:f src2:f len:20
220 float_cneq: dest:y src1:f src2:f len:20
221 float_cge: dest:y src1:f src2:f len:20
222 float_cle: dest:y src1:f src2:f len:20
223 float_conv_to_u: dest:i src1:f len:36
225 # R4 opcodes
226 rmove: dest:f src1:f len:4
227 r4_conv_to_i1: dest:i src1:f len:88
228 r4_conv_to_i2: dest:i src1:f len:88
229 r4_conv_to_i4: dest:i src1:f len:88
230 r4_conv_to_u1: dest:i src1:f len:88
231 r4_conv_to_u2: dest:i src1:f len:88
232 r4_conv_to_u4: dest:i src1:f len:88
233 r4_conv_to_r4: dest:f src1:f len:16
234 r4_conv_to_r8: dest:f src1:f len:16
235 r4_add: dest:f src1:f src2:f len:4
236 r4_sub: dest:f src1:f src2:f len:4
237 r4_mul: dest:f src1:f src2:f len:4
238 r4_div: dest:f src1:f src2:f len:4
239 r4_rem: dest:f src1:f src2:f len:16
240 r4_neg: dest:f src1:f len:4
241 r4_ceq: dest:i src1:f src2:f len:16
242 r4_cgt: dest:i src1:f src2:f len:16
243 r4_cgt_un: dest:i src1:f src2:f len:20
244 r4_clt: dest:i src1:f src2:f len:16
245 r4_clt_un: dest:i src1:f src2:f len:20
246 r4_cneq: dest:y src1:f src2:f len:20
247 r4_cge: dest:y src1:f src2:f len:20
248 r4_cle: dest:y src1:f src2:f len:20
250 setfret: src1:f len:12
251 aotconst: dest:i len:16
252 objc_get_selector: dest:i len:32
253 sqrt: dest:f src1:f len:4
254 adc: dest:i src1:i src2:i len:4
255 addcc: dest:i src1:i src2:i len:4
256 subcc: dest:i src1:i src2:i len:4
257 adc_imm: dest:i src1:i len:12
258 addcc_imm: dest:i src1:i len:12
259 subcc_imm: dest:i src1:i len:12
260 sbb: dest:i src1:i src2:i len:4
261 sbb_imm: dest:i src1:i len:12
262 br_reg: src1:i len:8
263 bigmul: len:8 dest:l src1:i src2:i
264 bigmul_un: len:8 dest:l src1:i src2:i
265 tls_get: len:16 dest:i
266 tls_set: len:16 src1:i clob:c
268 # 32 bit opcodes
269 int_add: dest:i src1:i src2:i len:4
270 int_sub: dest:i src1:i src2:i len:4
271 int_mul: dest:i src1:i src2:i len:4
272 int_div: dest:i src1:i src2:i len:4
273 int_div_un: dest:i src1:i src2:i len:4
274 int_rem: dest:i src1:i src2:i len:8
275 int_rem_un: dest:i src1:i src2:i len:8
276 int_and: dest:i src1:i src2:i len:4
277 int_or: dest:i src1:i src2:i len:4
278 int_xor: dest:i src1:i src2:i len:4
279 int_shl: dest:i src1:i src2:i len:4
280 int_shr: dest:i src1:i src2:i len:4
281 int_shr_un: dest:i src1:i src2:i len:4
282 int_neg: dest:i src1:i len:4
283 int_not: dest:i src1:i len:4
284 int_conv_to_i1: dest:i src1:i len:8
285 int_conv_to_i2: dest:i src1:i len:8
286 int_conv_to_i4: dest:i src1:i len:4
287 int_conv_to_r4: dest:f src1:i len:84
288 int_conv_to_r8: dest:f src1:i len:84
289 int_conv_to_u4: dest:i src1:i
290 int_conv_to_r_un: dest:f src1:i len:56
291 int_conv_to_u2: dest:i src1:i len:8
292 int_conv_to_u1: dest:i src1:i len:4
293 int_beq: len:16
294 int_bge: len:16
295 int_bgt: len:16
296 int_ble: len:16
297 int_blt: len:16
298 int_bne_un: len:16
299 int_bge_un: len:16
300 int_bgt_un: len:16
301 int_ble_un: len:16
302 int_blt_un: len:16
303 int_add_ovf: dest:i src1:i src2:i len:16
304 int_add_ovf_un: dest:i src1:i src2:i len:16
305 int_mul_ovf: dest:i src1:i src2:i len:16
306 int_mul_ovf_un: dest:i src1:i src2:i len:16
307 int_sub_ovf: dest:i src1:i src2:i len:16
308 int_sub_ovf_un: dest:i src1:i src2:i len:16
309 add_ovf_carry: dest:i src1:i src2:i len:16
310 sub_ovf_carry: dest:i src1:i src2:i len:16
311 add_ovf_un_carry: dest:i src1:i src2:i len:16
312 sub_ovf_un_carry: dest:i src1:i src2:i len:16
314 arm_rsbs_imm: dest:i src1:i len:4
315 arm_rsc_imm: dest:i src1:i len:4
317 # Linear IR opcodes
318 dummy_use: src1:i len:0
319 dummy_iconst: dest:i len:0
320 dummy_r8const: dest:f len:0
321 dummy_r4const: dest:f len:0
322 not_reached: len:0
323 not_null: src1:i len:0
325 int_adc: dest:i src1:i src2:i len:4
326 int_addcc: dest:i src1:i src2:i len:4
327 int_subcc: dest:i src1:i src2:i len:4
328 int_sbb: dest:i src1:i src2:i len:4
329 int_adc_imm: dest:i src1:i len:12
330 int_sbb_imm: dest:i src1:i len:12
332 int_add_imm: dest:i src1:i len:12
333 int_sub_imm: dest:i src1:i len:12
334 int_mul_imm: dest:i src1:i len:12
335 int_div_imm: dest:i src1:i len:20
336 int_div_un_imm: dest:i src1:i len:12
337 int_rem_imm: dest:i src1:i len:28
338 int_rem_un_imm: dest:i src1:i len:16
339 int_and_imm: dest:i src1:i len:12
340 int_or_imm: dest:i src1:i len:12
341 int_xor_imm: dest:i src1:i len:12
342 int_shl_imm: dest:i src1:i len:8
343 int_shr_imm: dest:i src1:i len:8
344 int_shr_un_imm: dest:i src1:i len:8
346 int_ceq: dest:i len:12
347 int_cgt: dest:i len:12
348 int_cgt_un: dest:i len:12
349 int_clt: dest:i len:12
350 int_clt_un: dest:i len:12
352 int_cneq: dest:i len:12
353 int_cge: dest:i len:12
354 int_cle: dest:i len:12
355 int_cge_un: dest:i len:12
356 int_cle_un: dest:i len:12
358 cond_exc_ieq: len:16
359 cond_exc_ine_un: len:16
360 cond_exc_ilt: len:16
361 cond_exc_ilt_un: len:16
362 cond_exc_igt: len:16
363 cond_exc_igt_un: len:16
364 cond_exc_ige: len:16
365 cond_exc_ige_un: len:16
366 cond_exc_ile: len:16
367 cond_exc_ile_un: len:16
368 cond_exc_iov: len:20
369 cond_exc_ino: len:16
370 cond_exc_ic: len:20
371 cond_exc_inc: len:16
373 icompare: src1:i src2:i len:4
374 icompare_imm: src1:i len:12
376 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
378 vcall2: len:64 clob:c
379 vcall2_reg: src1:i len:64 clob:c
380 vcall2_membase: src1:b len:64 clob:c
381 dyn_call: src1:i src2:i len:252 clob:c
383 # This is different from the original JIT opcodes
384 float_beq: len:32
385 float_bne_un: len:32
386 float_blt: len:32
387 float_blt_un: len:32
388 float_bgt: len:32
389 float_bgt_un: len:32
390 float_bge: len:32
391 float_bge_un: len:32
392 float_ble: len:32
393 float_ble_un: len:32
395 liverange_start: len:0
396 liverange_end: len:0
397 gc_liveness_def: len:0
398 gc_liveness_use: len:0
399 gc_spill_slot_liveness_def: len:0
400 gc_param_slot_liveness_def: len:0
401 gc_safe_point: clob:c src1:i len:40
403 atomic_add_i4: dest:i src1:i src2:i len:64
404 atomic_exchange_i4: dest:i src1:i src2:i len:64
405 atomic_cas_i4: dest:i src1:i src2:i src3:i len:64
406 memory_barrier: len:8 clob:a
407 atomic_load_i1: dest:i src1:b len:28
408 atomic_load_u1: dest:i src1:b len:28
409 atomic_load_i2: dest:i src1:b len:28
410 atomic_load_u2: dest:i src1:b len:28
411 atomic_load_i4: dest:i src1:b len:28
412 atomic_load_u4: dest:i src1:b len:28
413 atomic_load_r4: dest:f src1:b len:80
414 atomic_load_r8: dest:f src1:b len:32
415 atomic_store_i1: dest:b src1:i len:28
416 atomic_store_u1: dest:b src1:i len:28
417 atomic_store_i2: dest:b src1:i len:28
418 atomic_store_u2: dest:b src1:i len:28
419 atomic_store_i4: dest:b src1:i len:28
420 atomic_store_u4: dest:b src1:i len:28
421 atomic_store_r4: dest:b src1:f len:80
422 atomic_store_r8: dest:b src1:f len:32
424 generic_class_init: src1:a len:44 clob:c
426 fill_prof_call_ctx: src1:i len:128