| blob | 2e25c13875789004607eb65de1fad3a21d3d1e2c |
1 /**
2 * \file
3 * AMD64 backend for the Mono code generator
4 *
5 * Based on mini-x86.c.
6 *
7 * Authors:
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
10 * Patrik Torstensson
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
13 *
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
18 */
20 #include <string.h>
21 #include <math.h>
22 #include <assert.h>
23 #ifdef HAVE_UNISTD_H
24 #include <unistd.h>
25 #endif
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
40 #include <mono/utils/unlocked.h>
52 #ifdef MONO_XEN_OPT
54 #else
55 #define optimize_for_xen 0
56 #endif
61 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
63 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
65 /* The single step trampoline */
68 /* The breakpoint trampoline */
71 /* Offset between fp and the first argument in the callee */
72 #define ARGS_OFFSET 16
73 #define GP_SCRATCH_REG AMD64_R11
75 /* Max number of bblocks before we bail from using more advanced branch placement code */
76 #define MAX_BBLOCKS_FOR_BRANCH_OPTS 800
78 /*
79 * AMD64 register usage:
80 * - callee saved registers are used for global register allocation
81 * - %r11 is used for materializing 64 bit constants in opcodes
82 * - the rest is used for local allocation
83 */
85 /*
86 * Floating point comparison results:
87 * ZF PF CF
88 * A > B 0 0 0
89 * A < B 0 0 1
90 * A = B 1 0 0
91 * A > B 0 0 0
92 * UNORDERED 1 1 1
93 */
97 {
115 }
117 }
122 };
127 };
131 {
134 else
136 }
140 {
143 else
145 }
147 static gboolean
149 {
150 #if 0
152 #else
154 #endif
155 }
157 static gboolean
159 {
160 /* Skip REX */
165 }
167 static gboolean
169 {
174 }
176 void
178 {
180 }
182 static void
184 {
185 // NOTE: Sometimes code has just been generated, is not running yet,
186 // and has no alignment requirements. Sometimes it could be running while we patch it,
187 // and there are alignment requirements.
188 // FIXME Assert alignment.
192 /* Skip REX */
196 }
199 /* amd64_set_reg_template */
201 }
202 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
203 /* mov 0(%rip), %dreg */
208 }
210 /* call or jmp *<OFFSET>(%rip) */
211 // Patch the data, not the code.
214 }
215 else
217 }
219 void
221 {
223 }
225 #define DEBUG(a) if (cfg->verbose_level > 1) a
229 {
235 /* Since the same stack slot size is used for all arg */
236 /* types, it needs to be big enough to hold them all */
238 }
243 }
244 }
248 {
254 /* Since the same stack slot size is used for both float */
255 /* types, it needs to be big enough to hold them both */
257 }
259 /* A double register */
262 else
266 }
267 }
270 ARG_CLASS_NO_CLASS,
271 ARG_CLASS_MEMORY,
272 ARG_CLASS_INTEGER,
273 ARG_CLASS_SSE
276 static ArgumentClass
278 {
301 #ifdef TARGET_WIN32
303 #else
305 #endif
315 }
316 /* fall through */
324 }
326 }
329 }
331 /* Merge */
333 ;
340 else
344 }
351 /*
352 * collect_field_info_nested:
353 *
354 * Collect field info from KLASS recursively into FIELDS.
355 */
356 static void
357 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
358 {
367 collect_field_info_nested (mono_class_from_mono_type_internal (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
369 guint32 align;
370 StructFieldInfo f;
378 /* This can happen with .pack directives eg. 'fixed' arrays */
380 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
385 }
389 }
392 }
393 }
394 }
396 gpointer iter;
404 collect_field_info_nested (mono_class_from_mono_type_internal (field->type), fields_array, field->offset - MONO_ABI_SIZEOF (MonoObject), pinvoke, unicode);
407 StructFieldInfo f;
414 }
415 }
416 }
417 }
419 #ifdef TARGET_WIN32
421 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
422 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
424 static gboolean
425 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, const AMD64_Reg_No int_regs [], int int_reg_count, const AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
426 {
429 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
439 /* Pass parameter in integer register. */
445 /* Pass parameter in float register. */
446 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
450 }
455 }
458 }
460 static gboolean
461 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
462 {
463 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
464 }
466 static gboolean
467 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
468 {
469 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
470 }
472 static void
473 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
475 {
476 /* Windows x64 value type ABI.
477 *
478 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
479 *
480 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
481 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
482 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
483 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
484 *
485 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
486 *
487 * Integers/Float types smaller than or equal to 8 bytes
488 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
489 * Properly sized struct/unions (1,2,4,8)
490 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
491 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
492 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
493 */
495 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
499 /* Parameter cases. */
503 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
505 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
506 /* No more registers, fallback passing parameter on stack as value. */
507 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
509 /* Passing value directly on stack, so use size of value. */
515 }
517 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
519 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
520 /* No more registers, fallback passing address to parameter on stack. */
521 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
523 /* Passing an address to value on stack, so use size of register as argument size. */
529 }
530 }
532 /* Return value cases. */
536 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
538 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
540 /* Only RAX/XMM0 should be used to return valuetype. */
541 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
543 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
545 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
547 /* Only RAX should be used to return valuetype address. */
553 }
554 }
555 }
557 static void
558 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
559 {
563 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
566 /* Calculate argument class type and size of marshalled type. */
570 /* Calculate argument class type and size of managed type. */
572 }
574 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
578 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
580 }
582 /*
583 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
584 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
585 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
586 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
587 * it must be represented in call and cannot be dropped.
588 */
593 }
596 }
598 static void
601 {
604 ArgumentClass arg_class;
606 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
611 /* Only drop value type if its not an empty struct as input that must be represented in call */
612 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_info->pass_empty_struct && is_return)) {
616 /* Alocate storage for value type. */
617 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
618 }
619 }
623 static void
625 gboolean is_return,
627 {
628 #ifdef TARGET_WIN32
630 #else
632 /* Keep track of the size used in each quad so we can */
633 /* use the right size when copying args/return vars. */
646 /* We pass and return vtypes of size 8 in a register */
649 }
651 /* If this struct can't be split up naturally into 8-byte */
652 /* chunks (registers), pass it on the stack. */
659 }
660 /*
661 * Collect field information recursively to be able to
662 * handle nested structures.
663 */
673 }
674 }
680 }
683 /* Allways pass in memory */
692 }
696 else
705 /* Always pass in 1 or 2 integer registers */
708 /* Only the simplest cases are supported */
712 }
714 /*
715 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
716 * The X87 and SSEUP stuff is left out since there are no such types in
717 * the CLR.
718 */
723 }
734 }
739 ArgumentClass class1;
743 else
747 /* Unaligned field */
748 NOT_IMPLEMENTED;
749 }
751 /* Skip fields in other quad */
757 /* How far into this quad this data extends.*/
758 /* (8 is size of quad) */
762 }
763 /* Empty structs have a nonzero size, causing this assert to be hit */
767 }
768 }
772 /* Post merger cleanup */
776 /* Allocate registers */
777 {
783 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
802 else
805 }
816 }
824 }
825 }
829 /* Revert possible register assignments */
836 else
842 }
843 }
845 }
847 /*
848 * get_call_info:
849 *
850 * Obtain information about a call according to the calling convention.
851 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
852 * Draft Version 0.23" document for more information.
853 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
854 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
855 */
858 {
868 else
877 #ifdef TARGET_WIN32
878 /* Reserve space where the callee can save the argument registers */
880 #endif
882 /* return value */
917 }
921 }
922 /* fall through */
930 }
940 }
943 /*
944 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
945 * the first argument, allowing 'this' to be always passed in the first arg reg.
946 * Also do this if the first argument is a reference type, since virtual calls
947 * are sometimes made using calli without sig->hasthis set, like in the delegate
948 * invoke wrappers.
949 */
951 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
957 }
962 /* this */
969 }
970 }
976 /* Emit the signature cookie just before the implicit arguments */
978 }
984 #ifdef TARGET_WIN32
985 /* The float param registers and other param registers must be the same index on Windows x64.*/
990 #endif
993 /* We allways pass the sig cookie on the stack for simplicity */
994 /*
995 * Prevent implicit arguments + the sig cookie from being passed
996 * in registers.
997 */
1001 /* Emit the signature cookie just before the implicit arguments */
1003 }
1036 }
1038 /* gsharedvt arguments are passed by ref */
1042 else
1045 }
1046 /* fall through */
1064 /* gsharedvt arguments are passed by ref */
1069 else
1074 }
1075 }
1077 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1081 /* Emit the signature cookie just before the implicit arguments */
1083 }
1089 }
1091 static int
1093 {
1094 // Value types using one register doesn't need temp.
1098 }
1100 static gpointer
1102 {
1113 // Empty struct
1116 // Value type using one register can be stored
1117 // directly in its context gregs/fregs slot.
1127 }
1133 }
1134 }
1136 static void
1138 {
1142 /* Reconstruct the value type */
1156 }
1157 dest_cast++;
1158 }
1159 }
1161 static void
1163 {
1180 }
1181 src_cast++;
1182 }
1183 }
1185 void
1186 mono_arch_set_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1187 {
1190 gpointer storage;
1204 }
1205 }
1216 }
1222 else
1228 }
1231 }
1233 void
1234 mono_arch_set_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig, gpointer retp)
1235 {
1238 gpointer storage;
1251 #ifdef TARGET_WIN32
1252 // Windows x64 ABI ainfo implementation includes info on how to return value type address.
1253 // back to caller.
1256 #endif
1263 else
1269 }
1272 }
1274 gpointer
1275 mono_arch_get_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1276 {
1279 gpointer storage;
1289 }
1298 }
1301 }
1308 }
1311 }
1313 void
1314 mono_arch_get_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1315 {
1319 gpointer storage;
1321 /* No return value */
1329 /* The return values were stored directly at address passed in reg */
1338 }
1340 }
1343 }
1345 /*
1346 * mono_arch_get_argument_info:
1347 * @csig: a method signature
1348 * @param_count: the number of parameters to consider
1349 * @arg_info: an array to store the result infos
1350 *
1351 * Gathers information on parameters such as size, alignment and
1352 * padding. arg_info should be large enought to hold param_count + 1 entries.
1353 *
1354 * Returns the size of the argument area on the stack.
1355 */
1356 int
1357 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1358 {
1363 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1366 }
1370 /* FIXME: */
1372 }
1377 }
1379 #ifndef DISABLE_JIT
1380 gboolean
1381 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
1382 {
1388 // Limit stack_usage to 1G. Assume 32bit limits when we move parameters.
1392 // valuetype parameters are address of local
1398 }
1404 }
1407 /*
1408 * Initialize the cpu to execute managed code.
1409 */
1410 void
1412 {
1413 #ifndef _MSC_VER
1414 guint16 fpcw;
1416 /* spec compliance requires running with double precision */
1422 #else
1423 /* TODO: This is crashing on Win64 right now.
1424 * _control87 (_PC_53, MCW_PC);
1425 */
1426 #endif
1427 }
1429 /*
1430 * Initialize architecture specific code.
1431 */
1432 void
1434 {
1437 }
1439 /*
1440 * Cleanup architecture specific code.
1441 */
1442 void
1444 {
1445 }
1447 /*
1448 * This function returns the optimizations supported on this cpu.
1449 */
1450 guint32
1452 {
1462 else
1466 }
1469 }
1471 MonoCPUFeatures
1473 {
1501 }
1503 #ifndef DISABLE_JIT
1505 GList *
1507 {
1515 /* unused vars */
1527 }
1528 }
1533 }
1535 /**
1536 * mono_arch_compute_omit_fp:
1537 * Determine whether the frame pointer can be eliminated.
1538 */
1539 static void
1541 {
1558 /*
1559 * FIXME: Remove some of the restrictions.
1560 */
1569 /*
1570 if (cfg->method->save_lmf)
1571 cfg->arch.omit_fp = FALSE;
1572 */
1584 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1585 /*
1586 * The stack offset can only be determined when the frame
1587 * size is known.
1588 */
1590 }
1591 }
1599 }
1600 }
1602 GList *
1604 {
1612 /* We use the callee saved registers for global allocation */
1618 #ifdef TARGET_WIN32
1621 #endif
1624 }
1626 /*
1627 * mono_arch_regalloc_cost:
1628 *
1629 * Return the cost, in number of memory references, of the action of
1630 * allocating the variable VMV into a register during global register
1631 * allocation.
1632 */
1633 guint32
1635 {
1639 /* The register is already saved */
1640 /* substract 1 for the invisible store in the prolog */
1642 else
1643 /* push+pop */
1645 }
1647 /*
1648 * mono_arch_fill_argument_info:
1649 *
1650 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1651 * of the method.
1652 */
1653 void
1655 {
1665 /*
1666 * Contrary to mono_arch_allocate_vars (), the information should describe
1667 * where the arguments are at the beginning of the method, not where they can be
1668 * accessed during the execution of the method. The later makes no sense for the
1669 * global register allocator, since a variable can be in more than one location.
1670 */
1687 }
1707 /* Dummy */
1712 }
1713 }
1714 }
1716 void
1718 {
1734 /*
1735 * We use the ABI calling conventions for managed code as well.
1736 * Exception: valuetypes are only sometimes passed or returned in registers.
1737 */
1739 /*
1740 * The stack looks like this:
1741 * <incoming arguments passed on the stack>
1742 * <return value>
1743 * <lmf/caller saved registers>
1744 * <locals>
1745 * <spill area>
1746 * <localloc area> -> grows dynamically
1747 * <params area>
1748 */
1755 /* Locals are allocated backwards from %fp */
1758 }
1762 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1765 }
1769 /* Reserve space for callee saved registers */
1773 }
1788 /* The register is volatile */
1797 }
1801 }
1804 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1813 }
1817 }
1818 }
1820 /* Allocate locals */
1821 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1825 }
1832 }
1841 else
1843 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1844 }
1845 }
1852 }
1860 /* FIXME: Allocate volatile arguments to registers */
1864 /*
1865 * Under AMD64, all registers used to pass arguments to functions
1866 * are volatile across calls.
1867 * FIXME: Optimize this.
1868 */
1869 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1882 }
1897 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1906 }
1910 }
1916 }
1918 NOT_IMPLEMENTED;
1919 }
1921 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1924 /* These arguments are saved to the stack in the prolog */
1928 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (target_mgreg_t) : sizeof (target_mgreg_t);
1929 // Arguments are yet supported by the stack map creation code
1930 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1932 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (target_mgreg_t) : sizeof (target_mgreg_t);
1934 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1935 }
1936 }
1937 }
1938 }
1941 }
1943 void
1945 {
1958 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1963 }
1964 }
1973 }
1981 }
1988 }
1989 }
1991 static void
1992 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1993 {
2023 }
2024 }
2026 static int
2028 {
2031 #if defined(MONO_ARCH_ILP32)
2033 #else
2035 #endif
2042 }
2045 }
2047 static void
2049 {
2054 NOT_IMPLEMENTED;
2058 /*
2059 * mono_ArgIterator_Setup assumes the signature cookie is
2060 * passed first and all the arguments which were before it are
2061 * passed on the stack after the signature. So compensate by
2062 * passing a different signature.
2063 */
2064 tmp_sig = mono_metadata_signature_dup_full (m_class_get_image (cfg->method->klass), call->signature);
2067 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2072 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2073 }
2075 #ifdef ENABLE_LLVM
2076 static LLVMArgStorage
2078 {
2090 }
2091 }
2093 LLVMCallInfo*
2095 {
2108 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2110 /*
2111 * LLVM always uses the native ABI while we use our own ABI, the
2112 * only difference is the handling of vtypes:
2113 * - we only pass/receive them in registers in some cases, and only
2114 * in 1 or 2 integer registers.
2115 */
2129 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2130 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2134 }
2140 }
2143 /* Vtype returned using a hidden argument */
2150 }
2157 else
2174 else
2179 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2180 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2184 }
2188 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2202 }
2203 }
2206 }
2207 #endif
2209 void
2211 {
2224 /* We shouldn't be called in the llvm case */
2227 }
2229 /*
2230 * Emit all arguments which are passed on the stack to prevent register
2231 * allocation problems.
2232 */
2241 else
2245 //XXX what about ArgGSharedVtOnStack here?
2252 else
2256 }
2261 }
2262 }
2263 }
2265 /*
2266 * Emit all parameters passed in registers in non-reverse order for better readability
2267 * and to help the optimization in emit_prolog ().
2268 */
2276 }
2287 else
2293 /* Already done */
2306 /* Already emitted above */
2309 guint32 align;
2310 guint32 size;
2315 /*
2316 * Other backends use mono_type_stack_size (), but that
2317 * aligns the size to 8, which is larger than the size of
2318 * the source, leading to reads of invalid memory if the
2319 * source is at the end of address space.
2320 */
2322 }
2325 /* Avoid asserts in emit_memcpy () */
2326 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2327 /* Continue normally */
2328 }
2340 }
2342 }
2345 }
2348 /* Emit the signature cookie just before the implicit arguments */
2350 }
2352 /* Handle the case where there are no implicit arguments */
2359 /*
2360 * Tell the JIT to use a more efficient calling convention: call using
2361 * OP_CALL, compute the result location after the call, and save the
2362 * result there.
2363 */
2365 /*
2366 * Nullify the instruction computing the vret addr to enable
2367 * future optimizations.
2368 */
2373 NOT_IMPLEMENTED;
2374 /*
2375 * The valuetype is in RAX:RDX after the call, need to be copied to
2376 * the stack. Push the address here, so the call instruction can
2377 * access it.
2378 */
2381 /* Prevent it from being register allocated or optimized away */
2383 }
2386 }
2398 }
2401 }
2406 }
2409 }
2411 void
2413 {
2429 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2431 }
2447 }
2448 }
2453 }
2455 }
2460 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2484 }
2486 }
2488 /* Pass by addr */
2503 // FIXME: Code growth
2505 }
2509 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, m_class_get_byval_arg (ins->klass));
2510 }
2511 }
2512 }
2514 void
2516 {
2522 else
2528 }
2531 }
2535 #define EMIT_COND_BRANCH(ins,cond,sign) \
2536 if (ins->inst_true_bb->native_offset) { \
2537 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2538 } else { \
2539 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2540 if (optimize_branch_pred && \
2541 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2542 x86_branch8 (code, cond, 0, sign); \
2543 else \
2544 x86_branch32 (code, cond, 0, sign); \
2545 }
2553 static gboolean
2555 {
2568 }
2583 }
2584 }
2587 }
2589 /*
2590 * mono_arch_dyn_call_prepare:
2591 *
2592 * Return a pointer to an arch-specific structure which contains information
2593 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2594 * supported for SIG.
2595 * This function is equivalent to ffi_prep_cif in libffi.
2596 */
2597 MonoDynCallInfo*
2599 {
2609 }
2612 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2622 info->nstack_args = MAX (info->nstack_args, (ainfo->offset / sizeof (target_mgreg_t)) + (ainfo->arg_size / sizeof (target_mgreg_t)));
2626 }
2627 }
2638 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type_internal (t))) {
2643 /* Nullables need a temporary buffer, its stored at the end of DynCallArgs.regs after the stack args */
2646 }
2647 }
2651 }
2652 }
2656 /* Align to 16 bytes */
2661 }
2663 /*
2664 * mono_arch_dyn_call_free:
2665 *
2666 * Free a MonoDynCallInfo structure.
2667 */
2668 void
2670 {
2675 }
2677 int
2679 {
2682 /* Extend the 'regs' field dynamically */
2683 return sizeof (DynCallArgs) + (ainfo->nstack_args * sizeof (target_mgreg_t)) + ainfo->nullable_area;
2684 }
2686 #define PTR_TO_GREG(ptr) ((host_mgreg_t)(ptr))
2687 #define GREG_TO_PTR(greg) ((gpointer)(greg))
2689 /*
2690 * mono_arch_get_start_dyn_call:
2691 *
2692 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2693 * store the result into BUF.
2694 * ARGS should be an array of pointers pointing to the arguments.
2695 * RET should point to a memory buffer large enought to hold the result of the
2696 * call.
2697 * This function should be as fast as possible, any work which does not depend
2698 * on the actual values of the arguments should be done in
2699 * mono_arch_dyn_call_prepare ().
2700 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2701 * libffi.
2702 */
2703 void
2705 {
2726 }
2736 /* Stored after the stack arguments */
2743 }
2745 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2763 }
2768 }
2775 #if !defined(MONO_ARCH_ILP32)
2778 #endif
2781 #if defined(MONO_ARCH_ILP32)
2786 #endif
2814 }
2816 }
2823 }
2829 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type_internal (t))) {
2841 }
2843 /* The argument pointed to by arg is either a boxed vtype or null */
2847 /* Fall though */
2850 /* Fall through */
2851 }
2870 }
2879 }
2880 }
2884 // In DYNCALL use case value types are already copied when included in parameter array.
2885 // Currently no need to make an extra temporary value type on stack for this use case.
2895 }
2897 }
2900 }
2901 }
2902 }
2904 /*
2905 * mono_arch_finish_dyn_call:
2906 *
2907 * Store the result of a dyn call into the return value buffer passed to
2908 * start_dyn_call ().
2909 * This function should be as fast as possible, any work which does not depend
2910 * on the actual values of the arguments should be done in
2911 * mono_arch_dyn_call_prepare ().
2912 */
2913 void
2915 {
2969 /* Fall through */
2970 }
2972 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2973 /* Nothing to do */
2992 }
2993 }
2994 }
2998 }
2999 }
3001 #undef PTR_TO_GREG
3002 #undef GREG_TO_PTR
3004 /* emit an exception if condition is fail */
3005 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
3006 do { \
3007 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3008 if (tins == NULL) { \
3009 mono_add_patch_info (cfg, code - cfg->native_code, \
3010 MONO_PATCH_INFO_EXC, exc_name); \
3011 x86_branch32 (code, cond, 0, signed); \
3012 } else { \
3013 EMIT_COND_BRANCH (tins, cond, signed); \
3014 } \
3015 } while (0);
3017 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3018 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3019 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3020 amd64_ ##op (code); \
3021 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3022 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3023 } while (0);
3025 #ifndef DISABLE_JIT
3028 {
3030 MonoJumpInfoTarget patch;
3032 // FIXME? This is similar to mono_call_to_patch, except it favors MONO_PATCH_INFO_ABS over call->jit_icall_id.
3044 }
3046 /*
3047 * FIXME: Add support for thunks
3048 */
3049 {
3052 /*
3053 * Indirect calls are expensive so try to make a near call if possible.
3054 * The caller memory is allocated by the code manager so it is
3055 * guaranteed to be at a 32 bit offset.
3056 */
3060 /* The target is in memory allocated using the code manager */
3068 /* The callee might be an AOT method */
3071 /* The target is in malloc-ed memory */
3074 /*
3075 * The call might go directly to a native function without
3076 * the wrapper.
3077 */
3082 }
3096 /*
3097 * This is not really an optimization, but required because the
3098 * generic class init trampolines use R11 to pass the vtable.
3099 */
3101 }
3108 // Change patch from MONO_PATCH_INFO_ABS to MONO_PATCH_INFO_JIT_ICALL_ID.
3113 /* No wrapper */
3117 /* ?See the comment in mono_codegen ()? */
3119 }
3120 }
3124 }
3125 }
3126 }
3129 /* These methods are allocated using malloc */
3132 #ifdef MONO_ARCH_NOMAP32BIT
3134 #endif
3135 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3142 }
3145 /*
3146 * Align the call displacement to an address divisible by 4 so it does
3147 * not span cache lines. This is required for code patching to work on SMP
3148 * systems.
3149 */
3153 }
3156 }
3162 }
3166 }
3167 }
3172 }
3174 static int
3176 {
3184 }
3187 }
3190 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3192 /*
3193 * mono_arch_peephole_pass_1:
3194 *
3195 * Perform peephole opts which should/can be performed before local regalloc
3196 */
3197 void
3199 {
3210 /*
3211 * X86_LEA is like ADD, but doesn't have the
3212 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3213 * its operand to 64 bit.
3214 */
3217 }
3224 /*
3225 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3226 * the latter has length 2-3 instead of 6 (reverse constant
3227 * propagation). These instruction sequences are very common
3228 * in the initlocals bblock.
3229 */
3231 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3234 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3235 /* Continue */
3236 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3238 /* Continue */
3240 /* Continue */
3243 }
3244 }
3245 }
3249 /* OP_COMPARE_IMM (reg, 0)
3250 * -->
3251 * OP_AMD64_TEST_NULL (reg)
3252 */
3261 /*
3262 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3263 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3264 * -->
3265 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3266 * OP_COMPARE_IMM reg, imm
3267 *
3268 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3269 */
3276 /* check if we can remove cmp reg,0 with test null */
3279 }
3282 }
3285 }
3286 }
3288 void
3290 {
3298 /* reg = 0 -> XOR (reg, reg) */
3299 /* XOR sets cflags on x86, so we cant do it always */
3304 /* Fall through */
3307 }
3308 }
3310 /*
3311 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3312 * 0 result into 64 bits.
3313 */
3316 }
3317 /* Fall through */
3322 /*
3323 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3324 * the latter has length 2-3 instead of 6 (reverse constant
3325 * propagation). These instruction sequences are very common
3326 * in the initlocals bblock.
3327 */
3329 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3332 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3333 /* Continue */
3334 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3336 /* Continue */
3338 /* Continue */
3341 }
3342 }
3343 }
3353 }
3356 }
3357 }
3359 #define NEW_INS(cfg,ins,dest,op) do { \
3360 MONO_INST_NEW ((cfg), (dest), (op)); \
3361 (dest)->cil_code = (ins)->cil_code; \
3362 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3363 } while (0)
3365 #define NEW_SIMD_INS(cfg,ins,dest,op,d,s1,s2) do { \
3366 MONO_INST_NEW ((cfg), (dest), (op)); \
3367 (dest)->cil_code = (ins)->cil_code; \
3368 (dest)->dreg = d; \
3369 (dest)->sreg1 = s1; \
3370 (dest)->sreg2 = s2; \
3371 (dest)->type = STACK_VTYPE; \
3372 (dest)->klass = ins->klass; \
3373 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3374 } while (0)
3376 static int
3378 {
3395 }
3396 }
3398 static int
3400 {
3417 }
3418 }
3420 static int
3422 {
3436 }
3437 }
3439 static int
3441 {
3458 }
3459 }
3461 static int
3463 {
3471 //case MONO_TYPE_U8:
3472 // return OP_PMAXQ_UN; // AVX
3476 }
3477 }
3479 static int
3481 {
3498 }
3499 }
3501 static int
3503 {
3517 // case MONO_TYPE_I8: // AVX
3518 // case MONO_TYPE_U8:
3522 }
3523 }
3525 static int
3527 {
3541 // case MONO_TYPE_I8: // AVX
3542 // case MONO_TYPE_U8:
3546 }
3547 }
3549 static void
3550 emit_simd_comp_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3551 {
3554 if (!mono_hwcap_x86_has_sse42 && (ins->inst_c1 == MONO_TYPE_I8 || ins->inst_c1 == MONO_TYPE_U8)) {
3564 }
3565 }
3567 static void
3568 emit_simd_gt_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2);
3570 static void
3571 emit_simd_gt_un_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3572 {
3583 USE_MAX: {
3584 // dreg = max(sreg1, sreg2) != sreg2
3595 }
3598 USE_SIGNED_GT: {
3599 // convert to signed integer by subtracting (1 << (size - 1)) from each operand
3600 // and then use signed comparison
3614 }
3615 }
3616 }
3618 static void
3619 emit_simd_gt_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3620 {
3624 // Decompose 64-bit greater than to 32-bit
3625 //
3626 // t = (v1 > v2)
3627 // u = (v1 == v2)
3628 // v = (v1 > v2) unsigned
3629 //
3630 // z = shuffle(t, (3, 3, 1, 1))
3631 // t1 = shuffle(v, (2, 2, 0, 0))
3632 // u1 = shuffle(u, (3, 3, 1, 1))
3633 // w = and(t1, u1)
3634 // result = bitwise_or(z, w)
3657 }
3658 }
3660 static void
3661 emit_simd_min_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3662 {
3666 // SSE2, so always available
3669 // Decompose to t = (s1 > s2), d = (s1 & !t) | (s2 & t)
3675 else
3681 // SSE 4.1 has byte- and dword- operations
3683 }
3684 }
3686 static void
3687 emit_simd_max_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3688 {
3692 // SSE2, so always available
3695 // Decompose to t = (s1 > s2), d = (s1 & t) | (s2 & !t)
3701 else
3707 // SSE 4.1 has byte- and dword- operations
3709 }
3710 }
3712 /*
3713 * mono_arch_lowering_pass:
3714 *
3715 * Converts complex opcodes into simpler ones so that each IR instruction
3716 * corresponds to one machine instruction.
3717 */
3718 void
3720 {
3723 /*
3724 * FIXME: Need to add more instructions, but the current machine
3725 * description can't model some parts of the composite instructions like
3726 * cdq.
3727 */
3747 }
3749 #ifndef MONO_ARCH_ILP32
3751 #endif
3753 /* Don't generate memindex opcodes (to simplify */
3754 /* read sandboxing) */
3761 }
3763 #ifndef MONO_ARCH_ILP32
3765 #endif
3773 }
3775 #ifdef MONO_ARCH_SIMD_INTRINSICS
3797 }
3814 }
3820 {
3836 }
3861 }
3871 NEW_SIMD_INS (cfg, ins, temp, simd_type_to_max_un_op (ins->inst_c1), temp_reg1, ins->sreg1, ins->sreg2);
3883 }
3894 }
3899 }
3904 }
3910 {
3920 }
3923 }
3928 }
3932 {
3977 }
3979 }
3985 // TODO
3988 }
3989 #endif
3992 }
3993 }
3996 }
3998 static const int
3999 branch_cc_table [] = {
4003 };
4005 /* Maps CMP_... constants to X86_CC_... constants */
4006 static const int
4007 cc_table [] = {
4010 };
4012 static const int
4013 cc_signed_table [] = {
4016 };
4018 /*#include "cprop.c"*/
4021 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
4022 {
4023 // Use 8 as register size to get Nan/Inf conversion to uint result truncated to 0
4026 else
4034 }
4038 {
4042 #if defined(TARGET_WIN32)
4044 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4047 #endif
4052 /*
4053 * Under Windows:
4054 * If requested stack size is larger than one page,
4055 * perform stack-touch operation
4056 */
4057 /*
4058 * Generate stack probe code.
4059 * Under Windows, it is necessary to allocate one page at a time,
4060 * "touching" stack after each successful sub-allocation. This is
4061 * because of the way stack growth is implemented - there is a
4062 * guard page before the lowest stack page that is currently commited.
4063 * Stack normally grows sequentially so OS traps access to the
4064 * guard page and commits more pages when needed.
4065 */
4086 }
4087 else
4095 }
4099 }
4103 }
4123 }
4125 }
4129 {
4131 guint32 quad;
4133 /* Move return value to the target register */
4134 /* FIXME: do this in the local reg allocator */
4150 }
4154 }
4156 }
4173 /* Load the destination address */
4175 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
4180 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof (target_mgreg_t)), cinfo->ret.pair_regs [quad], sizeof (target_mgreg_t));
4191 NOT_IMPLEMENTED;
4192 }
4193 }
4194 }
4196 }
4199 }
4203 #ifdef TARGET_MACH
4205 #endif
4207 gboolean
4209 {
4210 #ifdef TARGET_MACH
4223 /*
4224 * We're looking for these two instructions:
4225 *
4226 * mov %gs:[offset](,%rdi,8),%rax
4227 * retq
4228 */
4241 /*
4242 * Apple now loads a different version of pthread_getspecific when launched from Xcode
4243 * For that version we're looking for these instructions:
4244 *
4245 * pushq %rbp
4246 * movq %rsp, %rbp
4247 * mov %gs:[offset](,%rdi,8),%rax
4248 * popq %rbp
4249 * retq
4250 */
4268 }
4272 #elif defined(TARGET_ANDROID)
4274 #else
4278 #endif
4279 }
4281 int
4283 {
4284 #ifdef TARGET_OSX
4286 #else
4289 #endif
4290 }
4292 /*
4293 * \param code buffer to store code to
4294 * \param dreg hard register where to place the result
4295 * \param tls_offset offset info
4296 * \return a pointer to the end of the stored code
4297 *
4298 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
4299 * the dreg register the item in the thread local storage identified
4300 * by tls_offset.
4301 */
4304 {
4305 #ifdef TARGET_WIN32
4313 /* Load TEB->TlsExpansionSlots */
4321 }
4322 #elif defined(TARGET_MACH)
4325 #else
4333 }
4334 #endif
4336 }
4340 {
4341 #ifdef TARGET_WIN32
4343 #elif defined(TARGET_MACH)
4346 #else
4350 #endif
4352 }
4354 /*
4355 * emit_setup_lmf:
4356 *
4357 * Emit code to initialize an LMF structure at LMF_OFFSET.
4358 */
4361 {
4362 /*
4363 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4364 */
4365 /*
4366 * sp is saved right before calls but we need to save it here too so
4367 * async stack walks would work.
4368 */
4369 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4370 /* Save rbp */
4371 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4373 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
4375 /* These can't contain refs */
4376 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
4377 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
4378 /* These are handled automatically by the stack marking code */
4379 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
4382 }
4384 #ifdef TARGET_WIN32
4386 #define TEB_LAST_ERROR_OFFSET 0x68
4390 {
4391 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
4395 }
4397 #else
4401 {
4403 }
4405 #endif
4407 /* benchmark and set based on cpu */
4408 #define LOOP_ALIGNMENT 8
4409 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
4411 #ifndef DISABLE_JIT
4415 {
4416 #ifndef TARGET_WIN32
4419 else
4421 #endif
4423 }
4426 amd64_handle_varargs_call (MonoCompile *cfg, guint8 *code, MonoCallInst *call, gboolean free_rax)
4427 {
4428 #ifdef TARGET_WIN32
4430 #else
4431 /*
4432 * The AMD64 ABI forces callers to know about varargs.
4433 */
4436 // deliberatly nothing -- but nreg = 0 and do not return
4437 } else if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE && m_class_get_image (cfg->method->klass) != mono_defaults.corlib) {
4438 /*
4439 * Since the unmanaged calling convention doesn't contain a
4440 * 'vararg' entry, we have to treat every pinvoke call as a
4441 * potential vararg call.
4442 */
4447 }
4452 }
4454 #endif
4455 }
4457 void
4459 {
4464 /* Fix max_offset estimate for each successor bb */
4465 gboolean optimize_branch_pred = (cfg->opt & MONO_OPT_BRANCH) && (cfg->max_block_num < MAX_BBLOCKS_FOR_BRANCH_OPTS);
4473 }
4474 }
4478 /* set alignment depending on cpu */
4481 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
4485 }
4486 }
4495 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4533 /* In AMD64 NaCl, pointers are 4 bytes, */
4534 /* so STORE_* != STOREI8_*. Likewise below. */
4536 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4545 /* In NaCl, this could be a PCONST type, which could */
4546 /* mean a pointer type was copied directly into the */
4547 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4548 /* the value would be 0x00000000FFFFFFFF which is */
4549 /* not proper for an imm32 unless you cast it. */
4551 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4558 #ifdef MONO_ARCH_ILP32
4559 /* In ILP32, pointers are 4 bytes, so separate these */
4560 /* cases, use literal 8 below where we really want 8 */
4564 #endif
4566 // FIXME: Decompose this earlier
4572 }
4579 // FIXME: Decompose this earlier
4585 }
4592 /* For NaCl, pointers are 4 bytes, so separate these */
4593 /* cases, use literal 8 below where we really want 8 */
4599 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4602 /* Use literal 8 instead of sizeof pointer or */
4603 /* register, we really want 8 for this opcode */
4614 /* The cpu zero extends the result into 64 bits */
4615 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4621 /* The cpu zero extends the result into 64 bits */
4622 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4649 /* Clean out the upper word */
4660 #if defined(MONO_ARCH_ILP32)
4661 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4665 #endif
4697 /* FIXME: Make a 64 version too */
4698 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4702 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4706 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4710 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4714 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4717 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4720 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4723 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4729 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4748 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4751 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4754 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4758 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4761 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4787 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4790 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4793 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4799 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4804 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4808 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4812 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4816 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4820 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4850 /* Load ss_tramp_var */
4851 /* This is equal to &ss_trampoline */
4853 /* Load the trampoline address */
4855 /* Call it if it is non-null */
4861 }
4863 /*
4864 * This is the address which is saved in seq points,
4865 */
4870 guint32 val;
4874 /* Load info var */
4877 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4882 /* Call the trampoline */
4889 /*
4890 * Emit a test+branch against a constant, the constant will be overwritten
4891 * by mono_arch_set_breakpoint () to cause the test to fail.
4892 */
4900 /* Load bp_tramp_var */
4901 /* This is equal to &bp_trampoline */
4903 /* Call the trampoline */
4906 }
4907 /*
4908 * Add an additional nop so skipping the bp doesn't cause the ip to point
4909 * to another IL offset.
4910 */
4913 }
4966 /* MOV r1, r2 */
4967 /* ADD r1, r1 */
4973 /* LEA r1, [r2 + r2*2] */
4977 /* LEA r1, [r2 + r2*4] */
4981 /* LEA r1, [r2 + r2*2] */
4982 /* ADD r1, r1 */
4987 /* LEA r1, [r2 + r2*8] */
4991 /* LEA r1, [r2 + r2*4] */
4992 /* ADD r1, r1 */
4997 /* LEA r1, [r2 + r2*2] */
4998 /* SHL r1, 2 */
5003 /* LEA r1, [r2 + r2*4] */
5004 /* LEA r1, [r1 + r1*4] */
5009 /* LEA r1, [r2 + r2*4] */
5010 /* SHL r1, 2 */
5011 /* LEA r1, [r1 + r1*4] */
5019 }
5021 }
5024 /* Regalloc magic makes the div/rem cases the same */
5032 }
5043 }
5054 }
5065 }
5198 /* the mul operation and the exception check should most likely be split */
5201 /*g_assert (ins->sreg2 == X86_EAX);
5202 g_assert (ins->dreg == X86_EAX);*/
5208 /* no need to save since we're going to store to it anyway */
5212 }
5215 }
5220 }
5224 }
5226 /* save before the check since pop and mov don't change the flags */
5235 }
5262 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5286 /* This needs to operate on 64 bit values */
5287 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
5301 else
5322 }
5324 }
5329 }
5332 // This opcode helps compute sizes, i.e.
5333 // of the subsequent OP_TAILCALL, but contributes no code.
5351 // FIXME hardcoding RAX here is not ideal.
5367 // FIXME Patch data instead of code.
5373 }
5374 }
5376 /* Restore callee saved registers */
5382 }
5387 // FIXME:
5389 NOT_IMPLEMENTED;
5392 /* Copy arguments on the stack to our argument area */
5393 // FIXME use rep mov for constant code size, before nonvolatiles
5394 // restored, first saving rsi, rdi into volatiles
5398 }
5400 #ifdef TARGET_WIN32
5404 #else
5406 #endif
5407 }
5409 #ifdef TARGET_WIN32
5410 // Redundant REX byte indicates a tailcall to the native unwinder. It means nothing to the processor.
5411 // https://github.com/dotnet/coreclr/blob/966dabb5bb3c4bf1ea885e1e8dc6528e8c64dc4f/src/unwinder/amd64/unwinder_amd64.cpp#L1394
5412 // FIXME This should be jmp rip+32 for AOT direct to same assembly.
5413 // FIXME This should be jmp [rip+32] for AOT direct to not-same assembly (through data).
5414 // FIXME This should be jmp [rip+32] for JIT direct -- patch data instead of code.
5415 // This is only close to ideal for tailcall_membase, and even then it should
5416 // have a more dynamic register allocation.
5419 #else
5420 // NT does not have varargs rax use, and NT ABI does not have red zone.
5421 // Use red-zone mov/jmp instead of push/ret to preserve call/ret speculation stack.
5422 // FIXME Just like NT the direct cases are are not ideal.
5426 #endif
5430 }
5432 /* ensure ins->sreg1 is not NULL */
5439 }
5467 }
5497 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5499 /* r10 = ftn */
5502 /* Save args buffer */
5505 /* Set fp arg regs */
5506 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (target_mgreg_t));
5511 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
5514 /* Allocate param area */
5515 /* This doesn't need to be freed since OP_DYN_CALL is never called in a loop */
5516 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
5519 /* Set stack args */
5520 /* rax/rcx/rdx/r8/r9 is scratch */
5525 amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
5527 amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof (target_mgreg_t)));
5543 /* Set argument registers */
5545 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof (target_mgreg_t)), sizeof (target_mgreg_t));
5547 /* Make the call */
5553 /* Save result */
5556 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5557 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
5559 }
5562 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5564 }
5589 else
5600 }
5606 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
5616 }
5619 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5631 /* keep alignment */
5659 }
5663 }
5667 }
5674 }
5681 }
5683 /* Align stack */
5687 /*
5688 * ins->inst_eh_blocks and bb->clause_holes are part of same GList.
5689 * Holes from bb->clause_holes will be added separately for the entire
5690 * basic block. Add only the rest of them.
5691 */
5694 /* Restore stack alignment */
5698 /* Even though we're saving RSP, use sizeof */
5699 /* gpointer because spvar is of type IntPtr */
5700 /* see: mono_create_spvar_for_region */
5702 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5708 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5709 }
5711 }
5714 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5717 }
5720 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5721 /* The local allocator will put the result into RAX */
5724 }
5733 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5734 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5735 //break;
5743 else
5745 }
5771 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5794 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5811 /* floating point opcodes */
5824 }
5826 }
5833 else
5843 }
5846 }
5848 }
5859 /* This requires a double->single conversion */
5861 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5862 }
5870 }
5878 }
5889 }
5900 }
5945 // Use 8 as register size to get Nan/Inf conversion result truncated to 0
5963 /* Based on gcc code */
5967 /* Positive case */
5972 /* Negative case */
5973 /* Save to the red zone */
5983 /* Restore */
5988 }
6013 }
6051 }
6053 }
6067 }
6069 }
6098 }
6102 }
6155 /*
6156 * The two arguments are swapped because the fbranch instructions
6157 * depend on this for the non-sse case to work.
6158 */
6162 /*
6163 * FIXME: Get rid of this.
6164 * The two arguments are swapped because the fbranch instructions
6165 * depend on this for the non-sse case to work.
6166 */
6171 /* zeroing the register at the start results in
6172 * shorter and faster code (we can also remove the widening op)
6173 */
6192 }
6194 }
6197 /* zeroing the register at the start results in
6198 * shorter and faster code (we can also remove the widening op)
6199 */
6214 }
6216 }
6226 }
6229 /* zeroing the register at the start results in
6230 * shorter and faster code (we can also remove the widening op)
6231 */
6243 }
6245 }
6255 }
6286 }
6311 }
6318 }
6320 }
6346 }
6368 }
6370 }
6377 }
6379 /* Branch if C013 != 100 */
6380 /* branch if !ZF or (PF|CF) */
6397 /* skip branch if C1=1 */
6400 /* branch if (C0 | C3) = 1 */
6406 }
6409 /* Branch if C013 == 100 or 001 */
6412 /* skip branch if C1=1 */
6415 /* branch if (C0 | C3) = 1 */
6419 }
6421 /* Branch if C013 == 000 */
6425 /* Branch if C013=000 or 100 */
6428 /* skip branch if C1=1 */
6431 /* branch if C0=0 */
6435 }
6437 /* Branch if C013 != 001 */
6442 /* Transfer value to the fp stack */
6460 }
6464 }
6469 }
6481 /* dreg contains the old value, add with sreg2 value */
6488 }
6493 /* LOCK prefix is implied. */
6498 }
6501 guint32 size;
6505 else
6508 /*
6509 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
6510 * an explanation of how this works.
6511 */
6522 }
6526 }
6530 }
6534 }
6538 }
6542 }
6546 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
6548 }
6555 }
6557 }
6561 }
6589 }
6596 }
6602 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6603 }
6608 }
6619 }
6625 gpointer card_table_mask;
6632 /*If either point to the stack we can simply avoid the WB. This happens due to
6633 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6634 */
6638 /*
6639 * We need one register we can clobber, we choose EDX and make sreg1
6640 * fixed EAX to work around limitations in the local register allocator.
6641 * sreg2 might get allocated to EDX, but that is not a problem since
6642 * we use it before clobbering EDX.
6643 */
6646 /*
6647 * This is the code we produce:
6648 *
6649 * edx = value
6650 * edx >>= nursery_shift
6651 * cmp edx, (nursery_start >> nursery_shift)
6652 * jne done
6653 * edx = ptr
6654 * edx >>= card_table_shift
6655 * edx += cardtable
6656 * [edx] = 1
6657 * done:
6658 */
6665 /*
6666 * The value we need to compare against is 64 bits, so we need
6667 * another spare register. We use RBX, which we save and
6668 * restore.
6669 */
6676 }
6678 }
6684 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6692 }
6693 #ifdef MONO_ARCH_SIMD_INTRINSICS
6694 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
7087 /*TODO: This is appart of the sse spec but not added
7088 case OP_PSARQ:
7089 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
7090 break;
7091 case OP_PSARQ_REG:
7092 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
7093 break;
7094 */
7139 }
7150 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
7151 if (ins->inst_c0)
7152 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
7159 else
7169 /*sreg1 is the extracted ireg (scratch)
7170 /sreg2 is the to be inserted ireg (scratch)
7171 /dreg is the xreg to receive the value*/
7173 /*clear the bits from the extracted word*/
7175 /*shift the value to insert if needed*/
7178 /*join them together*/
7191 else
7200 else
7207 else
7215 else
7223 else
7227 }
7232 else
7256 /*FIXME the peephole pass should have killed this*/
7291 }
7313 }
7323 else
7326 }
7327 #endif
7344 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
7347 }
7350 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
7353 }
7362 }
7379 amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (target_mgreg_t), i, sizeof (target_mgreg_t));
7384 }
7389 }
7392 }
7396 G_BEGIN_DECLS
7399 G_END_DECLS
7401 void
7403 {
7404 /* The signature doesn't matter */
7407 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
7408 #if _MSC_VER
7409 mono_register_jit_icall_info (&mono_get_jit_icall_info ()->mono_chkstk_win64, __chkstk, "mono_chkstk_win64", NULL, TRUE, "__chkstk");
7410 #else
7411 mono_register_jit_icall_info (&mono_get_jit_icall_info ()->mono_chkstk_win64, ___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, "___chkstk_ms");
7412 #endif
7413 #endif
7414 }
7416 void
7417 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
7418 {
7421 /*
7422 * Debug code to help track down problems where the target of a near call is
7423 * is not valid.
7424 */
7440 }
7441 }
7442 }
7445 }
7447 #ifndef DISABLE_JIT
7449 static int
7451 {
7460 }
7462 /*
7463 * This macro is used for testing whenever the unwinder works correctly at every point
7464 * where an async exception can happen.
7465 */
7466 /* This will generate a SIGSEGV at the given point in the code */
7467 #define async_exc_point(code) do { \
7468 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
7469 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
7470 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
7471 cfg->arch.async_point_count ++; \
7472 } \
7473 } while (0)
7475 #ifdef TARGET_WIN32
7477 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
7478 {
7481 /* Allocate windows stack frame using stack probing method */
7487 }
7494 }
7496 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
7497 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
7498 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
7499 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
7500 // that will retrieve the expected results.
7503 }
7508 }
7511 guint8 *
7513 {
7528 /* Amount of stack space allocated by register saving code */
7531 /* Offset between RSP and the CFA */
7534 /*
7535 * The prolog consists of the following parts:
7536 * FP present:
7537 * - push rbp
7538 * - mov rbp, rsp
7539 * - save callee saved regs using moves
7540 * - allocate frame
7541 * - save rgctx if needed
7542 * - save lmf if needed
7543 * FP not present:
7544 * - allocate frame
7545 * - save rgctx if needed
7546 * - save lmf if needed
7547 * - save callee saved regs using moves
7548 */
7550 // CFA = sp + 8
7553 // IP saved at CFA - 8
7564 /* These are handled automatically by the stack marking code */
7571 }
7573 /* The param area is always at offset 0 from sp */
7574 /* This needs to be allocated here, since it has to come after the spill area */
7577 // FIXME:
7580 }
7583 /*
7584 * On enter, the stack is misaligned by the pushing of the return
7585 * address. It is either made aligned by the pushing of %rbp, or by
7586 * this.
7587 */
7591 /* Mark the padding slot as NOREF */
7593 }
7597 /* Mark the padding slot as NOREF */
7599 }
7602 }
7608 /* Allocate stack frame */
7609 #ifdef TARGET_WIN32
7611 #else
7613 /* See mono_emit_stack_alloc */
7614 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7617 /* Use a loop for large sizes */
7631 }
7635 }
7637 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7645 }
7650 }
7657 }
7658 }
7659 #else
7665 }
7666 #endif
7667 }
7668 #endif
7670 /* Stack alignment check */
7671 #if 0
7672 {
7682 }
7683 #endif
7686 /* Fill the stack frame with a dummy value to force deterministic behavior */
7688 /* Save registers to the red zone */
7694 MONO_RESTORE_WARNING
7705 }
7707 /* Save LMF */
7711 /* Save callee saved registers */
7714 /* Save caller saved registers after sp is adjusted */
7715 /* The registers are saved at the bottom of the frame */
7716 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7718 /* The registers are saved just below the saved rbp */
7720 }
7728 /* These are handled automatically by the stack marking code */
7732 // FIXME: GC
7733 }
7737 }
7738 }
7740 /* store runtime generic context */
7745 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7747 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7748 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7749 }
7751 /* compute max_length in order to use short forward jumps */
7758 /* max alignment for loops */
7764 }
7766 /* Take prolog and epilog instrumentation into account */
7771 }
7772 }
7780 /* Save volatile arguments to the stack */
7782 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7783 }
7785 /* Keep this in sync with emit_load_volatile_arguments */
7792 /* Unused arguments */
7795 /* Save volatile arguments to the stack */
7801 /* FIXME: I1 etc */
7802 /*
7803 if (stack_offset & 0x1)
7804 size = 1;
7805 else if (stack_offset & 0x2)
7806 size = 2;
7807 else if (stack_offset & 0x4)
7808 size = 4;
7809 else
7810 size = 8;
7811 */
7814 /*
7815 * Save the original location of 'this',
7816 * get_generic_info_from_stack_frame () needs this to properly look up
7817 * the argument value during the handling of async exceptions.
7818 */
7821 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7822 }
7824 }
7835 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad], sizeof (target_mgreg_t));
7838 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad]);
7841 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad]);
7847 }
7848 }
7852 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (target_mgreg_t));
7861 }
7863 /* Argument allocated to (non-volatile) register */
7873 }
7879 }
7880 }
7881 }
7886 /*
7887 * Optimize the common case of the first bblock making a call with the same
7888 * arguments as the method. This works because the arguments are still in their
7889 * original argument registers.
7890 * FIXME: Generalize this
7891 */
7901 }
7914 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7921 /* Only continue if the instruction doesn't change argument regs */
7924 }
7925 }
7927 }
7930 }
7932 /* Argument allocated to (non-volatile) register */
7938 }
7942 }
7943 }
7947 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7950 }
7951 }
7952 }
7957 /* Initialize seq_point_info_var */
7959 /* Initialize the variable from a GOT slot */
7960 /* Same as OP_AOTCONST */
7961 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7965 }
7968 /* Initialize ss_tramp_var */
7973 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7976 /* Initialize ss_tramp_var */
7983 /* Initialize bp_tramp_var */
7989 }
7990 }
7995 }
7997 void
7999 {
8014 /* Mark the start of the epilog */
8017 /* Save the uwind state which is needed by the out-of-line code */
8020 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
8024 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
8026 /*
8027 * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
8028 * since its stack slot will become invalid.
8029 */
8031 }
8033 /* Restore callee saved regs */
8036 /* Restore only used_int_regs, not arch.saved_iregs */
8037 #if defined(MONO_SUPPORT_TASKLETS)
8039 #else
8041 #endif
8046 }
8048 }
8049 }
8051 /* Load returned vtypes into registers if needed */
8060 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_size [quad]);
8063 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)));
8066 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)));
8072 }
8073 }
8074 }
8079 }
8081 #ifdef TARGET_WIN32
8085 #else
8088 #endif
8089 }
8094 /* Restore the unwind state to be the same as before the epilog */
8098 }
8100 void
8102 {
8110 /* Compute needed space */
8120 }
8124 /* add code to raise exceptions */
8131 guint32 throw_ip;
8138 //x86_breakpoint (code);
8139 /* Find a throw sequence for the same exception class */
8147 }
8156 }
8157 amd64_mov_reg_imm (code, AMD64_ARG_REG1, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
8169 nthrows ++;
8170 }
8171 }
8173 }
8175 /* do nothing */
8177 }
8179 }
8181 /* Handle relocations with RIP relative addressing */
8190 guint32 target_pos;
8192 /* The SSE opcodes require a 16 byte alignment */
8199 }
8203 }
8211 }
8217 }
8224 /*loading is faster against aligned addresses.*/
8230 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
8233 else
8241 }
8244 }
8253 ;
8255 }
8256 }
8258 }
8261 }
8265 MONO_NEVER_INLINE
8266 void
8268 {
8269 /* call/ret required (or likely other control transfer) */
8270 }
8272 void
8274 {
8275 }
8277 gboolean
8279 {
8281 }
8283 /*
8284 * Determine whenever the trap whose info is in SIGINFO is caused by
8285 * integer overflow.
8286 */
8287 gboolean
8289 {
8290 MonoContext ctx;
8293 gint64 value;
8301 rip ++;
8302 }
8303 else
8306 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
8307 /* idiv REG */
8314 }
8317 }
8319 guint32
8321 {
8323 }
8325 /**
8326 * \return TRUE if no sw breakpoint was present.
8327 *
8328 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
8329 * breakpoints in the original code, they are removed in the copy.
8330 */
8331 gboolean
8332 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
8333 {
8334 /*
8335 * If method_start is non-NULL we need to perform bound checks, since we access memory
8336 * at code - offset we could go before the start of the method and end up in a different
8337 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
8338 * instead.
8339 */
8346 }
8348 }
8350 int
8352 {
8354 }
8356 gpointer
8358 {
8360 }
8362 #define MAX_ARCH_DELEGATE_PARAMS 10
8364 static gpointer
8366 {
8375 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8379 /* Replace the this argument with the target */
8381 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8388 /* We have to shift the arguments left */
8391 #ifdef TARGET_WIN32
8394 else
8396 #else
8398 #endif
8399 }
8402 }
8403 }
8406 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8411 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8416 }
8422 else
8427 }
8428 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
8431 }
8433 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8435 static gpointer
8437 {
8446 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8450 /* Replace the this argument with the target */
8452 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8455 /* Load the IMT reg */
8456 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8457 }
8459 /* Load the vtable */
8460 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8465 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
8472 }
8474 /*
8475 * mono_arch_get_delegate_invoke_impls:
8476 *
8477 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8478 * trampolines.
8479 */
8480 GSList*
8482 {
8493 }
8498 }
8505 }
8508 }
8510 gpointer
8512 {
8519 /* FIXME: Support more cases */
8535 }
8560 }
8565 }
8568 }
8570 gpointer
8571 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8572 {
8574 gpointer code;
8580 }
8582 void
8584 {
8585 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8587 #endif
8588 }
8590 #define CMP_SIZE (6 + 1)
8591 #define CMP_REG_REG_SIZE (4 + 1)
8592 #define BR_SMALL_SIZE 2
8593 #define BR_LARGE_SIZE 6
8594 #define MOV_REG_IMM_SIZE 10
8595 #define MOV_REG_IMM_32BIT_SIZE 6
8596 #define JUMP_REG_SIZE (2 + 1)
8598 static int
8600 {
8605 }
8607 /*
8608 * LOCKING: called with the domain lock held
8609 */
8610 gpointer
8611 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8612 gpointer fail_tramp)
8613 {
8627 else
8629 }
8635 else
8637 }
8646 else
8649 /* with assert below:
8650 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8651 */
8652 }
8653 }
8657 else
8661 }
8663 }
8665 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (mono_domain_ambient_memory_manager (domain), size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8668 code = (guint8 *)mono_mem_manager_code_reserve (mem_manager, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8669 }
8683 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8687 }
8688 }
8695 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8697 }
8704 }
8706 /* enable the commented code to assert on wrong method */
8707 #if 0
8709 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8713 }
8716 /* See the comment below about R10 */
8717 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8722 #else
8723 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8724 needs to be preserved. R10 needs
8725 to be preserved for calls which
8726 require a runtime generic context,
8727 but interface calls don't. */
8728 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8730 #endif
8731 }
8734 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (target_mgreg_t));
8738 }
8742 else
8744 }
8745 g_assertf (code - item->code_target <= item->chunk_size, "%X %X", (guint)(code - item->code_target), (guint)item->chunk_size);
8746 }
8747 /* patch the branches to get to the target items */
8753 }
8754 }
8755 }
8760 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8762 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8764 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8767 }
8769 MonoMethod*
8771 {
8773 }
8775 MonoVTable*
8777 {
8779 }
8781 GSList*
8783 {
8790 }
8792 #ifndef DISABLE_JIT
8794 MonoInst*
8795 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8796 {
8805 }
8813 }
8835 }
8836 }
8845 }
8847 #if 0
8848 /* OP_FREM is not IEEE compatible */
8853 }
8854 #endif
8856 if ((mini_get_cpu_features (cfg) & MONO_CPU_X86_SSE41) != 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
8873 }
8874 }
8875 }
8878 }
8879 #endif
8881 host_mgreg_t
8883 {
8885 }
8887 void
8889 {
8891 }
8893 /*
8894 * mono_arch_emit_load_aotconst:
8895 *
8896 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8897 * TARGET from the mscorlib GOT in full-aot code.
8898 * On AMD64, the result is placed into R11.
8899 */
8900 guint8*
8901 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8902 {
8907 }
8909 /*
8910 * mono_arch_get_trampolines:
8911 *
8912 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8913 * for AOT.
8914 */
8915 GSList *
8917 {
8919 }
8921 /* Soft Debug support */
8922 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8924 /*
8925 * mono_arch_set_breakpoint:
8926 *
8927 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8928 * The location should contain code emitted by OP_SEQ_POINT.
8929 */
8930 void
8932 {
8937 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8942 /* ip points to a mov r11, 0 */
8946 }
8947 }
8949 /*
8950 * mono_arch_clear_breakpoint:
8951 *
8952 * Clear the breakpoint at IP.
8953 */
8954 void
8956 {
8961 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8966 }
8967 }
8969 gboolean
8971 {
8972 /* We use soft breakpoints on amd64 */
8974 }
8976 /*
8977 * mono_arch_skip_breakpoint:
8978 *
8979 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8980 * we resume, the instruction is not executed again.
8981 */
8982 void
8984 {
8986 }
8988 /*
8989 * mono_arch_start_single_stepping:
8990 *
8991 * Start single stepping.
8992 */
8993 void
8995 {
8997 }
8999 /*
9000 * mono_arch_stop_single_stepping:
9001 *
9002 * Stop single stepping.
9003 */
9004 void
9006 {
9008 }
9010 /*
9011 * mono_arch_is_single_step_event:
9012 *
9013 * Return whenever the machine state in SIGCTX corresponds to a single
9014 * step event.
9015 */
9016 gboolean
9018 {
9019 /* We use soft breakpoints on amd64 */
9021 }
9023 /*
9024 * mono_arch_skip_single_step:
9025 *
9026 * Modify CTX so the ip is placed after the single step trigger instruction,
9027 * we resume, the instruction is not executed again.
9028 */
9029 void
9031 {
9033 }
9035 /*
9036 * mono_arch_create_seq_point_info:
9037 *
9038 * Return a pointer to a data structure which is used by the sequence
9039 * point implementation in AOTed code.
9040 */
9041 SeqPointInfo*
9043 {
9047 // FIXME: Add a free function
9051 code);
9058 // FIXME: Optimize the size
9059 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
9067 }
9070 }
9072 #endif
9074 gboolean
9076 {
9107 }
9108 }
9110 CallInfo*
9112 {
9114 }
9116 gpointer
9118 {
9121 #undef MONO_AOT_ICALL
9122 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
9129 }
9131 }