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[jit] Constant folding for some Math operations on doubles (#9281)
[mono-project.git] / mono / mini / mini-x86.c
blobf54b73e4204f2f590c49af4be2ecc87cd114e5f1
1 /**
2 * \file
3 * x86 backend for the Mono code generator
4 *
5 * Authors:
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
8 * Patrik Torstensson
9 *
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
14 */
15 #include "mini.h"
16 #include <string.h>
17 #include <math.h>
18 #ifdef HAVE_UNISTD_H
19 #include <unistd.h>
20 #endif
21
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
36
37 #include "mini-x86.h"
38 #include "cpu-x86.h"
39 #include "ir-emit.h"
40 #include "mini-gc.h"
41 #include "aot-runtime.h"
42 #include "mini-runtime.h"
43
44 #ifndef TARGET_WIN32
45 #ifdef MONO_XEN_OPT
46 static gboolean optimize_for_xen = TRUE;
47 #else
48 #define optimize_for_xen 0
49 #endif
50 #endif
51
52 static GENERATE_TRY_GET_CLASS_WITH_CACHE (math, "System", "Math")
53
54
55 /* The single step trampoline */
56 static gpointer ss_trampoline;
57
58 /* The breakpoint trampoline */
59 static gpointer bp_trampoline;
60
61 /* This mutex protects architecture specific caches */
62 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
63 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
64 static mono_mutex_t mini_arch_mutex;
65
66 #define ARGS_OFFSET 8
67
68 #ifdef TARGET_WIN32
69 /* Under windows, the default pinvoke calling convention is stdcall */
70 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
71 #else
72 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
73 #endif
74
75 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
76
77 #define OP_SEQ_POINT_BP_OFFSET 7
78
79 const char*
80 mono_arch_regname (int reg)
81 {
82 switch (reg) {
83 case X86_EAX: return "%eax";
84 case X86_EBX: return "%ebx";
85 case X86_ECX: return "%ecx";
86 case X86_EDX: return "%edx";
87 case X86_ESP: return "%esp";
88 case X86_EBP: return "%ebp";
89 case X86_EDI: return "%edi";
90 case X86_ESI: return "%esi";
91 }
92 return "unknown";
93 }
94
95 const char*
96 mono_arch_fregname (int reg)
97 {
98 switch (reg) {
99 case 0:
100 return "%fr0";
101 case 1:
102 return "%fr1";
103 case 2:
104 return "%fr2";
105 case 3:
106 return "%fr3";
107 case 4:
108 return "%fr4";
109 case 5:
110 return "%fr5";
111 case 6:
112 return "%fr6";
113 case 7:
114 return "%fr7";
115 default:
116 return "unknown";
117 }
118 }
119
120 const char *
121 mono_arch_xregname (int reg)
122 {
123 switch (reg) {
124 case 0:
125 return "%xmm0";
126 case 1:
127 return "%xmm1";
128 case 2:
129 return "%xmm2";
130 case 3:
131 return "%xmm3";
132 case 4:
133 return "%xmm4";
134 case 5:
135 return "%xmm5";
136 case 6:
137 return "%xmm6";
138 case 7:
139 return "%xmm7";
140 default:
141 return "unknown";
142 }
143 }
144
145 void
146 mono_x86_patch (unsigned char* code, gpointer target)
147 {
148 x86_patch (code, (unsigned char*)target);
149 }
150
151 #define FLOAT_PARAM_REGS 0
152
153 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
154
155 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
156 {
157 if (!sig->pinvoke)
158 return NULL;
159
160 switch (sig->call_convention) {
161 case MONO_CALL_THISCALL:
162 return thiscall_param_regs;
163 default:
164 return NULL;
165 }
166 }
167
168 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
169 #define SMALL_STRUCTS_IN_REGS
170 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
171 #endif
172
173 static void inline
174 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
175 {
176 ainfo->offset = *stack_size;
177
178 if (!param_regs || param_regs [*gr] == X86_NREG) {
179 ainfo->storage = ArgOnStack;
180 ainfo->nslots = 1;
181 (*stack_size) += sizeof (target_mgreg_t);
182 }
183 else {
184 ainfo->storage = ArgInIReg;
185 ainfo->reg = param_regs [*gr];
186 (*gr) ++;
187 }
188 }
189
190 static void inline
191 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
192 {
193 ainfo->offset = *stack_size;
194
195 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
196
197 ainfo->storage = ArgOnStack;
198 (*stack_size) += sizeof (target_mgreg_t) * 2;
199 ainfo->nslots = 2;
200 }
201
202 static void inline
203 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
204 {
205 ainfo->offset = *stack_size;
206
207 if (*gr >= FLOAT_PARAM_REGS) {
208 ainfo->storage = ArgOnStack;
209 (*stack_size) += is_double ? 8 : 4;
210 ainfo->nslots = is_double ? 2 : 1;
211 }
212 else {
213 /* A double register */
214 if (is_double)
215 ainfo->storage = ArgInDoubleSSEReg;
216 else
217 ainfo->storage = ArgInFloatSSEReg;
218 ainfo->reg = *gr;
219 (*gr) += 1;
220 }
221 }
222
223
224 static void
225 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
226 gboolean is_return,
227 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
228 {
229 guint32 size;
230 MonoClass *klass;
231
232 klass = mono_class_from_mono_type_internal (type);
233 size = mini_type_stack_size_full (m_class_get_byval_arg (klass), NULL, sig->pinvoke);
234
235 #if defined(TARGET_WIN32)
236 /*
237 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
238 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
239 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
240 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
241 * it must be represented in call and cannot be dropped.
242 */
243 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
244 /* Empty structs (1 byte size) needs to be represented in a stack slot */
245 ainfo->pass_empty_struct = TRUE;
246 size = 1;
247 }
248 #endif
249
250 #ifdef SMALL_STRUCTS_IN_REGS
251 if (sig->pinvoke && is_return) {
252 MonoMarshalType *info;
253
254 info = mono_marshal_load_type_info (klass);
255 g_assert (info);
256
257 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
258
259 /* Ignore empty struct return value, if used. */
260 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
261 ainfo->storage = ArgValuetypeInReg;
262 return;
263 }
264
265 /*
266 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
267 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
268 * This is different compared to for example float or double return types (not in struct) that will be returned
269 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
270 *
271 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
272 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
273 * This means that structs with one float or double will be returned in ST(0). For more details,
274 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
275 */
276 #if !defined(TARGET_WIN32)
277
278 /* Special case structs with only a float member */
279 if (info->num_fields == 1) {
280 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
281 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
282 ainfo->storage = ArgValuetypeInReg;
283 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
284 return;
285 }
286 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
287 ainfo->storage = ArgValuetypeInReg;
288 ainfo->pair_storage [0] = ArgOnFloatFpStack;
289 return;
290 }
291 }
292 #endif
293
294 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
295 ainfo->storage = ArgValuetypeInReg;
296 ainfo->pair_storage [0] = ArgInIReg;
297 ainfo->pair_regs [0] = return_regs [0];
298 if (info->native_size > 4) {
299 ainfo->pair_storage [1] = ArgInIReg;
300 ainfo->pair_regs [1] = return_regs [1];
301 }
302 return;
303 }
304 }
305 #endif
306
307 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
308 g_assert (size <= 4);
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->reg = param_regs [*gr];
311 (*gr)++;
312 return;
313 }
314
315 ainfo->offset = *stack_size;
316 ainfo->storage = ArgOnStack;
317 *stack_size += ALIGN_TO (size, sizeof (target_mgreg_t));
318 ainfo->nslots = ALIGN_TO (size, sizeof (target_mgreg_t)) / sizeof (target_mgreg_t);
319 }
320
321 /*
322 * get_call_info:
323 *
324 * Obtain information about a call according to the calling convention.
325 * For x86 ELF, see the "System V Application Binary Interface Intel386
326 * Architecture Processor Supplment, Fourth Edition" document for more
327 * information.
328 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
329 */
330 static CallInfo*
331 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
332 {
333 guint32 i, gr, fr, pstart;
334 const guint32 *param_regs;
335 MonoType *ret_type;
336 int n = sig->hasthis + sig->param_count;
337 guint32 stack_size = 0;
338 gboolean is_pinvoke = sig->pinvoke;
339
340 gr = 0;
341 fr = 0;
342 cinfo->nargs = n;
343
344 param_regs = callconv_param_regs(sig);
345
346 /* return value */
347 {
348 ret_type = mini_get_underlying_type (sig->ret);
349 switch (ret_type->type) {
350 case MONO_TYPE_I1:
351 case MONO_TYPE_U1:
352 case MONO_TYPE_I2:
353 case MONO_TYPE_U2:
354 case MONO_TYPE_I4:
355 case MONO_TYPE_U4:
356 case MONO_TYPE_I:
357 case MONO_TYPE_U:
358 case MONO_TYPE_PTR:
359 case MONO_TYPE_FNPTR:
360 case MONO_TYPE_OBJECT:
361 cinfo->ret.storage = ArgInIReg;
362 cinfo->ret.reg = X86_EAX;
363 break;
364 case MONO_TYPE_U8:
365 case MONO_TYPE_I8:
366 cinfo->ret.storage = ArgInIReg;
367 cinfo->ret.reg = X86_EAX;
368 cinfo->ret.is_pair = TRUE;
369 break;
370 case MONO_TYPE_R4:
371 cinfo->ret.storage = ArgOnFloatFpStack;
372 break;
373 case MONO_TYPE_R8:
374 cinfo->ret.storage = ArgOnDoubleFpStack;
375 break;
376 case MONO_TYPE_GENERICINST:
377 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
378 cinfo->ret.storage = ArgInIReg;
379 cinfo->ret.reg = X86_EAX;
380 break;
381 }
382 if (mini_is_gsharedvt_type (ret_type)) {
383 cinfo->ret.storage = ArgOnStack;
384 cinfo->vtype_retaddr = TRUE;
385 break;
386 }
387 /* Fall through */
388 case MONO_TYPE_VALUETYPE:
389 case MONO_TYPE_TYPEDBYREF: {
390 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
391
392 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
393 if (cinfo->ret.storage == ArgOnStack) {
394 cinfo->vtype_retaddr = TRUE;
395 /* The caller passes the address where the value is stored */
396 }
397 break;
398 }
399 case MONO_TYPE_VAR:
400 case MONO_TYPE_MVAR:
401 g_assert (mini_is_gsharedvt_type (ret_type));
402 cinfo->ret.storage = ArgOnStack;
403 cinfo->vtype_retaddr = TRUE;
404 break;
405 case MONO_TYPE_VOID:
406 cinfo->ret.storage = ArgNone;
407 break;
408 default:
409 g_error ("Can't handle as return value 0x%x", ret_type->type);
410 }
411 }
412
413 pstart = 0;
414 /*
415 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
416 * the first argument, allowing 'this' to be always passed in the first arg reg.
417 * Also do this if the first argument is a reference type, since virtual calls
418 * are sometimes made using calli without sig->hasthis set, like in the delegate
419 * invoke wrappers.
420 */
421 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
422 if (sig->hasthis) {
423 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
424 } else {
425 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
426 pstart = 1;
427 }
428 cinfo->vret_arg_offset = stack_size;
429 add_general (&gr, NULL, &stack_size, &cinfo->ret);
430 cinfo->vret_arg_index = 1;
431 } else {
432 /* this */
433 if (sig->hasthis)
434 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
435
436 if (cinfo->vtype_retaddr)
437 add_general (&gr, NULL, &stack_size, &cinfo->ret);
438 }
439
440 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
441 fr = FLOAT_PARAM_REGS;
442
443 /* Emit the signature cookie just before the implicit arguments */
444 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
445 }
446
447 for (i = pstart; i < sig->param_count; ++i) {
448 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
449 MonoType *ptype;
450
451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
452 /* We allways pass the sig cookie on the stack for simplicity */
453 /*
454 * Prevent implicit arguments + the sig cookie from being passed
455 * in registers.
456 */
457 fr = FLOAT_PARAM_REGS;
458
459 /* Emit the signature cookie just before the implicit arguments */
460 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
461 }
462
463 if (sig->params [i]->byref) {
464 add_general (&gr, param_regs, &stack_size, ainfo);
465 continue;
466 }
467 ptype = mini_get_underlying_type (sig->params [i]);
468 switch (ptype->type) {
469 case MONO_TYPE_I1:
470 case MONO_TYPE_U1:
471 add_general (&gr, param_regs, &stack_size, ainfo);
472 break;
473 case MONO_TYPE_I2:
474 case MONO_TYPE_U2:
475 add_general (&gr, param_regs, &stack_size, ainfo);
476 break;
477 case MONO_TYPE_I4:
478 case MONO_TYPE_U4:
479 add_general (&gr, param_regs, &stack_size, ainfo);
480 break;
481 case MONO_TYPE_I:
482 case MONO_TYPE_U:
483 case MONO_TYPE_PTR:
484 case MONO_TYPE_FNPTR:
485 case MONO_TYPE_OBJECT:
486 add_general (&gr, param_regs, &stack_size, ainfo);
487 break;
488 case MONO_TYPE_GENERICINST:
489 if (!mono_type_generic_inst_is_valuetype (ptype)) {
490 add_general (&gr, param_regs, &stack_size, ainfo);
491 break;
492 }
493 if (mini_is_gsharedvt_type (ptype)) {
494 /* gsharedvt arguments are passed by ref */
495 add_general (&gr, param_regs, &stack_size, ainfo);
496 g_assert (ainfo->storage == ArgOnStack);
497 ainfo->storage = ArgGSharedVt;
498 break;
499 }
500 /* Fall through */
501 case MONO_TYPE_VALUETYPE:
502 case MONO_TYPE_TYPEDBYREF:
503 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
504 break;
505 case MONO_TYPE_U8:
506 case MONO_TYPE_I8:
507 add_general_pair (&gr, param_regs, &stack_size, ainfo);
508 break;
509 case MONO_TYPE_R4:
510 add_float (&fr, &stack_size, ainfo, FALSE);
511 break;
512 case MONO_TYPE_R8:
513 add_float (&fr, &stack_size, ainfo, TRUE);
514 break;
515 case MONO_TYPE_VAR:
516 case MONO_TYPE_MVAR:
517 /* gsharedvt arguments are passed by ref */
518 g_assert (mini_is_gsharedvt_type (ptype));
519 add_general (&gr, param_regs, &stack_size, ainfo);
520 g_assert (ainfo->storage == ArgOnStack);
521 ainfo->storage = ArgGSharedVt;
522 break;
523 default:
524 g_error ("unexpected type 0x%x", ptype->type);
525 g_assert_not_reached ();
526 }
527 }
528
529 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
530 fr = FLOAT_PARAM_REGS;
531
532 /* Emit the signature cookie just before the implicit arguments */
533 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
534 }
535
536 if (cinfo->vtype_retaddr) {
537 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
538 cinfo->callee_stack_pop = 4;
539 } else if (CALLCONV_IS_STDCALL (sig)) {
540 /* Have to compensate for the stack space popped by the native callee */
541 cinfo->callee_stack_pop = stack_size;
542 }
543
544 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
545 cinfo->need_stack_align = TRUE;
546 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
547 stack_size += cinfo->stack_align_amount;
548 }
549
550 cinfo->stack_usage = stack_size;
551 cinfo->reg_usage = gr;
552 cinfo->freg_usage = fr;
553 return cinfo;
554 }
555
556 static CallInfo*
557 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
558 {
559 int n = sig->hasthis + sig->param_count;
560 CallInfo *cinfo;
561
562 if (mp)
563 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
564 else
565 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
566
567 return get_call_info_internal (cinfo, sig);
568 }
569
570 static gboolean storage_in_ireg (ArgStorage storage)
571 {
572 return (storage == ArgInIReg || storage == ArgValuetypeInReg);
573 }
574
575 /*
576 * mono_arch_get_argument_info:
577 * @csig: a method signature
578 * @param_count: the number of parameters to consider
579 * @arg_info: an array to store the result infos
580 *
581 * Gathers information on parameters such as size, alignment and
582 * padding. arg_info should be large enought to hold param_count + 1 entries.
583 *
584 * Returns the size of the argument area on the stack.
585 * This should be signal safe, since it is called from
586 * mono_arch_unwind_frame ().
587 * FIXME: The metadata calls might not be signal safe.
588 */
589 int
590 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
591 {
592 int len, k, args_size = 0;
593 int size, pad;
594 guint32 align;
595 int offset = 8;
596 CallInfo *cinfo;
597 int prev_stackarg;
598 int num_regs;
599
600 /* Avoid g_malloc as it is not signal safe */
601 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
602 cinfo = (CallInfo*)g_alloca (len);
603 memset (cinfo, 0, len);
604
605 cinfo = get_call_info_internal (cinfo, csig);
606
607 arg_info [0].offset = offset;
608
609 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
610 args_size += sizeof (target_mgreg_t);
611 offset += 4;
612 }
613
614 if (csig->hasthis && !storage_in_ireg (cinfo->args [0].storage)) {
615 args_size += sizeof (target_mgreg_t);
616 offset += 4;
617 }
618
619 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
620 /* Emitted after this */
621 args_size += sizeof (target_mgreg_t);
622 offset += 4;
623 }
624
625 arg_info [0].size = args_size;
626 prev_stackarg = 0;
627
628 for (k = 0; k < param_count; k++) {
629 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
630
631 if (storage_in_ireg (cinfo->args [csig->hasthis + k].storage)) {
632 /* not in stack, we'll give it an offset at the end */
633 arg_info [k + 1].pad = 0;
634 arg_info [k + 1].size = size;
635 } else {
636 /* ignore alignment for now */
637 align = 1;
638
639 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
640 arg_info [prev_stackarg].pad = pad;
641 args_size += size;
642 arg_info [k + 1].pad = 0;
643 arg_info [k + 1].size = size;
644 offset += pad;
645 arg_info [k + 1].offset = offset;
646 offset += size;
647 prev_stackarg = k + 1;
648 }
649
650 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
651 /* Emitted after the first arg */
652 args_size += sizeof (target_mgreg_t);
653 offset += 4;
654 }
655 }
656
657 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
658 align = MONO_ARCH_FRAME_ALIGNMENT;
659 else
660 align = 4;
661 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
662 arg_info [k].pad = pad;
663
664 /* Add offsets for any reg parameters */
665 num_regs = 0;
666 if (csig->hasthis && storage_in_ireg (cinfo->args [0].storage))
667 arg_info [0].offset = args_size + 4 * num_regs++;
668 for (k=0; k < param_count; k++) {
669 if (storage_in_ireg (cinfo->args[csig->hasthis + k].storage)) {
670 arg_info [k + 1].offset = args_size + 4 * num_regs++;
671 }
672 }
673
674 return args_size;
675 }
676
677 #ifndef DISABLE_JIT
678
679 gboolean
680 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
681 {
682 g_assert (caller_sig);
683 g_assert (callee_sig);
684
685 // Direct AOT calls usually go through the PLT/GOT.
686 // Unless we can determine here if is_direct_callable will return TRUE?
687 // But the PLT/GOT is addressed with nonvolatile ebx, which
688 // gets restored before the jump.
689 // See https://github.com/mono/mono/commit/f5373adc8a89d4b0d1d549fdd6d9adc3ded4b400
690 // See https://github.com/mono/mono/issues/11265
691 if (!virtual_ && cfg->compile_aot && !cfg->full_aot)
692 return FALSE;
693
694 CallInfo *caller_info = get_call_info (NULL, caller_sig);
695 CallInfo *callee_info = get_call_info (NULL, callee_sig);
696
697 /*
698 * Tailcalls with more callee stack usage than the caller cannot be supported, since
699 * the extra stack space would be left on the stack after the tailcall.
700 */
701 gboolean res = IS_SUPPORTED_TAILCALL (callee_info->stack_usage <= caller_info->stack_usage)
702 && IS_SUPPORTED_TAILCALL (caller_info->ret.storage == callee_info->ret.storage);
703 if (!res && !mono_tailcall_print_enabled ())
704 goto exit;
705
706 // Limit stack_usage to 1G.
707 res &= IS_SUPPORTED_TAILCALL (callee_info->stack_usage < (1 << 30));
708 res &= IS_SUPPORTED_TAILCALL (caller_info->stack_usage < (1 << 30));
709
710 exit:
711 g_free (caller_info);
712 g_free (callee_info);
713
714 return res;
715 }
716
717 #endif
718
719 /*
720 * Initialize the cpu to execute managed code.
721 */
722 void
723 mono_arch_cpu_init (void)
724 {
725 /* spec compliance requires running with double precision */
726 #ifndef _MSC_VER
727 guint16 fpcw;
728
729 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
730 fpcw &= ~X86_FPCW_PRECC_MASK;
731 fpcw |= X86_FPCW_PREC_DOUBLE;
732 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
733 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
734 #else
735 _control87 (_PC_53, MCW_PC);
736 #endif
737 }
738
739 /*
740 * Initialize architecture specific code.
741 */
742 void
743 mono_arch_init (void)
744 {
745 mono_os_mutex_init_recursive (&mini_arch_mutex);
746
747 if (!mono_aot_only)
748 bp_trampoline = mini_get_breakpoint_trampoline ();
749
750 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
751 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
752 #if defined (MONO_ARCH_GSHAREDVT_SUPPORTED)
753 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
754 #endif
755 }
756
757 /*
758 * Cleanup architecture specific code.
759 */
760 void
761 mono_arch_cleanup (void)
762 {
763 mono_os_mutex_destroy (&mini_arch_mutex);
764 }
765
766 /*
767 * This function returns the optimizations supported on this cpu.
768 */
769 guint32
770 mono_arch_cpu_optimizations (guint32 *exclude_mask)
771 {
772 guint32 opts = 0;
773
774 *exclude_mask = 0;
775
776 if (mono_hwcap_x86_has_cmov) {
777 opts |= MONO_OPT_CMOV;
778
779 if (mono_hwcap_x86_has_fcmov)
780 opts |= MONO_OPT_FCMOV;
781 else
782 *exclude_mask |= MONO_OPT_FCMOV;
783 } else {
784 *exclude_mask |= MONO_OPT_CMOV;
785 }
786
787 if (mono_hwcap_x86_has_sse2)
788 opts |= MONO_OPT_SSE2;
789 else
790 *exclude_mask |= MONO_OPT_SSE2;
791
792 #ifdef MONO_ARCH_SIMD_INTRINSICS
793 /*SIMD intrinsics require at least SSE2.*/
794 if (!mono_hwcap_x86_has_sse2)
795 *exclude_mask |= MONO_OPT_SIMD;
796 #endif
797
798 return opts;
799 }
800
801 /*
802 * This function test for all SSE functions supported.
803 *
804 * Returns a bitmask corresponding to all supported versions.
805 *
806 */
807 guint32
808 mono_arch_cpu_enumerate_simd_versions (void)
809 {
810 guint32 sse_opts = 0;
811
812 if (mono_hwcap_x86_has_sse1)
813 sse_opts |= SIMD_VERSION_SSE1;
814
815 if (mono_hwcap_x86_has_sse2)
816 sse_opts |= SIMD_VERSION_SSE2;
817
818 if (mono_hwcap_x86_has_sse3)
819 sse_opts |= SIMD_VERSION_SSE3;
820
821 if (mono_hwcap_x86_has_ssse3)
822 sse_opts |= SIMD_VERSION_SSSE3;
823
824 if (mono_hwcap_x86_has_sse41)
825 sse_opts |= SIMD_VERSION_SSE41;
826
827 if (mono_hwcap_x86_has_sse42)
828 sse_opts |= SIMD_VERSION_SSE42;
829
830 if (mono_hwcap_x86_has_sse4a)
831 sse_opts |= SIMD_VERSION_SSE4a;
832
833 return sse_opts;
834 }
835
836 /*
837 * Determine whenever the trap whose info is in SIGINFO is caused by
838 * integer overflow.
839 */
840 gboolean
841 mono_arch_is_int_overflow (void *sigctx, void *info)
842 {
843 MonoContext ctx;
844 guint8* ip;
845
846 mono_sigctx_to_monoctx (sigctx, &ctx);
847
848 ip = (guint8*)ctx.eip;
849
850 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
851 gint32 reg;
852
853 /* idiv REG */
854 switch (x86_modrm_rm (ip [1])) {
855 case X86_EAX:
856 reg = ctx.eax;
857 break;
858 case X86_ECX:
859 reg = ctx.ecx;
860 break;
861 case X86_EDX:
862 reg = ctx.edx;
863 break;
864 case X86_EBX:
865 reg = ctx.ebx;
866 break;
867 case X86_ESI:
868 reg = ctx.esi;
869 break;
870 case X86_EDI:
871 reg = ctx.edi;
872 break;
873 default:
874 g_assert_not_reached ();
875 reg = -1;
876 }
877
878 if (reg == -1)
879 return TRUE;
880 }
881
882 return FALSE;
883 }
884
885 GList *
886 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
887 {
888 GList *vars = NULL;
889 int i;
890
891 for (i = 0; i < cfg->num_varinfo; i++) {
892 MonoInst *ins = cfg->varinfo [i];
893 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
894
895 /* unused vars */
896 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
897 continue;
898
899 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
900 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
901 continue;
902
903 /* we dont allocate I1 to registers because there is no simply way to sign extend
904 * 8bit quantities in caller saved registers on x86 */
905 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
906 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
907 g_assert (i == vmv->idx);
908 vars = g_list_prepend (vars, vmv);
909 }
910 }
911
912 vars = mono_varlist_sort (cfg, vars, 0);
913
914 return vars;
915 }
916
917 GList *
918 mono_arch_get_global_int_regs (MonoCompile *cfg)
919 {
920 GList *regs = NULL;
921
922 /* we can use 3 registers for global allocation */
923 regs = g_list_prepend (regs, (gpointer)X86_EBX);
924 regs = g_list_prepend (regs, (gpointer)X86_ESI);
925 regs = g_list_prepend (regs, (gpointer)X86_EDI);
926
927 return regs;
928 }
929
930 /*
931 * mono_arch_regalloc_cost:
932 *
933 * Return the cost, in number of memory references, of the action of
934 * allocating the variable VMV into a register during global register
935 * allocation.
936 */
937 guint32
938 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
939 {
940 MonoInst *ins = cfg->varinfo [vmv->idx];
941
942 if (cfg->method->save_lmf)
943 /* The register is already saved */
944 return (ins->opcode == OP_ARG) ? 1 : 0;
945 else
946 /* push+pop+possible load if it is an argument */
947 return (ins->opcode == OP_ARG) ? 3 : 2;
948 }
949
950 static void
951 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
952 {
953 static int inited = FALSE;
954 static int count = 0;
955
956 if (cfg->arch.need_stack_frame_inited) {
957 g_assert (cfg->arch.need_stack_frame == flag);
958 return;
959 }
960
961 cfg->arch.need_stack_frame = flag;
962 cfg->arch.need_stack_frame_inited = TRUE;
963
964 if (flag)
965 return;
966
967 if (!inited) {
968 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
969 inited = TRUE;
970 }
971 ++count;
972
973 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
974 }
975
976 static gboolean
977 needs_stack_frame (MonoCompile *cfg)
978 {
979 MonoMethodSignature *sig;
980 MonoMethodHeader *header;
981 gboolean result = FALSE;
982
983 #if defined (__APPLE__)
984 /*OSX requires stack frame code to have the correct alignment. */
985 return TRUE;
986 #endif
987
988 if (cfg->arch.need_stack_frame_inited)
989 return cfg->arch.need_stack_frame;
990
991 header = cfg->header;
992 sig = mono_method_signature_internal (cfg->method);
993
994 if (cfg->disable_omit_fp)
995 result = TRUE;
996 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
997 result = TRUE;
998 else if (cfg->method->save_lmf)
999 result = TRUE;
1000 else if (cfg->stack_offset)
1001 result = TRUE;
1002 else if (cfg->param_area)
1003 result = TRUE;
1004 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAILCALL))
1005 result = TRUE;
1006 else if (header->num_clauses)
1007 result = TRUE;
1008 else if (sig->param_count + sig->hasthis)
1009 result = TRUE;
1010 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1011 result = TRUE;
1012
1013 set_needs_stack_frame (cfg, result);
1014
1015 return cfg->arch.need_stack_frame;
1016 }
1017
1018 /*
1019 * Set var information according to the calling convention. X86 version.
1020 * The locals var stuff should most likely be split in another method.
1021 */
1022 void
1023 mono_arch_allocate_vars (MonoCompile *cfg)
1024 {
1025 MonoMethodSignature *sig;
1026 MonoMethodHeader *header;
1027 MonoInst *inst;
1028 guint32 locals_stack_size, locals_stack_align;
1029 int i, offset;
1030 gint32 *offsets;
1031 CallInfo *cinfo;
1032
1033 header = cfg->header;
1034 sig = mono_method_signature_internal (cfg->method);
1035
1036 if (!cfg->arch.cinfo)
1037 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1038 cinfo = cfg->arch.cinfo;
1039
1040 cfg->frame_reg = X86_EBP;
1041 offset = 0;
1042
1043 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1044 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1045 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1046 }
1047
1048 /* Reserve space to save LMF and caller saved registers */
1049
1050 if (cfg->method->save_lmf) {
1051 /* The LMF var is allocated normally */
1052 } else {
1053 if (cfg->used_int_regs & (1 << X86_EBX)) {
1054 offset += 4;
1055 }
1056
1057 if (cfg->used_int_regs & (1 << X86_EDI)) {
1058 offset += 4;
1059 }
1060
1061 if (cfg->used_int_regs & (1 << X86_ESI)) {
1062 offset += 4;
1063 }
1064 }
1065
1066 switch (cinfo->ret.storage) {
1067 case ArgValuetypeInReg:
1068 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1069 offset += 8;
1070 cfg->ret->opcode = OP_REGOFFSET;
1071 cfg->ret->inst_basereg = X86_EBP;
1072 cfg->ret->inst_offset = - offset;
1073 break;
1074 default:
1075 break;
1076 }
1077
1078 /* Allocate a local for any register arguments that need them. */
1079 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1080 ArgInfo *ainfo = &cinfo->args [i];
1081 inst = cfg->args [i];
1082 if (inst->opcode != OP_REGVAR && storage_in_ireg (ainfo->storage)) {
1083 offset += 4;
1084 cfg->args[i]->opcode = OP_REGOFFSET;
1085 cfg->args[i]->inst_basereg = X86_EBP;
1086 cfg->args[i]->inst_offset = - offset;
1087 }
1088 }
1089
1090 /* Allocate locals */
1091 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1092 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1093 char *mname = mono_method_full_name (cfg->method, TRUE);
1094 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1095 g_free (mname);
1096 return;
1097 }
1098 if (locals_stack_align) {
1099 int prev_offset = offset;
1100
1101 offset += (locals_stack_align - 1);
1102 offset &= ~(locals_stack_align - 1);
1103
1104 while (prev_offset < offset) {
1105 prev_offset += 4;
1106 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1107 }
1108 }
1109 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1110 cfg->locals_max_stack_offset = - offset;
1111 /*
1112 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1113 * have locals larger than 8 bytes we need to make sure that
1114 * they have the appropriate offset.
1115 */
1116 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1117 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (target_mgreg_t) * 2;
1118 offset += extra_size;
1119 locals_stack_size += extra_size;
1120 }
1121 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1122 if (offsets [i] != -1) {
1123 MonoInst *inst = cfg->varinfo [i];
1124 inst->opcode = OP_REGOFFSET;
1125 inst->inst_basereg = X86_EBP;
1126 inst->inst_offset = - (offset + offsets [i]);
1127 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1128 }
1129 }
1130 offset += locals_stack_size;
1131
1132
1133 /*
1134 * Allocate arguments+return value
1135 */
1136
1137 switch (cinfo->ret.storage) {
1138 case ArgOnStack:
1139 if (cfg->vret_addr) {
1140 /*
1141 * In the new IR, the cfg->vret_addr variable represents the
1142 * vtype return value.
1143 */
1144 cfg->vret_addr->opcode = OP_REGOFFSET;
1145 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1146 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1147 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1148 printf ("vret_addr =");
1149 mono_print_ins (cfg->vret_addr);
1150 }
1151 } else {
1152 cfg->ret->opcode = OP_REGOFFSET;
1153 cfg->ret->inst_basereg = X86_EBP;
1154 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1155 }
1156 break;
1157 case ArgValuetypeInReg:
1158 break;
1159 case ArgInIReg:
1160 cfg->ret->opcode = OP_REGVAR;
1161 cfg->ret->inst_c0 = cinfo->ret.reg;
1162 cfg->ret->dreg = cinfo->ret.reg;
1163 break;
1164 case ArgNone:
1165 case ArgOnFloatFpStack:
1166 case ArgOnDoubleFpStack:
1167 break;
1168 default:
1169 g_assert_not_reached ();
1170 }
1171
1172 if (sig->call_convention == MONO_CALL_VARARG) {
1173 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1174 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1175 }
1176
1177 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1178 ArgInfo *ainfo = &cinfo->args [i];
1179 inst = cfg->args [i];
1180 if (inst->opcode != OP_REGVAR) {
1181 if (storage_in_ireg (ainfo->storage)) {
1182 /* We already allocated locals for register arguments. */
1183 } else {
1184 inst->opcode = OP_REGOFFSET;
1185 inst->inst_basereg = X86_EBP;
1186 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1187 }
1188 }
1189 }
1190
1191 cfg->stack_offset = offset;
1192 }
1193
1194 void
1195 mono_arch_create_vars (MonoCompile *cfg)
1196 {
1197 MonoType *sig_ret;
1198 MonoMethodSignature *sig;
1199 CallInfo *cinfo;
1200
1201 sig = mono_method_signature_internal (cfg->method);
1202
1203 if (!cfg->arch.cinfo)
1204 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1205 cinfo = cfg->arch.cinfo;
1206
1207 sig_ret = mini_get_underlying_type (sig->ret);
1208
1209 if (cinfo->ret.storage == ArgValuetypeInReg)
1210 cfg->ret_var_is_local = TRUE;
1211 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1212 cfg->vret_addr = mono_compile_create_var (cfg, mono_get_int_type (), OP_ARG);
1213 }
1214
1215 if (cfg->gen_sdb_seq_points) {
1216 MonoInst *ins;
1217
1218 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1219 ins->flags |= MONO_INST_VOLATILE;
1220 cfg->arch.ss_tramp_var = ins;
1221
1222 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1223 ins->flags |= MONO_INST_VOLATILE;
1224 cfg->arch.bp_tramp_var = ins;
1225 }
1226
1227 if (cfg->method->save_lmf) {
1228 cfg->create_lmf_var = TRUE;
1229 cfg->lmf_ir = TRUE;
1230 }
1231
1232 cfg->arch_eh_jit_info = 1;
1233 }
1234
1235 /*
1236 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1237 * so we try to do it just once when we have multiple fp arguments in a row.
1238 * We don't use this mechanism generally because for int arguments the generated code
1239 * is slightly bigger and new generation cpus optimize away the dependency chains
1240 * created by push instructions on the esp value.
1241 * fp_arg_setup is the first argument in the execution sequence where the esp register
1242 * is modified.
1243 */
1244 static G_GNUC_UNUSED int
1245 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1246 {
1247 int fp_space = 0;
1248 MonoType *t;
1249
1250 for (; start_arg < sig->param_count; ++start_arg) {
1251 t = mini_get_underlying_type (sig->params [start_arg]);
1252 if (!t->byref && t->type == MONO_TYPE_R8) {
1253 fp_space += sizeof (double);
1254 *fp_arg_setup = start_arg;
1255 } else {
1256 break;
1257 }
1258 }
1259 return fp_space;
1260 }
1261
1262 static void
1263 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1264 {
1265 MonoMethodSignature *tmp_sig;
1266 int sig_reg;
1267
1268 /*
1269 * mono_ArgIterator_Setup assumes the signature cookie is
1270 * passed first and all the arguments which were before it are
1271 * passed on the stack after the signature. So compensate by
1272 * passing a different signature.
1273 */
1274 tmp_sig = mono_metadata_signature_dup (call->signature);
1275 tmp_sig->param_count -= call->signature->sentinelpos;
1276 tmp_sig->sentinelpos = 0;
1277 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1278
1279 if (cfg->compile_aot) {
1280 sig_reg = mono_alloc_ireg (cfg);
1281 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1282 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1283 } else {
1284 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1285 }
1286 }
1287
1288 #ifdef ENABLE_LLVM
1289 LLVMCallInfo*
1290 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1291 {
1292 int i, n;
1293 CallInfo *cinfo;
1294 ArgInfo *ainfo;
1295 LLVMCallInfo *linfo;
1296 MonoType *t, *sig_ret;
1297
1298 n = sig->param_count + sig->hasthis;
1299
1300 cinfo = get_call_info (cfg->mempool, sig);
1301 sig_ret = sig->ret;
1302
1303 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1304
1305 /*
1306 * LLVM always uses the native ABI while we use our own ABI, the
1307 * only difference is the handling of vtypes:
1308 * - we only pass/receive them in registers in some cases, and only
1309 * in 1 or 2 integer registers.
1310 */
1311 if (cinfo->ret.storage == ArgValuetypeInReg) {
1312 if (sig->pinvoke) {
1313 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1314 cfg->disable_llvm = TRUE;
1315 return linfo;
1316 }
1317
1318 cfg->exception_message = g_strdup ("vtype ret in call");
1319 cfg->disable_llvm = TRUE;
1320 /*
1321 linfo->ret.storage = LLVMArgVtypeInReg;
1322 for (j = 0; j < 2; ++j)
1323 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1324 */
1325 }
1326
1327 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1328 /* Vtype returned using a hidden argument */
1329 linfo->ret.storage = LLVMArgVtypeRetAddr;
1330 linfo->vret_arg_index = cinfo->vret_arg_index;
1331 }
1332
1333 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1334 // FIXME:
1335 cfg->exception_message = g_strdup ("vtype ret in call");
1336 cfg->disable_llvm = TRUE;
1337 }
1338
1339 for (i = 0; i < n; ++i) {
1340 ainfo = cinfo->args + i;
1341
1342 if (i >= sig->hasthis)
1343 t = sig->params [i - sig->hasthis];
1344 else
1345 t = mono_get_int_type ();
1346
1347 linfo->args [i].storage = LLVMArgNone;
1348
1349 switch (ainfo->storage) {
1350 case ArgInIReg:
1351 linfo->args [i].storage = LLVMArgNormal;
1352 break;
1353 case ArgInDoubleSSEReg:
1354 case ArgInFloatSSEReg:
1355 linfo->args [i].storage = LLVMArgNormal;
1356 break;
1357 case ArgOnStack:
1358 if (mini_type_is_vtype (t)) {
1359 if (mono_class_value_size (mono_class_from_mono_type_internal (t), NULL) == 0)
1360 /* LLVM seems to allocate argument space for empty structures too */
1361 linfo->args [i].storage = LLVMArgNone;
1362 else
1363 linfo->args [i].storage = LLVMArgVtypeByVal;
1364 } else {
1365 linfo->args [i].storage = LLVMArgNormal;
1366 }
1367 break;
1368 case ArgValuetypeInReg:
1369 if (sig->pinvoke) {
1370 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1371 cfg->disable_llvm = TRUE;
1372 return linfo;
1373 }
1374
1375 cfg->exception_message = g_strdup ("vtype arg");
1376 cfg->disable_llvm = TRUE;
1377 /*
1378 linfo->args [i].storage = LLVMArgVtypeInReg;
1379 for (j = 0; j < 2; ++j)
1380 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1381 */
1382 break;
1383 case ArgGSharedVt:
1384 linfo->args [i].storage = LLVMArgGSharedVt;
1385 break;
1386 default:
1387 cfg->exception_message = g_strdup ("ainfo->storage");
1388 cfg->disable_llvm = TRUE;
1389 break;
1390 }
1391 }
1392
1393 return linfo;
1394 }
1395 #endif
1396
1397 static void
1398 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1399 {
1400 if (cfg->compute_gc_maps) {
1401 MonoInst *def;
1402
1403 /* Needs checking if the feature will be enabled again */
1404 g_assert_not_reached ();
1405
1406 /* On x86, the offsets are from the sp value before the start of the call sequence */
1407 if (t == NULL)
1408 t = mono_get_int_type ();
1409 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1410 }
1411 }
1412
1413 void
1414 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1415 {
1416 MonoType *sig_ret;
1417 MonoInst *arg, *in;
1418 MonoMethodSignature *sig;
1419 int i, j, n;
1420 CallInfo *cinfo;
1421 int sentinelpos = 0, sp_offset = 0;
1422
1423 sig = call->signature;
1424 n = sig->param_count + sig->hasthis;
1425 sig_ret = mini_get_underlying_type (sig->ret);
1426
1427 cinfo = get_call_info (cfg->mempool, sig);
1428 call->call_info = cinfo;
1429
1430 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1431 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1432
1433 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1434 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1435 /*
1436 * Tell the JIT to use a more efficient calling convention: call using
1437 * OP_CALL, compute the result location after the call, and save the
1438 * result there.
1439 */
1440 call->vret_in_reg = TRUE;
1441 #if defined (__APPLE__)
1442 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1443 call->vret_in_reg_fp = TRUE;
1444 #endif
1445 if (call->vret_var)
1446 NULLIFY_INS (call->vret_var);
1447 }
1448 }
1449
1450 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1451
1452 /* Handle the case where there are no implicit arguments */
1453 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1454 emit_sig_cookie (cfg, call, cinfo);
1455 sp_offset = cinfo->sig_cookie.offset;
1456 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 }
1458
1459 /* Arguments are pushed in the reverse order */
1460 for (i = n - 1; i >= 0; i --) {
1461 ArgInfo *ainfo = cinfo->args + i;
1462 MonoType *orig_type, *t;
1463 int argsize;
1464
1465 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1466 MonoInst *vtarg;
1467
1468 /* Push the vret arg before the first argument */
1469 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1470 vtarg->type = STACK_MP;
1471 vtarg->inst_destbasereg = X86_ESP;
1472 vtarg->sreg1 = call->vret_var->dreg;
1473 vtarg->inst_offset = cinfo->ret.offset;
1474 MONO_ADD_INS (cfg->cbb, vtarg);
1475 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1476 }
1477
1478 if (i >= sig->hasthis)
1479 t = sig->params [i - sig->hasthis];
1480 else
1481 t = mono_get_int_type ();
1482 orig_type = t;
1483 t = mini_get_underlying_type (t);
1484
1485 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1486
1487 in = call->args [i];
1488 arg->cil_code = in->cil_code;
1489 arg->sreg1 = in->dreg;
1490 arg->type = in->type;
1491
1492 g_assert (in->dreg != -1);
1493
1494 if (ainfo->storage == ArgGSharedVt) {
1495 arg->opcode = OP_OUTARG_VT;
1496 arg->sreg1 = in->dreg;
1497 arg->klass = in->klass;
1498 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1499 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1500 sp_offset += 4;
1501 MONO_ADD_INS (cfg->cbb, arg);
1502 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1503 guint32 align;
1504 guint32 size;
1505
1506 g_assert (in->klass);
1507
1508 if (t->type == MONO_TYPE_TYPEDBYREF) {
1509 size = MONO_ABI_SIZEOF (MonoTypedRef);
1510 align = sizeof (target_mgreg_t);
1511 }
1512 else {
1513 size = mini_type_stack_size_full (m_class_get_byval_arg (in->klass), &align, sig->pinvoke);
1514 }
1515
1516 if (size > 0 || ainfo->pass_empty_struct) {
1517 arg->opcode = OP_OUTARG_VT;
1518 arg->sreg1 = in->dreg;
1519 arg->klass = in->klass;
1520 arg->backend.size = size;
1521 arg->inst_p0 = call;
1522 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1523 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1524
1525 MONO_ADD_INS (cfg->cbb, arg);
1526 if (ainfo->storage != ArgValuetypeInReg) {
1527 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1528 }
1529 }
1530 } else {
1531 switch (ainfo->storage) {
1532 case ArgOnStack:
1533 if (!t->byref) {
1534 if (t->type == MONO_TYPE_R4) {
1535 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1536 argsize = 4;
1537 } else if (t->type == MONO_TYPE_R8) {
1538 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1539 argsize = 8;
1540 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1541 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1542 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1543 argsize = 4;
1544 } else {
1545 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1546 argsize = 4;
1547 }
1548 } else {
1549 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1550 argsize = 4;
1551 }
1552 break;
1553 case ArgInIReg:
1554 arg->opcode = OP_MOVE;
1555 arg->dreg = ainfo->reg;
1556 MONO_ADD_INS (cfg->cbb, arg);
1557 argsize = 0;
1558 break;
1559 default:
1560 g_assert_not_reached ();
1561 }
1562
1563 if (cfg->compute_gc_maps) {
1564 if (argsize == 4) {
1565 /* FIXME: The == STACK_OBJ check might be fragile ? */
1566 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1567 /* this */
1568 if (call->need_unbox_trampoline)
1569 /* The unbox trampoline transforms this into a managed pointer */
1570 emit_gc_param_slot_def (cfg, ainfo->offset, m_class_get_this_arg (mono_defaults.int_class));
1571 else
1572 emit_gc_param_slot_def (cfg, ainfo->offset, mono_get_object_type ());
1573 } else {
1574 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1575 }
1576 } else {
1577 /* i8/r8 */
1578 for (j = 0; j < argsize; j += 4)
1579 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1580 }
1581 }
1582 }
1583
1584 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1585 /* Emit the signature cookie just before the implicit arguments */
1586 emit_sig_cookie (cfg, call, cinfo);
1587 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1588 }
1589 }
1590
1591 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1592 MonoInst *vtarg;
1593
1594 if (cinfo->ret.storage == ArgValuetypeInReg) {
1595 /* Already done */
1596 }
1597 else if (cinfo->ret.storage == ArgInIReg) {
1598 NOT_IMPLEMENTED;
1599 /* The return address is passed in a register */
1600 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1601 vtarg->sreg1 = call->inst.dreg;
1602 vtarg->dreg = mono_alloc_ireg (cfg);
1603 MONO_ADD_INS (cfg->cbb, vtarg);
1604
1605 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1606 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1607 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1608 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1609 }
1610 }
1611
1612 call->stack_usage = cinfo->stack_usage;
1613 call->stack_align_amount = cinfo->stack_align_amount;
1614 }
1615
1616 void
1617 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1618 {
1619 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1620 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1621 int size = ins->backend.size;
1622
1623 if (ainfo->storage == ArgValuetypeInReg) {
1624 int dreg = mono_alloc_ireg (cfg);
1625 switch (size) {
1626 case 1:
1627 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1628 break;
1629 case 2:
1630 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1631 break;
1632 case 4:
1633 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1634 break;
1635 case 3: /* FIXME */
1636 default:
1637 g_assert_not_reached ();
1638 }
1639 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1640 }
1641 else {
1642 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1643 /* Pass by addr */
1644 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1645 } else if (size <= 4) {
1646 int dreg = mono_alloc_ireg (cfg);
1647 if (ainfo->pass_empty_struct) {
1648 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1649 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1650 } else {
1651 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1652 }
1653 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1654 } else if (size <= 20) {
1655 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1656 } else {
1657 // FIXME: Code growth
1658 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1659 }
1660 }
1661 }
1662
1663 void
1664 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1665 {
1666 MonoType *ret = mini_get_underlying_type (mono_method_signature_internal (method)->ret);
1667
1668 if (!ret->byref) {
1669 if (ret->type == MONO_TYPE_R4) {
1670 if (COMPILE_LLVM (cfg))
1671 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1672 /* Nothing to do */
1673 return;
1674 } else if (ret->type == MONO_TYPE_R8) {
1675 if (COMPILE_LLVM (cfg))
1676 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1677 /* Nothing to do */
1678 return;
1679 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1680 if (COMPILE_LLVM (cfg))
1681 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1682 else {
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1684 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1685 }
1686 return;
1687 }
1688 }
1689
1690 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1691 }
1692
1693 #define EMIT_COND_BRANCH(ins,cond,sign) \
1694 if (ins->inst_true_bb->native_offset) { \
1695 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1696 } else { \
1697 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1698 if ((cfg->opt & MONO_OPT_BRANCH) && \
1699 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1700 x86_branch8 (code, cond, 0, sign); \
1701 else \
1702 x86_branch32 (code, cond, 0, sign); \
1703 }
1704
1705 /*
1706 * Emit an exception if condition is fail and
1707 * if possible do a directly branch to target
1708 */
1709 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1710 do { \
1711 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1712 if (tins == NULL) { \
1713 mono_add_patch_info (cfg, code - cfg->native_code, \
1714 MONO_PATCH_INFO_EXC, exc_name); \
1715 x86_branch32 (code, cond, 0, signed); \
1716 } else { \
1717 EMIT_COND_BRANCH (tins, cond, signed); \
1718 } \
1719 } while (0);
1720
1721 #define EMIT_FPCOMPARE(code) do { \
1722 x86_fcompp (code); \
1723 x86_fnstsw (code); \
1724 } while (0);
1725
1726 static guint8*
1727 x86_align_and_patch (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1728 {
1729 gboolean needs_paddings = TRUE;
1730 guint32 pad_size;
1731 MonoJumpInfo *jinfo = NULL;
1732
1733 if (cfg->abs_patches) {
1734 jinfo = (MonoJumpInfo*)g_hash_table_lookup (cfg->abs_patches, data);
1735 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1736 needs_paddings = FALSE;
1737 }
1738
1739 if (cfg->compile_aot)
1740 needs_paddings = FALSE;
1741 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1742 This is required for code patching to be safe on SMP machines.
1743 */
1744 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1745 if (needs_paddings && pad_size)
1746 x86_padding (code, 4 - pad_size);
1747
1748 mono_add_patch_info (cfg, code - cfg->native_code, (MonoJumpInfoType)patch_type, data);
1749
1750 return code;
1751 }
1752
1753 static guint8*
1754 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1755 {
1756 code = x86_align_and_patch (cfg, code, patch_type, data);
1757
1758 x86_call_code (code, 0);
1759
1760 return code;
1761 }
1762
1763 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1764
1765 /*
1766 * mono_peephole_pass_1:
1767 *
1768 * Perform peephole opts which should/can be performed before local regalloc
1769 */
1770 void
1771 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1772 {
1773 MonoInst *ins, *n;
1774
1775 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1776 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1777
1778 switch (ins->opcode) {
1779 case OP_IADD_IMM:
1780 case OP_ADD_IMM:
1781 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1782 /*
1783 * X86_LEA is like ADD, but doesn't have the
1784 * sreg1==dreg restriction.
1785 */
1786 ins->opcode = OP_X86_LEA_MEMBASE;
1787 ins->inst_basereg = ins->sreg1;
1788 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1789 ins->opcode = OP_X86_INC_REG;
1790 break;
1791 case OP_SUB_IMM:
1792 case OP_ISUB_IMM:
1793 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1794 ins->opcode = OP_X86_LEA_MEMBASE;
1795 ins->inst_basereg = ins->sreg1;
1796 ins->inst_imm = -ins->inst_imm;
1797 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1798 ins->opcode = OP_X86_DEC_REG;
1799 break;
1800 case OP_COMPARE_IMM:
1801 case OP_ICOMPARE_IMM:
1802 /* OP_COMPARE_IMM (reg, 0)
1803 * -->
1804 * OP_X86_TEST_NULL (reg)
1805 */
1806 if (!ins->inst_imm)
1807 ins->opcode = OP_X86_TEST_NULL;
1808 break;
1809 case OP_X86_COMPARE_MEMBASE_IMM:
1810 /*
1811 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1812 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1813 * -->
1814 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1815 * OP_COMPARE_IMM reg, imm
1816 *
1817 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1818 */
1819 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1820 ins->inst_basereg == last_ins->inst_destbasereg &&
1821 ins->inst_offset == last_ins->inst_offset) {
1822 ins->opcode = OP_COMPARE_IMM;
1823 ins->sreg1 = last_ins->sreg1;
1824
1825 /* check if we can remove cmp reg,0 with test null */
1826 if (!ins->inst_imm)
1827 ins->opcode = OP_X86_TEST_NULL;
1828 }
1829
1830 break;
1831 case OP_X86_PUSH_MEMBASE:
1832 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1833 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1834 ins->inst_basereg == last_ins->inst_destbasereg &&
1835 ins->inst_offset == last_ins->inst_offset) {
1836 ins->opcode = OP_X86_PUSH;
1837 ins->sreg1 = last_ins->sreg1;
1838 }
1839 break;
1840 }
1841
1842 mono_peephole_ins (bb, ins);
1843 }
1844 }
1845
1846 void
1847 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1848 {
1849 MonoInst *ins, *n;
1850
1851 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1852 switch (ins->opcode) {
1853 case OP_ICONST:
1854 /* reg = 0 -> XOR (reg, reg) */
1855 /* XOR sets cflags on x86, so we cant do it always */
1856 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1857 MonoInst *ins2;
1858
1859 ins->opcode = OP_IXOR;
1860 ins->sreg1 = ins->dreg;
1861 ins->sreg2 = ins->dreg;
1862
1863 /*
1864 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1865 * since it takes 3 bytes instead of 7.
1866 */
1867 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1868 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1869 ins2->opcode = OP_STORE_MEMBASE_REG;
1870 ins2->sreg1 = ins->dreg;
1871 }
1872 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1873 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1874 ins2->sreg1 = ins->dreg;
1875 }
1876 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1877 /* Continue iteration */
1878 }
1879 else
1880 break;
1881 }
1882 }
1883 break;
1884 case OP_IADD_IMM:
1885 case OP_ADD_IMM:
1886 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1887 ins->opcode = OP_X86_INC_REG;
1888 break;
1889 case OP_ISUB_IMM:
1890 case OP_SUB_IMM:
1891 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1892 ins->opcode = OP_X86_DEC_REG;
1893 break;
1894 }
1895
1896 mono_peephole_ins (bb, ins);
1897 }
1898 }
1899
1900 #define NEW_INS(cfg,ins,dest,op) do { \
1901 MONO_INST_NEW ((cfg), (dest), (op)); \
1902 (dest)->cil_code = (ins)->cil_code; \
1903 mono_bblock_insert_before_ins (bb, ins, (dest)); \
1904 } while (0)
1905
1906 /*
1907 * mono_arch_lowering_pass:
1908 *
1909 * Converts complex opcodes into simpler ones so that each IR instruction
1910 * corresponds to one machine instruction.
1911 */
1912 void
1913 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1914 {
1915 MonoInst *ins, *next;
1916
1917 /*
1918 * FIXME: Need to add more instructions, but the current machine
1919 * description can't model some parts of the composite instructions like
1920 * cdq.
1921 */
1922 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1923 switch (ins->opcode) {
1924 case OP_IREM_IMM:
1925 case OP_IDIV_IMM:
1926 case OP_IDIV_UN_IMM:
1927 case OP_IREM_UN_IMM:
1928 /*
1929 * Keep the cases where we could generated optimized code, otherwise convert
1930 * to the non-imm variant.
1931 */
1932 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1933 break;
1934 mono_decompose_op_imm (cfg, bb, ins);
1935 break;
1936 #ifdef MONO_ARCH_SIMD_INTRINSICS
1937 case OP_EXPAND_I1: {
1938 MonoInst *temp;
1939 int temp_reg1 = mono_alloc_ireg (cfg);
1940 int temp_reg2 = mono_alloc_ireg (cfg);
1941 int original_reg = ins->sreg1;
1942
1943 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
1944 temp->sreg1 = original_reg;
1945 temp->dreg = temp_reg1;
1946
1947 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
1948 temp->sreg1 = temp_reg1;
1949 temp->dreg = temp_reg2;
1950 temp->inst_imm = 8;
1951
1952 NEW_INS (cfg, ins, temp, OP_IOR);
1953 temp->sreg1 = temp->dreg = temp_reg2;
1954 temp->sreg2 = temp_reg1;
1955
1956 ins->opcode = OP_EXPAND_I2;
1957 ins->sreg1 = temp_reg2;
1958 }
1959 break;
1960 #endif
1961 default:
1962 break;
1963 }
1964 }
1965
1966 bb->max_vreg = cfg->next_vreg;
1967 }
1968
1969 static const int
1970 branch_cc_table [] = {
1971 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1972 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1973 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1974 };
1975
1976 /* Maps CMP_... constants to X86_CC_... constants */
1977 static const int
1978 cc_table [] = {
1979 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1980 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1981 };
1982
1983 static const int
1984 cc_signed_table [] = {
1985 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1986 FALSE, FALSE, FALSE, FALSE
1987 };
1988
1989 static unsigned char*
1990 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1991 {
1992 #define XMM_TEMP_REG 0
1993 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1994 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1995 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1996 /* optimize by assigning a local var for this use so we avoid
1997 * the stack manipulations */
1998 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1999 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2000 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2001 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2002 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2003 if (size == 1)
2004 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2005 else if (size == 2)
2006 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2007 return code;
2008 }
2009 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2010 x86_fnstcw_membase(code, X86_ESP, 0);
2011 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2012 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2013 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2014 x86_fldcw_membase (code, X86_ESP, 2);
2015 if (size == 8) {
2016 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2017 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2018 x86_pop_reg (code, dreg);
2019 /* FIXME: need the high register
2020 * x86_pop_reg (code, dreg_high);
2021 */
2022 } else {
2023 x86_push_reg (code, X86_EAX); // SP = SP - 4
2024 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2025 x86_pop_reg (code, dreg);
2026 }
2027 x86_fldcw_membase (code, X86_ESP, 0);
2028 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2029
2030 if (size == 1)
2031 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2032 else if (size == 2)
2033 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2034 return code;
2035 }
2036
2037 static unsigned char*
2038 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2039 {
2040 int sreg = tree->sreg1;
2041 int need_touch = FALSE;
2042
2043 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2044 need_touch = TRUE;
2045 #endif
2046
2047 if (need_touch) {
2048 guint8* br[5];
2049
2050 /*
2051 * Under Windows:
2052 * If requested stack size is larger than one page,
2053 * perform stack-touch operation
2054 */
2055 /*
2056 * Generate stack probe code.
2057 * Under Windows, it is necessary to allocate one page at a time,
2058 * "touching" stack after each successful sub-allocation. This is
2059 * because of the way stack growth is implemented - there is a
2060 * guard page before the lowest stack page that is currently commited.
2061 * Stack normally grows sequentially so OS traps access to the
2062 * guard page and commits more pages when needed.
2063 */
2064 x86_test_reg_imm (code, sreg, ~0xFFF);
2065 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2066
2067 br[2] = code; /* loop */
2068 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2069 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2070
2071 /*
2072 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2073 * that follows only initializes the last part of the area.
2074 */
2075 /* Same as the init code below with size==0x1000 */
2076 if (tree->flags & MONO_INST_INIT) {
2077 x86_push_reg (code, X86_EAX);
2078 x86_push_reg (code, X86_ECX);
2079 x86_push_reg (code, X86_EDI);
2080 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2081 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2082 if (cfg->param_area)
2083 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2084 else
2085 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2086 x86_cld (code);
2087 x86_prefix (code, X86_REP_PREFIX);
2088 x86_stosl (code);
2089 x86_pop_reg (code, X86_EDI);
2090 x86_pop_reg (code, X86_ECX);
2091 x86_pop_reg (code, X86_EAX);
2092 }
2093
2094 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2095 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2096 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2097 x86_patch (br[3], br[2]);
2098 x86_test_reg_reg (code, sreg, sreg);
2099 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2100 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2101
2102 br[1] = code; x86_jump8 (code, 0);
2103
2104 x86_patch (br[0], code);
2105 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2106 x86_patch (br[1], code);
2107 x86_patch (br[4], code);
2108 }
2109 else
2110 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2111
2112 if (tree->flags & MONO_INST_INIT) {
2113 int offset = 0;
2114 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2115 x86_push_reg (code, X86_EAX);
2116 offset += 4;
2117 }
2118 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2119 x86_push_reg (code, X86_ECX);
2120 offset += 4;
2121 }
2122 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2123 x86_push_reg (code, X86_EDI);
2124 offset += 4;
2125 }
2126
2127 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2128 x86_mov_reg_reg (code, X86_ECX, sreg);
2129 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2130
2131 if (cfg->param_area)
2132 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2133 else
2134 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2135 x86_cld (code);
2136 x86_prefix (code, X86_REP_PREFIX);
2137 x86_stosl (code);
2138
2139 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2140 x86_pop_reg (code, X86_EDI);
2141 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2142 x86_pop_reg (code, X86_ECX);
2143 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2144 x86_pop_reg (code, X86_EAX);
2145 }
2146 return code;
2147 }
2148
2149
2150 static guint8*
2151 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2152 {
2153 /* Move return value to the target register */
2154 switch (ins->opcode) {
2155 case OP_CALL:
2156 case OP_CALL_REG:
2157 case OP_CALL_MEMBASE:
2158 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2159 break;
2160 default:
2161 break;
2162 }
2163
2164 return code;
2165 }
2166
2167 #ifdef TARGET_MACH
2168 static int tls_gs_offset;
2169 #endif
2170
2171 gboolean
2172 mono_arch_have_fast_tls (void)
2173 {
2174 #ifdef TARGET_MACH
2175 static gboolean have_fast_tls = FALSE;
2176 static gboolean inited = FALSE;
2177 guint32 *ins;
2178
2179 if (mini_get_debug_options ()->use_fallback_tls)
2180 return FALSE;
2181 if (inited)
2182 return have_fast_tls;
2183
2184 ins = (guint32*)pthread_getspecific;
2185 /*
2186 * We're looking for these two instructions:
2187 *
2188 * mov 0x4(%esp),%eax
2189 * mov %gs:[offset](,%eax,4),%eax
2190 */
2191 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2192 tls_gs_offset = ins [2];
2193 inited = TRUE;
2194
2195 return have_fast_tls;
2196 #elif defined(TARGET_ANDROID)
2197 return FALSE;
2198 #else
2199 if (mini_get_debug_options ()->use_fallback_tls)
2200 return FALSE;
2201 return TRUE;
2202 #endif
2203 }
2204
2205 static guint8*
2206 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2207 {
2208 #if defined (TARGET_MACH)
2209 x86_prefix (code, X86_GS_PREFIX);
2210 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2211 #elif defined (TARGET_WIN32)
2212 /*
2213 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2214 * Journal and/or a disassembly of the TlsGet () function.
2215 */
2216 x86_prefix (code, X86_FS_PREFIX);
2217 x86_mov_reg_mem (code, dreg, 0x18, 4);
2218 if (tls_offset < 64) {
2219 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2220 } else {
2221 guint8 *buf [16];
2222
2223 g_assert (tls_offset < 0x440);
2224 /* Load TEB->TlsExpansionSlots */
2225 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2226 x86_test_reg_reg (code, dreg, dreg);
2227 buf [0] = code;
2228 x86_branch (code, X86_CC_EQ, code, TRUE);
2229 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2230 x86_patch (buf [0], code);
2231 }
2232 #else
2233 if (optimize_for_xen) {
2234 x86_prefix (code, X86_GS_PREFIX);
2235 x86_mov_reg_mem (code, dreg, 0, 4);
2236 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2237 } else {
2238 x86_prefix (code, X86_GS_PREFIX);
2239 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2240 }
2241 #endif
2242 return code;
2243 }
2244
2245 static guint8*
2246 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2247 {
2248 #if defined (TARGET_MACH)
2249 x86_prefix (code, X86_GS_PREFIX);
2250 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2251 #elif defined (TARGET_WIN32)
2252 g_assert_not_reached ();
2253 #else
2254 x86_prefix (code, X86_GS_PREFIX);
2255 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2256 #endif
2257 return code;
2258 }
2259
2260 /*
2261 * emit_setup_lmf:
2262 *
2263 * Emit code to initialize an LMF structure at LMF_OFFSET.
2264 */
2265 static guint8*
2266 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2267 {
2268 /* save all caller saved regs */
2269 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (target_mgreg_t));
2270 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2271 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (target_mgreg_t));
2272 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2273 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (target_mgreg_t));
2274 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2275 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (target_mgreg_t));
2276
2277 /* save the current IP */
2278 if (cfg->compile_aot) {
2279 /* This pushes the current ip */
2280 x86_call_imm (code, 0);
2281 x86_pop_reg (code, X86_EAX);
2282 } else {
2283 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2284 x86_mov_reg_imm (code, X86_EAX, 0);
2285 }
2286 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (target_mgreg_t));
2287
2288 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2289 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2290 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2291 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2292 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2293 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2294 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2295 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2296 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2297
2298 return code;
2299 }
2300
2301 /* benchmark and set based on cpu */
2302 #define LOOP_ALIGNMENT 8
2303 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2304
2305 #ifndef DISABLE_JIT
2306 void
2307 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2308 {
2309 MonoInst *ins;
2310 MonoCallInst *call;
2311 guint8 *code = cfg->native_code + cfg->code_len;
2312
2313 if (cfg->opt & MONO_OPT_LOOP) {
2314 int pad, align = LOOP_ALIGNMENT;
2315 /* set alignment depending on cpu */
2316 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2317 pad = align - pad;
2318 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2319 x86_padding (code, pad);
2320 cfg->code_len += pad;
2321 bb->native_offset = cfg->code_len;
2322 }
2323 }
2324
2325 if (cfg->verbose_level > 2)
2326 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2327
2328 int cpos = bb->max_offset;
2329
2330 set_code_cursor (cfg, code);
2331
2332 mono_debug_open_block (cfg, bb, code - cfg->native_code);
2333
2334 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2335 x86_breakpoint (code);
2336
2337 MONO_BB_FOR_EACH_INS (bb, ins) {
2338 const guint offset = code - cfg->native_code;
2339 set_code_cursor (cfg, code);
2340 int max_len = ins_get_size (ins->opcode);
2341 code = realloc_code (cfg, max_len);
2342
2343 if (cfg->debug_info)
2344 mono_debug_record_line_number (cfg, ins, offset);
2345
2346 switch (ins->opcode) {
2347 case OP_BIGMUL:
2348 x86_mul_reg (code, ins->sreg2, TRUE);
2349 break;
2350 case OP_BIGMUL_UN:
2351 x86_mul_reg (code, ins->sreg2, FALSE);
2352 break;
2353 case OP_X86_SETEQ_MEMBASE:
2354 case OP_X86_SETNE_MEMBASE:
2355 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2356 ins->inst_basereg, ins->inst_offset, TRUE);
2357 break;
2358 case OP_STOREI1_MEMBASE_IMM:
2359 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2360 break;
2361 case OP_STOREI2_MEMBASE_IMM:
2362 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2363 break;
2364 case OP_STORE_MEMBASE_IMM:
2365 case OP_STOREI4_MEMBASE_IMM:
2366 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2367 break;
2368 case OP_STOREI1_MEMBASE_REG:
2369 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2370 break;
2371 case OP_STOREI2_MEMBASE_REG:
2372 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2373 break;
2374 case OP_STORE_MEMBASE_REG:
2375 case OP_STOREI4_MEMBASE_REG:
2376 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2377 break;
2378 case OP_STORE_MEM_IMM:
2379 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2380 break;
2381 case OP_LOADU4_MEM:
2382 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2383 break;
2384 case OP_LOAD_MEM:
2385 case OP_LOADI4_MEM:
2386 /* These are created by the cprop pass so they use inst_imm as the source */
2387 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2388 break;
2389 case OP_LOADU1_MEM:
2390 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2391 break;
2392 case OP_LOADU2_MEM:
2393 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2394 break;
2395 case OP_LOAD_MEMBASE:
2396 case OP_LOADI4_MEMBASE:
2397 case OP_LOADU4_MEMBASE:
2398 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2399 break;
2400 case OP_LOADU1_MEMBASE:
2401 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2402 break;
2403 case OP_LOADI1_MEMBASE:
2404 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2405 break;
2406 case OP_LOADU2_MEMBASE:
2407 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2408 break;
2409 case OP_LOADI2_MEMBASE:
2410 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2411 break;
2412 case OP_ICONV_TO_I1:
2413 case OP_SEXT_I1:
2414 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2415 break;
2416 case OP_ICONV_TO_I2:
2417 case OP_SEXT_I2:
2418 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2419 break;
2420 case OP_ICONV_TO_U1:
2421 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2422 break;
2423 case OP_ICONV_TO_U2:
2424 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2425 break;
2426 case OP_COMPARE:
2427 case OP_ICOMPARE:
2428 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2429 break;
2430 case OP_COMPARE_IMM:
2431 case OP_ICOMPARE_IMM:
2432 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2433 break;
2434 case OP_X86_COMPARE_MEMBASE_REG:
2435 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2436 break;
2437 case OP_X86_COMPARE_MEMBASE_IMM:
2438 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2439 break;
2440 case OP_X86_COMPARE_MEMBASE8_IMM:
2441 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2442 break;
2443 case OP_X86_COMPARE_REG_MEMBASE:
2444 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2445 break;
2446 case OP_X86_COMPARE_MEM_IMM:
2447 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2448 break;
2449 case OP_X86_TEST_NULL:
2450 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2451 break;
2452 case OP_X86_ADD_MEMBASE_IMM:
2453 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2454 break;
2455 case OP_X86_ADD_REG_MEMBASE:
2456 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2457 break;
2458 case OP_X86_SUB_MEMBASE_IMM:
2459 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2460 break;
2461 case OP_X86_SUB_REG_MEMBASE:
2462 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2463 break;
2464 case OP_X86_AND_MEMBASE_IMM:
2465 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2466 break;
2467 case OP_X86_OR_MEMBASE_IMM:
2468 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2469 break;
2470 case OP_X86_XOR_MEMBASE_IMM:
2471 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2472 break;
2473 case OP_X86_ADD_MEMBASE_REG:
2474 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2475 break;
2476 case OP_X86_SUB_MEMBASE_REG:
2477 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2478 break;
2479 case OP_X86_AND_MEMBASE_REG:
2480 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2481 break;
2482 case OP_X86_OR_MEMBASE_REG:
2483 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2484 break;
2485 case OP_X86_XOR_MEMBASE_REG:
2486 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2487 break;
2488 case OP_X86_INC_MEMBASE:
2489 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2490 break;
2491 case OP_X86_INC_REG:
2492 x86_inc_reg (code, ins->dreg);
2493 break;
2494 case OP_X86_DEC_MEMBASE:
2495 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2496 break;
2497 case OP_X86_DEC_REG:
2498 x86_dec_reg (code, ins->dreg);
2499 break;
2500 case OP_X86_MUL_REG_MEMBASE:
2501 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2502 break;
2503 case OP_X86_AND_REG_MEMBASE:
2504 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2505 break;
2506 case OP_X86_OR_REG_MEMBASE:
2507 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2508 break;
2509 case OP_X86_XOR_REG_MEMBASE:
2510 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2511 break;
2512 case OP_BREAK:
2513 x86_breakpoint (code);
2514 break;
2515 case OP_RELAXED_NOP:
2516 x86_prefix (code, X86_REP_PREFIX);
2517 x86_nop (code);
2518 break;
2519 case OP_HARD_NOP:
2520 x86_nop (code);
2521 break;
2522 case OP_NOP:
2523 case OP_DUMMY_USE:
2524 case OP_DUMMY_ICONST:
2525 case OP_DUMMY_R8CONST:
2526 case OP_DUMMY_R4CONST:
2527 case OP_NOT_REACHED:
2528 case OP_NOT_NULL:
2529 break;
2530 case OP_IL_SEQ_POINT:
2531 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2532 break;
2533 case OP_SEQ_POINT: {
2534 int i;
2535
2536 if (cfg->compile_aot)
2537 NOT_IMPLEMENTED;
2538
2539 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2540
2541 /*
2542 * We do this _before_ the breakpoint, so single stepping after
2543 * a breakpoint is hit will step to the next IL offset.
2544 */
2545 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2546 MonoInst *var = cfg->arch.ss_tramp_var;
2547 guint8 *br [1];
2548
2549 g_assert (var);
2550 g_assert (var->opcode == OP_REGOFFSET);
2551 /* Load ss_tramp_var */
2552 /* This is equal to &ss_trampoline */
2553 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (target_mgreg_t));
2554 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (target_mgreg_t));
2555 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2556 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2557 x86_call_reg (code, X86_ECX);
2558 x86_patch (br [0], code);
2559 }
2560
2561 /*
2562 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2563 * This means we have to put the loading of bp_tramp_var after the offset.
2564 */
2565
2566 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2567
2568 MonoInst *var = cfg->arch.bp_tramp_var;
2569
2570 g_assert (var);
2571 g_assert (var->opcode == OP_REGOFFSET);
2572 /* Load the address of the bp trampoline */
2573 /* This needs to be constant size */
2574 guint8 *start = code;
2575 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2576 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2577 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2578 x86_padding (code, size);
2579 }
2580 /*
2581 * A placeholder for a possible breakpoint inserted by
2582 * mono_arch_set_breakpoint ().
2583 */
2584 for (i = 0; i < 2; ++i)
2585 x86_nop (code);
2586 /*
2587 * Add an additional nop so skipping the bp doesn't cause the ip to point
2588 * to another IL offset.
2589 */
2590 x86_nop (code);
2591 break;
2592 }
2593 case OP_ADDCC:
2594 case OP_IADDCC:
2595 case OP_IADD:
2596 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2597 break;
2598 case OP_ADC:
2599 case OP_IADC:
2600 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2601 break;
2602 case OP_ADDCC_IMM:
2603 case OP_ADD_IMM:
2604 case OP_IADD_IMM:
2605 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2606 break;
2607 case OP_ADC_IMM:
2608 case OP_IADC_IMM:
2609 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2610 break;
2611 case OP_SUBCC:
2612 case OP_ISUBCC:
2613 case OP_ISUB:
2614 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2615 break;
2616 case OP_SBB:
2617 case OP_ISBB:
2618 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2619 break;
2620 case OP_SUBCC_IMM:
2621 case OP_SUB_IMM:
2622 case OP_ISUB_IMM:
2623 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2624 break;
2625 case OP_SBB_IMM:
2626 case OP_ISBB_IMM:
2627 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2628 break;
2629 case OP_IAND:
2630 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2631 break;
2632 case OP_AND_IMM:
2633 case OP_IAND_IMM:
2634 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2635 break;
2636 case OP_IDIV:
2637 case OP_IREM:
2638 /*
2639 * The code is the same for div/rem, the allocator will allocate dreg
2640 * to RAX/RDX as appropriate.
2641 */
2642 if (ins->sreg2 == X86_EDX) {
2643 /* cdq clobbers this */
2644 x86_push_reg (code, ins->sreg2);
2645 x86_cdq (code);
2646 x86_div_membase (code, X86_ESP, 0, TRUE);
2647 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2648 } else {
2649 x86_cdq (code);
2650 x86_div_reg (code, ins->sreg2, TRUE);
2651 }
2652 break;
2653 case OP_IDIV_UN:
2654 case OP_IREM_UN:
2655 if (ins->sreg2 == X86_EDX) {
2656 x86_push_reg (code, ins->sreg2);
2657 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2658 x86_div_membase (code, X86_ESP, 0, FALSE);
2659 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2660 } else {
2661 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2662 x86_div_reg (code, ins->sreg2, FALSE);
2663 }
2664 break;
2665 case OP_DIV_IMM:
2666 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2667 x86_cdq (code);
2668 x86_div_reg (code, ins->sreg2, TRUE);
2669 break;
2670 case OP_IREM_IMM: {
2671 int power = mono_is_power_of_two (ins->inst_imm);
2672
2673 g_assert (ins->sreg1 == X86_EAX);
2674 g_assert (ins->dreg == X86_EAX);
2675 g_assert (power >= 0);
2676
2677 if (power == 1) {
2678 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2679 x86_cdq (code);
2680 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2681 /*
2682 * If the divident is >= 0, this does not nothing. If it is positive, it
2683 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2684 */
2685 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2686 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2687 } else if (power == 0) {
2688 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2689 } else {
2690 /* Based on gcc code */
2691
2692 /* Add compensation for negative dividents */
2693 x86_cdq (code);
2694 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2695 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2696 /* Compute remainder */
2697 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2698 /* Remove compensation */
2699 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2700 }
2701 break;
2702 }
2703 case OP_IOR:
2704 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2705 break;
2706 case OP_OR_IMM:
2707 case OP_IOR_IMM:
2708 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2709 break;
2710 case OP_IXOR:
2711 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2712 break;
2713 case OP_XOR_IMM:
2714 case OP_IXOR_IMM:
2715 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2716 break;
2717 case OP_ISHL:
2718 g_assert (ins->sreg2 == X86_ECX);
2719 x86_shift_reg (code, X86_SHL, ins->dreg);
2720 break;
2721 case OP_ISHR:
2722 g_assert (ins->sreg2 == X86_ECX);
2723 x86_shift_reg (code, X86_SAR, ins->dreg);
2724 break;
2725 case OP_SHR_IMM:
2726 case OP_ISHR_IMM:
2727 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2728 break;
2729 case OP_SHR_UN_IMM:
2730 case OP_ISHR_UN_IMM:
2731 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2732 break;
2733 case OP_ISHR_UN:
2734 g_assert (ins->sreg2 == X86_ECX);
2735 x86_shift_reg (code, X86_SHR, ins->dreg);
2736 break;
2737 case OP_SHL_IMM:
2738 case OP_ISHL_IMM:
2739 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2740 break;
2741 case OP_LSHL: {
2742 guint8 *jump_to_end;
2743
2744 /* handle shifts below 32 bits */
2745 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2746 x86_shift_reg (code, X86_SHL, ins->sreg1);
2747
2748 x86_test_reg_imm (code, X86_ECX, 32);
2749 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2750
2751 /* handle shift over 32 bit */
2752 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2753 x86_clear_reg (code, ins->sreg1);
2754
2755 x86_patch (jump_to_end, code);
2756 }
2757 break;
2758 case OP_LSHR: {
2759 guint8 *jump_to_end;
2760
2761 /* handle shifts below 32 bits */
2762 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2763 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2764
2765 x86_test_reg_imm (code, X86_ECX, 32);
2766 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2767
2768 /* handle shifts over 31 bits */
2769 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2770 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2771
2772 x86_patch (jump_to_end, code);
2773 }
2774 break;
2775 case OP_LSHR_UN: {
2776 guint8 *jump_to_end;
2777
2778 /* handle shifts below 32 bits */
2779 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2780 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2781
2782 x86_test_reg_imm (code, X86_ECX, 32);
2783 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2784
2785 /* handle shifts over 31 bits */
2786 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2787 x86_clear_reg (code, ins->backend.reg3);
2788
2789 x86_patch (jump_to_end, code);
2790 }
2791 break;
2792 case OP_LSHL_IMM:
2793 if (ins->inst_imm >= 32) {
2794 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2795 x86_clear_reg (code, ins->sreg1);
2796 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2797 } else {
2798 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2799 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2800 }
2801 break;
2802 case OP_LSHR_IMM:
2803 if (ins->inst_imm >= 32) {
2804 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2805 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2806 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2807 } else {
2808 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2809 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2810 }
2811 break;
2812 case OP_LSHR_UN_IMM:
2813 if (ins->inst_imm >= 32) {
2814 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2815 x86_clear_reg (code, ins->backend.reg3);
2816 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2817 } else {
2818 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2819 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2820 }
2821 break;
2822 case OP_INOT:
2823 x86_not_reg (code, ins->sreg1);
2824 break;
2825 case OP_INEG:
2826 x86_neg_reg (code, ins->sreg1);
2827 break;
2828
2829 case OP_IMUL:
2830 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2831 break;
2832 case OP_MUL_IMM:
2833 case OP_IMUL_IMM:
2834 switch (ins->inst_imm) {
2835 case 2:
2836 /* MOV r1, r2 */
2837 /* ADD r1, r1 */
2838 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2839 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2840 break;
2841 case 3:
2842 /* LEA r1, [r2 + r2*2] */
2843 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2844 break;
2845 case 5:
2846 /* LEA r1, [r2 + r2*4] */
2847 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2848 break;
2849 case 6:
2850 /* LEA r1, [r2 + r2*2] */
2851 /* ADD r1, r1 */
2852 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2853 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2854 break;
2855 case 9:
2856 /* LEA r1, [r2 + r2*8] */
2857 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2858 break;
2859 case 10:
2860 /* LEA r1, [r2 + r2*4] */
2861 /* ADD r1, r1 */
2862 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2863 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2864 break;
2865 case 12:
2866 /* LEA r1, [r2 + r2*2] */
2867 /* SHL r1, 2 */
2868 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2869 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2870 break;
2871 case 25:
2872 /* LEA r1, [r2 + r2*4] */
2873 /* LEA r1, [r1 + r1*4] */
2874 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2875 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2876 break;
2877 case 100:
2878 /* LEA r1, [r2 + r2*4] */
2879 /* SHL r1, 2 */
2880 /* LEA r1, [r1 + r1*4] */
2881 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2882 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2883 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2884 break;
2885 default:
2886 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2887 break;
2888 }
2889 break;
2890 case OP_IMUL_OVF:
2891 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2892 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2893 break;
2894 case OP_IMUL_OVF_UN: {
2895 /* the mul operation and the exception check should most likely be split */
2896 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2897 /*g_assert (ins->sreg2 == X86_EAX);
2898 g_assert (ins->dreg == X86_EAX);*/
2899 if (ins->sreg2 == X86_EAX) {
2900 non_eax_reg = ins->sreg1;
2901 } else if (ins->sreg1 == X86_EAX) {
2902 non_eax_reg = ins->sreg2;
2903 } else {
2904 /* no need to save since we're going to store to it anyway */
2905 if (ins->dreg != X86_EAX) {
2906 saved_eax = TRUE;
2907 x86_push_reg (code, X86_EAX);
2908 }
2909 x86_mov_reg_reg (code, X86_EAX, ins->sreg1);
2910 non_eax_reg = ins->sreg2;
2911 }
2912 if (ins->dreg == X86_EDX) {
2913 if (!saved_eax) {
2914 saved_eax = TRUE;
2915 x86_push_reg (code, X86_EAX);
2916 }
2917 } else {
2918 saved_edx = TRUE;
2919 x86_push_reg (code, X86_EDX);
2920 }
2921 x86_mul_reg (code, non_eax_reg, FALSE);
2922 /* save before the check since pop and mov don't change the flags */
2923 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2924 if (saved_edx)
2925 x86_pop_reg (code, X86_EDX);
2926 if (saved_eax)
2927 x86_pop_reg (code, X86_EAX);
2928 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2929 break;
2930 }
2931 case OP_ICONST:
2932 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2933 break;
2934 case OP_AOTCONST:
2935 g_assert_not_reached ();
2936 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2937 x86_mov_reg_imm (code, ins->dreg, 0);
2938 break;
2939 case OP_JUMP_TABLE:
2940 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2941 x86_mov_reg_imm (code, ins->dreg, 0);
2942 break;
2943 case OP_LOAD_GOTADDR:
2944 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2945 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2946 break;
2947 case OP_GOT_ENTRY:
2948 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2949 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2950 break;
2951 case OP_X86_PUSH_GOT_ENTRY:
2952 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2953 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2954 break;
2955 case OP_MOVE:
2956 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2957 break;
2958
2959 case OP_TAILCALL_PARAMETER:
2960 // This opcode helps compute sizes, i.e.
2961 // of the subsequent OP_TAILCALL, but contributes no code.
2962 g_assert (ins->next);
2963 break;
2964
2965 case OP_TAILCALL:
2966 case OP_TAILCALL_MEMBASE:
2967 case OP_TAILCALL_REG: {
2968 call = (MonoCallInst*)ins;
2969 int pos = 0, i;
2970 gboolean const tailcall_membase = ins->opcode == OP_TAILCALL_MEMBASE;
2971 gboolean const tailcall_reg = (ins->opcode == OP_TAILCALL_REG);
2972 int const sreg1 = ins->sreg1;
2973 gboolean const sreg1_ecx = sreg1 == X86_ECX;
2974 gboolean const tailcall_membase_ecx = tailcall_membase && sreg1_ecx;
2975 gboolean const tailcall_membase_not_ecx = tailcall_membase && !sreg1_ecx;
2976
2977 max_len += (call->stack_usage - call->stack_align_amount) / sizeof (target_mgreg_t) * ins_get_size (OP_TAILCALL_PARAMETER);
2978 code = realloc_code (cfg, max_len);
2979
2980 ins->flags |= MONO_INST_GC_CALLSITE;
2981 ins->backend.pc_offset = code - cfg->native_code;
2982
2983 g_assert (!cfg->method->save_lmf);
2984
2985 // Ecx is volatile, not used for parameters, or rgctx/imt (edx).
2986 // It is also not used for return value, though that does not matter.
2987 // Ecx is preserved across the tailcall formation.
2988 //
2989 // Eax could also be used here at the cost of a push/pop moving the parameters.
2990 // Edx must be preserved as it is rgctx/imt.
2991 //
2992 // If ecx happens to be the base of the tailcall_membase, then
2993 // just end with jmp [ecx+offset] -- one instruction.
2994 // if ecx is not the base, then move ecx, [reg+offset] and later jmp [ecx] -- two instructions.
2995
2996 if (tailcall_reg) {
2997 g_assert (sreg1 > -1);
2998 x86_mov_reg_reg (code, X86_ECX, sreg1);
2999 } else if (tailcall_membase_not_ecx) {
3000 g_assert (sreg1 > -1);
3001 x86_mov_reg_membase (code, X86_ECX, sreg1, ins->inst_offset, 4);
3002 }
3003
3004 /* restore callee saved registers */
3005 for (i = 0; i < X86_NREG; ++i)
3006 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3007 pos -= 4;
3008 if (cfg->used_int_regs & (1 << X86_ESI)) {
3009 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3010 pos += 4;
3011 }
3012 if (cfg->used_int_regs & (1 << X86_EDI)) {
3013 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3014 pos += 4;
3015 }
3016 if (cfg->used_int_regs & (1 << X86_EBX)) {
3017 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3018 pos += 4;
3019 }
3020
3021 /* Copy arguments on the stack to our argument area */
3022 // FIXME use rep mov for constant code size, before nonvolatiles
3023 // restored, first saving esi, edi into volatiles
3024 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3025 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3026 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3027 }
3028
3029 /* restore ESP/EBP */
3030 x86_leave (code);
3031
3032 if (tailcall_membase_ecx) {
3033 x86_jump_membase (code, X86_ECX, ins->inst_offset);
3034 } else if (tailcall_reg || tailcall_membase_not_ecx) {
3035 x86_jump_reg (code, X86_ECX);
3036 } else {
3037 // FIXME Patch data instead of code.
3038 code = x86_align_and_patch (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3039 x86_jump32 (code, 0);
3040 }
3041
3042 ins->flags |= MONO_INST_GC_CALLSITE;
3043 break;
3044 }
3045 case OP_CHECK_THIS:
3046 /* ensure ins->sreg1 is not NULL
3047 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3048 * cmp DWORD PTR [eax], 0
3049 */
3050 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3051 break;
3052 case OP_ARGLIST: {
3053 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3054 x86_push_reg (code, hreg);
3055 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3056 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3057 x86_pop_reg (code, hreg);
3058 break;
3059 }
3060 case OP_FCALL:
3061 case OP_LCALL:
3062 case OP_VCALL:
3063 case OP_VCALL2:
3064 case OP_VOIDCALL:
3065 case OP_CALL:
3066 case OP_FCALL_REG:
3067 case OP_LCALL_REG:
3068 case OP_VCALL_REG:
3069 case OP_VCALL2_REG:
3070 case OP_VOIDCALL_REG:
3071 case OP_CALL_REG:
3072 case OP_FCALL_MEMBASE:
3073 case OP_LCALL_MEMBASE:
3074 case OP_VCALL_MEMBASE:
3075 case OP_VCALL2_MEMBASE:
3076 case OP_VOIDCALL_MEMBASE:
3077 case OP_CALL_MEMBASE: {
3078 CallInfo *cinfo;
3079
3080 call = (MonoCallInst*)ins;
3081 cinfo = call->call_info;
3082
3083 switch (ins->opcode) {
3084 case OP_FCALL:
3085 case OP_LCALL:
3086 case OP_VCALL:
3087 case OP_VCALL2:
3088 case OP_VOIDCALL:
3089 case OP_CALL:
3090 if (ins->flags & MONO_INST_HAS_METHOD)
3091 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3092 else
3093 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3094 break;
3095 case OP_FCALL_REG:
3096 case OP_LCALL_REG:
3097 case OP_VCALL_REG:
3098 case OP_VCALL2_REG:
3099 case OP_VOIDCALL_REG:
3100 case OP_CALL_REG:
3101 x86_call_reg (code, ins->sreg1);
3102 break;
3103 case OP_FCALL_MEMBASE:
3104 case OP_LCALL_MEMBASE:
3105 case OP_VCALL_MEMBASE:
3106 case OP_VCALL2_MEMBASE:
3107 case OP_VOIDCALL_MEMBASE:
3108 case OP_CALL_MEMBASE:
3109 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3110 break;
3111 default:
3112 g_assert_not_reached ();
3113 break;
3114 }
3115 ins->flags |= MONO_INST_GC_CALLSITE;
3116 ins->backend.pc_offset = code - cfg->native_code;
3117 if (cinfo->callee_stack_pop) {
3118 /* Have to compensate for the stack space popped by the callee */
3119 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3120 }
3121 code = emit_move_return_value (cfg, ins, code);
3122 break;
3123 }
3124 case OP_X86_LEA:
3125 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3126 break;
3127 case OP_X86_LEA_MEMBASE:
3128 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3129 break;
3130 case OP_X86_XCHG:
3131 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3132 break;
3133 case OP_LOCALLOC:
3134 /* keep alignment */
3135 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3136 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3137 code = mono_emit_stack_alloc (cfg, code, ins);
3138 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3139 if (cfg->param_area)
3140 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3141 break;
3142 case OP_LOCALLOC_IMM: {
3143 guint32 size = ins->inst_imm;
3144 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3145
3146 if (ins->flags & MONO_INST_INIT) {
3147 /* FIXME: Optimize this */
3148 x86_mov_reg_imm (code, ins->dreg, size);
3149 ins->sreg1 = ins->dreg;
3150
3151 code = mono_emit_stack_alloc (cfg, code, ins);
3152 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3153 } else {
3154 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3155 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3156 }
3157 if (cfg->param_area)
3158 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3159 break;
3160 }
3161 case OP_THROW: {
3162 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3163 x86_push_reg (code, ins->sreg1);
3164 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL,
3165 (gpointer)"mono_arch_throw_exception");
3166 ins->flags |= MONO_INST_GC_CALLSITE;
3167 ins->backend.pc_offset = code - cfg->native_code;
3168 break;
3169 }
3170 case OP_RETHROW: {
3171 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3172 x86_push_reg (code, ins->sreg1);
3173 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL,
3174 (gpointer)"mono_arch_rethrow_exception");
3175 ins->flags |= MONO_INST_GC_CALLSITE;
3176 ins->backend.pc_offset = code - cfg->native_code;
3177 break;
3178 }
3179 case OP_CALL_HANDLER:
3180 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3181 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3182 x86_call_imm (code, 0);
3183 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
3184 mono_cfg_add_try_hole (cfg, ((MonoLeaveClause *) tmp->data)->clause, code, bb);
3185 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3186 break;
3187 case OP_START_HANDLER: {
3188 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3189 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3190 if (cfg->param_area)
3191 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3192 break;
3193 }
3194 case OP_ENDFINALLY: {
3195 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3196 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3197 x86_ret (code);
3198 break;
3199 }
3200 case OP_ENDFILTER: {
3201 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3202 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3203 /* The local allocator will put the result into EAX */
3204 x86_ret (code);
3205 break;
3206 }
3207 case OP_GET_EX_OBJ:
3208 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
3209 break;
3210
3211 case OP_LABEL:
3212 ins->inst_c0 = code - cfg->native_code;
3213 break;
3214 case OP_BR:
3215 if (ins->inst_target_bb->native_offset) {
3216 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3217 } else {
3218 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3219 if ((cfg->opt & MONO_OPT_BRANCH) &&
3220 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3221 x86_jump8 (code, 0);
3222 else
3223 x86_jump32 (code, 0);
3224 }
3225 break;
3226 case OP_BR_REG:
3227 x86_jump_reg (code, ins->sreg1);
3228 break;
3229 case OP_ICNEQ:
3230 case OP_ICGE:
3231 case OP_ICLE:
3232 case OP_ICGE_UN:
3233 case OP_ICLE_UN:
3234
3235 case OP_CEQ:
3236 case OP_CLT:
3237 case OP_CLT_UN:
3238 case OP_CGT:
3239 case OP_CGT_UN:
3240 case OP_CNE:
3241 case OP_ICEQ:
3242 case OP_ICLT:
3243 case OP_ICLT_UN:
3244 case OP_ICGT:
3245 case OP_ICGT_UN:
3246 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3247 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3248 break;
3249 case OP_COND_EXC_EQ:
3250 case OP_COND_EXC_NE_UN:
3251 case OP_COND_EXC_LT:
3252 case OP_COND_EXC_LT_UN:
3253 case OP_COND_EXC_GT:
3254 case OP_COND_EXC_GT_UN:
3255 case OP_COND_EXC_GE:
3256 case OP_COND_EXC_GE_UN:
3257 case OP_COND_EXC_LE:
3258 case OP_COND_EXC_LE_UN:
3259 case OP_COND_EXC_IEQ:
3260 case OP_COND_EXC_INE_UN:
3261 case OP_COND_EXC_ILT:
3262 case OP_COND_EXC_ILT_UN:
3263 case OP_COND_EXC_IGT:
3264 case OP_COND_EXC_IGT_UN:
3265 case OP_COND_EXC_IGE:
3266 case OP_COND_EXC_IGE_UN:
3267 case OP_COND_EXC_ILE:
3268 case OP_COND_EXC_ILE_UN:
3269 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char*)ins->inst_p1);
3270 break;
3271 case OP_COND_EXC_OV:
3272 case OP_COND_EXC_NO:
3273 case OP_COND_EXC_C:
3274 case OP_COND_EXC_NC:
3275 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), (const char*)ins->inst_p1);
3276 break;
3277 case OP_COND_EXC_IOV:
3278 case OP_COND_EXC_INO:
3279 case OP_COND_EXC_IC:
3280 case OP_COND_EXC_INC:
3281 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), (const char*)ins->inst_p1);
3282 break;
3283 case OP_IBEQ:
3284 case OP_IBNE_UN:
3285 case OP_IBLT:
3286 case OP_IBLT_UN:
3287 case OP_IBGT:
3288 case OP_IBGT_UN:
3289 case OP_IBGE:
3290 case OP_IBGE_UN:
3291 case OP_IBLE:
3292 case OP_IBLE_UN:
3293 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3294 break;
3295
3296 case OP_CMOV_IEQ:
3297 case OP_CMOV_IGE:
3298 case OP_CMOV_IGT:
3299 case OP_CMOV_ILE:
3300 case OP_CMOV_ILT:
3301 case OP_CMOV_INE_UN:
3302 case OP_CMOV_IGE_UN:
3303 case OP_CMOV_IGT_UN:
3304 case OP_CMOV_ILE_UN:
3305 case OP_CMOV_ILT_UN:
3306 g_assert (ins->dreg == ins->sreg1);
3307 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3308 break;
3309
3310 /* floating point opcodes */
3311 case OP_R8CONST: {
3312 double d = *(double *)ins->inst_p0;
3313
3314 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3315 x86_fldz (code);
3316 } else if (d == 1.0) {
3317 x86_fld1 (code);
3318 } else {
3319 if (cfg->compile_aot) {
3320 guint32 *val = (guint32*)&d;
3321 x86_push_imm (code, val [1]);
3322 x86_push_imm (code, val [0]);
3323 x86_fld_membase (code, X86_ESP, 0, TRUE);
3324 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3325 }
3326 else {
3327 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3328 x86_fld (code, NULL, TRUE);
3329 }
3330 }
3331 break;
3332 }
3333 case OP_R4CONST: {
3334 float f = *(float *)ins->inst_p0;
3335
3336 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3337 x86_fldz (code);
3338 } else if (f == 1.0) {
3339 x86_fld1 (code);
3340 } else {
3341 if (cfg->compile_aot) {
3342 guint32 val = *(guint32*)&f;
3343 x86_push_imm (code, val);
3344 x86_fld_membase (code, X86_ESP, 0, FALSE);
3345 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3346 }
3347 else {
3348 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3349 x86_fld (code, NULL, FALSE);
3350 }
3351 }
3352 break;
3353 }
3354 case OP_STORER8_MEMBASE_REG:
3355 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3356 break;
3357 case OP_LOADR8_MEMBASE:
3358 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3359 break;
3360 case OP_STORER4_MEMBASE_REG:
3361 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3362 break;
3363 case OP_LOADR4_MEMBASE:
3364 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3365 break;
3366 case OP_ICONV_TO_R4:
3367 x86_push_reg (code, ins->sreg1);
3368 x86_fild_membase (code, X86_ESP, 0, FALSE);
3369 /* Change precision */
3370 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3371 x86_fld_membase (code, X86_ESP, 0, FALSE);
3372 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3373 break;
3374 case OP_ICONV_TO_R8:
3375 x86_push_reg (code, ins->sreg1);
3376 x86_fild_membase (code, X86_ESP, 0, FALSE);
3377 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3378 break;
3379 case OP_ICONV_TO_R_UN:
3380 x86_push_imm (code, 0);
3381 x86_push_reg (code, ins->sreg1);
3382 x86_fild_membase (code, X86_ESP, 0, TRUE);
3383 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3384 break;
3385 case OP_X86_FP_LOAD_I8:
3386 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3387 break;
3388 case OP_X86_FP_LOAD_I4:
3389 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3390 break;
3391 case OP_FCONV_TO_R4:
3392 /* Change precision */
3393 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3394 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3395 x86_fld_membase (code, X86_ESP, 0, FALSE);
3396 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3397 break;
3398 case OP_FCONV_TO_I1:
3399 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3400 break;
3401 case OP_FCONV_TO_U1:
3402 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3403 break;
3404 case OP_FCONV_TO_I2:
3405 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3406 break;
3407 case OP_FCONV_TO_U2:
3408 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3409 break;
3410 case OP_FCONV_TO_I4:
3411 case OP_FCONV_TO_I:
3412 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3413 break;
3414 case OP_FCONV_TO_I8:
3415 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3416 x86_fnstcw_membase(code, X86_ESP, 0);
3417 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3418 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3419 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3420 x86_fldcw_membase (code, X86_ESP, 2);
3421 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3422 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3423 x86_pop_reg (code, ins->dreg);
3424 x86_pop_reg (code, ins->backend.reg3);
3425 x86_fldcw_membase (code, X86_ESP, 0);
3426 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3427 break;
3428 case OP_LCONV_TO_R8_2:
3429 x86_push_reg (code, ins->sreg2);
3430 x86_push_reg (code, ins->sreg1);
3431 x86_fild_membase (code, X86_ESP, 0, TRUE);
3432 /* Change precision */
3433 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3434 x86_fld_membase (code, X86_ESP, 0, TRUE);
3435 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3436 break;
3437 case OP_LCONV_TO_R4_2:
3438 x86_push_reg (code, ins->sreg2);
3439 x86_push_reg (code, ins->sreg1);
3440 x86_fild_membase (code, X86_ESP, 0, TRUE);
3441 /* Change precision */
3442 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3443 x86_fld_membase (code, X86_ESP, 0, FALSE);
3444 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3445 break;
3446 case OP_LCONV_TO_R_UN_2: {
3447 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3448 guint8 *br;
3449
3450 /* load 64bit integer to FP stack */
3451 x86_push_reg (code, ins->sreg2);
3452 x86_push_reg (code, ins->sreg1);
3453 x86_fild_membase (code, X86_ESP, 0, TRUE);
3454
3455 /* test if lreg is negative */
3456 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3457 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3458
3459 /* add correction constant mn */
3460 if (cfg->compile_aot) {
3461 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3462 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3463 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3464 x86_fld80_membase (code, X86_ESP, 2);
3465 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3466 } else {
3467 x86_fld80_mem (code, mn);
3468 }
3469 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3470
3471 x86_patch (br, code);
3472
3473 /* Change precision */
3474 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3475 x86_fld_membase (code, X86_ESP, 0, TRUE);
3476
3477 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3478
3479 break;
3480 }
3481 case OP_LCONV_TO_OVF_I:
3482 case OP_LCONV_TO_OVF_I4_2: {
3483 guint8 *br [3], *label [1];
3484 MonoInst *tins;
3485
3486 /*
3487 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3488 */
3489 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3490
3491 /* If the low word top bit is set, see if we are negative */
3492 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3493 /* We are not negative (no top bit set, check for our top word to be zero */
3494 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3495 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3496 label [0] = code;
3497
3498 /* throw exception */
3499 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3500 if (tins) {
3501 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3502 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3503 x86_jump8 (code, 0);
3504 else
3505 x86_jump32 (code, 0);
3506 } else {
3507 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3508 x86_jump32 (code, 0);
3509 }
3510
3511
3512 x86_patch (br [0], code);
3513 /* our top bit is set, check that top word is 0xfffffff */
3514 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3515
3516 x86_patch (br [1], code);
3517 /* nope, emit exception */
3518 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3519 x86_patch (br [2], label [0]);
3520
3521 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
3522 break;
3523 }
3524 case OP_FMOVE:
3525 /* Not needed on the fp stack */
3526 break;
3527 case OP_MOVE_F_TO_I4:
3528 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3529 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3530 break;
3531 case OP_MOVE_I4_TO_F:
3532 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3533 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3534 break;
3535 case OP_FADD:
3536 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3537 break;
3538 case OP_FSUB:
3539 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3540 break;
3541 case OP_FMUL:
3542 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3543 break;
3544 case OP_FDIV:
3545 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3546 break;
3547 case OP_FNEG:
3548 x86_fchs (code);
3549 break;
3550 case OP_SIN:
3551 x86_fsin (code);
3552 x86_fldz (code);
3553 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3554 break;
3555 case OP_COS:
3556 x86_fcos (code);
3557 x86_fldz (code);
3558 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3559 break;
3560 case OP_ABS:
3561 x86_fabs (code);
3562 break;
3563 case OP_TAN: {
3564 /*
3565 * it really doesn't make sense to inline all this code,
3566 * it's here just to show that things may not be as simple
3567 * as they appear.
3568 */
3569 guchar *check_pos, *end_tan, *pop_jump;
3570 x86_push_reg (code, X86_EAX);
3571 x86_fptan (code);
3572 x86_fnstsw (code);
3573 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3574 check_pos = code;
3575 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3576 x86_fstp (code, 0); /* pop the 1.0 */
3577 end_tan = code;
3578 x86_jump8 (code, 0);
3579 x86_fldpi (code);
3580 x86_fp_op (code, X86_FADD, 0);
3581 x86_fxch (code, 1);
3582 x86_fprem1 (code);
3583 x86_fstsw (code);
3584 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3585 pop_jump = code;
3586 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3587 x86_fstp (code, 1);
3588 x86_fptan (code);
3589 x86_patch (pop_jump, code);
3590 x86_fstp (code, 0); /* pop the 1.0 */
3591 x86_patch (check_pos, code);
3592 x86_patch (end_tan, code);
3593 x86_fldz (code);
3594 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3595 x86_pop_reg (code, X86_EAX);
3596 break;
3597 }
3598 case OP_ATAN:
3599 x86_fld1 (code);
3600 x86_fpatan (code);
3601 x86_fldz (code);
3602 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3603 break;
3604 case OP_SQRT:
3605 x86_fsqrt (code);
3606 break;
3607 case OP_ROUND:
3608 x86_frndint (code);
3609 break;
3610 case OP_IMIN:
3611 g_assert (cfg->opt & MONO_OPT_CMOV);
3612 g_assert (ins->dreg == ins->sreg1);
3613 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3614 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3615 break;
3616 case OP_IMIN_UN:
3617 g_assert (cfg->opt & MONO_OPT_CMOV);
3618 g_assert (ins->dreg == ins->sreg1);
3619 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3620 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3621 break;
3622 case OP_IMAX:
3623 g_assert (cfg->opt & MONO_OPT_CMOV);
3624 g_assert (ins->dreg == ins->sreg1);
3625 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3626 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3627 break;
3628 case OP_IMAX_UN:
3629 g_assert (cfg->opt & MONO_OPT_CMOV);
3630 g_assert (ins->dreg == ins->sreg1);
3631 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3632 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3633 break;
3634 case OP_X86_FPOP:
3635 x86_fstp (code, 0);
3636 break;
3637 case OP_X86_FXCH:
3638 x86_fxch (code, ins->inst_imm);
3639 break;
3640 case OP_FREM: {
3641 guint8 *l1, *l2;
3642
3643 x86_push_reg (code, X86_EAX);
3644 /* we need to exchange ST(0) with ST(1) */
3645 x86_fxch (code, 1);
3646
3647 /* this requires a loop, because fprem somtimes
3648 * returns a partial remainder */
3649 l1 = code;
3650 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3651 /* x86_fprem1 (code); */
3652 x86_fprem (code);
3653 x86_fnstsw (code);
3654 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3655 l2 = code;
3656 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3657 x86_patch (l2, l1);
3658
3659 /* pop result */
3660 x86_fstp (code, 1);
3661
3662 x86_pop_reg (code, X86_EAX);
3663 break;
3664 }
3665 case OP_FCOMPARE:
3666 if (cfg->opt & MONO_OPT_FCMOV) {
3667 x86_fcomip (code, 1);
3668 x86_fstp (code, 0);
3669 break;
3670 }
3671 /* this overwrites EAX */
3672 EMIT_FPCOMPARE(code);
3673 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3674 break;
3675 case OP_FCEQ:
3676 case OP_FCNEQ:
3677 if (cfg->opt & MONO_OPT_FCMOV) {
3678 /* zeroing the register at the start results in
3679 * shorter and faster code (we can also remove the widening op)
3680 */
3681 guchar *unordered_check;
3682 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3683 x86_fcomip (code, 1);
3684 x86_fstp (code, 0);
3685 unordered_check = code;
3686 x86_branch8 (code, X86_CC_P, 0, FALSE);
3687 if (ins->opcode == OP_FCEQ) {
3688 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3689 x86_patch (unordered_check, code);
3690 } else {
3691 guchar *jump_to_end;
3692 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3693 jump_to_end = code;
3694 x86_jump8 (code, 0);
3695 x86_patch (unordered_check, code);
3696 x86_inc_reg (code, ins->dreg);
3697 x86_patch (jump_to_end, code);
3698 }
3699
3700 break;
3701 }
3702 if (ins->dreg != X86_EAX)
3703 x86_push_reg (code, X86_EAX);
3704
3705 EMIT_FPCOMPARE(code);
3706 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3707 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3708 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3709 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3710
3711 if (ins->dreg != X86_EAX)
3712 x86_pop_reg (code, X86_EAX);
3713 break;
3714 case OP_FCLT:
3715 case OP_FCLT_UN:
3716 if (cfg->opt & MONO_OPT_FCMOV) {
3717 /* zeroing the register at the start results in
3718 * shorter and faster code (we can also remove the widening op)
3719 */
3720 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3721 x86_fcomip (code, 1);
3722 x86_fstp (code, 0);
3723 if (ins->opcode == OP_FCLT_UN) {
3724 guchar *unordered_check = code;
3725 guchar *jump_to_end;
3726 x86_branch8 (code, X86_CC_P, 0, FALSE);
3727 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3728 jump_to_end = code;
3729 x86_jump8 (code, 0);
3730 x86_patch (unordered_check, code);
3731 x86_inc_reg (code, ins->dreg);
3732 x86_patch (jump_to_end, code);
3733 } else {
3734 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3735 }
3736 break;
3737 }
3738 if (ins->dreg != X86_EAX)
3739 x86_push_reg (code, X86_EAX);
3740
3741 EMIT_FPCOMPARE(code);
3742 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3743 if (ins->opcode == OP_FCLT_UN) {
3744 guchar *is_not_zero_check, *end_jump;
3745 is_not_zero_check = code;
3746 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3747 end_jump = code;
3748 x86_jump8 (code, 0);
3749 x86_patch (is_not_zero_check, code);
3750 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3751
3752 x86_patch (end_jump, code);
3753 }
3754 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3755 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3756
3757 if (ins->dreg != X86_EAX)
3758 x86_pop_reg (code, X86_EAX);
3759 break;
3760 case OP_FCLE: {
3761 guchar *unordered_check;
3762 guchar *jump_to_end;
3763 if (cfg->opt & MONO_OPT_FCMOV) {
3764 /* zeroing the register at the start results in
3765 * shorter and faster code (we can also remove the widening op)
3766 */
3767 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3768 x86_fcomip (code, 1);
3769 x86_fstp (code, 0);
3770 unordered_check = code;
3771 x86_branch8 (code, X86_CC_P, 0, FALSE);
3772 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3773 x86_patch (unordered_check, code);
3774 break;
3775 }
3776 if (ins->dreg != X86_EAX)
3777 x86_push_reg (code, X86_EAX);
3778
3779 EMIT_FPCOMPARE(code);
3780 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3781 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3782 unordered_check = code;
3783 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3784
3785 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3786 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3787 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3788 jump_to_end = code;
3789 x86_jump8 (code, 0);
3790 x86_patch (unordered_check, code);
3791 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3792 x86_patch (jump_to_end, code);
3793
3794 if (ins->dreg != X86_EAX)
3795 x86_pop_reg (code, X86_EAX);
3796 break;
3797 }
3798 case OP_FCGT:
3799 case OP_FCGT_UN:
3800 if (cfg->opt & MONO_OPT_FCMOV) {
3801 /* zeroing the register at the start results in
3802 * shorter and faster code (we can also remove the widening op)
3803 */
3804 guchar *unordered_check;
3805 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3806 x86_fcomip (code, 1);
3807 x86_fstp (code, 0);
3808 if (ins->opcode == OP_FCGT) {
3809 unordered_check = code;
3810 x86_branch8 (code, X86_CC_P, 0, FALSE);
3811 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3812 x86_patch (unordered_check, code);
3813 } else {
3814 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3815 }
3816 break;
3817 }
3818 if (ins->dreg != X86_EAX)
3819 x86_push_reg (code, X86_EAX);
3820
3821 EMIT_FPCOMPARE(code);
3822 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3823 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3824 if (ins->opcode == OP_FCGT_UN) {
3825 guchar *is_not_zero_check, *end_jump;
3826 is_not_zero_check = code;
3827 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3828 end_jump = code;
3829 x86_jump8 (code, 0);
3830 x86_patch (is_not_zero_check, code);
3831 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3832
3833 x86_patch (end_jump, code);
3834 }
3835 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3836 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3837
3838 if (ins->dreg != X86_EAX)
3839 x86_pop_reg (code, X86_EAX);
3840 break;
3841 case OP_FCGE: {
3842 guchar *unordered_check;
3843 guchar *jump_to_end;
3844 if (cfg->opt & MONO_OPT_FCMOV) {
3845 /* zeroing the register at the start results in
3846 * shorter and faster code (we can also remove the widening op)
3847 */
3848 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3849 x86_fcomip (code, 1);
3850 x86_fstp (code, 0);
3851 unordered_check = code;
3852 x86_branch8 (code, X86_CC_P, 0, FALSE);
3853 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3854 x86_patch (unordered_check, code);
3855 break;
3856 }
3857 if (ins->dreg != X86_EAX)
3858 x86_push_reg (code, X86_EAX);
3859
3860 EMIT_FPCOMPARE(code);
3861 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3862 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3863 unordered_check = code;
3864 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3865
3866 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3867 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3868 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3869 jump_to_end = code;
3870 x86_jump8 (code, 0);
3871 x86_patch (unordered_check, code);
3872 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3873 x86_patch (jump_to_end, code);
3874
3875 if (ins->dreg != X86_EAX)
3876 x86_pop_reg (code, X86_EAX);
3877 break;
3878 }
3879 case OP_FBEQ:
3880 if (cfg->opt & MONO_OPT_FCMOV) {
3881 guchar *jump = code;
3882 x86_branch8 (code, X86_CC_P, 0, TRUE);
3883 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3884 x86_patch (jump, code);
3885 break;
3886 }
3887 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3888 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3889 break;
3890 case OP_FBNE_UN:
3891 /* Branch if C013 != 100 */
3892 if (cfg->opt & MONO_OPT_FCMOV) {
3893 /* branch if !ZF or (PF|CF) */
3894 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3895 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3896 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3897 break;
3898 }
3899 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3900 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3901 break;
3902 case OP_FBLT:
3903 if (cfg->opt & MONO_OPT_FCMOV) {
3904 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3905 break;
3906 }
3907 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3908 break;
3909 case OP_FBLT_UN:
3910 if (cfg->opt & MONO_OPT_FCMOV) {
3911 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3912 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3913 break;
3914 }
3915 if (ins->opcode == OP_FBLT_UN) {
3916 guchar *is_not_zero_check, *end_jump;
3917 is_not_zero_check = code;
3918 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3919 end_jump = code;
3920 x86_jump8 (code, 0);
3921 x86_patch (is_not_zero_check, code);
3922 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3923
3924 x86_patch (end_jump, code);
3925 }
3926 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3927 break;
3928 case OP_FBGT:
3929 case OP_FBGT_UN:
3930 if (cfg->opt & MONO_OPT_FCMOV) {
3931 if (ins->opcode == OP_FBGT) {
3932 guchar *br1;
3933
3934 /* skip branch if C1=1 */
3935 br1 = code;
3936 x86_branch8 (code, X86_CC_P, 0, FALSE);
3937 /* branch if (C0 | C3) = 1 */
3938 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3939 x86_patch (br1, code);
3940 } else {
3941 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3942 }
3943 break;
3944 }
3945 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3946 if (ins->opcode == OP_FBGT_UN) {
3947 guchar *is_not_zero_check, *end_jump;
3948 is_not_zero_check = code;
3949 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3950 end_jump = code;
3951 x86_jump8 (code, 0);
3952 x86_patch (is_not_zero_check, code);
3953 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3954
3955 x86_patch (end_jump, code);
3956 }
3957 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3958 break;
3959 case OP_FBGE:
3960 /* Branch if C013 == 100 or 001 */
3961 if (cfg->opt & MONO_OPT_FCMOV) {
3962 guchar *br1;
3963
3964 /* skip branch if C1=1 */
3965 br1 = code;
3966 x86_branch8 (code, X86_CC_P, 0, FALSE);
3967 /* branch if (C0 | C3) = 1 */
3968 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3969 x86_patch (br1, code);
3970 break;
3971 }
3972 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3973 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3974 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3975 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3976 break;
3977 case OP_FBGE_UN:
3978 /* Branch if C013 == 000 */
3979 if (cfg->opt & MONO_OPT_FCMOV) {
3980 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3981 break;
3982 }
3983 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3984 break;
3985 case OP_FBLE:
3986 /* Branch if C013=000 or 100 */
3987 if (cfg->opt & MONO_OPT_FCMOV) {
3988 guchar *br1;
3989
3990 /* skip branch if C1=1 */
3991 br1 = code;
3992 x86_branch8 (code, X86_CC_P, 0, FALSE);
3993 /* branch if C0=0 */
3994 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3995 x86_patch (br1, code);
3996 break;
3997 }
3998 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3999 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4000 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4001 break;
4002 case OP_FBLE_UN:
4003 /* Branch if C013 != 001 */
4004 if (cfg->opt & MONO_OPT_FCMOV) {
4005 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4006 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4007 break;
4008 }
4009 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4010 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4011 break;
4012 case OP_CKFINITE: {
4013 guchar *br1;
4014 x86_push_reg (code, X86_EAX);
4015 x86_fxam (code);
4016 x86_fnstsw (code);
4017 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4018 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4019 x86_pop_reg (code, X86_EAX);
4020
4021 /* Have to clean up the fp stack before throwing the exception */
4022 br1 = code;
4023 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4024
4025 x86_fstp (code, 0);
4026 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4027
4028 x86_patch (br1, code);
4029 break;
4030 }
4031 case OP_TLS_GET: {
4032 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4033 break;
4034 }
4035 case OP_TLS_SET: {
4036 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4037 break;
4038 }
4039 case OP_MEMORY_BARRIER: {
4040 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4041 x86_prefix (code, X86_LOCK_PREFIX);
4042 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4043 }
4044 break;
4045 }
4046 case OP_ATOMIC_ADD_I4: {
4047 int dreg = ins->dreg;
4048
4049 g_assert (cfg->has_atomic_add_i4);
4050
4051 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4052 if (ins->sreg2 == dreg) {
4053 if (dreg == X86_EBX) {
4054 dreg = X86_EDI;
4055 if (ins->inst_basereg == X86_EDI)
4056 dreg = X86_ESI;
4057 } else {
4058 dreg = X86_EBX;
4059 if (ins->inst_basereg == X86_EBX)
4060 dreg = X86_EDI;
4061 }
4062 } else if (ins->inst_basereg == dreg) {
4063 if (dreg == X86_EBX) {
4064 dreg = X86_EDI;
4065 if (ins->sreg2 == X86_EDI)
4066 dreg = X86_ESI;
4067 } else {
4068 dreg = X86_EBX;
4069 if (ins->sreg2 == X86_EBX)
4070 dreg = X86_EDI;
4071 }
4072 }
4073
4074 if (dreg != ins->dreg) {
4075 x86_push_reg (code, dreg);
4076 }
4077
4078 x86_mov_reg_reg (code, dreg, ins->sreg2);
4079 x86_prefix (code, X86_LOCK_PREFIX);
4080 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4081 /* dreg contains the old value, add with sreg2 value */
4082 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4083
4084 if (ins->dreg != dreg) {
4085 x86_mov_reg_reg (code, ins->dreg, dreg);
4086 x86_pop_reg (code, dreg);
4087 }
4088
4089 break;
4090 }
4091 case OP_ATOMIC_EXCHANGE_I4: {
4092 guchar *br[2];
4093 int sreg2 = ins->sreg2;
4094 int breg = ins->inst_basereg;
4095
4096 g_assert (cfg->has_atomic_exchange_i4);
4097
4098 /* cmpxchg uses eax as comperand, need to make sure we can use it
4099 * hack to overcome limits in x86 reg allocator
4100 * (req: dreg == eax and sreg2 != eax and breg != eax)
4101 */
4102 g_assert (ins->dreg == X86_EAX);
4103
4104 /* We need the EAX reg for the cmpxchg */
4105 if (ins->sreg2 == X86_EAX) {
4106 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4107 x86_push_reg (code, sreg2);
4108 x86_mov_reg_reg (code, sreg2, X86_EAX);
4109 }
4110
4111 if (breg == X86_EAX) {
4112 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4113 x86_push_reg (code, breg);
4114 x86_mov_reg_reg (code, breg, X86_EAX);
4115 }
4116
4117 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4118
4119 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4120 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4121 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4122 x86_patch (br [1], br [0]);
4123
4124 if (breg != ins->inst_basereg)
4125 x86_pop_reg (code, breg);
4126
4127 if (ins->sreg2 != sreg2)
4128 x86_pop_reg (code, sreg2);
4129
4130 break;
4131 }
4132 case OP_ATOMIC_CAS_I4: {
4133 g_assert (ins->dreg == X86_EAX);
4134 g_assert (ins->sreg3 == X86_EAX);
4135 g_assert (ins->sreg1 != X86_EAX);
4136 g_assert (ins->sreg1 != ins->sreg2);
4137
4138 x86_prefix (code, X86_LOCK_PREFIX);
4139 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4140 break;
4141 }
4142 case OP_ATOMIC_LOAD_I1: {
4143 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4144 break;
4145 }
4146 case OP_ATOMIC_LOAD_U1: {
4147 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4148 break;
4149 }
4150 case OP_ATOMIC_LOAD_I2: {
4151 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4152 break;
4153 }
4154 case OP_ATOMIC_LOAD_U2: {
4155 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4156 break;
4157 }
4158 case OP_ATOMIC_LOAD_I4:
4159 case OP_ATOMIC_LOAD_U4: {
4160 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4161 break;
4162 }
4163 case OP_ATOMIC_LOAD_R4:
4164 case OP_ATOMIC_LOAD_R8: {
4165 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4166 break;
4167 }
4168 case OP_ATOMIC_STORE_I1:
4169 case OP_ATOMIC_STORE_U1:
4170 case OP_ATOMIC_STORE_I2:
4171 case OP_ATOMIC_STORE_U2:
4172 case OP_ATOMIC_STORE_I4:
4173 case OP_ATOMIC_STORE_U4: {
4174 int size;
4175
4176 switch (ins->opcode) {
4177 case OP_ATOMIC_STORE_I1:
4178 case OP_ATOMIC_STORE_U1:
4179 size = 1;
4180 break;
4181 case OP_ATOMIC_STORE_I2:
4182 case OP_ATOMIC_STORE_U2:
4183 size = 2;
4184 break;
4185 case OP_ATOMIC_STORE_I4:
4186 case OP_ATOMIC_STORE_U4:
4187 size = 4;
4188 break;
4189 }
4190
4191 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4192
4193 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4194 x86_mfence (code);
4195 break;
4196 }
4197 case OP_ATOMIC_STORE_R4:
4198 case OP_ATOMIC_STORE_R8: {
4199 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4200
4201 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4202 x86_mfence (code);
4203 break;
4204 }
4205 case OP_CARD_TABLE_WBARRIER: {
4206 int ptr = ins->sreg1;
4207 int value = ins->sreg2;
4208 guchar *br = NULL;
4209 int nursery_shift, card_table_shift;
4210 gpointer card_table_mask;
4211 size_t nursery_size;
4212 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4213 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4214 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4215
4216 /*
4217 * We need one register we can clobber, we choose EDX and make sreg1
4218 * fixed EAX to work around limitations in the local register allocator.
4219 * sreg2 might get allocated to EDX, but that is not a problem since
4220 * we use it before clobbering EDX.
4221 */
4222 g_assert (ins->sreg1 == X86_EAX);
4223
4224 /*
4225 * This is the code we produce:
4226 *
4227 * edx = value
4228 * edx >>= nursery_shift
4229 * cmp edx, (nursery_start >> nursery_shift)
4230 * jne done
4231 * edx = ptr
4232 * edx >>= card_table_shift
4233 * card_table[edx] = 1
4234 * done:
4235 */
4236
4237 if (card_table_nursery_check) {
4238 if (value != X86_EDX)
4239 x86_mov_reg_reg (code, X86_EDX, value);
4240 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4241 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4242 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4243 }
4244 x86_mov_reg_reg (code, X86_EDX, ptr);
4245 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4246 if (card_table_mask)
4247 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4248 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4249 if (card_table_nursery_check)
4250 x86_patch (br, code);
4251 break;
4252 }
4253 #ifdef MONO_ARCH_SIMD_INTRINSICS
4254 case OP_ADDPS:
4255 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4256 break;
4257 case OP_DIVPS:
4258 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4259 break;
4260 case OP_MULPS:
4261 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4262 break;
4263 case OP_SUBPS:
4264 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4265 break;
4266 case OP_MAXPS:
4267 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4268 break;
4269 case OP_MINPS:
4270 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4271 break;
4272 case OP_COMPPS:
4273 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4274 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4275 break;
4276 case OP_ANDPS:
4277 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4278 break;
4279 case OP_ANDNPS:
4280 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4281 break;
4282 case OP_ORPS:
4283 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4284 break;
4285 case OP_XORPS:
4286 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4287 break;
4288 case OP_SQRTPS:
4289 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4290 break;
4291 case OP_RSQRTPS:
4292 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4293 break;
4294 case OP_RCPPS:
4295 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4296 break;
4297 case OP_ADDSUBPS:
4298 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4299 break;
4300 case OP_HADDPS:
4301 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4302 break;
4303 case OP_HSUBPS:
4304 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4305 break;
4306 case OP_DUPPS_HIGH:
4307 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4308 break;
4309 case OP_DUPPS_LOW:
4310 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4311 break;
4312
4313 case OP_PSHUFLEW_HIGH:
4314 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4315 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4316 break;
4317 case OP_PSHUFLEW_LOW:
4318 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4319 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4320 break;
4321 case OP_PSHUFLED:
4322 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4323 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4324 break;
4325 case OP_SHUFPS:
4326 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4327 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4328 break;
4329 case OP_SHUFPD:
4330 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4331 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4332 break;
4333
4334 case OP_ADDPD:
4335 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4336 break;
4337 case OP_DIVPD:
4338 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4339 break;
4340 case OP_MULPD:
4341 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4342 break;
4343 case OP_SUBPD:
4344 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4345 break;
4346 case OP_MAXPD:
4347 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4348 break;
4349 case OP_MINPD:
4350 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4351 break;
4352 case OP_COMPPD:
4353 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4354 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4355 break;
4356 case OP_ANDPD:
4357 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4358 break;
4359 case OP_ANDNPD:
4360 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4361 break;
4362 case OP_ORPD:
4363 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4364 break;
4365 case OP_XORPD:
4366 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4367 break;
4368 case OP_SQRTPD:
4369 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4370 break;
4371 case OP_ADDSUBPD:
4372 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4373 break;
4374 case OP_HADDPD:
4375 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4376 break;
4377 case OP_HSUBPD:
4378 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4379 break;
4380 case OP_DUPPD:
4381 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4382 break;
4383
4384 case OP_EXTRACT_MASK:
4385 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4386 break;
4387
4388 case OP_PAND:
4389 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4390 break;
4391 case OP_POR:
4392 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4393 break;
4394 case OP_PXOR:
4395 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4396 break;
4397
4398 case OP_PADDB:
4399 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4400 break;
4401 case OP_PADDW:
4402 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4403 break;
4404 case OP_PADDD:
4405 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4406 break;
4407 case OP_PADDQ:
4408 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4409 break;
4410
4411 case OP_PSUBB:
4412 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4413 break;
4414 case OP_PSUBW:
4415 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4416 break;
4417 case OP_PSUBD:
4418 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4419 break;
4420 case OP_PSUBQ:
4421 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4422 break;
4423
4424 case OP_PMAXB_UN:
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4426 break;
4427 case OP_PMAXW_UN:
4428 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4429 break;
4430 case OP_PMAXD_UN:
4431 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4432 break;
4433
4434 case OP_PMAXB:
4435 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4436 break;
4437 case OP_PMAXW:
4438 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4439 break;
4440 case OP_PMAXD:
4441 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4442 break;
4443
4444 case OP_PAVGB_UN:
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4446 break;
4447 case OP_PAVGW_UN:
4448 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4449 break;
4450
4451 case OP_PMINB_UN:
4452 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4453 break;
4454 case OP_PMINW_UN:
4455 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4456 break;
4457 case OP_PMIND_UN:
4458 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4459 break;
4460
4461 case OP_PMINB:
4462 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4463 break;
4464 case OP_PMINW:
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4466 break;
4467 case OP_PMIND:
4468 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4469 break;
4470
4471 case OP_PCMPEQB:
4472 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4473 break;
4474 case OP_PCMPEQW:
4475 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4476 break;
4477 case OP_PCMPEQD:
4478 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4479 break;
4480 case OP_PCMPEQQ:
4481 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4482 break;
4483
4484 case OP_PCMPGTB:
4485 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4486 break;
4487 case OP_PCMPGTW:
4488 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4489 break;
4490 case OP_PCMPGTD:
4491 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4492 break;
4493 case OP_PCMPGTQ:
4494 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4495 break;
4496
4497 case OP_PSUM_ABS_DIFF:
4498 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4499 break;
4500
4501 case OP_UNPACK_LOWB:
4502 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4503 break;
4504 case OP_UNPACK_LOWW:
4505 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4506 break;
4507 case OP_UNPACK_LOWD:
4508 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4509 break;
4510 case OP_UNPACK_LOWQ:
4511 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4512 break;
4513 case OP_UNPACK_LOWPS:
4514 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4515 break;
4516 case OP_UNPACK_LOWPD:
4517 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4518 break;
4519
4520 case OP_UNPACK_HIGHB:
4521 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4522 break;
4523 case OP_UNPACK_HIGHW:
4524 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4525 break;
4526 case OP_UNPACK_HIGHD:
4527 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4528 break;
4529 case OP_UNPACK_HIGHQ:
4530 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4531 break;
4532 case OP_UNPACK_HIGHPS:
4533 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4534 break;
4535 case OP_UNPACK_HIGHPD:
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4537 break;
4538
4539 case OP_PACKW:
4540 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4541 break;
4542 case OP_PACKD:
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4544 break;
4545 case OP_PACKW_UN:
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4547 break;
4548 case OP_PACKD_UN:
4549 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4550 break;
4551
4552 case OP_PADDB_SAT_UN:
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4554 break;
4555 case OP_PSUBB_SAT_UN:
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4557 break;
4558 case OP_PADDW_SAT_UN:
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4560 break;
4561 case OP_PSUBW_SAT_UN:
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4563 break;
4564
4565 case OP_PADDB_SAT:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4567 break;
4568 case OP_PSUBB_SAT:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4570 break;
4571 case OP_PADDW_SAT:
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4573 break;
4574 case OP_PSUBW_SAT:
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4576 break;
4577
4578 case OP_PMULW:
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4580 break;
4581 case OP_PMULD:
4582 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4583 break;
4584 case OP_PMULQ:
4585 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4586 break;
4587 case OP_PMULW_HIGH_UN:
4588 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4589 break;
4590 case OP_PMULW_HIGH:
4591 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4592 break;
4593
4594 case OP_PSHRW:
4595 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4596 break;
4597 case OP_PSHRW_REG:
4598 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4599 break;
4600
4601 case OP_PSARW:
4602 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4603 break;
4604 case OP_PSARW_REG:
4605 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4606 break;
4607
4608 case OP_PSHLW:
4609 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4610 break;
4611 case OP_PSHLW_REG:
4612 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4613 break;
4614
4615 case OP_PSHRD:
4616 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4617 break;
4618 case OP_PSHRD_REG:
4619 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4620 break;
4621
4622 case OP_PSARD:
4623 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4624 break;
4625 case OP_PSARD_REG:
4626 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4627 break;
4628
4629 case OP_PSHLD:
4630 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4631 break;
4632 case OP_PSHLD_REG:
4633 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4634 break;
4635
4636 case OP_PSHRQ:
4637 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4638 break;
4639 case OP_PSHRQ_REG:
4640 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4641 break;
4642
4643 case OP_PSHLQ:
4644 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4645 break;
4646 case OP_PSHLQ_REG:
4647 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4648 break;
4649
4650 case OP_ICONV_TO_X:
4651 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4652 break;
4653 case OP_EXTRACT_I4:
4654 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4655 break;
4656 case OP_EXTRACT_I1:
4657 case OP_EXTRACT_U1:
4658 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4659 if (ins->inst_c0)
4660 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4661 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4662 break;
4663 case OP_EXTRACT_I2:
4664 case OP_EXTRACT_U2:
4665 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4666 if (ins->inst_c0)
4667 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4668 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4669 break;
4670 case OP_EXTRACT_R8:
4671 if (ins->inst_c0)
4672 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4673 else
4674 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4675 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4676 break;
4677
4678 case OP_INSERT_I2:
4679 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4680 break;
4681 case OP_EXTRACTX_U2:
4682 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4683 break;
4684 case OP_INSERTX_U1_SLOW:
4685 /*sreg1 is the extracted ireg (scratch)
4686 /sreg2 is the to be inserted ireg (scratch)
4687 /dreg is the xreg to receive the value*/
4688
4689 /*clear the bits from the extracted word*/
4690 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4691 /*shift the value to insert if needed*/
4692 if (ins->inst_c0 & 1)
4693 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4694 /*join them together*/
4695 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4697 break;
4698 case OP_INSERTX_I4_SLOW:
4699 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4700 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4701 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4702 break;
4703
4704 case OP_INSERTX_R4_SLOW:
4705 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4706 /*TODO if inst_c0 == 0 use movss*/
4707 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4708 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4709 break;
4710 case OP_INSERTX_R8_SLOW:
4711 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4712 if (cfg->verbose_level)
4713 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4714 if (ins->inst_c0)
4715 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4716 else
4717 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4718 break;
4719
4720 case OP_STOREX_MEMBASE_REG:
4721 case OP_STOREX_MEMBASE:
4722 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4723 break;
4724 case OP_LOADX_MEMBASE:
4725 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4726 break;
4727 case OP_LOADX_ALIGNED_MEMBASE:
4728 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4729 break;
4730 case OP_STOREX_ALIGNED_MEMBASE_REG:
4731 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4732 break;
4733 case OP_STOREX_NTA_MEMBASE_REG:
4734 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4735 break;
4736 case OP_PREFETCH_MEMBASE:
4737 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4738
4739 break;
4740 case OP_XMOVE:
4741 /*FIXME the peephole pass should have killed this*/
4742 if (ins->dreg != ins->sreg1)
4743 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4744 break;
4745 case OP_XZERO:
4746 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4747 break;
4748 case OP_XONES:
4749 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4750 break;
4751
4752 case OP_FCONV_TO_R8_X:
4753 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4754 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4755 break;
4756
4757 case OP_XCONV_R8_TO_I4:
4758 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4759 switch (ins->backend.source_opcode) {
4760 case OP_FCONV_TO_I1:
4761 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4762 break;
4763 case OP_FCONV_TO_U1:
4764 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4765 break;
4766 case OP_FCONV_TO_I2:
4767 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4768 break;
4769 case OP_FCONV_TO_U2:
4770 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4771 break;
4772 }
4773 break;
4774
4775 case OP_EXPAND_I2:
4776 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4777 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4778 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4779 break;
4780 case OP_EXPAND_I4:
4781 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4782 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4783 break;
4784 case OP_EXPAND_R4:
4785 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4786 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4787 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4788 break;
4789 case OP_EXPAND_R8:
4790 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4791 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4792 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4793 break;
4794
4795 case OP_CVTDQ2PD:
4796 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4797 break;
4798 case OP_CVTDQ2PS:
4799 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4800 break;
4801 case OP_CVTPD2DQ:
4802 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4803 break;
4804 case OP_CVTPD2PS:
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4806 break;
4807 case OP_CVTPS2DQ:
4808 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4809 break;
4810 case OP_CVTPS2PD:
4811 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4812 break;
4813 case OP_CVTTPD2DQ:
4814 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4815 break;
4816 case OP_CVTTPS2DQ:
4817 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4818 break;
4819
4820 #endif
4821 case OP_LIVERANGE_START: {
4822 if (cfg->verbose_level > 1)
4823 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4824 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4825 break;
4826 }
4827 case OP_LIVERANGE_END: {
4828 if (cfg->verbose_level > 1)
4829 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4830 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4831 break;
4832 }
4833 case OP_GC_SAFE_POINT: {
4834 guint8 *br [1];
4835
4836 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4837 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4838 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL, "mono_threads_state_poll");
4839 x86_patch (br [0], code);
4840
4841 break;
4842 }
4843 case OP_GC_LIVENESS_DEF:
4844 case OP_GC_LIVENESS_USE:
4845 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4846 ins->backend.pc_offset = code - cfg->native_code;
4847 break;
4848 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4849 ins->backend.pc_offset = code - cfg->native_code;
4850 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4851 break;
4852 case OP_GET_SP:
4853 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
4854 break;
4855 case OP_SET_SP:
4856 x86_mov_reg_reg (code, X86_ESP, ins->sreg1);
4857 break;
4858 case OP_FILL_PROF_CALL_CTX:
4859 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (target_mgreg_t));
4860 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (target_mgreg_t));
4861 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (target_mgreg_t));
4862 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (target_mgreg_t));
4863 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (target_mgreg_t));
4864 break;
4865 default:
4866 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4867 g_assert_not_reached ();
4868 }
4869
4870 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4871 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4872 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4873 g_assert_not_reached ();
4874 }
4875
4876 cpos += max_len;
4877 }
4878
4879 set_code_cursor (cfg, code);
4880 }
4881
4882 #endif /* DISABLE_JIT */
4883
4884 void
4885 mono_arch_register_lowlevel_calls (void)
4886 {
4887 }
4888
4889 void
4890 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4891 {
4892 unsigned char *ip = ji->ip.i + code;
4893
4894 switch (ji->type) {
4895 case MONO_PATCH_INFO_IP:
4896 *((gconstpointer *)(ip)) = target;
4897 break;
4898 case MONO_PATCH_INFO_ABS:
4899 case MONO_PATCH_INFO_METHOD:
4900 case MONO_PATCH_INFO_METHOD_JUMP:
4901 case MONO_PATCH_INFO_JIT_ICALL:
4902 case MONO_PATCH_INFO_BB:
4903 case MONO_PATCH_INFO_LABEL:
4904 case MONO_PATCH_INFO_RGCTX_FETCH:
4905 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4906 x86_patch (ip, (unsigned char*)target);
4907 break;
4908 case MONO_PATCH_INFO_NONE:
4909 break;
4910 case MONO_PATCH_INFO_R4:
4911 case MONO_PATCH_INFO_R8: {
4912 guint32 offset = mono_arch_get_patch_offset (ip);
4913 *((gconstpointer *)(ip + offset)) = target;
4914 break;
4915 }
4916 default: {
4917 guint32 offset = mono_arch_get_patch_offset (ip);
4918 *((gconstpointer *)(ip + offset)) = target;
4919 break;
4920 }
4921 }
4922 }
4923
4924 static G_GNUC_UNUSED void
4925 stack_unaligned (MonoMethod *m, gpointer caller)
4926 {
4927 printf ("%s\n", mono_method_full_name (m, TRUE));
4928 g_assert_not_reached ();
4929 }
4930
4931 guint8 *
4932 mono_arch_emit_prolog (MonoCompile *cfg)
4933 {
4934 MonoMethod *method = cfg->method;
4935 MonoBasicBlock *bb;
4936 MonoMethodSignature *sig;
4937 MonoInst *inst;
4938 CallInfo *cinfo;
4939 ArgInfo *ainfo;
4940 int alloc_size, pos, max_offset, i, cfa_offset;
4941 guint8 *code;
4942 gboolean need_stack_frame;
4943
4944 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4945
4946 code = cfg->native_code = g_malloc (cfg->code_size);
4947
4948 #if 0
4949 {
4950 guint8 *br [16];
4951
4952 /* Check that the stack is aligned on osx */
4953 x86_mov_reg_reg (code, X86_EAX, X86_ESP);
4954 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
4955 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
4956 br [0] = code;
4957 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
4958 x86_push_membase (code, X86_ESP, 0);
4959 x86_push_imm (code, cfg->method);
4960 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
4961 x86_call_reg (code, X86_EAX);
4962 x86_patch (br [0], code);
4963 }
4964 #endif
4965
4966 /* Offset between RSP and the CFA */
4967 cfa_offset = 0;
4968
4969 // CFA = sp + 4
4970 cfa_offset = 4;
4971 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, cfa_offset);
4972 // IP saved at CFA - 4
4973 /* There is no IP reg on x86 */
4974 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4975 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4976
4977 need_stack_frame = needs_stack_frame (cfg);
4978
4979 if (need_stack_frame) {
4980 x86_push_reg (code, X86_EBP);
4981 cfa_offset += 4;
4982 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4983 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4984 x86_mov_reg_reg (code, X86_EBP, X86_ESP);
4985 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4986 /* These are handled automatically by the stack marking code */
4987 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4988 } else {
4989 cfg->frame_reg = X86_ESP;
4990 }
4991
4992 cfg->stack_offset += cfg->param_area;
4993 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4994
4995 alloc_size = cfg->stack_offset;
4996 pos = 0;
4997
4998 if (!method->save_lmf) {
4999 if (cfg->used_int_regs & (1 << X86_EBX)) {
5000 x86_push_reg (code, X86_EBX);
5001 pos += 4;
5002 cfa_offset += 4;
5003 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5004 /* These are handled automatically by the stack marking code */
5005 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5006 }
5007
5008 if (cfg->used_int_regs & (1 << X86_EDI)) {
5009 x86_push_reg (code, X86_EDI);
5010 pos += 4;
5011 cfa_offset += 4;
5012 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5013 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5014 }
5015
5016 if (cfg->used_int_regs & (1 << X86_ESI)) {
5017 x86_push_reg (code, X86_ESI);
5018 pos += 4;
5019 cfa_offset += 4;
5020 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5021 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5022 }
5023 }
5024
5025 alloc_size -= pos;
5026
5027 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5028 if (mono_do_x86_stack_align && need_stack_frame) {
5029 int tot = alloc_size + pos + 4; /* ret ip */
5030 if (need_stack_frame)
5031 tot += 4; /* ebp */
5032 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5033 if (tot) {
5034 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5035 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (target_mgreg_t))
5036 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5037 }
5038 }
5039
5040 cfg->arch.sp_fp_offset = alloc_size + pos;
5041
5042 if (alloc_size) {
5043 /* See mono_emit_stack_alloc */
5044 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5045 guint32 remaining_size = alloc_size;
5046 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5047 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5048 set_code_cursor (cfg, code);
5049 code = realloc_code (cfg, required_code_size);
5050 while (remaining_size >= 0x1000) {
5051 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5052 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5053 remaining_size -= 0x1000;
5054 }
5055 if (remaining_size)
5056 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5057 #else
5058 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5059 #endif
5060
5061 g_assert (need_stack_frame);
5062 }
5063
5064 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5065 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5066 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5067 }
5068
5069 #if DEBUG_STACK_ALIGNMENT
5070 /* check the stack is aligned */
5071 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5072 x86_mov_reg_reg (code, X86_ECX, X86_ESP);
5073 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5074 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5075 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5076 x86_breakpoint (code);
5077 }
5078 #endif
5079
5080 /* compute max_offset in order to use short forward jumps */
5081 max_offset = 0;
5082 if (cfg->opt & MONO_OPT_BRANCH) {
5083 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5084 MonoInst *ins;
5085 bb->max_offset = max_offset;
5086
5087 /* max alignment for loops */
5088 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5089 max_offset += LOOP_ALIGNMENT;
5090 MONO_BB_FOR_EACH_INS (bb, ins) {
5091 if (ins->opcode == OP_LABEL)
5092 ins->inst_c1 = max_offset;
5093 max_offset += ins_get_size (ins->opcode);
5094 }
5095 }
5096 }
5097
5098 /* store runtime generic context */
5099 if (cfg->rgctx_var) {
5100 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5101
5102 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5103 }
5104
5105 if (method->save_lmf)
5106 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5107
5108 {
5109 MonoInst *ins;
5110
5111 if (cfg->arch.ss_tramp_var) {
5112 /* Initialize ss_tramp_var */
5113 ins = cfg->arch.ss_tramp_var;
5114 g_assert (ins->opcode == OP_REGOFFSET);
5115
5116 g_assert (!cfg->compile_aot);
5117 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5118 }
5119
5120 if (cfg->arch.bp_tramp_var) {
5121 /* Initialize bp_tramp_var */
5122 ins = cfg->arch.bp_tramp_var;
5123 g_assert (ins->opcode == OP_REGOFFSET);
5124
5125 g_assert (!cfg->compile_aot);
5126 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5127 }
5128 }
5129
5130 /* load arguments allocated to register from the stack */
5131 sig = mono_method_signature_internal (method);
5132 pos = 0;
5133
5134 cinfo = cfg->arch.cinfo;
5135
5136 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5137 inst = cfg->args [pos];
5138 ainfo = &cinfo->args [pos];
5139 if (inst->opcode == OP_REGVAR) {
5140 if (storage_in_ireg (ainfo->storage)) {
5141 x86_mov_reg_reg (code, inst->dreg, ainfo->reg);
5142 } else {
5143 g_assert (need_stack_frame);
5144 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5145 }
5146 if (cfg->verbose_level > 2)
5147 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5148 } else {
5149 if (storage_in_ireg (ainfo->storage)) {
5150 x86_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, 4);
5151 }
5152 }
5153 pos++;
5154 }
5155
5156 set_code_cursor (cfg, code);
5157
5158 return code;
5159 }
5160
5161 void
5162 mono_arch_emit_epilog (MonoCompile *cfg)
5163 {
5164 MonoMethod *method = cfg->method;
5165 MonoMethodSignature *sig = mono_method_signature_internal (method);
5166 int i, quad, pos;
5167 guint32 stack_to_pop;
5168 guint8 *code;
5169 int max_epilog_size = 16;
5170 CallInfo *cinfo;
5171 gboolean need_stack_frame = needs_stack_frame (cfg);
5172
5173 if (cfg->method->save_lmf)
5174 max_epilog_size += 128;
5175
5176 code = realloc_code (cfg, max_epilog_size);
5177
5178 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5179 pos = 0;
5180
5181 if (method->save_lmf) {
5182 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5183
5184 /* restore caller saved regs */
5185 if (cfg->used_int_regs & (1 << X86_EBX)) {
5186 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5187 }
5188
5189 if (cfg->used_int_regs & (1 << X86_EDI)) {
5190 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5191 }
5192 if (cfg->used_int_regs & (1 << X86_ESI)) {
5193 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5194 }
5195
5196 /* EBP is restored by LEAVE */
5197 } else {
5198 for (i = 0; i < X86_NREG; ++i) {
5199 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5200 pos -= 4;
5201 }
5202 }
5203
5204 g_assert (!pos || need_stack_frame);
5205 if (pos) {
5206 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5207 }
5208
5209 if (cfg->used_int_regs & (1 << X86_ESI)) {
5210 x86_pop_reg (code, X86_ESI);
5211 }
5212 if (cfg->used_int_regs & (1 << X86_EDI)) {
5213 x86_pop_reg (code, X86_EDI);
5214 }
5215 if (cfg->used_int_regs & (1 << X86_EBX)) {
5216 x86_pop_reg (code, X86_EBX);
5217 }
5218 }
5219
5220 /* Load returned vtypes into registers if needed */
5221 cinfo = cfg->arch.cinfo;
5222 if (cinfo->ret.storage == ArgValuetypeInReg) {
5223 for (quad = 0; quad < 2; quad ++) {
5224 switch (cinfo->ret.pair_storage [quad]) {
5225 case ArgInIReg:
5226 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), 4);
5227 break;
5228 case ArgOnFloatFpStack:
5229 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), FALSE);
5230 break;
5231 case ArgOnDoubleFpStack:
5232 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), TRUE);
5233 break;
5234 case ArgNone:
5235 break;
5236 default:
5237 g_assert_not_reached ();
5238 }
5239 }
5240 }
5241
5242 if (need_stack_frame)
5243 x86_leave (code);
5244
5245 if (CALLCONV_IS_STDCALL (sig)) {
5246 MonoJitArgumentInfo *arg_info = g_newa (MonoJitArgumentInfo, sig->param_count + 1);
5247
5248 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5249 } else if (cinfo->callee_stack_pop)
5250 stack_to_pop = cinfo->callee_stack_pop;
5251 else
5252 stack_to_pop = 0;
5253
5254 if (stack_to_pop) {
5255 g_assert (need_stack_frame);
5256 x86_ret_imm (code, stack_to_pop);
5257 } else {
5258 x86_ret (code);
5259 }
5260
5261 set_code_cursor (cfg, code);
5262 }
5263
5264 void
5265 mono_arch_emit_exceptions (MonoCompile *cfg)
5266 {
5267 MonoJumpInfo *patch_info;
5268 int nthrows, i;
5269 guint8 *code;
5270 MonoClass *exc_classes [16];
5271 guint8 *exc_throw_start [16], *exc_throw_end [16];
5272 guint32 code_size;
5273 int exc_count = 0;
5274
5275 /* Compute needed space */
5276 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5277 if (patch_info->type == MONO_PATCH_INFO_EXC)
5278 exc_count++;
5279 }
5280
5281 /*
5282 * make sure we have enough space for exceptions
5283 * 16 is the size of two push_imm instructions and a call
5284 */
5285 if (cfg->compile_aot)
5286 code_size = exc_count * 32;
5287 else
5288 code_size = exc_count * 16;
5289
5290 code = realloc_code (cfg, code_size);
5291
5292 nthrows = 0;
5293 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5294 switch (patch_info->type) {
5295 case MONO_PATCH_INFO_EXC: {
5296 MonoClass *exc_class;
5297 guint8 *buf, *buf2;
5298 guint32 throw_ip;
5299
5300 x86_patch (patch_info->ip.i + cfg->native_code, code);
5301
5302 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5303 throw_ip = patch_info->ip.i;
5304
5305 /* Find a throw sequence for the same exception class */
5306 for (i = 0; i < nthrows; ++i)
5307 if (exc_classes [i] == exc_class)
5308 break;
5309 if (i < nthrows) {
5310 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5311 x86_jump_code (code, exc_throw_start [i]);
5312 patch_info->type = MONO_PATCH_INFO_NONE;
5313 }
5314 else {
5315 guint32 size;
5316
5317 /* Compute size of code following the push <OFFSET> */
5318 size = 5 + 5;
5319
5320 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5321
5322 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5323 /* Use the shorter form */
5324 buf = buf2 = code;
5325 x86_push_imm (code, 0);
5326 }
5327 else {
5328 buf = code;
5329 x86_push_imm (code, 0xf0f0f0f0);
5330 buf2 = code;
5331 }
5332
5333 if (nthrows < 16) {
5334 exc_classes [nthrows] = exc_class;
5335 exc_throw_start [nthrows] = code;
5336 }
5337
5338 x86_push_imm (code, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
5339 patch_info->data.name = "mono_arch_throw_corlib_exception";
5340 patch_info->type = MONO_PATCH_INFO_JIT_ICALL;
5341 patch_info->ip.i = code - cfg->native_code;
5342 x86_call_code (code, 0);
5343 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5344 while (buf < buf2)
5345 x86_nop (buf);
5346
5347 if (nthrows < 16) {
5348 exc_throw_end [nthrows] = code;
5349 nthrows ++;
5350 }
5351 }
5352 break;
5353 }
5354 default:
5355 /* do nothing */
5356 break;
5357 }
5358 set_code_cursor (cfg, code);
5359 }
5360 set_code_cursor (cfg, code);
5361 }
5362
5363 MONO_NEVER_INLINE
5364 void
5365 mono_arch_flush_icache (guint8 *code, gint size)
5366 {
5367 /* call/ret required (or likely other control transfer) */
5368 }
5369
5370 void
5371 mono_arch_flush_register_windows (void)
5372 {
5373 }
5374
5375 gboolean
5376 mono_arch_is_inst_imm (int opcode, int imm_opcode, gint64 imm)
5377 {
5378 return TRUE;
5379 }
5380
5381 void
5382 mono_arch_finish_init (void)
5383 {
5384 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5385 if (!mono_no_tls) {
5386 #ifndef TARGET_WIN32
5387 #if MONO_XEN_OPT
5388 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5389 #endif
5390 #endif
5391 } else {
5392 g_free (mono_no_tls);
5393 }
5394 }
5395
5396 void
5397 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5398 {
5399 }
5400
5401 // Linear handler, the bsearch head compare is shorter
5402 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5403 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5404 // x86_patch(ins,target)
5405 //[1 + 5] x86_jump_mem(inst,mem)
5406
5407 #define CMP_SIZE 6
5408 #define BR_SMALL_SIZE 2
5409 #define BR_LARGE_SIZE 5
5410 #define JUMP_IMM_SIZE 6
5411 #define ENABLE_WRONG_METHOD_CHECK 0
5412 #define DEBUG_IMT 0
5413
5414 static int
5415 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5416 {
5417 int i, distance = 0;
5418 for (i = start; i < target; ++i)
5419 distance += imt_entries [i]->chunk_size;
5420 return distance;
5421 }
5422
5423 /*
5424 * LOCKING: called with the domain lock held
5425 */
5426 gpointer
5427 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5428 gpointer fail_tramp)
5429 {
5430 int i;
5431 int size = 0;
5432 guint8 *code, *start;
5433 GSList *unwind_ops;
5434
5435 for (i = 0; i < count; ++i) {
5436 MonoIMTCheckItem *item = imt_entries [i];
5437 if (item->is_equals) {
5438 if (item->check_target_idx) {
5439 if (!item->compare_done)
5440 item->chunk_size += CMP_SIZE;
5441 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5442 } else {
5443 if (fail_tramp) {
5444 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5445 } else {
5446 item->chunk_size += JUMP_IMM_SIZE;
5447 #if ENABLE_WRONG_METHOD_CHECK
5448 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5449 #endif
5450 }
5451 }
5452 } else {
5453 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5454 imt_entries [item->check_target_idx]->compare_done = TRUE;
5455 }
5456 size += item->chunk_size;
5457 }
5458 if (fail_tramp)
5459 code = (guint8*)mono_method_alloc_generic_virtual_trampoline (domain, size);
5460 else
5461 code = mono_domain_code_reserve (domain, size);
5462 start = code;
5463
5464 unwind_ops = mono_arch_get_cie_program ();
5465
5466 for (i = 0; i < count; ++i) {
5467 MonoIMTCheckItem *item = imt_entries [i];
5468 item->code_target = code;
5469 if (item->is_equals) {
5470 if (item->check_target_idx) {
5471 if (!item->compare_done)
5472 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5473 item->jmp_code = code;
5474 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5475 if (item->has_target_code)
5476 x86_jump_code (code, item->value.target_code);
5477 else
5478 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5479 } else {
5480 if (fail_tramp) {
5481 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5482 item->jmp_code = code;
5483 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5484 if (item->has_target_code)
5485 x86_jump_code (code, item->value.target_code);
5486 else
5487 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5488 x86_patch (item->jmp_code, code);
5489 x86_jump_code (code, fail_tramp);
5490 item->jmp_code = NULL;
5491 } else {
5492 /* enable the commented code to assert on wrong method */
5493 #if ENABLE_WRONG_METHOD_CHECK
5494 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5495 item->jmp_code = code;
5496 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5497 #endif
5498 if (item->has_target_code)
5499 x86_jump_code (code, item->value.target_code);
5500 else
5501 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5502 #if ENABLE_WRONG_METHOD_CHECK
5503 x86_patch (item->jmp_code, code);
5504 x86_breakpoint (code);
5505 item->jmp_code = NULL;
5506 #endif
5507 }
5508 }
5509 } else {
5510 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5511 item->jmp_code = code;
5512 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5513 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5514 else
5515 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5516 }
5517 }
5518 /* patch the branches to get to the target items */
5519 for (i = 0; i < count; ++i) {
5520 MonoIMTCheckItem *item = imt_entries [i];
5521 if (item->jmp_code) {
5522 if (item->check_target_idx) {
5523 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5524 }
5525 }
5526 }
5527
5528 if (!fail_tramp)
5529 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
5530 g_assert (code - start <= size);
5531
5532 #if DEBUG_IMT
5533 {
5534 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5535 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5536 g_free (buff);
5537 }
5538 #endif
5539 if (mono_jit_map_is_enabled ()) {
5540 char *buff;
5541 if (vtable)
5542 buff = g_strdup_printf ("imt_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5543 else
5544 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5545 mono_emit_jit_tramp (start, code - start, buff);
5546 g_free (buff);
5547 }
5548
5549 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5550
5551 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5552
5553 return start;
5554 }
5555
5556 MonoMethod*
5557 mono_arch_find_imt_method (host_mgreg_t *regs, guint8 *code)
5558 {
5559 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5560 }
5561
5562 MonoVTable*
5563 mono_arch_find_static_call_vtable (host_mgreg_t *regs, guint8 *code)
5564 {
5565 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5566 }
5567
5568 GSList*
5569 mono_arch_get_cie_program (void)
5570 {
5571 GSList *l = NULL;
5572
5573 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5574 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5575
5576 return l;
5577 }
5578
5579 MonoInst*
5580 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5581 {
5582 MonoInst *ins = NULL;
5583 int opcode = 0;
5584
5585 if (cmethod->klass == mono_class_try_get_math_class ()) {
5586 if (strcmp (cmethod->name, "Sin") == 0) {
5587 opcode = OP_SIN;
5588 } else if (strcmp (cmethod->name, "Cos") == 0) {
5589 opcode = OP_COS;
5590 } else if (strcmp (cmethod->name, "Tan") == 0) {
5591 opcode = OP_TAN;
5592 } else if (strcmp (cmethod->name, "Atan") == 0) {
5593 opcode = OP_ATAN;
5594 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5595 opcode = OP_SQRT;
5596 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5597 opcode = OP_ABS;
5598 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5599 opcode = OP_ROUND;
5600 }
5601
5602 if (opcode && fsig->param_count == 1) {
5603 MONO_INST_NEW (cfg, ins, opcode);
5604 ins->type = STACK_R8;
5605 ins->dreg = mono_alloc_freg (cfg);
5606 ins->sreg1 = args [0]->dreg;
5607 MONO_ADD_INS (cfg->cbb, ins);
5608 }
5609
5610 if (cfg->opt & MONO_OPT_CMOV) {
5611 opcode = 0;
5612
5613 if (strcmp (cmethod->name, "Min") == 0) {
5614 if (fsig->params [0]->type == MONO_TYPE_I4)
5615 opcode = OP_IMIN;
5616 } else if (strcmp (cmethod->name, "Max") == 0) {
5617 if (fsig->params [0]->type == MONO_TYPE_I4)
5618 opcode = OP_IMAX;
5619 }
5620
5621 if (opcode && fsig->param_count == 2) {
5622 MONO_INST_NEW (cfg, ins, opcode);
5623 ins->type = STACK_I4;
5624 ins->dreg = mono_alloc_ireg (cfg);
5625 ins->sreg1 = args [0]->dreg;
5626 ins->sreg2 = args [1]->dreg;
5627 MONO_ADD_INS (cfg->cbb, ins);
5628 }
5629 }
5630
5631 #if 0
5632 /* OP_FREM is not IEEE compatible */
5633 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5634 MONO_INST_NEW (cfg, ins, OP_FREM);
5635 ins->inst_i0 = args [0];
5636 ins->inst_i1 = args [1];
5637 }
5638 #endif
5639 }
5640
5641 return ins;
5642 }
5643
5644 guint32
5645 mono_arch_get_patch_offset (guint8 *code)
5646 {
5647 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5648 return 2;
5649 else if (code [0] == 0xba)
5650 return 1;
5651 else if (code [0] == 0x68)
5652 /* push IMM */
5653 return 1;
5654 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5655 /* push <OFFSET>(<REG>) */
5656 return 2;
5657 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5658 /* call *<OFFSET>(<REG>) */
5659 return 2;
5660 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5661 /* fldl <ADDR> */
5662 return 2;
5663 else if ((code [0] == 0x58) && (code [1] == 0x05))
5664 /* pop %eax; add <OFFSET>, %eax */
5665 return 2;
5666 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5667 /* pop <REG>; add <OFFSET>, <REG> */
5668 return 3;
5669 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5670 /* mov <REG>, imm */
5671 return 1;
5672 else if (code [0] == 0xE9)
5673 /* jmp eip+32b */
5674 return 1;
5675 g_assert_not_reached ();
5676 return -1;
5677 }
5678
5679 /**
5680 * \return TRUE if no sw breakpoint was present.
5681 *
5682 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5683 * breakpoints in the original code, they are removed in the copy.
5684 */
5685 gboolean
5686 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5687 {
5688 /*
5689 * If method_start is non-NULL we need to perform bound checks, since we access memory
5690 * at code - offset we could go before the start of the method and end up in a different
5691 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5692 * instead.
5693 */
5694 if (!method_start || code - offset >= method_start) {
5695 memcpy (buf, code - offset, size);
5696 } else {
5697 int diff = code - method_start;
5698 memset (buf, 0, size);
5699 memcpy (buf + offset - diff, method_start, diff + size - offset);
5700 }
5701 return TRUE;
5702 }
5703
5704 /*
5705 * mono_x86_get_this_arg_offset:
5706 *
5707 * Return the offset of the stack location where this is passed during a virtual
5708 * call.
5709 */
5710 guint32
5711 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5712 {
5713 return 0;
5714 }
5715
5716 gpointer
5717 mono_arch_get_this_arg_from_call (host_mgreg_t *regs, guint8 *code)
5718 {
5719 host_mgreg_t esp = regs [X86_ESP];
5720 gpointer res;
5721 int offset;
5722
5723 offset = 0;
5724
5725 /*
5726 * The stack looks like:
5727 * <other args>
5728 * <this=delegate>
5729 */
5730 res = ((MonoObject**)esp) [0];
5731 return res;
5732 }
5733
5734 #define MAX_ARCH_DELEGATE_PARAMS 10
5735
5736 static gpointer
5737 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5738 {
5739 guint8 *code, *start;
5740 int code_reserve = 64;
5741 GSList *unwind_ops;
5742
5743 unwind_ops = mono_arch_get_cie_program ();
5744
5745 /*
5746 * The stack contains:
5747 * <delegate>
5748 * <return addr>
5749 */
5750
5751 if (has_target) {
5752 start = code = mono_global_codeman_reserve (code_reserve);
5753
5754 /* Replace the this argument with the target */
5755 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5756 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5757 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5758 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5759
5760 g_assert ((code - start) < code_reserve);
5761 } else {
5762 int i = 0;
5763 /* 8 for mov_reg and jump, plus 8 for each parameter */
5764 code_reserve = 8 + (param_count * 8);
5765 /*
5766 * The stack contains:
5767 * <args in reverse order>
5768 * <delegate>
5769 * <return addr>
5770 *
5771 * and we need:
5772 * <args in reverse order>
5773 * <return addr>
5774 *
5775 * without unbalancing the stack.
5776 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5777 * and leaving original spot of first arg as placeholder in stack so
5778 * when callee pops stack everything works.
5779 */
5780
5781 start = code = mono_global_codeman_reserve (code_reserve);
5782
5783 /* store delegate for access to method_ptr */
5784 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5785
5786 /* move args up */
5787 for (i = 0; i < param_count; ++i) {
5788 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5789 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5790 }
5791
5792 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5793
5794 g_assert ((code - start) < code_reserve);
5795 }
5796
5797 if (has_target) {
5798 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5799 } else {
5800 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5801 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5802 g_free (name);
5803 }
5804
5805 if (mono_jit_map_is_enabled ()) {
5806 char *buff;
5807 if (has_target)
5808 buff = (char*)"delegate_invoke_has_target";
5809 else
5810 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5811 mono_emit_jit_tramp (start, code - start, buff);
5812 if (!has_target)
5813 g_free (buff);
5814 }
5815 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5816
5817 return start;
5818 }
5819
5820 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5821
5822 static gpointer
5823 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5824 {
5825 guint8 *code, *start;
5826 int size = 24;
5827 char *tramp_name;
5828 GSList *unwind_ops;
5829
5830 if (offset / (int)sizeof (target_mgreg_t) > MAX_VIRTUAL_DELEGATE_OFFSET)
5831 return NULL;
5832
5833 /*
5834 * The stack contains:
5835 * <delegate>
5836 * <return addr>
5837 */
5838 start = code = mono_global_codeman_reserve (size);
5839
5840 unwind_ops = mono_arch_get_cie_program ();
5841
5842 /* Replace the this argument with the target */
5843 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5844 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5845 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5846
5847 if (load_imt_reg) {
5848 /* Load the IMT reg */
5849 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5850 }
5851
5852 /* Load the vtable */
5853 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5854 x86_jump_membase (code, X86_EAX, offset);
5855 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5856
5857 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5858 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5859 g_free (tramp_name);
5860
5861
5862 return start;
5863 }
5864
5865 GSList*
5866 mono_arch_get_delegate_invoke_impls (void)
5867 {
5868 GSList *res = NULL;
5869 MonoTrampInfo *info;
5870 int i;
5871
5872 get_delegate_invoke_impl (&info, TRUE, 0);
5873 res = g_slist_prepend (res, info);
5874
5875 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5876 get_delegate_invoke_impl (&info, FALSE, i);
5877 res = g_slist_prepend (res, info);
5878 }
5879
5880 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5881 get_delegate_virtual_invoke_impl (&info, TRUE, - i * TARGET_SIZEOF_VOID_P);
5882 res = g_slist_prepend (res, info);
5883
5884 get_delegate_virtual_invoke_impl (&info, FALSE, i * TARGET_SIZEOF_VOID_P);
5885 res = g_slist_prepend (res, info);
5886 }
5887
5888 return res;
5889 }
5890
5891 gpointer
5892 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5893 {
5894 guint8 *code, *start;
5895
5896 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5897 return NULL;
5898
5899 /* FIXME: Support more cases */
5900 if (MONO_TYPE_ISSTRUCT (sig->ret))
5901 return NULL;
5902
5903 /*
5904 * The stack contains:
5905 * <delegate>
5906 * <return addr>
5907 */
5908
5909 if (has_target) {
5910 static guint8* cached = NULL;
5911 if (cached)
5912 return cached;
5913
5914 if (mono_ee_features.use_aot_trampolines) {
5915 start = (guint8*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
5916 } else {
5917 MonoTrampInfo *info;
5918 start = (guint8*)get_delegate_invoke_impl (&info, TRUE, 0);
5919 mono_tramp_info_register (info, NULL);
5920 }
5921
5922 mono_memory_barrier ();
5923
5924 cached = start;
5925 } else {
5926 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5927 int i = 0;
5928
5929 for (i = 0; i < sig->param_count; ++i)
5930 if (!mono_is_regsize_var (sig->params [i]))
5931 return NULL;
5932
5933 code = cache [sig->param_count];
5934 if (code)
5935 return code;
5936
5937 if (mono_ee_features.use_aot_trampolines) {
5938 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5939 start = (guint8*)mono_aot_get_trampoline (name);
5940 g_free (name);
5941 } else {
5942 MonoTrampInfo *info;
5943 start = (guint8*)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
5944 mono_tramp_info_register (info, NULL);
5945 }
5946
5947 mono_memory_barrier ();
5948
5949 cache [sig->param_count] = start;
5950 }
5951
5952 return start;
5953 }
5954
5955 gpointer
5956 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
5957 {
5958 MonoTrampInfo *info;
5959 gpointer code;
5960
5961 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
5962 if (code)
5963 mono_tramp_info_register (info, NULL);
5964 return code;
5965 }
5966
5967 host_mgreg_t
5968 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5969 {
5970 switch (reg) {
5971 case X86_EAX: return ctx->eax;
5972 case X86_EBX: return ctx->ebx;
5973 case X86_ECX: return ctx->ecx;
5974 case X86_EDX: return ctx->edx;
5975 case X86_ESP: return ctx->esp;
5976 case X86_EBP: return ctx->ebp;
5977 case X86_ESI: return ctx->esi;
5978 case X86_EDI: return ctx->edi;
5979 default:
5980 g_assert_not_reached ();
5981 return 0;
5982 }
5983 }
5984
5985 void
5986 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, host_mgreg_t val)
5987 {
5988 switch (reg) {
5989 case X86_EAX:
5990 ctx->eax = val;
5991 break;
5992 case X86_EBX:
5993 ctx->ebx = val;
5994 break;
5995 case X86_ECX:
5996 ctx->ecx = val;
5997 break;
5998 case X86_EDX:
5999 ctx->edx = val;
6000 break;
6001 case X86_ESP:
6002 ctx->esp = val;
6003 break;
6004 case X86_EBP:
6005 ctx->ebp = val;
6006 break;
6007 case X86_ESI:
6008 ctx->esi = val;
6009 break;
6010 case X86_EDI:
6011 ctx->edi = val;
6012 break;
6013 default:
6014 g_assert_not_reached ();
6015 }
6016 }
6017
6018 #ifdef MONO_ARCH_SIMD_INTRINSICS
6019
6020 static MonoInst*
6021 get_float_to_x_spill_area (MonoCompile *cfg)
6022 {
6023 if (!cfg->fconv_to_r8_x_var) {
6024 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
6025 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6026 }
6027 return cfg->fconv_to_r8_x_var;
6028 }
6029
6030 /*
6031 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6032 */
6033 void
6034 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6035 {
6036 MonoInst *fconv;
6037 int dreg, src_opcode;
6038
6039 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6040 return;
6041
6042 switch (src_opcode = ins->opcode) {
6043 case OP_FCONV_TO_I1:
6044 case OP_FCONV_TO_U1:
6045 case OP_FCONV_TO_I2:
6046 case OP_FCONV_TO_U2:
6047 case OP_FCONV_TO_I4:
6048 case OP_FCONV_TO_I:
6049 break;
6050 default:
6051 return;
6052 }
6053
6054 /* dreg is the IREG and sreg1 is the FREG */
6055 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6056 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6057 fconv->sreg1 = ins->sreg1;
6058 fconv->dreg = mono_alloc_ireg (cfg);
6059 fconv->type = STACK_VTYPE;
6060 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6061
6062 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6063
6064 dreg = ins->dreg;
6065 NULLIFY_INS (ins);
6066 ins->opcode = OP_XCONV_R8_TO_I4;
6067
6068 ins->klass = mono_defaults.int32_class;
6069 ins->sreg1 = fconv->dreg;
6070 ins->dreg = dreg;
6071 ins->type = STACK_I4;
6072 ins->backend.source_opcode = src_opcode;
6073 }
6074
6075 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6076
6077 void
6078 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6079 {
6080 MonoInst *ins;
6081 int vreg;
6082
6083 if (long_ins->opcode == OP_LNEG) {
6084 ins = long_ins;
6085 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6086 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6087 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6088 NULLIFY_INS (ins);
6089 return;
6090 }
6091
6092 #ifdef MONO_ARCH_SIMD_INTRINSICS
6093
6094 if (!(cfg->opt & MONO_OPT_SIMD))
6095 return;
6096
6097 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6098 switch (long_ins->opcode) {
6099 case OP_EXTRACT_I8:
6100 vreg = long_ins->sreg1;
6101
6102 if (long_ins->inst_c0) {
6103 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6104 ins->klass = long_ins->klass;
6105 ins->sreg1 = long_ins->sreg1;
6106 ins->inst_c0 = 2;
6107 ins->type = STACK_VTYPE;
6108 ins->dreg = vreg = alloc_ireg (cfg);
6109 MONO_ADD_INS (cfg->cbb, ins);
6110 }
6111
6112 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6113 ins->klass = mono_defaults.int32_class;
6114 ins->sreg1 = vreg;
6115 ins->type = STACK_I4;
6116 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6117 MONO_ADD_INS (cfg->cbb, ins);
6118
6119 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6120 ins->klass = long_ins->klass;
6121 ins->sreg1 = long_ins->sreg1;
6122 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6123 ins->type = STACK_VTYPE;
6124 ins->dreg = vreg = alloc_ireg (cfg);
6125 MONO_ADD_INS (cfg->cbb, ins);
6126
6127 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6128 ins->klass = mono_defaults.int32_class;
6129 ins->sreg1 = vreg;
6130 ins->type = STACK_I4;
6131 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6132 MONO_ADD_INS (cfg->cbb, ins);
6133
6134 long_ins->opcode = OP_NOP;
6135 break;
6136 case OP_INSERTX_I8_SLOW:
6137 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6138 ins->dreg = long_ins->dreg;
6139 ins->sreg1 = long_ins->dreg;
6140 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6141 ins->inst_c0 = long_ins->inst_c0 * 2;
6142 MONO_ADD_INS (cfg->cbb, ins);
6143
6144 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6145 ins->dreg = long_ins->dreg;
6146 ins->sreg1 = long_ins->dreg;
6147 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6148 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6149 MONO_ADD_INS (cfg->cbb, ins);
6150
6151 long_ins->opcode = OP_NOP;
6152 break;
6153 case OP_EXPAND_I8:
6154 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6155 ins->dreg = long_ins->dreg;
6156 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6157 ins->klass = long_ins->klass;
6158 ins->type = STACK_VTYPE;
6159 MONO_ADD_INS (cfg->cbb, ins);
6160
6161 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6162 ins->dreg = long_ins->dreg;
6163 ins->sreg1 = long_ins->dreg;
6164 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6165 ins->inst_c0 = 1;
6166 ins->klass = long_ins->klass;
6167 ins->type = STACK_VTYPE;
6168 MONO_ADD_INS (cfg->cbb, ins);
6169
6170 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6171 ins->dreg = long_ins->dreg;
6172 ins->sreg1 = long_ins->dreg;;
6173 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6174 ins->klass = long_ins->klass;
6175 ins->type = STACK_VTYPE;
6176 MONO_ADD_INS (cfg->cbb, ins);
6177
6178 long_ins->opcode = OP_NOP;
6179 break;
6180 }
6181 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6182 }
6183
6184 /*
6185 * mono_aot_emit_load_got_addr:
6186 *
6187 * Emit code to load the got address.
6188 * On x86, the result is placed into EBX.
6189 */
6190 guint8*
6191 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6192 {
6193 x86_call_imm (code, 0);
6194 /*
6195 * The patch needs to point to the pop, since the GOT offset needs
6196 * to be added to that address.
6197 */
6198 if (cfg)
6199 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6200 else
6201 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6202 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6203 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6204
6205 set_code_cursor (cfg, code);
6206 return code;
6207 }
6208
6209 /*
6210 * mono_arch_emit_load_aotconst:
6211 *
6212 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6213 * TARGET from the mscorlib GOT in full-aot code.
6214 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6215 * EAX.
6216 */
6217 guint8*
6218 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6219 {
6220 /* Load the mscorlib got address */
6221 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (target_mgreg_t), 4);
6222 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6223 /* arch_emit_got_access () patches this */
6224 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6225
6226 return code;
6227 }
6228
6229 /* Can't put this into mini-x86.h */
6230 gpointer
6231 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6232
6233 GSList *
6234 mono_arch_get_trampolines (gboolean aot)
6235 {
6236 MonoTrampInfo *info;
6237 GSList *tramps = NULL;
6238
6239 mono_x86_get_signal_exception_trampoline (&info, aot);
6240
6241 tramps = g_slist_append (tramps, info);
6242
6243 return tramps;
6244 }
6245
6246 /* Soft Debug support */
6247 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6248
6249 /*
6250 * mono_arch_set_breakpoint:
6251 *
6252 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6253 * The location should contain code emitted by OP_SEQ_POINT.
6254 */
6255 void
6256 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6257 {
6258 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6259
6260 g_assert (code [0] == 0x90);
6261 x86_call_membase (code, X86_ECX, 0);
6262 }
6263
6264 /*
6265 * mono_arch_clear_breakpoint:
6266 *
6267 * Clear the breakpoint at IP.
6268 */
6269 void
6270 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6271 {
6272 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6273 int i;
6274
6275 for (i = 0; i < 2; ++i)
6276 x86_nop (code);
6277 }
6278
6279 /*
6280 * mono_arch_start_single_stepping:
6281 *
6282 * Start single stepping.
6283 */
6284 void
6285 mono_arch_start_single_stepping (void)
6286 {
6287 ss_trampoline = mini_get_single_step_trampoline ();
6288 }
6289
6290 /*
6291 * mono_arch_stop_single_stepping:
6292 *
6293 * Stop single stepping.
6294 */
6295 void
6296 mono_arch_stop_single_stepping (void)
6297 {
6298 ss_trampoline = NULL;
6299 }
6300
6301 /*
6302 * mono_arch_is_single_step_event:
6303 *
6304 * Return whenever the machine state in SIGCTX corresponds to a single
6305 * step event.
6306 */
6307 gboolean
6308 mono_arch_is_single_step_event (void *info, void *sigctx)
6309 {
6310 /* We use soft breakpoints */
6311 return FALSE;
6312 }
6313
6314 gboolean
6315 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6316 {
6317 /* We use soft breakpoints */
6318 return FALSE;
6319 }
6320
6321 #define BREAKPOINT_SIZE 2
6322
6323 /*
6324 * mono_arch_skip_breakpoint:
6325 *
6326 * See mini-amd64.c for docs.
6327 */
6328 void
6329 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6330 {
6331 g_assert_not_reached ();
6332 }
6333
6334 /*
6335 * mono_arch_skip_single_step:
6336 *
6337 * See mini-amd64.c for docs.
6338 */
6339 void
6340 mono_arch_skip_single_step (MonoContext *ctx)
6341 {
6342 g_assert_not_reached ();
6343 }
6344
6345 /*
6346 * mono_arch_get_seq_point_info:
6347 *
6348 * See mini-amd64.c for docs.
6349 */
6350 SeqPointInfo*
6351 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6352 {
6353 NOT_IMPLEMENTED;
6354 return NULL;
6355 }
6356
6357 #endif
6358
6359 gboolean
6360 mono_arch_opcode_supported (int opcode)
6361 {
6362 switch (opcode) {
6363 case OP_ATOMIC_ADD_I4:
6364 case OP_ATOMIC_EXCHANGE_I4:
6365 case OP_ATOMIC_CAS_I4:
6366 case OP_ATOMIC_LOAD_I1:
6367 case OP_ATOMIC_LOAD_I2:
6368 case OP_ATOMIC_LOAD_I4:
6369 case OP_ATOMIC_LOAD_U1:
6370 case OP_ATOMIC_LOAD_U2:
6371 case OP_ATOMIC_LOAD_U4:
6372 case OP_ATOMIC_LOAD_R4:
6373 case OP_ATOMIC_LOAD_R8:
6374 case OP_ATOMIC_STORE_I1:
6375 case OP_ATOMIC_STORE_I2:
6376 case OP_ATOMIC_STORE_I4:
6377 case OP_ATOMIC_STORE_U1:
6378 case OP_ATOMIC_STORE_U2:
6379 case OP_ATOMIC_STORE_U4:
6380 case OP_ATOMIC_STORE_R4:
6381 case OP_ATOMIC_STORE_R8:
6382 return TRUE;
6383 default:
6384 return FALSE;
6385 }
6386 }
6387
6388 CallInfo*
6389 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6390 {
6391 return get_call_info (mp, sig);
6392 }
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