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[jit] Pass the type token index instead of the full type token to the throw corlib...
[mono-project.git] / mono / mini / mini-arm.c
bloba7df6fc1c1b282990ba87401cf50423291a546f0
1 /*
2 * mini-arm.c: ARM backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 *
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 */
12 #include "mini.h"
13 #include <string.h>
14
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
22
23 #include "mini-arm.h"
24 #include "mini-arm-tls.h"
25 #include "cpu-arm.h"
26 #include "trace.h"
27 #include "ir-emit.h"
28 #include "debugger-agent.h"
29 #include "mini-gc.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
31
32 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
35 #define HAVE_FAST_TLS
36 #endif
37
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
41 #endif
42
43 /*
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
47 *
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
50 */
51
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
55 #define IS_VFP (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
60 #else
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
63 #define IS_VFP (TRUE)
64 #endif
65
66 #define THUNK_SIZE (3 * 4)
67
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
72
73 guint8 *
74 mono_arch_nacl_pad (guint8 *code, int pad)
75 {
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
78 return code;
79 }
80
81 guint8 *
82 mono_arch_nacl_skip_nops (guint8 *code)
83 {
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
86 return code;
87 }
88
89 #endif /* __native_client_codegen__ */
90
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
92
93 #if __APPLE__
94 void sys_icache_invalidate (void *start, size_t len);
95 #endif
96
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
101
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
109 /*
110 * Whenever to use the ARM EABI
111 */
112 static gboolean eabi_supported = FALSE;
113
114 /*
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
120 */
121 static gboolean iphone_abi = FALSE;
122
123 /*
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
126 */
127 static MonoArmFPU arm_fpu;
128
129 #if defined(ARM_FPU_VFP_HARD)
130 /*
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
136 */
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
139 #else
140 /*
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
143 */
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
146 #endif
147
148 static int i8_align;
149
150 static gpointer single_step_tramp, breakpoint_tramp;
151
152 /*
153 * The code generated for sequence points reads from this location, which is
154 * made read-only when single stepping is enabled.
155 */
156 static gpointer ss_trigger_page;
157
158 /* Enabled breakpoints read from this trigger page */
159 static gpointer bp_trigger_page;
160
161 /*
162 * TODO:
163 * floating point support: on ARM it is a mess, there are at least 3
164 * different setups, each of which binary incompat with the other.
165 * 1) FPA: old and ugly, but unfortunately what current distros use
166 * the double binary format has the two words swapped. 8 double registers.
167 * Implemented usually by kernel emulation.
168 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
169 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
170 * 3) VFP: the new and actually sensible and useful FP support. Implemented
171 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
172 *
173 * We do not care about FPA. We will support soft float and VFP.
174 */
175 int mono_exc_esp_offset = 0;
176
177 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
178 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
179 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
180
181 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
182 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
183 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
184
185 //#define DEBUG_IMT 0
186
187 #ifndef DISABLE_JIT
188 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
189 #endif
190
191 const char*
192 mono_arch_regname (int reg)
193 {
194 static const char * rnames[] = {
195 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
196 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
197 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
198 "arm_pc"
199 };
200 if (reg >= 0 && reg < 16)
201 return rnames [reg];
202 return "unknown";
203 }
204
205 const char*
206 mono_arch_fregname (int reg)
207 {
208 static const char * rnames[] = {
209 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
210 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
211 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
212 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
213 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
214 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
215 "arm_f30", "arm_f31"
216 };
217 if (reg >= 0 && reg < 32)
218 return rnames [reg];
219 return "unknown";
220 }
221
222
223 #ifndef DISABLE_JIT
224 static guint8*
225 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
226 {
227 int imm8, rot_amount;
228 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
229 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
230 return code;
231 }
232 if (dreg == sreg) {
233 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
234 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
235 } else {
236 code = mono_arm_emit_load_imm (code, dreg, imm);
237 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
238 }
239 return code;
240 }
241
242 /* If dreg == sreg, this clobbers IP */
243 static guint8*
244 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
245 {
246 int imm8, rot_amount;
247 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
248 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
249 return code;
250 }
251 if (dreg == sreg) {
252 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
253 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
254 } else {
255 code = mono_arm_emit_load_imm (code, dreg, imm);
256 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
257 }
258 return code;
259 }
260
261 static guint8*
262 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
263 {
264 /* we can use r0-r3, since this is called only for incoming args on the stack */
265 if (size > sizeof (gpointer) * 4) {
266 guint8 *start_loop;
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
270 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
271 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
272 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
274 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
275 ARM_B_COND (code, ARMCOND_NE, 0);
276 arm_patch (code - 4, start_loop);
277 return code;
278 }
279 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
280 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
281 while (size >= 4) {
282 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
284 doffset += 4;
285 soffset += 4;
286 size -= 4;
287 }
288 } else if (size) {
289 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
290 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
291 doffset = soffset = 0;
292 while (size >= 4) {
293 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
294 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
295 doffset += 4;
296 soffset += 4;
297 size -= 4;
298 }
299 }
300 g_assert (size == 0);
301 return code;
302 }
303
304 static guint8*
305 emit_call_reg (guint8 *code, int reg)
306 {
307 if (v5_supported) {
308 ARM_BLX_REG (code, reg);
309 } else {
310 #ifdef USE_JUMP_TABLES
311 g_assert_not_reached ();
312 #endif
313 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
314 if (thumb_supported)
315 ARM_BX (code, reg);
316 else
317 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
318 }
319 return code;
320 }
321
322 static guint8*
323 emit_call_seq (MonoCompile *cfg, guint8 *code)
324 {
325 #ifdef USE_JUMP_TABLES
326 code = mono_arm_patchable_bl (code, ARMCOND_AL);
327 #else
328 if (cfg->method->dynamic) {
329 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
330 ARM_B (code, 0);
331 *(gpointer*)code = NULL;
332 code += 4;
333 code = emit_call_reg (code, ARMREG_IP);
334 } else {
335 ARM_BL (code, 0);
336 }
337 cfg->thunk_area += THUNK_SIZE;
338 #endif
339 return code;
340 }
341
342 guint8*
343 mono_arm_patchable_b (guint8 *code, int cond)
344 {
345 #ifdef USE_JUMP_TABLES
346 gpointer *jte;
347
348 jte = mono_jumptable_add_entry ();
349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
350 ARM_BX_COND (code, cond, ARMREG_IP);
351 #else
352 ARM_B_COND (code, cond, 0);
353 #endif
354 return code;
355 }
356
357 guint8*
358 mono_arm_patchable_bl (guint8 *code, int cond)
359 {
360 #ifdef USE_JUMP_TABLES
361 gpointer *jte;
362
363 jte = mono_jumptable_add_entry ();
364 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
365 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
366 #else
367 ARM_BL_COND (code, cond, 0);
368 #endif
369 return code;
370 }
371
372 #ifdef USE_JUMP_TABLES
373 guint8*
374 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
375 {
376 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
377 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
378 return code;
379 }
380
381 guint8*
382 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
383 {
384 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
385 ARM_LDR_IMM (code, reg, reg, 0);
386 return code;
387 }
388 #endif
389
390 static guint8*
391 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
392 {
393 #ifdef HAVE_FAST_TLS
394 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
396 "mono_get_tls_key");
397 code = emit_call_seq (cfg, code);
398 if (dreg != ARMREG_R0)
399 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
400 #else
401 g_assert_not_reached ();
402 #endif
403 return code;
404 }
405
406 static guint8*
407 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
408 {
409 #ifdef HAVE_FAST_TLS
410 if (tls_offset_reg != ARMREG_R0)
411 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
412 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
413 "mono_get_tls_key");
414 code = emit_call_seq (cfg, code);
415 if (dreg != ARMREG_R0)
416 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
417 #else
418 g_assert_not_reached ();
419 #endif
420 return code;
421 }
422
423 static guint8*
424 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
425 {
426 #ifdef HAVE_FAST_TLS
427 if (sreg != ARMREG_R1)
428 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
429 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
430 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
431 "mono_set_tls_key");
432 code = emit_call_seq (cfg, code);
433 #else
434 g_assert_not_reached ();
435 #endif
436 return code;
437 }
438
439 static guint8*
440 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
441 {
442 #ifdef HAVE_FAST_TLS
443 /* Get sreg in R1 and tls_offset_reg in R0 */
444 if (tls_offset_reg == ARMREG_R1) {
445 if (sreg == ARMREG_R0) {
446 /* swap sreg and tls_offset_reg */
447 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
448 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
450 } else {
451 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
452 if (sreg != ARMREG_R1)
453 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
454 }
455 } else {
456 if (sreg != ARMREG_R1)
457 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (tls_offset_reg != ARMREG_R0)
459 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
460 }
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
462 "mono_set_tls_key");
463 code = emit_call_seq (cfg, code);
464 #else
465 g_assert_not_reached ();
466 #endif
467 return code;
468 }
469
470 /*
471 * emit_save_lmf:
472 *
473 * Emit code to push an LMF structure on the LMF stack.
474 * On arm, this is intermixed with the initialization of other fields of the structure.
475 */
476 static guint8*
477 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
478 {
479 gboolean get_lmf_fast = FALSE;
480 int i;
481
482 if (mono_arm_have_tls_get ()) {
483 get_lmf_fast = TRUE;
484 if (cfg->compile_aot) {
485 /* OP_AOTCONST */
486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
487 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
488 ARM_B (code, 0);
489 *(gpointer*)code = NULL;
490 code += 4;
491 /* Load the value from the GOT */
492 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
493 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
494 } else {
495 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
496 g_assert (lmf_addr_tls_offset != -1);
497 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
498 }
499 }
500
501 if (!get_lmf_fast) {
502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
503 (gpointer)"mono_get_lmf_addr");
504 code = emit_call_seq (cfg, code);
505 }
506 /* we build the MonoLMF structure on the stack - see mini-arm.h */
507 /* lmf_offset is the offset from the previous stack pointer,
508 * alloc_size is the total stack space allocated, so the offset
509 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
510 * The pointer to the struct is put in r1 (new_lmf).
511 * ip is used as scratch
512 * The callee-saved registers are already in the MonoLMF structure
513 */
514 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
515 /* r0 is the result from mono_get_lmf_addr () */
516 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
517 /* new_lmf->previous_lmf = *lmf_addr */
518 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
519 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 /* *(lmf_addr) = r1 */
521 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* Skip method (only needed for trampoline LMF frames) */
523 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
524 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
525 /* save the current IP */
526 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
528
529 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
530 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
531
532 return code;
533 }
534
535 typedef struct {
536 gint32 vreg;
537 gint32 hreg;
538 } FloatArgData;
539
540 static guint8 *
541 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
542 {
543 GSList *list;
544
545 g_assert (!cfg->r4fp);
546
547 for (list = inst->float_args; list; list = list->next) {
548 FloatArgData *fad = list->data;
549 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
550 gboolean imm = arm_is_fpimm8 (var->inst_offset);
551
552 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
553 if (!imm)
554 *max_len += 20 + 4;
555
556 *max_len += 4;
557
558 if (*offset + *max_len > cfg->code_size) {
559 cfg->code_size += *max_len;
560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
561
562 code = cfg->native_code + *offset;
563 }
564
565 if (!imm) {
566 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
567 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
568 } else
569 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
570
571 *offset = code - cfg->native_code;
572 }
573
574 return code;
575 }
576
577 static guint8 *
578 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
579 {
580 MonoInst *inst;
581
582 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
583
584 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
585
586 if (IS_HARD_FLOAT) {
587 if (!arm_is_fpimm8 (inst->inst_offset)) {
588 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
589 ARM_FSTD (code, reg, ARMREG_LR, 0);
590 } else
591 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
592 }
593
594 return code;
595 }
596
597 static guint8 *
598 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
599 {
600 MonoInst *inst;
601
602 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
603
604 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
605
606 if (IS_HARD_FLOAT) {
607 if (!arm_is_fpimm8 (inst->inst_offset)) {
608 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
609 ARM_FLDD (code, reg, ARMREG_LR, 0);
610 } else
611 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
612 }
613
614 return code;
615 }
616
617 /*
618 * emit_restore_lmf:
619 *
620 * Emit code to pop an LMF structure from the LMF stack.
621 */
622 static guint8*
623 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
624 {
625 int basereg, offset;
626
627 if (lmf_offset < 32) {
628 basereg = cfg->frame_reg;
629 offset = lmf_offset;
630 } else {
631 basereg = ARMREG_R2;
632 offset = 0;
633 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
634 }
635
636 /* ip = previous_lmf */
637 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
638 /* lr = lmf_addr */
639 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
640 /* *(lmf_addr) = previous_lmf */
641 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
642
643 return code;
644 }
645
646 #endif /* #ifndef DISABLE_JIT */
647
648 /*
649 * mono_arm_have_tls_get:
650 *
651 * Returns whether we have tls access implemented on the current
652 * platform
653 */
654 gboolean
655 mono_arm_have_tls_get (void)
656 {
657 #ifdef HAVE_FAST_TLS
658 return TRUE;
659 #else
660 return FALSE;
661 #endif
662 }
663
664 /*
665 * mono_arch_get_argument_info:
666 * @csig: a method signature
667 * @param_count: the number of parameters to consider
668 * @arg_info: an array to store the result infos
669 *
670 * Gathers information on parameters such as size, alignment and
671 * padding. arg_info should be large enought to hold param_count + 1 entries.
672 *
673 * Returns the size of the activation frame.
674 */
675 int
676 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
677 {
678 int k, frame_size = 0;
679 guint32 size, align, pad;
680 int offset = 8;
681 MonoType *t;
682
683 t = mini_get_underlying_type (csig->ret);
684 if (MONO_TYPE_ISSTRUCT (t)) {
685 frame_size += sizeof (gpointer);
686 offset += 4;
687 }
688
689 arg_info [0].offset = offset;
690
691 if (csig->hasthis) {
692 frame_size += sizeof (gpointer);
693 offset += 4;
694 }
695
696 arg_info [0].size = frame_size;
697
698 for (k = 0; k < param_count; k++) {
699 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
700
701 /* ignore alignment for now */
702 align = 1;
703
704 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
705 arg_info [k].pad = pad;
706 frame_size += size;
707 arg_info [k + 1].pad = 0;
708 arg_info [k + 1].size = size;
709 offset += pad;
710 arg_info [k + 1].offset = offset;
711 offset += size;
712 }
713
714 align = MONO_ARCH_FRAME_ALIGNMENT;
715 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
716 arg_info [k].pad = pad;
717
718 return frame_size;
719 }
720
721 #define MAX_ARCH_DELEGATE_PARAMS 3
722
723 static gpointer
724 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
725 {
726 guint8 *code, *start;
727 GSList *unwind_ops = mono_arch_get_cie_program ();
728
729 if (has_target) {
730 start = code = mono_global_codeman_reserve (12);
731
732 /* Replace the this argument with the target */
733 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
734 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
735 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
736
737 g_assert ((code - start) <= 12);
738
739 mono_arch_flush_icache (start, 12);
740 } else {
741 int size, i;
742
743 size = 8 + param_count * 4;
744 start = code = mono_global_codeman_reserve (size);
745
746 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
747 /* slide down the arguments */
748 for (i = 0; i < param_count; ++i) {
749 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
750 }
751 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
752
753 g_assert ((code - start) <= size);
754
755 mono_arch_flush_icache (start, size);
756 }
757
758 if (has_target) {
759 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
760 } else {
761 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
762 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
763 g_free (name);
764 }
765
766 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
767
768 return start;
769 }
770
771 /*
772 * mono_arch_get_delegate_invoke_impls:
773 *
774 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
775 * trampolines.
776 */
777 GSList*
778 mono_arch_get_delegate_invoke_impls (void)
779 {
780 GSList *res = NULL;
781 MonoTrampInfo *info;
782 int i;
783
784 get_delegate_invoke_impl (&info, TRUE, 0);
785 res = g_slist_prepend (res, info);
786
787 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
788 get_delegate_invoke_impl (&info, FALSE, i);
789 res = g_slist_prepend (res, info);
790 }
791
792 return res;
793 }
794
795 gpointer
796 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
797 {
798 guint8 *code, *start;
799 MonoType *sig_ret;
800
801 /* FIXME: Support more cases */
802 sig_ret = mini_get_underlying_type (sig->ret);
803 if (MONO_TYPE_ISSTRUCT (sig_ret))
804 return NULL;
805
806 if (has_target) {
807 static guint8* cached = NULL;
808 mono_mini_arch_lock ();
809 if (cached) {
810 mono_mini_arch_unlock ();
811 return cached;
812 }
813
814 if (mono_aot_only) {
815 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
816 } else {
817 MonoTrampInfo *info;
818 start = get_delegate_invoke_impl (&info, TRUE, 0);
819 mono_tramp_info_register (info, NULL);
820 }
821 cached = start;
822 mono_mini_arch_unlock ();
823 return cached;
824 } else {
825 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
826 int i;
827
828 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
829 return NULL;
830 for (i = 0; i < sig->param_count; ++i)
831 if (!mono_is_regsize_var (sig->params [i]))
832 return NULL;
833
834 mono_mini_arch_lock ();
835 code = cache [sig->param_count];
836 if (code) {
837 mono_mini_arch_unlock ();
838 return code;
839 }
840
841 if (mono_aot_only) {
842 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
843 start = mono_aot_get_trampoline (name);
844 g_free (name);
845 } else {
846 MonoTrampInfo *info;
847 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
848 mono_tramp_info_register (info, NULL);
849 }
850 cache [sig->param_count] = start;
851 mono_mini_arch_unlock ();
852 return start;
853 }
854
855 return NULL;
856 }
857
858 gpointer
859 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
860 {
861 return NULL;
862 }
863
864 gpointer
865 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
866 {
867 return (gpointer)regs [ARMREG_R0];
868 }
869
870 /*
871 * Initialize the cpu to execute managed code.
872 */
873 void
874 mono_arch_cpu_init (void)
875 {
876 i8_align = MONO_ABI_ALIGNOF (gint64);
877 #ifdef MONO_CROSS_COMPILE
878 /* Need to set the alignment of i8 since it can different on the target */
879 #ifdef TARGET_ANDROID
880 /* linux gnueabi */
881 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
882 #endif
883 #endif
884 }
885
886 /*
887 * Initialize architecture specific code.
888 */
889 void
890 mono_arch_init (void)
891 {
892 const char *cpu_arch;
893
894 mono_os_mutex_init_recursive (&mini_arch_mutex);
895 if (mini_get_debug_options ()->soft_breakpoints) {
896 breakpoint_tramp = mini_get_breakpoint_trampoline ();
897 } else {
898 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
899 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
901 }
902
903 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
905 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
906 #if defined(ENABLE_GSHAREDVT)
907 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
908 #endif
909 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
910
911 #if defined(__ARM_EABI__)
912 eabi_supported = TRUE;
913 #endif
914
915 #if defined(ARM_FPU_VFP_HARD)
916 arm_fpu = MONO_ARM_FPU_VFP_HARD;
917 #else
918 arm_fpu = MONO_ARM_FPU_VFP;
919
920 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
921 /*
922 * If we're compiling with a soft float fallback and it
923 * turns out that no VFP unit is available, we need to
924 * switch to soft float. We don't do this for iOS, since
925 * iOS devices always have a VFP unit.
926 */
927 if (!mono_hwcap_arm_has_vfp)
928 arm_fpu = MONO_ARM_FPU_NONE;
929
930 /*
931 * This environment variable can be useful in testing
932 * environments to make sure the soft float fallback
933 * works. Most ARM devices have VFP units these days, so
934 * normally soft float code would not be exercised much.
935 */
936 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
937
938 if (soft && !strncmp (soft, "1", 1))
939 arm_fpu = MONO_ARM_FPU_NONE;
940 #endif
941 #endif
942
943 v5_supported = mono_hwcap_arm_is_v5;
944 v6_supported = mono_hwcap_arm_is_v6;
945 v7_supported = mono_hwcap_arm_is_v7;
946
947 #if defined(__APPLE__)
948 /* iOS is special-cased here because we don't yet
949 have a way to properly detect CPU features on it. */
950 thumb_supported = TRUE;
951 iphone_abi = TRUE;
952 #else
953 thumb_supported = mono_hwcap_arm_has_thumb;
954 thumb2_supported = mono_hwcap_arm_has_thumb2;
955 #endif
956
957 /* Format: armv(5|6|7[s])[-thumb[2]] */
958 cpu_arch = g_getenv ("MONO_CPU_ARCH");
959
960 /* Do this here so it overrides any detection. */
961 if (cpu_arch) {
962 if (strncmp (cpu_arch, "armv", 4) == 0) {
963 v5_supported = cpu_arch [4] >= '5';
964 v6_supported = cpu_arch [4] >= '6';
965 v7_supported = cpu_arch [4] >= '7';
966 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
967 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
968 }
969
970 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
971 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
972 }
973 }
974
975 /*
976 * Cleanup architecture specific code.
977 */
978 void
979 mono_arch_cleanup (void)
980 {
981 }
982
983 /*
984 * This function returns the optimizations supported on this cpu.
985 */
986 guint32
987 mono_arch_cpu_optimizations (guint32 *exclude_mask)
988 {
989 /* no arm-specific optimizations yet */
990 *exclude_mask = 0;
991 return 0;
992 }
993
994 /*
995 * This function test for all SIMD functions supported.
996 *
997 * Returns a bitmask corresponding to all supported versions.
998 *
999 */
1000 guint32
1001 mono_arch_cpu_enumerate_simd_versions (void)
1002 {
1003 /* SIMD is currently unimplemented */
1004 return 0;
1005 }
1006
1007
1008 #ifndef DISABLE_JIT
1009
1010 gboolean
1011 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1012 {
1013 if (v7s_supported || v7k_supported) {
1014 switch (opcode) {
1015 case OP_IDIV:
1016 case OP_IREM:
1017 case OP_IDIV_UN:
1018 case OP_IREM_UN:
1019 return FALSE;
1020 default:
1021 break;
1022 }
1023 }
1024 return TRUE;
1025 }
1026
1027 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1028 gboolean
1029 mono_arch_is_soft_float (void)
1030 {
1031 return arm_fpu == MONO_ARM_FPU_NONE;
1032 }
1033 #endif
1034
1035 gboolean
1036 mono_arm_is_hard_float (void)
1037 {
1038 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1039 }
1040
1041 static gboolean
1042 is_regsize_var (MonoType *t)
1043 {
1044 if (t->byref)
1045 return TRUE;
1046 t = mini_get_underlying_type (t);
1047 switch (t->type) {
1048 case MONO_TYPE_I4:
1049 case MONO_TYPE_U4:
1050 case MONO_TYPE_I:
1051 case MONO_TYPE_U:
1052 case MONO_TYPE_PTR:
1053 case MONO_TYPE_FNPTR:
1054 return TRUE;
1055 case MONO_TYPE_OBJECT:
1056 case MONO_TYPE_STRING:
1057 case MONO_TYPE_CLASS:
1058 case MONO_TYPE_SZARRAY:
1059 case MONO_TYPE_ARRAY:
1060 return TRUE;
1061 case MONO_TYPE_GENERICINST:
1062 if (!mono_type_generic_inst_is_valuetype (t))
1063 return TRUE;
1064 return FALSE;
1065 case MONO_TYPE_VALUETYPE:
1066 return FALSE;
1067 }
1068 return FALSE;
1069 }
1070
1071 GList *
1072 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1073 {
1074 GList *vars = NULL;
1075 int i;
1076
1077 for (i = 0; i < cfg->num_varinfo; i++) {
1078 MonoInst *ins = cfg->varinfo [i];
1079 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1080
1081 /* unused vars */
1082 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1083 continue;
1084
1085 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1086 continue;
1087
1088 /* we can only allocate 32 bit values */
1089 if (is_regsize_var (ins->inst_vtype)) {
1090 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1091 g_assert (i == vmv->idx);
1092 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1093 }
1094 }
1095
1096 return vars;
1097 }
1098
1099 GList *
1100 mono_arch_get_global_int_regs (MonoCompile *cfg)
1101 {
1102 GList *regs = NULL;
1103
1104 mono_arch_compute_omit_fp (cfg);
1105
1106 /*
1107 * FIXME: Interface calls might go through a static rgctx trampoline which
1108 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1109 * avoid using it.
1110 */
1111 if (cfg->flags & MONO_CFG_HAS_CALLS)
1112 cfg->uses_rgctx_reg = TRUE;
1113
1114 if (cfg->arch.omit_fp)
1115 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1119 if (iphone_abi)
1120 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1121 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1122 else
1123 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1124 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1125 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1126 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1127 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1129
1130 return regs;
1131 }
1132
1133 /*
1134 * mono_arch_regalloc_cost:
1135 *
1136 * Return the cost, in number of memory references, of the action of
1137 * allocating the variable VMV into a register during global register
1138 * allocation.
1139 */
1140 guint32
1141 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1142 {
1143 /* FIXME: */
1144 return 2;
1145 }
1146
1147 #endif /* #ifndef DISABLE_JIT */
1148
1149 void
1150 mono_arch_flush_icache (guint8 *code, gint size)
1151 {
1152 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1153 // For Native Client we don't have to flush i-cache here,
1154 // as it's being done by dyncode interface.
1155 #elif __APPLE__
1156 sys_icache_invalidate (code, size);
1157 #else
1158 __builtin___clear_cache (code, code + size);
1159 #endif
1160 }
1161
1162 typedef enum {
1163 RegTypeNone,
1164 /* Passed/returned in an ireg */
1165 RegTypeGeneral,
1166 /* Passed/returned in a pair of iregs */
1167 RegTypeIRegPair,
1168 /* Passed on the stack */
1169 RegTypeBase,
1170 /* First word in r3, second word on the stack */
1171 RegTypeBaseGen,
1172 /* FP value passed in either an ireg or a vfp reg */
1173 RegTypeFP,
1174 RegTypeStructByVal,
1175 RegTypeStructByAddr,
1176 /* gsharedvt argument passed by addr in greg */
1177 RegTypeGSharedVtInReg,
1178 /* gsharedvt argument passed by addr on stack */
1179 RegTypeGSharedVtOnStack,
1180 RegTypeHFA
1181 } ArgStorage;
1182
1183 typedef struct {
1184 gint32 offset;
1185 guint16 vtsize; /* in param area */
1186 /* RegTypeHFA */
1187 int esize;
1188 /* RegTypeHFA */
1189 int nregs;
1190 guint8 reg;
1191 ArgStorage storage;
1192 gint32 struct_size;
1193 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1194 } ArgInfo;
1195
1196 typedef struct {
1197 int nargs;
1198 guint32 stack_usage;
1199 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1200 int vret_arg_index;
1201 ArgInfo ret;
1202 ArgInfo sig_cookie;
1203 ArgInfo args [1];
1204 } CallInfo;
1205
1206 #define DEBUG(a)
1207
1208 static void inline
1209 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1210 {
1211 if (simple) {
1212 if (*gr > ARMREG_R3) {
1213 ainfo->size = 4;
1214 ainfo->offset = *stack_size;
1215 ainfo->reg = ARMREG_SP; /* in the caller */
1216 ainfo->storage = RegTypeBase;
1217 *stack_size += 4;
1218 } else {
1219 ainfo->storage = RegTypeGeneral;
1220 ainfo->reg = *gr;
1221 }
1222 } else {
1223 gboolean split;
1224
1225 if (eabi_supported)
1226 split = i8_align == 4;
1227 else
1228 split = TRUE;
1229
1230 ainfo->size = 8;
1231 if (*gr == ARMREG_R3 && split) {
1232 /* first word in r3 and the second on the stack */
1233 ainfo->offset = *stack_size;
1234 ainfo->reg = ARMREG_SP; /* in the caller */
1235 ainfo->storage = RegTypeBaseGen;
1236 *stack_size += 4;
1237 } else if (*gr >= ARMREG_R3) {
1238 if (eabi_supported) {
1239 /* darwin aligns longs to 4 byte only */
1240 if (i8_align == 8) {
1241 *stack_size += 7;
1242 *stack_size &= ~7;
1243 }
1244 }
1245 ainfo->offset = *stack_size;
1246 ainfo->reg = ARMREG_SP; /* in the caller */
1247 ainfo->storage = RegTypeBase;
1248 *stack_size += 8;
1249 } else {
1250 if (eabi_supported) {
1251 if (i8_align == 8 && ((*gr) & 1))
1252 (*gr) ++;
1253 }
1254 ainfo->storage = RegTypeIRegPair;
1255 ainfo->reg = *gr;
1256 }
1257 (*gr) ++;
1258 }
1259 (*gr) ++;
1260 }
1261
1262 static void inline
1263 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1264 {
1265 /*
1266 * If we're calling a function like this:
1267 *
1268 * void foo(float a, double b, float c)
1269 *
1270 * We pass a in s0 and b in d1. That leaves us
1271 * with s1 being unused. The armhf ABI recognizes
1272 * this and requires register assignment to then
1273 * use that for the next single-precision arg,
1274 * i.e. c in this example. So float_spare either
1275 * tells us which reg to use for the next single-
1276 * precision arg, or it's -1, meaning use *fpr.
1277 *
1278 * Note that even though most of the JIT speaks
1279 * double-precision, fpr represents single-
1280 * precision registers.
1281 *
1282 * See parts 5.5 and 6.1.2 of the AAPCS for how
1283 * this all works.
1284 */
1285
1286 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1287 ainfo->storage = RegTypeFP;
1288
1289 if (is_double) {
1290 /*
1291 * If we're passing a double-precision value
1292 * and *fpr is odd (e.g. it's s1, s3, ...)
1293 * we need to use the next even register. So
1294 * we mark the current *fpr as a spare that
1295 * can be used for the next single-precision
1296 * value.
1297 */
1298 if (*fpr % 2) {
1299 *float_spare = *fpr;
1300 (*fpr)++;
1301 }
1302
1303 /*
1304 * At this point, we have an even register
1305 * so we assign that and move along.
1306 */
1307 ainfo->reg = *fpr;
1308 *fpr += 2;
1309 } else if (*float_spare >= 0) {
1310 /*
1311 * We're passing a single-precision value
1312 * and it looks like a spare single-
1313 * precision register is available. Let's
1314 * use it.
1315 */
1316
1317 ainfo->reg = *float_spare;
1318 *float_spare = -1;
1319 } else {
1320 /*
1321 * If we hit this branch, we're passing a
1322 * single-precision value and we can simply
1323 * use the next available register.
1324 */
1325
1326 ainfo->reg = *fpr;
1327 (*fpr)++;
1328 }
1329 } else {
1330 /*
1331 * We've exhausted available floating point
1332 * regs, so pass the rest on the stack.
1333 */
1334
1335 if (is_double) {
1336 *stack_size += 7;
1337 *stack_size &= ~7;
1338 }
1339
1340 ainfo->offset = *stack_size;
1341 ainfo->reg = ARMREG_SP;
1342 ainfo->storage = RegTypeBase;
1343
1344 *stack_size += 8;
1345 }
1346 }
1347
1348 static gboolean
1349 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1350 {
1351 MonoClass *klass;
1352 gpointer iter;
1353 MonoClassField *field;
1354 MonoType *ftype, *prev_ftype = NULL;
1355 int nfields = 0;
1356
1357 klass = mono_class_from_mono_type (t);
1358 iter = NULL;
1359 while ((field = mono_class_get_fields (klass, &iter))) {
1360 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1361 continue;
1362 ftype = mono_field_get_type (field);
1363 ftype = mini_get_underlying_type (ftype);
1364
1365 if (MONO_TYPE_ISSTRUCT (ftype)) {
1366 int nested_nfields, nested_esize;
1367
1368 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1369 return FALSE;
1370 if (nested_esize == 4)
1371 ftype = &mono_defaults.single_class->byval_arg;
1372 else
1373 ftype = &mono_defaults.double_class->byval_arg;
1374 if (prev_ftype && prev_ftype->type != ftype->type)
1375 return FALSE;
1376 prev_ftype = ftype;
1377 nfields += nested_nfields;
1378 } else {
1379 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1380 return FALSE;
1381 if (prev_ftype && prev_ftype->type != ftype->type)
1382 return FALSE;
1383 prev_ftype = ftype;
1384 nfields ++;
1385 }
1386 }
1387 if (nfields == 0 || nfields > 4)
1388 return FALSE;
1389 *out_nfields = nfields;
1390 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1391 return TRUE;
1392 }
1393
1394 static CallInfo*
1395 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1396 {
1397 guint i, gr, fpr, pstart;
1398 gint float_spare;
1399 int n = sig->hasthis + sig->param_count;
1400 int nfields, esize;
1401 guint32 align;
1402 MonoType *t;
1403 guint32 stack_size = 0;
1404 CallInfo *cinfo;
1405 gboolean is_pinvoke = sig->pinvoke;
1406 gboolean vtype_retaddr = FALSE;
1407
1408 if (mp)
1409 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1410 else
1411 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1412
1413 cinfo->nargs = n;
1414 gr = ARMREG_R0;
1415 fpr = ARM_VFP_F0;
1416 float_spare = -1;
1417
1418 t = mini_get_underlying_type (sig->ret);
1419 switch (t->type) {
1420 case MONO_TYPE_I1:
1421 case MONO_TYPE_U1:
1422 case MONO_TYPE_I2:
1423 case MONO_TYPE_U2:
1424 case MONO_TYPE_I4:
1425 case MONO_TYPE_U4:
1426 case MONO_TYPE_I:
1427 case MONO_TYPE_U:
1428 case MONO_TYPE_PTR:
1429 case MONO_TYPE_FNPTR:
1430 case MONO_TYPE_CLASS:
1431 case MONO_TYPE_OBJECT:
1432 case MONO_TYPE_SZARRAY:
1433 case MONO_TYPE_ARRAY:
1434 case MONO_TYPE_STRING:
1435 cinfo->ret.storage = RegTypeGeneral;
1436 cinfo->ret.reg = ARMREG_R0;
1437 break;
1438 case MONO_TYPE_U8:
1439 case MONO_TYPE_I8:
1440 cinfo->ret.storage = RegTypeIRegPair;
1441 cinfo->ret.reg = ARMREG_R0;
1442 break;
1443 case MONO_TYPE_R4:
1444 case MONO_TYPE_R8:
1445 cinfo->ret.storage = RegTypeFP;
1446
1447 if (t->type == MONO_TYPE_R4)
1448 cinfo->ret.size = 4;
1449 else
1450 cinfo->ret.size = 8;
1451
1452 if (IS_HARD_FLOAT) {
1453 cinfo->ret.reg = ARM_VFP_F0;
1454 } else {
1455 cinfo->ret.reg = ARMREG_R0;
1456 }
1457 break;
1458 case MONO_TYPE_GENERICINST:
1459 if (!mono_type_generic_inst_is_valuetype (t)) {
1460 cinfo->ret.storage = RegTypeGeneral;
1461 cinfo->ret.reg = ARMREG_R0;
1462 break;
1463 }
1464 if (mini_is_gsharedvt_variable_type (t)) {
1465 cinfo->ret.storage = RegTypeStructByAddr;
1466 break;
1467 }
1468 /* Fall through */
1469 case MONO_TYPE_VALUETYPE:
1470 case MONO_TYPE_TYPEDBYREF:
1471 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1472 cinfo->ret.storage = RegTypeHFA;
1473 cinfo->ret.reg = 0;
1474 cinfo->ret.nregs = nfields;
1475 cinfo->ret.esize = esize;
1476 } else {
1477 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1478 cinfo->ret.storage = RegTypeStructByVal;
1479 else
1480 cinfo->ret.storage = RegTypeStructByAddr;
1481 }
1482 break;
1483 case MONO_TYPE_VAR:
1484 case MONO_TYPE_MVAR:
1485 g_assert (mini_is_gsharedvt_type (t));
1486 cinfo->ret.storage = RegTypeStructByAddr;
1487 break;
1488 case MONO_TYPE_VOID:
1489 break;
1490 default:
1491 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1492 }
1493
1494 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1495
1496 pstart = 0;
1497 n = 0;
1498 /*
1499 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1500 * the first argument, allowing 'this' to be always passed in the first arg reg.
1501 * Also do this if the first argument is a reference type, since virtual calls
1502 * are sometimes made using calli without sig->hasthis set, like in the delegate
1503 * invoke wrappers.
1504 */
1505 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1506 if (sig->hasthis) {
1507 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1508 } else {
1509 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1510 pstart = 1;
1511 }
1512 n ++;
1513 cinfo->ret.reg = gr;
1514 gr ++;
1515 cinfo->vret_arg_index = 1;
1516 } else {
1517 /* this */
1518 if (sig->hasthis) {
1519 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1520 n ++;
1521 }
1522 if (vtype_retaddr) {
1523 cinfo->ret.reg = gr;
1524 gr ++;
1525 }
1526 }
1527
1528 DEBUG(g_print("params: %d\n", sig->param_count));
1529 for (i = pstart; i < sig->param_count; ++i) {
1530 ArgInfo *ainfo = &cinfo->args [n];
1531
1532 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1533 /* Prevent implicit arguments and sig_cookie from
1534 being passed in registers */
1535 gr = ARMREG_R3 + 1;
1536 fpr = ARM_VFP_F16;
1537 /* Emit the signature cookie just before the implicit arguments */
1538 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1539 }
1540 DEBUG(g_print("param %d: ", i));
1541 if (sig->params [i]->byref) {
1542 DEBUG(g_print("byref\n"));
1543 add_general (&gr, &stack_size, ainfo, TRUE);
1544 n++;
1545 continue;
1546 }
1547 t = mini_get_underlying_type (sig->params [i]);
1548 switch (t->type) {
1549 case MONO_TYPE_I1:
1550 case MONO_TYPE_U1:
1551 cinfo->args [n].size = 1;
1552 add_general (&gr, &stack_size, ainfo, TRUE);
1553 break;
1554 case MONO_TYPE_I2:
1555 case MONO_TYPE_U2:
1556 cinfo->args [n].size = 2;
1557 add_general (&gr, &stack_size, ainfo, TRUE);
1558 break;
1559 case MONO_TYPE_I4:
1560 case MONO_TYPE_U4:
1561 cinfo->args [n].size = 4;
1562 add_general (&gr, &stack_size, ainfo, TRUE);
1563 break;
1564 case MONO_TYPE_I:
1565 case MONO_TYPE_U:
1566 case MONO_TYPE_PTR:
1567 case MONO_TYPE_FNPTR:
1568 case MONO_TYPE_CLASS:
1569 case MONO_TYPE_OBJECT:
1570 case MONO_TYPE_STRING:
1571 case MONO_TYPE_SZARRAY:
1572 case MONO_TYPE_ARRAY:
1573 cinfo->args [n].size = sizeof (gpointer);
1574 add_general (&gr, &stack_size, ainfo, TRUE);
1575 break;
1576 case MONO_TYPE_GENERICINST:
1577 if (!mono_type_generic_inst_is_valuetype (t)) {
1578 cinfo->args [n].size = sizeof (gpointer);
1579 add_general (&gr, &stack_size, ainfo, TRUE);
1580 break;
1581 }
1582 if (mini_is_gsharedvt_variable_type (t)) {
1583 /* gsharedvt arguments are passed by ref */
1584 g_assert (mini_is_gsharedvt_type (t));
1585 add_general (&gr, &stack_size, ainfo, TRUE);
1586 switch (ainfo->storage) {
1587 case RegTypeGeneral:
1588 ainfo->storage = RegTypeGSharedVtInReg;
1589 break;
1590 case RegTypeBase:
1591 ainfo->storage = RegTypeGSharedVtOnStack;
1592 break;
1593 default:
1594 g_assert_not_reached ();
1595 }
1596 break;
1597 }
1598 /* Fall through */
1599 case MONO_TYPE_TYPEDBYREF:
1600 case MONO_TYPE_VALUETYPE: {
1601 gint size;
1602 int align_size;
1603 int nwords, nfields, esize;
1604 guint32 align;
1605
1606 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1607 if (fpr + nfields < ARM_VFP_F16) {
1608 ainfo->storage = RegTypeHFA;
1609 ainfo->reg = fpr;
1610 ainfo->nregs = nfields;
1611 ainfo->esize = esize;
1612 if (esize == 4)
1613 fpr += nfields;
1614 else
1615 fpr += nfields * 2;
1616 break;
1617 } else {
1618 fpr = ARM_VFP_F16;
1619 }
1620 }
1621
1622 if (t->type == MONO_TYPE_TYPEDBYREF) {
1623 size = sizeof (MonoTypedRef);
1624 align = sizeof (gpointer);
1625 } else {
1626 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1627 if (is_pinvoke)
1628 size = mono_class_native_size (klass, &align);
1629 else
1630 size = mini_type_stack_size_full (t, &align, FALSE);
1631 }
1632 DEBUG(g_print ("load %d bytes struct\n", size));
1633 align_size = size;
1634 nwords = 0;
1635 align_size += (sizeof (gpointer) - 1);
1636 align_size &= ~(sizeof (gpointer) - 1);
1637 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1638 ainfo->storage = RegTypeStructByVal;
1639 ainfo->struct_size = size;
1640 /* FIXME: align stack_size if needed */
1641 if (eabi_supported) {
1642 if (align >= 8 && (gr & 1))
1643 gr ++;
1644 }
1645 if (gr > ARMREG_R3) {
1646 ainfo->size = 0;
1647 ainfo->vtsize = nwords;
1648 } else {
1649 int rest = ARMREG_R3 - gr + 1;
1650 int n_in_regs = rest >= nwords? nwords: rest;
1651
1652 ainfo->size = n_in_regs;
1653 ainfo->vtsize = nwords - n_in_regs;
1654 ainfo->reg = gr;
1655 gr += n_in_regs;
1656 nwords -= n_in_regs;
1657 }
1658 if (sig->call_convention == MONO_CALL_VARARG)
1659 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1660 stack_size = ALIGN_TO (stack_size, align);
1661 ainfo->offset = stack_size;
1662 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1663 stack_size += nwords * sizeof (gpointer);
1664 break;
1665 }
1666 case MONO_TYPE_U8:
1667 case MONO_TYPE_I8:
1668 ainfo->size = 8;
1669 add_general (&gr, &stack_size, ainfo, FALSE);
1670 break;
1671 case MONO_TYPE_R4:
1672 ainfo->size = 4;
1673
1674 if (IS_HARD_FLOAT)
1675 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1676 else
1677 add_general (&gr, &stack_size, ainfo, TRUE);
1678 break;
1679 case MONO_TYPE_R8:
1680 ainfo->size = 8;
1681
1682 if (IS_HARD_FLOAT)
1683 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1684 else
1685 add_general (&gr, &stack_size, ainfo, FALSE);
1686 break;
1687 case MONO_TYPE_VAR:
1688 case MONO_TYPE_MVAR:
1689 /* gsharedvt arguments are passed by ref */
1690 g_assert (mini_is_gsharedvt_type (t));
1691 add_general (&gr, &stack_size, ainfo, TRUE);
1692 switch (ainfo->storage) {
1693 case RegTypeGeneral:
1694 ainfo->storage = RegTypeGSharedVtInReg;
1695 break;
1696 case RegTypeBase:
1697 ainfo->storage = RegTypeGSharedVtOnStack;
1698 break;
1699 default:
1700 g_assert_not_reached ();
1701 }
1702 break;
1703 default:
1704 g_error ("Can't handle 0x%x", sig->params [i]->type);
1705 }
1706 n ++;
1707 }
1708
1709 /* Handle the case where there are no implicit arguments */
1710 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1711 /* Prevent implicit arguments and sig_cookie from
1712 being passed in registers */
1713 gr = ARMREG_R3 + 1;
1714 fpr = ARM_VFP_F16;
1715 /* Emit the signature cookie just before the implicit arguments */
1716 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1717 }
1718
1719 /* align stack size to 8 */
1720 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1721 stack_size = (stack_size + 7) & ~7;
1722
1723 cinfo->stack_usage = stack_size;
1724 return cinfo;
1725 }
1726
1727
1728 gboolean
1729 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1730 {
1731 MonoType *callee_ret;
1732 CallInfo *c1, *c2;
1733 gboolean res;
1734
1735 c1 = get_call_info (NULL, caller_sig);
1736 c2 = get_call_info (NULL, callee_sig);
1737
1738 /*
1739 * Tail calls with more callee stack usage than the caller cannot be supported, since
1740 * the extra stack space would be left on the stack after the tail call.
1741 */
1742 res = c1->stack_usage >= c2->stack_usage;
1743 callee_ret = mini_get_underlying_type (callee_sig->ret);
1744 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1745 /* An address on the callee's stack is passed as the first argument */
1746 res = FALSE;
1747
1748 if (c2->stack_usage > 16 * 4)
1749 res = FALSE;
1750
1751 g_free (c1);
1752 g_free (c2);
1753
1754 return res;
1755 }
1756
1757 #ifndef DISABLE_JIT
1758
1759 static gboolean
1760 debug_omit_fp (void)
1761 {
1762 #if 0
1763 return mono_debug_count ();
1764 #else
1765 return TRUE;
1766 #endif
1767 }
1768
1769 /**
1770 * mono_arch_compute_omit_fp:
1771 *
1772 * Determine whenever the frame pointer can be eliminated.
1773 */
1774 static void
1775 mono_arch_compute_omit_fp (MonoCompile *cfg)
1776 {
1777 MonoMethodSignature *sig;
1778 MonoMethodHeader *header;
1779 int i, locals_size;
1780 CallInfo *cinfo;
1781
1782 if (cfg->arch.omit_fp_computed)
1783 return;
1784
1785 header = cfg->header;
1786
1787 sig = mono_method_signature (cfg->method);
1788
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = cfg->arch.cinfo;
1792
1793 /*
1794 * FIXME: Remove some of the restrictions.
1795 */
1796 cfg->arch.omit_fp = TRUE;
1797 cfg->arch.omit_fp_computed = TRUE;
1798
1799 if (cfg->disable_omit_fp)
1800 cfg->arch.omit_fp = FALSE;
1801 if (!debug_omit_fp ())
1802 cfg->arch.omit_fp = FALSE;
1803 /*
1804 if (cfg->method->save_lmf)
1805 cfg->arch.omit_fp = FALSE;
1806 */
1807 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1808 cfg->arch.omit_fp = FALSE;
1809 if (header->num_clauses)
1810 cfg->arch.omit_fp = FALSE;
1811 if (cfg->param_area)
1812 cfg->arch.omit_fp = FALSE;
1813 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1814 cfg->arch.omit_fp = FALSE;
1815 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1816 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1817 cfg->arch.omit_fp = FALSE;
1818 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1819 ArgInfo *ainfo = &cinfo->args [i];
1820
1821 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1822 /*
1823 * The stack offset can only be determined when the frame
1824 * size is known.
1825 */
1826 cfg->arch.omit_fp = FALSE;
1827 }
1828 }
1829
1830 locals_size = 0;
1831 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1832 MonoInst *ins = cfg->varinfo [i];
1833 int ialign;
1834
1835 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1836 }
1837 }
1838
1839 /*
1840 * Set var information according to the calling convention. arm version.
1841 * The locals var stuff should most likely be split in another method.
1842 */
1843 void
1844 mono_arch_allocate_vars (MonoCompile *cfg)
1845 {
1846 MonoMethodSignature *sig;
1847 MonoMethodHeader *header;
1848 MonoInst *ins;
1849 MonoType *sig_ret;
1850 int i, offset, size, align, curinst;
1851 CallInfo *cinfo;
1852 ArgInfo *ainfo;
1853 guint32 ualign;
1854
1855 sig = mono_method_signature (cfg->method);
1856
1857 if (!cfg->arch.cinfo)
1858 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1859 cinfo = cfg->arch.cinfo;
1860 sig_ret = mini_get_underlying_type (sig->ret);
1861
1862 mono_arch_compute_omit_fp (cfg);
1863
1864 if (cfg->arch.omit_fp)
1865 cfg->frame_reg = ARMREG_SP;
1866 else
1867 cfg->frame_reg = ARMREG_FP;
1868
1869 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1870
1871 /* allow room for the vararg method args: void* and long/double */
1872 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1873 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1874
1875 header = cfg->header;
1876
1877 /* See mono_arch_get_global_int_regs () */
1878 if (cfg->flags & MONO_CFG_HAS_CALLS)
1879 cfg->uses_rgctx_reg = TRUE;
1880
1881 if (cfg->frame_reg != ARMREG_SP)
1882 cfg->used_int_regs |= 1 << cfg->frame_reg;
1883
1884 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1885 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1886 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1887
1888 offset = 0;
1889 curinst = 0;
1890 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1891 if (sig_ret->type != MONO_TYPE_VOID) {
1892 cfg->ret->opcode = OP_REGVAR;
1893 cfg->ret->inst_c0 = ARMREG_R0;
1894 }
1895 }
1896 /* local vars are at a positive offset from the stack pointer */
1897 /*
1898 * also note that if the function uses alloca, we use FP
1899 * to point at the local variables.
1900 */
1901 offset = 0; /* linkage area */
1902 /* align the offset to 16 bytes: not sure this is needed here */
1903 //offset += 8 - 1;
1904 //offset &= ~(8 - 1);
1905
1906 /* add parameter area size for called functions */
1907 offset += cfg->param_area;
1908 offset += 8 - 1;
1909 offset &= ~(8 - 1);
1910 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1911 offset += 8;
1912
1913 /* allow room to save the return value */
1914 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1915 offset += 8;
1916
1917 switch (cinfo->ret.storage) {
1918 case RegTypeStructByVal:
1919 cfg->ret->opcode = OP_REGOFFSET;
1920 cfg->ret->inst_basereg = cfg->frame_reg;
1921 offset += sizeof (gpointer) - 1;
1922 offset &= ~(sizeof (gpointer) - 1);
1923 cfg->ret->inst_offset = - offset;
1924 offset += sizeof(gpointer);
1925 break;
1926 case RegTypeHFA:
1927 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1928 offset = ALIGN_TO (offset, 8);
1929 cfg->ret->opcode = OP_REGOFFSET;
1930 cfg->ret->inst_basereg = cfg->frame_reg;
1931 cfg->ret->inst_offset = offset;
1932 // FIXME:
1933 offset += 32;
1934 break;
1935 case RegTypeStructByAddr:
1936 ins = cfg->vret_addr;
1937 offset += sizeof(gpointer) - 1;
1938 offset &= ~(sizeof(gpointer) - 1);
1939 ins->inst_offset = offset;
1940 ins->opcode = OP_REGOFFSET;
1941 ins->inst_basereg = cfg->frame_reg;
1942 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943 g_print ("vret_addr =");
1944 mono_print_ins (cfg->vret_addr);
1945 }
1946 offset += sizeof(gpointer);
1947 break;
1948 default:
1949 break;
1950 }
1951
1952 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1953 if (cfg->arch.seq_point_info_var) {
1954 MonoInst *ins;
1955
1956 ins = cfg->arch.seq_point_info_var;
1957
1958 size = 4;
1959 align = 4;
1960 offset += align - 1;
1961 offset &= ~(align - 1);
1962 ins->opcode = OP_REGOFFSET;
1963 ins->inst_basereg = cfg->frame_reg;
1964 ins->inst_offset = offset;
1965 offset += size;
1966
1967 ins = cfg->arch.ss_trigger_page_var;
1968 size = 4;
1969 align = 4;
1970 offset += align - 1;
1971 offset &= ~(align - 1);
1972 ins->opcode = OP_REGOFFSET;
1973 ins->inst_basereg = cfg->frame_reg;
1974 ins->inst_offset = offset;
1975 offset += size;
1976 }
1977
1978 if (cfg->arch.seq_point_ss_method_var) {
1979 MonoInst *ins;
1980
1981 ins = cfg->arch.seq_point_ss_method_var;
1982 size = 4;
1983 align = 4;
1984 offset += align - 1;
1985 offset &= ~(align - 1);
1986 ins->opcode = OP_REGOFFSET;
1987 ins->inst_basereg = cfg->frame_reg;
1988 ins->inst_offset = offset;
1989 offset += size;
1990
1991 ins = cfg->arch.seq_point_bp_method_var;
1992 size = 4;
1993 align = 4;
1994 offset += align - 1;
1995 offset &= ~(align - 1);
1996 ins->opcode = OP_REGOFFSET;
1997 ins->inst_basereg = cfg->frame_reg;
1998 ins->inst_offset = offset;
1999 offset += size;
2000 }
2001
2002 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2003 /* Allocate a temporary used by the atomic ops */
2004 size = 4;
2005 align = 4;
2006
2007 /* Allocate a local slot to hold the sig cookie address */
2008 offset += align - 1;
2009 offset &= ~(align - 1);
2010 cfg->arch.atomic_tmp_offset = offset;
2011 offset += size;
2012 } else {
2013 cfg->arch.atomic_tmp_offset = -1;
2014 }
2015
2016 cfg->locals_min_stack_offset = offset;
2017
2018 curinst = cfg->locals_start;
2019 for (i = curinst; i < cfg->num_varinfo; ++i) {
2020 MonoType *t;
2021
2022 ins = cfg->varinfo [i];
2023 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2024 continue;
2025
2026 t = ins->inst_vtype;
2027 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2028 continue;
2029
2030 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2031 * pinvoke wrappers when they call functions returning structure */
2032 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2033 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2034 align = ualign;
2035 }
2036 else
2037 size = mono_type_size (t, &align);
2038
2039 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2040 * since it loads/stores misaligned words, which don't do the right thing.
2041 */
2042 if (align < 4 && size >= 4)
2043 align = 4;
2044 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2045 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2046 offset += align - 1;
2047 offset &= ~(align - 1);
2048 ins->opcode = OP_REGOFFSET;
2049 ins->inst_offset = offset;
2050 ins->inst_basereg = cfg->frame_reg;
2051 offset += size;
2052 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2053 }
2054
2055 cfg->locals_max_stack_offset = offset;
2056
2057 curinst = 0;
2058 if (sig->hasthis) {
2059 ins = cfg->args [curinst];
2060 if (ins->opcode != OP_REGVAR) {
2061 ins->opcode = OP_REGOFFSET;
2062 ins->inst_basereg = cfg->frame_reg;
2063 offset += sizeof (gpointer) - 1;
2064 offset &= ~(sizeof (gpointer) - 1);
2065 ins->inst_offset = offset;
2066 offset += sizeof (gpointer);
2067 }
2068 curinst++;
2069 }
2070
2071 if (sig->call_convention == MONO_CALL_VARARG) {
2072 size = 4;
2073 align = 4;
2074
2075 /* Allocate a local slot to hold the sig cookie address */
2076 offset += align - 1;
2077 offset &= ~(align - 1);
2078 cfg->sig_cookie = offset;
2079 offset += size;
2080 }
2081
2082 for (i = 0; i < sig->param_count; ++i) {
2083 ainfo = cinfo->args + i;
2084
2085 ins = cfg->args [curinst];
2086
2087 switch (ainfo->storage) {
2088 case RegTypeHFA:
2089 offset = ALIGN_TO (offset, 8);
2090 ins->opcode = OP_REGOFFSET;
2091 ins->inst_basereg = cfg->frame_reg;
2092 /* These arguments are saved to the stack in the prolog */
2093 ins->inst_offset = offset;
2094 if (cfg->verbose_level >= 2)
2095 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2096 // FIXME:
2097 offset += 32;
2098 break;
2099 default:
2100 break;
2101 }
2102
2103 if (ins->opcode != OP_REGVAR) {
2104 ins->opcode = OP_REGOFFSET;
2105 ins->inst_basereg = cfg->frame_reg;
2106 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2107 align = ualign;
2108 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2109 * since it loads/stores misaligned words, which don't do the right thing.
2110 */
2111 if (align < 4 && size >= 4)
2112 align = 4;
2113 /* The code in the prolog () stores words when storing vtypes received in a register */
2114 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2115 align = 4;
2116 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2117 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2118 offset += align - 1;
2119 offset &= ~(align - 1);
2120 ins->inst_offset = offset;
2121 offset += size;
2122 }
2123 curinst++;
2124 }
2125
2126 /* align the offset to 8 bytes */
2127 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2128 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2129 offset += 8 - 1;
2130 offset &= ~(8 - 1);
2131
2132 /* change sign? */
2133 cfg->stack_offset = offset;
2134 }
2135
2136 void
2137 mono_arch_create_vars (MonoCompile *cfg)
2138 {
2139 MonoMethodSignature *sig;
2140 CallInfo *cinfo;
2141 int i;
2142
2143 sig = mono_method_signature (cfg->method);
2144
2145 if (!cfg->arch.cinfo)
2146 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2147 cinfo = cfg->arch.cinfo;
2148
2149 if (IS_HARD_FLOAT) {
2150 for (i = 0; i < 2; i++) {
2151 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2152 inst->flags |= MONO_INST_VOLATILE;
2153
2154 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2155 }
2156 }
2157
2158 if (cinfo->ret.storage == RegTypeStructByVal)
2159 cfg->ret_var_is_local = TRUE;
2160
2161 if (cinfo->ret.storage == RegTypeStructByAddr) {
2162 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2163 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2164 g_print ("vret_addr = ");
2165 mono_print_ins (cfg->vret_addr);
2166 }
2167 }
2168
2169 if (cfg->gen_sdb_seq_points) {
2170 if (cfg->soft_breakpoints) {
2171 MonoInst *ins;
2172
2173 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2174 ins->flags |= MONO_INST_VOLATILE;
2175 cfg->arch.seq_point_ss_method_var = ins;
2176
2177 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2178 ins->flags |= MONO_INST_VOLATILE;
2179 cfg->arch.seq_point_bp_method_var = ins;
2180
2181 g_assert (!cfg->compile_aot);
2182 } else if (cfg->compile_aot) {
2183 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2184 ins->flags |= MONO_INST_VOLATILE;
2185 cfg->arch.seq_point_info_var = ins;
2186
2187 /* Allocate a separate variable for this to save 1 load per seq point */
2188 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2189 ins->flags |= MONO_INST_VOLATILE;
2190 cfg->arch.ss_trigger_page_var = ins;
2191 }
2192 }
2193 }
2194
2195 static void
2196 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2197 {
2198 MonoMethodSignature *tmp_sig;
2199 int sig_reg;
2200
2201 if (call->tail_call)
2202 NOT_IMPLEMENTED;
2203
2204 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2205
2206 /*
2207 * mono_ArgIterator_Setup assumes the signature cookie is
2208 * passed first and all the arguments which were before it are
2209 * passed on the stack after the signature. So compensate by
2210 * passing a different signature.
2211 */
2212 tmp_sig = mono_metadata_signature_dup (call->signature);
2213 tmp_sig->param_count -= call->signature->sentinelpos;
2214 tmp_sig->sentinelpos = 0;
2215 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2216
2217 sig_reg = mono_alloc_ireg (cfg);
2218 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2219
2220 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2221 }
2222
2223 #ifdef ENABLE_LLVM
2224 LLVMCallInfo*
2225 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2226 {
2227 int i, n;
2228 CallInfo *cinfo;
2229 ArgInfo *ainfo;
2230 LLVMCallInfo *linfo;
2231
2232 n = sig->param_count + sig->hasthis;
2233
2234 cinfo = get_call_info (cfg->mempool, sig);
2235
2236 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2237
2238 /*
2239 * LLVM always uses the native ABI while we use our own ABI, the
2240 * only difference is the handling of vtypes:
2241 * - we only pass/receive them in registers in some cases, and only
2242 * in 1 or 2 integer registers.
2243 */
2244 switch (cinfo->ret.storage) {
2245 case RegTypeGeneral:
2246 case RegTypeNone:
2247 case RegTypeFP:
2248 case RegTypeIRegPair:
2249 break;
2250 case RegTypeStructByAddr:
2251 /* Vtype returned using a hidden argument */
2252 linfo->ret.storage = LLVMArgVtypeRetAddr;
2253 linfo->vret_arg_index = cinfo->vret_arg_index;
2254 break;
2255 default:
2256 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2257 cfg->disable_llvm = TRUE;
2258 return linfo;
2259 }
2260
2261 for (i = 0; i < n; ++i) {
2262 ainfo = cinfo->args + i;
2263
2264 linfo->args [i].storage = LLVMArgNone;
2265
2266 switch (ainfo->storage) {
2267 case RegTypeGeneral:
2268 case RegTypeIRegPair:
2269 case RegTypeBase:
2270 case RegTypeBaseGen:
2271 linfo->args [i].storage = LLVMArgNormal;
2272 break;
2273 case RegTypeStructByVal:
2274 linfo->args [i].storage = LLVMArgAsIArgs;
2275 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2276 break;
2277 default:
2278 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2279 cfg->disable_llvm = TRUE;
2280 break;
2281 }
2282 }
2283
2284 return linfo;
2285 }
2286 #endif
2287
2288 void
2289 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2290 {
2291 MonoInst *in, *ins;
2292 MonoMethodSignature *sig;
2293 int i, n;
2294 CallInfo *cinfo;
2295
2296 sig = call->signature;
2297 n = sig->param_count + sig->hasthis;
2298
2299 cinfo = get_call_info (cfg->mempool, sig);
2300
2301 switch (cinfo->ret.storage) {
2302 case RegTypeStructByVal:
2303 /* The JIT will transform this into a normal call */
2304 call->vret_in_reg = TRUE;
2305 break;
2306 case RegTypeHFA:
2307 /*
2308 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2309 * the location pointed to by it after call in emit_move_return_value ().
2310 */
2311 if (!cfg->arch.vret_addr_loc) {
2312 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2313 /* Prevent it from being register allocated or optimized away */
2314 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2315 }
2316
2317 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2318 break;
2319 case RegTypeStructByAddr: {
2320 MonoInst *vtarg;
2321 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2322 vtarg->sreg1 = call->vret_var->dreg;
2323 vtarg->dreg = mono_alloc_preg (cfg);
2324 MONO_ADD_INS (cfg->cbb, vtarg);
2325
2326 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2327 break;
2328 }
2329 default:
2330 break;
2331 }
2332
2333 for (i = 0; i < n; ++i) {
2334 ArgInfo *ainfo = cinfo->args + i;
2335 MonoType *t;
2336
2337 if (i >= sig->hasthis)
2338 t = sig->params [i - sig->hasthis];
2339 else
2340 t = &mono_defaults.int_class->byval_arg;
2341 t = mini_get_underlying_type (t);
2342
2343 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2344 /* Emit the signature cookie just before the implicit arguments */
2345 emit_sig_cookie (cfg, call, cinfo);
2346 }
2347
2348 in = call->args [i];
2349
2350 switch (ainfo->storage) {
2351 case RegTypeGeneral:
2352 case RegTypeIRegPair:
2353 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2354 MONO_INST_NEW (cfg, ins, OP_MOVE);
2355 ins->dreg = mono_alloc_ireg (cfg);
2356 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2357 MONO_ADD_INS (cfg->cbb, ins);
2358 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2359
2360 MONO_INST_NEW (cfg, ins, OP_MOVE);
2361 ins->dreg = mono_alloc_ireg (cfg);
2362 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2363 MONO_ADD_INS (cfg->cbb, ins);
2364 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2365 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2366 if (ainfo->size == 4) {
2367 if (IS_SOFT_FLOAT) {
2368 /* mono_emit_call_args () have already done the r8->r4 conversion */
2369 /* The converted value is in an int vreg */
2370 MONO_INST_NEW (cfg, ins, OP_MOVE);
2371 ins->dreg = mono_alloc_ireg (cfg);
2372 ins->sreg1 = in->dreg;
2373 MONO_ADD_INS (cfg->cbb, ins);
2374 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2375 } else {
2376 int creg;
2377
2378 cfg->param_area = MAX (cfg->param_area, 8);
2379 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2380 creg = mono_alloc_ireg (cfg);
2381 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2382 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2383 }
2384 } else {
2385 if (IS_SOFT_FLOAT) {
2386 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2387 ins->dreg = mono_alloc_ireg (cfg);
2388 ins->sreg1 = in->dreg;
2389 MONO_ADD_INS (cfg->cbb, ins);
2390 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2391
2392 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2393 ins->dreg = mono_alloc_ireg (cfg);
2394 ins->sreg1 = in->dreg;
2395 MONO_ADD_INS (cfg->cbb, ins);
2396 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2397 } else {
2398 int creg;
2399
2400 cfg->param_area = MAX (cfg->param_area, 8);
2401 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2402 creg = mono_alloc_ireg (cfg);
2403 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2404 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2405 creg = mono_alloc_ireg (cfg);
2406 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2407 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2408 }
2409 }
2410 cfg->flags |= MONO_CFG_HAS_FPOUT;
2411 } else {
2412 MONO_INST_NEW (cfg, ins, OP_MOVE);
2413 ins->dreg = mono_alloc_ireg (cfg);
2414 ins->sreg1 = in->dreg;
2415 MONO_ADD_INS (cfg->cbb, ins);
2416
2417 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2418 }
2419 break;
2420 case RegTypeStructByAddr:
2421 NOT_IMPLEMENTED;
2422 #if 0
2423 /* FIXME: where si the data allocated? */
2424 arg->backend.reg3 = ainfo->reg;
2425 call->used_iregs |= 1 << ainfo->reg;
2426 g_assert_not_reached ();
2427 #endif
2428 break;
2429 case RegTypeStructByVal:
2430 case RegTypeGSharedVtInReg:
2431 case RegTypeGSharedVtOnStack:
2432 case RegTypeHFA:
2433 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2434 ins->opcode = OP_OUTARG_VT;
2435 ins->sreg1 = in->dreg;
2436 ins->klass = in->klass;
2437 ins->inst_p0 = call;
2438 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2439 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2440 mono_call_inst_add_outarg_vt (cfg, call, ins);
2441 MONO_ADD_INS (cfg->cbb, ins);
2442 break;
2443 case RegTypeBase:
2444 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2445 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2446 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2447 if (t->type == MONO_TYPE_R8) {
2448 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2449 } else {
2450 if (IS_SOFT_FLOAT)
2451 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2452 else
2453 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2454 }
2455 } else {
2456 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2457 }
2458 break;
2459 case RegTypeBaseGen:
2460 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2461 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2462 MONO_INST_NEW (cfg, ins, OP_MOVE);
2463 ins->dreg = mono_alloc_ireg (cfg);
2464 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2465 MONO_ADD_INS (cfg->cbb, ins);
2466 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2467 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2468 int creg;
2469
2470 /* This should work for soft-float as well */
2471
2472 cfg->param_area = MAX (cfg->param_area, 8);
2473 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2474 creg = mono_alloc_ireg (cfg);
2475 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2476 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2477 creg = mono_alloc_ireg (cfg);
2478 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2479 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2480 cfg->flags |= MONO_CFG_HAS_FPOUT;
2481 } else {
2482 g_assert_not_reached ();
2483 }
2484 break;
2485 case RegTypeFP: {
2486 int fdreg = mono_alloc_freg (cfg);
2487
2488 if (ainfo->size == 8) {
2489 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2490 ins->sreg1 = in->dreg;
2491 ins->dreg = fdreg;
2492 MONO_ADD_INS (cfg->cbb, ins);
2493
2494 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2495 } else {
2496 FloatArgData *fad;
2497
2498 /*
2499 * Mono's register allocator doesn't speak single-precision registers that
2500 * overlap double-precision registers (i.e. armhf). So we have to work around
2501 * the register allocator and load the value from memory manually.
2502 *
2503 * So we create a variable for the float argument and an instruction to store
2504 * the argument into the variable. We then store the list of these arguments
2505 * in cfg->float_args. This list is then used by emit_float_args later to
2506 * pass the arguments in the various call opcodes.
2507 *
2508 * This is not very nice, and we should really try to fix the allocator.
2509 */
2510
2511 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2512
2513 /* Make sure the instruction isn't seen as pointless and removed.
2514 */
2515 float_arg->flags |= MONO_INST_VOLATILE;
2516
2517 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2518
2519 /* We use the dreg to look up the instruction later. The hreg is used to
2520 * emit the instruction that loads the value into the FP reg.
2521 */
2522 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2523 fad->vreg = float_arg->dreg;
2524 fad->hreg = ainfo->reg;
2525
2526 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2527 }
2528
2529 call->used_iregs |= 1 << ainfo->reg;
2530 cfg->flags |= MONO_CFG_HAS_FPOUT;
2531 break;
2532 }
2533 default:
2534 g_assert_not_reached ();
2535 }
2536 }
2537
2538 /* Handle the case where there are no implicit arguments */
2539 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2540 emit_sig_cookie (cfg, call, cinfo);
2541
2542 call->call_info = cinfo;
2543 call->stack_usage = cinfo->stack_usage;
2544 }
2545
2546 static void
2547 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2548 {
2549 MonoInst *ins;
2550
2551 switch (storage) {
2552 case RegTypeFP:
2553 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2554 ins->dreg = mono_alloc_freg (cfg);
2555 ins->sreg1 = arg->dreg;
2556 MONO_ADD_INS (cfg->cbb, ins);
2557 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2558 break;
2559 default:
2560 g_assert_not_reached ();
2561 break;
2562 }
2563 }
2564
2565 void
2566 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2567 {
2568 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2569 MonoInst *load;
2570 ArgInfo *ainfo = ins->inst_p1;
2571 int ovf_size = ainfo->vtsize;
2572 int doffset = ainfo->offset;
2573 int struct_size = ainfo->struct_size;
2574 int i, soffset, dreg, tmpreg;
2575
2576 switch (ainfo->storage) {
2577 case RegTypeGSharedVtInReg:
2578 /* Pass by addr */
2579 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2580 break;
2581 case RegTypeGSharedVtOnStack:
2582 /* Pass by addr on stack */
2583 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2584 break;
2585 case RegTypeHFA:
2586 for (i = 0; i < ainfo->nregs; ++i) {
2587 if (ainfo->esize == 4)
2588 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2589 else
2590 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2591 load->dreg = mono_alloc_freg (cfg);
2592 load->inst_basereg = src->dreg;
2593 load->inst_offset = i * ainfo->esize;
2594 MONO_ADD_INS (cfg->cbb, load);
2595
2596 if (ainfo->esize == 4) {
2597 FloatArgData *fad;
2598
2599 /* See RegTypeFP in mono_arch_emit_call () */
2600 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2601 float_arg->flags |= MONO_INST_VOLATILE;
2602 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2603
2604 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2605 fad->vreg = float_arg->dreg;
2606 fad->hreg = ainfo->reg + i;
2607
2608 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2609 } else {
2610 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2611 }
2612 }
2613 break;
2614 default:
2615 soffset = 0;
2616 for (i = 0; i < ainfo->size; ++i) {
2617 dreg = mono_alloc_ireg (cfg);
2618 switch (struct_size) {
2619 case 1:
2620 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2621 break;
2622 case 2:
2623 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2624 break;
2625 case 3:
2626 tmpreg = mono_alloc_ireg (cfg);
2627 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2629 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2630 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2631 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2632 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2633 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2634 break;
2635 default:
2636 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2637 break;
2638 }
2639 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2640 soffset += sizeof (gpointer);
2641 struct_size -= sizeof (gpointer);
2642 }
2643 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2644 if (ovf_size != 0)
2645 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2646 break;
2647 }
2648 }
2649
2650 void
2651 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2652 {
2653 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2654
2655 if (!ret->byref) {
2656 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2657 MonoInst *ins;
2658
2659 if (COMPILE_LLVM (cfg)) {
2660 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2661 } else {
2662 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2663 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2664 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2665 MONO_ADD_INS (cfg->cbb, ins);
2666 }
2667 return;
2668 }
2669 switch (arm_fpu) {
2670 case MONO_ARM_FPU_NONE:
2671 if (ret->type == MONO_TYPE_R8) {
2672 MonoInst *ins;
2673
2674 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2675 ins->dreg = cfg->ret->dreg;
2676 ins->sreg1 = val->dreg;
2677 MONO_ADD_INS (cfg->cbb, ins);
2678 return;
2679 }
2680 if (ret->type == MONO_TYPE_R4) {
2681 /* Already converted to an int in method_to_ir () */
2682 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2683 return;
2684 }
2685 break;
2686 case MONO_ARM_FPU_VFP:
2687 case MONO_ARM_FPU_VFP_HARD:
2688 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2689 MonoInst *ins;
2690
2691 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2692 ins->dreg = cfg->ret->dreg;
2693 ins->sreg1 = val->dreg;
2694 MONO_ADD_INS (cfg->cbb, ins);
2695 return;
2696 }
2697 break;
2698 default:
2699 g_assert_not_reached ();
2700 }
2701 }
2702
2703 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2704 }
2705
2706 #endif /* #ifndef DISABLE_JIT */
2707
2708 gboolean
2709 mono_arch_is_inst_imm (gint64 imm)
2710 {
2711 return TRUE;
2712 }
2713
2714 typedef struct {
2715 MonoMethodSignature *sig;
2716 CallInfo *cinfo;
2717 MonoType *rtype;
2718 MonoType **param_types;
2719 } ArchDynCallInfo;
2720
2721 static gboolean
2722 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2723 {
2724 int i;
2725
2726 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2727 return FALSE;
2728
2729 switch (cinfo->ret.storage) {
2730 case RegTypeNone:
2731 case RegTypeGeneral:
2732 case RegTypeIRegPair:
2733 case RegTypeStructByAddr:
2734 break;
2735 case RegTypeFP:
2736 if (IS_VFP)
2737 break;
2738 else
2739 return FALSE;
2740 default:
2741 return FALSE;
2742 }
2743
2744 for (i = 0; i < cinfo->nargs; ++i) {
2745 ArgInfo *ainfo = &cinfo->args [i];
2746 int last_slot;
2747
2748 switch (ainfo->storage) {
2749 case RegTypeGeneral:
2750 case RegTypeIRegPair:
2751 case RegTypeBaseGen:
2752 break;
2753 case RegTypeBase:
2754 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2755 return FALSE;
2756 break;
2757 case RegTypeStructByVal:
2758 if (ainfo->size == 0)
2759 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2760 else
2761 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2762 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2763 return FALSE;
2764 break;
2765 default:
2766 return FALSE;
2767 }
2768 }
2769
2770 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2771 for (i = 0; i < sig->param_count; ++i) {
2772 MonoType *t = sig->params [i];
2773
2774 if (t->byref)
2775 continue;
2776
2777 t = mini_get_underlying_type (t);
2778
2779 switch (t->type) {
2780 case MONO_TYPE_R4:
2781 case MONO_TYPE_R8:
2782 if (IS_SOFT_FLOAT)
2783 return FALSE;
2784 else
2785 break;
2786 /*
2787 case MONO_TYPE_I8:
2788 case MONO_TYPE_U8:
2789 return FALSE;
2790 */
2791 default:
2792 break;
2793 }
2794 }
2795
2796 return TRUE;
2797 }
2798
2799 MonoDynCallInfo*
2800 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2801 {
2802 ArchDynCallInfo *info;
2803 CallInfo *cinfo;
2804 int i;
2805
2806 cinfo = get_call_info (NULL, sig);
2807
2808 if (!dyn_call_supported (cinfo, sig)) {
2809 g_free (cinfo);
2810 return NULL;
2811 }
2812
2813 info = g_new0 (ArchDynCallInfo, 1);
2814 // FIXME: Preprocess the info to speed up start_dyn_call ()
2815 info->sig = sig;
2816 info->cinfo = cinfo;
2817 info->rtype = mini_get_underlying_type (sig->ret);
2818 info->param_types = g_new0 (MonoType*, sig->param_count);
2819 for (i = 0; i < sig->param_count; ++i)
2820 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2821
2822 return (MonoDynCallInfo*)info;
2823 }
2824
2825 void
2826 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2827 {
2828 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2829
2830 g_free (ainfo->cinfo);
2831 g_free (ainfo);
2832 }
2833
2834 void
2835 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2836 {
2837 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2838 DynCallArgs *p = (DynCallArgs*)buf;
2839 int arg_index, greg, i, j, pindex;
2840 MonoMethodSignature *sig = dinfo->sig;
2841
2842 g_assert (buf_len >= sizeof (DynCallArgs));
2843
2844 p->res = 0;
2845 p->ret = ret;
2846
2847 arg_index = 0;
2848 greg = 0;
2849 pindex = 0;
2850
2851 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2852 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2853 if (!sig->hasthis)
2854 pindex = 1;
2855 }
2856
2857 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2858 p->regs [greg ++] = (mgreg_t)ret;
2859
2860 for (i = pindex; i < sig->param_count; i++) {
2861 MonoType *t = dinfo->param_types [i];
2862 gpointer *arg = args [arg_index ++];
2863 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2864 int slot = -1;
2865
2866 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2867 slot = ainfo->reg;
2868 } else if (ainfo->storage == RegTypeBase) {
2869 slot = PARAM_REGS + (ainfo->offset / 4);
2870 } else if (ainfo->storage == RegTypeBaseGen) {
2871 /* slot + 1 is the first stack slot, so the code below will work */
2872 slot = 3;
2873 } else {
2874 g_assert_not_reached ();
2875 }
2876
2877 if (t->byref) {
2878 p->regs [slot] = (mgreg_t)*arg;
2879 continue;
2880 }
2881
2882 switch (t->type) {
2883 case MONO_TYPE_STRING:
2884 case MONO_TYPE_CLASS:
2885 case MONO_TYPE_ARRAY:
2886 case MONO_TYPE_SZARRAY:
2887 case MONO_TYPE_OBJECT:
2888 case MONO_TYPE_PTR:
2889 case MONO_TYPE_I:
2890 case MONO_TYPE_U:
2891 p->regs [slot] = (mgreg_t)*arg;
2892 break;
2893 case MONO_TYPE_U1:
2894 p->regs [slot] = *(guint8*)arg;
2895 break;
2896 case MONO_TYPE_I1:
2897 p->regs [slot] = *(gint8*)arg;
2898 break;
2899 case MONO_TYPE_I2:
2900 p->regs [slot] = *(gint16*)arg;
2901 break;
2902 case MONO_TYPE_U2:
2903 p->regs [slot] = *(guint16*)arg;
2904 break;
2905 case MONO_TYPE_I4:
2906 p->regs [slot] = *(gint32*)arg;
2907 break;
2908 case MONO_TYPE_U4:
2909 p->regs [slot] = *(guint32*)arg;
2910 break;
2911 case MONO_TYPE_I8:
2912 case MONO_TYPE_U8:
2913 p->regs [slot ++] = (mgreg_t)arg [0];
2914 p->regs [slot] = (mgreg_t)arg [1];
2915 break;
2916 case MONO_TYPE_R4:
2917 p->regs [slot] = *(mgreg_t*)arg;
2918 break;
2919 case MONO_TYPE_R8:
2920 p->regs [slot ++] = (mgreg_t)arg [0];
2921 p->regs [slot] = (mgreg_t)arg [1];
2922 break;
2923 case MONO_TYPE_GENERICINST:
2924 if (MONO_TYPE_IS_REFERENCE (t)) {
2925 p->regs [slot] = (mgreg_t)*arg;
2926 break;
2927 } else {
2928 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2929 MonoClass *klass = mono_class_from_mono_type (t);
2930 guint8 *nullable_buf;
2931 int size;
2932
2933 size = mono_class_value_size (klass, NULL);
2934 nullable_buf = g_alloca (size);
2935 g_assert (nullable_buf);
2936
2937 /* The argument pointed to by arg is either a boxed vtype or null */
2938 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2939
2940 arg = (gpointer*)nullable_buf;
2941 /* Fall though */
2942 } else {
2943 /* Fall though */
2944 }
2945 }
2946 case MONO_TYPE_VALUETYPE:
2947 g_assert (ainfo->storage == RegTypeStructByVal);
2948
2949 if (ainfo->size == 0)
2950 slot = PARAM_REGS + (ainfo->offset / 4);
2951 else
2952 slot = ainfo->reg;
2953
2954 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2955 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2956 break;
2957 default:
2958 g_assert_not_reached ();
2959 }
2960 }
2961 }
2962
2963 void
2964 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2965 {
2966 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2967 MonoType *ptype = ainfo->rtype;
2968 guint8 *ret = ((DynCallArgs*)buf)->ret;
2969 mgreg_t res = ((DynCallArgs*)buf)->res;
2970 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2971
2972 switch (ptype->type) {
2973 case MONO_TYPE_VOID:
2974 *(gpointer*)ret = NULL;
2975 break;
2976 case MONO_TYPE_STRING:
2977 case MONO_TYPE_CLASS:
2978 case MONO_TYPE_ARRAY:
2979 case MONO_TYPE_SZARRAY:
2980 case MONO_TYPE_OBJECT:
2981 case MONO_TYPE_I:
2982 case MONO_TYPE_U:
2983 case MONO_TYPE_PTR:
2984 *(gpointer*)ret = (gpointer)res;
2985 break;
2986 case MONO_TYPE_I1:
2987 *(gint8*)ret = res;
2988 break;
2989 case MONO_TYPE_U1:
2990 *(guint8*)ret = res;
2991 break;
2992 case MONO_TYPE_I2:
2993 *(gint16*)ret = res;
2994 break;
2995 case MONO_TYPE_U2:
2996 *(guint16*)ret = res;
2997 break;
2998 case MONO_TYPE_I4:
2999 *(gint32*)ret = res;
3000 break;
3001 case MONO_TYPE_U4:
3002 *(guint32*)ret = res;
3003 break;
3004 case MONO_TYPE_I8:
3005 case MONO_TYPE_U8:
3006 /* This handles endianness as well */
3007 ((gint32*)ret) [0] = res;
3008 ((gint32*)ret) [1] = res2;
3009 break;
3010 case MONO_TYPE_GENERICINST:
3011 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3012 *(gpointer*)ret = (gpointer)res;
3013 break;
3014 } else {
3015 /* Fall though */
3016 }
3017 case MONO_TYPE_VALUETYPE:
3018 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3019 /* Nothing to do */
3020 break;
3021 case MONO_TYPE_R4:
3022 g_assert (IS_VFP);
3023 *(float*)ret = *(float*)&res;
3024 break;
3025 case MONO_TYPE_R8: {
3026 mgreg_t regs [2];
3027
3028 g_assert (IS_VFP);
3029 regs [0] = res;
3030 regs [1] = res2;
3031
3032 *(double*)ret = *(double*)&regs;
3033 break;
3034 }
3035 default:
3036 g_assert_not_reached ();
3037 }
3038 }
3039
3040 #ifndef DISABLE_JIT
3041
3042 /*
3043 * Allow tracing to work with this interface (with an optional argument)
3044 */
3045
3046 void*
3047 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3048 {
3049 guchar *code = p;
3050
3051 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3052 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3053 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3054 code = emit_call_reg (code, ARMREG_R2);
3055 return code;
3056 }
3057
3058 enum {
3059 SAVE_NONE,
3060 SAVE_STRUCT,
3061 SAVE_ONE,
3062 SAVE_TWO,
3063 SAVE_ONE_FP,
3064 SAVE_TWO_FP
3065 };
3066
3067 void*
3068 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3069 {
3070 guchar *code = p;
3071 int save_mode = SAVE_NONE;
3072 int offset;
3073 MonoMethod *method = cfg->method;
3074 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3075 int rtype = ret_type->type;
3076 int save_offset = cfg->param_area;
3077 save_offset += 7;
3078 save_offset &= ~7;
3079
3080 offset = code - cfg->native_code;
3081 /* we need about 16 instructions */
3082 if (offset > (cfg->code_size - 16 * 4)) {
3083 cfg->code_size *= 2;
3084 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3085 code = cfg->native_code + offset;
3086 }
3087 switch (rtype) {
3088 case MONO_TYPE_VOID:
3089 /* special case string .ctor icall */
3090 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3091 save_mode = SAVE_ONE;
3092 else
3093 save_mode = SAVE_NONE;
3094 break;
3095 case MONO_TYPE_I8:
3096 case MONO_TYPE_U8:
3097 save_mode = SAVE_TWO;
3098 break;
3099 case MONO_TYPE_R4:
3100 if (IS_HARD_FLOAT)
3101 save_mode = SAVE_ONE_FP;
3102 else
3103 save_mode = SAVE_ONE;
3104 break;
3105 case MONO_TYPE_R8:
3106 if (IS_HARD_FLOAT)
3107 save_mode = SAVE_TWO_FP;
3108 else
3109 save_mode = SAVE_TWO;
3110 break;
3111 case MONO_TYPE_GENERICINST:
3112 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3113 save_mode = SAVE_ONE;
3114 break;
3115 }
3116 /* Fall through */
3117 case MONO_TYPE_VALUETYPE:
3118 save_mode = SAVE_STRUCT;
3119 break;
3120 default:
3121 save_mode = SAVE_ONE;
3122 break;
3123 }
3124
3125 switch (save_mode) {
3126 case SAVE_TWO:
3127 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3128 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3129 if (enable_arguments) {
3130 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3131 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3132 }
3133 break;
3134 case SAVE_ONE:
3135 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3136 if (enable_arguments) {
3137 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3138 }
3139 break;
3140 case SAVE_ONE_FP:
3141 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3142 if (enable_arguments) {
3143 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3144 }
3145 break;
3146 case SAVE_TWO_FP:
3147 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3148 if (enable_arguments) {
3149 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3150 }
3151 break;
3152 case SAVE_STRUCT:
3153 if (enable_arguments) {
3154 /* FIXME: get the actual address */
3155 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3156 }
3157 break;
3158 case SAVE_NONE:
3159 default:
3160 break;
3161 }
3162
3163 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3164 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3165 code = emit_call_reg (code, ARMREG_IP);
3166
3167 switch (save_mode) {
3168 case SAVE_TWO:
3169 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3170 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3171 break;
3172 case SAVE_ONE:
3173 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3174 break;
3175 case SAVE_ONE_FP:
3176 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3177 break;
3178 case SAVE_TWO_FP:
3179 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3180 break;
3181 case SAVE_NONE:
3182 default:
3183 break;
3184 }
3185
3186 return code;
3187 }
3188
3189 /*
3190 * The immediate field for cond branches is big enough for all reasonable methods
3191 */
3192 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3193 if (0 && ins->inst_true_bb->native_offset) { \
3194 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3195 } else { \
3196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3197 ARM_B_COND (code, (condcode), 0); \
3198 }
3199
3200 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3201
3202 /* emit an exception if condition is fail
3203 *
3204 * We assign the extra code used to throw the implicit exceptions
3205 * to cfg->bb_exit as far as the big branch handling is concerned
3206 */
3207 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3208 do { \
3209 mono_add_patch_info (cfg, code - cfg->native_code, \
3210 MONO_PATCH_INFO_EXC, exc_name); \
3211 ARM_BL_COND (code, (condcode), 0); \
3212 } while (0);
3213
3214 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3215
3216 void
3217 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3218 {
3219 }
3220
3221 void
3222 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3223 {
3224 MonoInst *ins, *n;
3225
3226 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3227 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3228
3229 switch (ins->opcode) {
3230 case OP_MUL_IMM:
3231 case OP_IMUL_IMM:
3232 /* Already done by an arch-independent pass */
3233 break;
3234 case OP_LOAD_MEMBASE:
3235 case OP_LOADI4_MEMBASE:
3236 /*
3237 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3238 * OP_LOAD_MEMBASE offset(basereg), reg
3239 */
3240 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3241 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3242 ins->inst_basereg == last_ins->inst_destbasereg &&
3243 ins->inst_offset == last_ins->inst_offset) {
3244 if (ins->dreg == last_ins->sreg1) {
3245 MONO_DELETE_INS (bb, ins);
3246 continue;
3247 } else {
3248 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3249 ins->opcode = OP_MOVE;
3250 ins->sreg1 = last_ins->sreg1;
3251 }
3252
3253 /*
3254 * Note: reg1 must be different from the basereg in the second load
3255 * OP_LOAD_MEMBASE offset(basereg), reg1
3256 * OP_LOAD_MEMBASE offset(basereg), reg2
3257 * -->
3258 * OP_LOAD_MEMBASE offset(basereg), reg1
3259 * OP_MOVE reg1, reg2
3260 */
3261 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3262 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3263 ins->inst_basereg != last_ins->dreg &&
3264 ins->inst_basereg == last_ins->inst_basereg &&
3265 ins->inst_offset == last_ins->inst_offset) {
3266
3267 if (ins->dreg == last_ins->dreg) {
3268 MONO_DELETE_INS (bb, ins);
3269 continue;
3270 } else {
3271 ins->opcode = OP_MOVE;
3272 ins->sreg1 = last_ins->dreg;
3273 }
3274
3275 //g_assert_not_reached ();
3276
3277 #if 0
3278 /*
3279 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3280 * OP_LOAD_MEMBASE offset(basereg), reg
3281 * -->
3282 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3283 * OP_ICONST reg, imm
3284 */
3285 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3286 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3287 ins->inst_basereg == last_ins->inst_destbasereg &&
3288 ins->inst_offset == last_ins->inst_offset) {
3289 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3290 ins->opcode = OP_ICONST;
3291 ins->inst_c0 = last_ins->inst_imm;
3292 g_assert_not_reached (); // check this rule
3293 #endif
3294 }
3295 break;
3296 case OP_LOADU1_MEMBASE:
3297 case OP_LOADI1_MEMBASE:
3298 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3299 ins->inst_basereg == last_ins->inst_destbasereg &&
3300 ins->inst_offset == last_ins->inst_offset) {
3301 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3302 ins->sreg1 = last_ins->sreg1;
3303 }
3304 break;
3305 case OP_LOADU2_MEMBASE:
3306 case OP_LOADI2_MEMBASE:
3307 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3308 ins->inst_basereg == last_ins->inst_destbasereg &&
3309 ins->inst_offset == last_ins->inst_offset) {
3310 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3311 ins->sreg1 = last_ins->sreg1;
3312 }
3313 break;
3314 case OP_MOVE:
3315 ins->opcode = OP_MOVE;
3316 /*
3317 * OP_MOVE reg, reg
3318 */
3319 if (ins->dreg == ins->sreg1) {
3320 MONO_DELETE_INS (bb, ins);
3321 continue;
3322 }
3323 /*
3324 * OP_MOVE sreg, dreg
3325 * OP_MOVE dreg, sreg
3326 */
3327 if (last_ins && last_ins->opcode == OP_MOVE &&
3328 ins->sreg1 == last_ins->dreg &&
3329 ins->dreg == last_ins->sreg1) {
3330 MONO_DELETE_INS (bb, ins);
3331 continue;
3332 }
3333 break;
3334 }
3335 }
3336 }
3337
3338 /*
3339 * the branch_cc_table should maintain the order of these
3340 * opcodes.
3341 case CEE_BEQ:
3342 case CEE_BGE:
3343 case CEE_BGT:
3344 case CEE_BLE:
3345 case CEE_BLT:
3346 case CEE_BNE_UN:
3347 case CEE_BGE_UN:
3348 case CEE_BGT_UN:
3349 case CEE_BLE_UN:
3350 case CEE_BLT_UN:
3351 */
3352 static const guchar
3353 branch_cc_table [] = {
3354 ARMCOND_EQ,
3355 ARMCOND_GE,
3356 ARMCOND_GT,
3357 ARMCOND_LE,
3358 ARMCOND_LT,
3359
3360 ARMCOND_NE,
3361 ARMCOND_HS,
3362 ARMCOND_HI,
3363 ARMCOND_LS,
3364 ARMCOND_LO
3365 };
3366
3367 #define ADD_NEW_INS(cfg,dest,op) do { \
3368 MONO_INST_NEW ((cfg), (dest), (op)); \
3369 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3370 } while (0)
3371
3372 static int
3373 map_to_reg_reg_op (int op)
3374 {
3375 switch (op) {
3376 case OP_ADD_IMM:
3377 return OP_IADD;
3378 case OP_SUB_IMM:
3379 return OP_ISUB;
3380 case OP_AND_IMM:
3381 return OP_IAND;
3382 case OP_COMPARE_IMM:
3383 return OP_COMPARE;
3384 case OP_ICOMPARE_IMM:
3385 return OP_ICOMPARE;
3386 case OP_ADDCC_IMM:
3387 return OP_ADDCC;
3388 case OP_ADC_IMM:
3389 return OP_ADC;
3390 case OP_SUBCC_IMM:
3391 return OP_SUBCC;
3392 case OP_SBB_IMM:
3393 return OP_SBB;
3394 case OP_OR_IMM:
3395 return OP_IOR;
3396 case OP_XOR_IMM:
3397 return OP_IXOR;
3398 case OP_LOAD_MEMBASE:
3399 return OP_LOAD_MEMINDEX;
3400 case OP_LOADI4_MEMBASE:
3401 return OP_LOADI4_MEMINDEX;
3402 case OP_LOADU4_MEMBASE:
3403 return OP_LOADU4_MEMINDEX;
3404 case OP_LOADU1_MEMBASE:
3405 return OP_LOADU1_MEMINDEX;
3406 case OP_LOADI2_MEMBASE:
3407 return OP_LOADI2_MEMINDEX;
3408 case OP_LOADU2_MEMBASE:
3409 return OP_LOADU2_MEMINDEX;
3410 case OP_LOADI1_MEMBASE:
3411 return OP_LOADI1_MEMINDEX;
3412 case OP_STOREI1_MEMBASE_REG:
3413 return OP_STOREI1_MEMINDEX;
3414 case OP_STOREI2_MEMBASE_REG:
3415 return OP_STOREI2_MEMINDEX;
3416 case OP_STOREI4_MEMBASE_REG:
3417 return OP_STOREI4_MEMINDEX;
3418 case OP_STORE_MEMBASE_REG:
3419 return OP_STORE_MEMINDEX;
3420 case OP_STORER4_MEMBASE_REG:
3421 return OP_STORER4_MEMINDEX;
3422 case OP_STORER8_MEMBASE_REG:
3423 return OP_STORER8_MEMINDEX;
3424 case OP_STORE_MEMBASE_IMM:
3425 return OP_STORE_MEMBASE_REG;
3426 case OP_STOREI1_MEMBASE_IMM:
3427 return OP_STOREI1_MEMBASE_REG;
3428 case OP_STOREI2_MEMBASE_IMM:
3429 return OP_STOREI2_MEMBASE_REG;
3430 case OP_STOREI4_MEMBASE_IMM:
3431 return OP_STOREI4_MEMBASE_REG;
3432 }
3433 g_assert_not_reached ();
3434 }
3435
3436 /*
3437 * Remove from the instruction list the instructions that can't be
3438 * represented with very simple instructions with no register
3439 * requirements.
3440 */
3441 void
3442 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3443 {
3444 MonoInst *ins, *temp, *last_ins = NULL;
3445 int rot_amount, imm8, low_imm;
3446
3447 MONO_BB_FOR_EACH_INS (bb, ins) {
3448 loop_start:
3449 switch (ins->opcode) {
3450 case OP_ADD_IMM:
3451 case OP_SUB_IMM:
3452 case OP_AND_IMM:
3453 case OP_COMPARE_IMM:
3454 case OP_ICOMPARE_IMM:
3455 case OP_ADDCC_IMM:
3456 case OP_ADC_IMM:
3457 case OP_SUBCC_IMM:
3458 case OP_SBB_IMM:
3459 case OP_OR_IMM:
3460 case OP_XOR_IMM:
3461 case OP_IADD_IMM:
3462 case OP_ISUB_IMM:
3463 case OP_IAND_IMM:
3464 case OP_IADC_IMM:
3465 case OP_ISBB_IMM:
3466 case OP_IOR_IMM:
3467 case OP_IXOR_IMM:
3468 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3469 int opcode2 = mono_op_imm_to_op (ins->opcode);
3470 ADD_NEW_INS (cfg, temp, OP_ICONST);
3471 temp->inst_c0 = ins->inst_imm;
3472 temp->dreg = mono_alloc_ireg (cfg);
3473 ins->sreg2 = temp->dreg;
3474 if (opcode2 == -1)
3475 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3476 ins->opcode = opcode2;
3477 }
3478 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3479 goto loop_start;
3480 else
3481 break;
3482 case OP_MUL_IMM:
3483 case OP_IMUL_IMM:
3484 if (ins->inst_imm == 1) {
3485 ins->opcode = OP_MOVE;
3486 break;
3487 }
3488 if (ins->inst_imm == 0) {
3489 ins->opcode = OP_ICONST;
3490 ins->inst_c0 = 0;
3491 break;
3492 }
3493 imm8 = mono_is_power_of_two (ins->inst_imm);
3494 if (imm8 > 0) {
3495 ins->opcode = OP_SHL_IMM;
3496 ins->inst_imm = imm8;
3497 break;
3498 }
3499 ADD_NEW_INS (cfg, temp, OP_ICONST);
3500 temp->inst_c0 = ins->inst_imm;
3501 temp->dreg = mono_alloc_ireg (cfg);
3502 ins->sreg2 = temp->dreg;
3503 ins->opcode = OP_IMUL;
3504 break;
3505 case OP_SBB:
3506 case OP_ISBB:
3507 case OP_SUBCC:
3508 case OP_ISUBCC:
3509 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3510 /* ARM sets the C flag to 1 if there was _no_ overflow */
3511 ins->next->opcode = OP_COND_EXC_NC;
3512 break;
3513 case OP_IDIV_IMM:
3514 case OP_IDIV_UN_IMM:
3515 case OP_IREM_IMM:
3516 case OP_IREM_UN_IMM: {
3517 int opcode2 = mono_op_imm_to_op (ins->opcode);
3518 ADD_NEW_INS (cfg, temp, OP_ICONST);
3519 temp->inst_c0 = ins->inst_imm;
3520 temp->dreg = mono_alloc_ireg (cfg);
3521 ins->sreg2 = temp->dreg;
3522 if (opcode2 == -1)
3523 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3524 ins->opcode = opcode2;
3525 break;
3526 }
3527 case OP_LOCALLOC_IMM:
3528 ADD_NEW_INS (cfg, temp, OP_ICONST);
3529 temp->inst_c0 = ins->inst_imm;
3530 temp->dreg = mono_alloc_ireg (cfg);
3531 ins->sreg1 = temp->dreg;
3532 ins->opcode = OP_LOCALLOC;
3533 break;
3534 case OP_LOAD_MEMBASE:
3535 case OP_LOADI4_MEMBASE:
3536 case OP_LOADU4_MEMBASE:
3537 case OP_LOADU1_MEMBASE:
3538 /* we can do two things: load the immed in a register
3539 * and use an indexed load, or see if the immed can be
3540 * represented as an ad_imm + a load with a smaller offset
3541 * that fits. We just do the first for now, optimize later.
3542 */
3543 if (arm_is_imm12 (ins->inst_offset))
3544 break;
3545 ADD_NEW_INS (cfg, temp, OP_ICONST);
3546 temp->inst_c0 = ins->inst_offset;
3547 temp->dreg = mono_alloc_ireg (cfg);
3548 ins->sreg2 = temp->dreg;
3549 ins->opcode = map_to_reg_reg_op (ins->opcode);
3550 break;
3551 case OP_LOADI2_MEMBASE:
3552 case OP_LOADU2_MEMBASE:
3553 case OP_LOADI1_MEMBASE:
3554 if (arm_is_imm8 (ins->inst_offset))
3555 break;
3556 ADD_NEW_INS (cfg, temp, OP_ICONST);
3557 temp->inst_c0 = ins->inst_offset;
3558 temp->dreg = mono_alloc_ireg (cfg);
3559 ins->sreg2 = temp->dreg;
3560 ins->opcode = map_to_reg_reg_op (ins->opcode);
3561 break;
3562 case OP_LOADR4_MEMBASE:
3563 case OP_LOADR8_MEMBASE:
3564 if (arm_is_fpimm8 (ins->inst_offset))
3565 break;
3566 low_imm = ins->inst_offset & 0x1ff;
3567 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3568 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3569 temp->inst_imm = ins->inst_offset & ~0x1ff;
3570 temp->sreg1 = ins->inst_basereg;
3571 temp->dreg = mono_alloc_ireg (cfg);
3572 ins->inst_basereg = temp->dreg;
3573 ins->inst_offset = low_imm;
3574 } else {
3575 MonoInst *add_ins;
3576
3577 ADD_NEW_INS (cfg, temp, OP_ICONST);
3578 temp->inst_c0 = ins->inst_offset;
3579 temp->dreg = mono_alloc_ireg (cfg);
3580
3581 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3582 add_ins->sreg1 = ins->inst_basereg;
3583 add_ins->sreg2 = temp->dreg;
3584 add_ins->dreg = mono_alloc_ireg (cfg);
3585
3586 ins->inst_basereg = add_ins->dreg;
3587 ins->inst_offset = 0;
3588 }
3589 break;
3590 case OP_STORE_MEMBASE_REG:
3591 case OP_STOREI4_MEMBASE_REG:
3592 case OP_STOREI1_MEMBASE_REG:
3593 if (arm_is_imm12 (ins->inst_offset))
3594 break;
3595 ADD_NEW_INS (cfg, temp, OP_ICONST);
3596 temp->inst_c0 = ins->inst_offset;
3597 temp->dreg = mono_alloc_ireg (cfg);
3598 ins->sreg2 = temp->dreg;
3599 ins->opcode = map_to_reg_reg_op (ins->opcode);
3600 break;
3601 case OP_STOREI2_MEMBASE_REG:
3602 if (arm_is_imm8 (ins->inst_offset))
3603 break;
3604 ADD_NEW_INS (cfg, temp, OP_ICONST);
3605 temp->inst_c0 = ins->inst_offset;
3606 temp->dreg = mono_alloc_ireg (cfg);
3607 ins->sreg2 = temp->dreg;
3608 ins->opcode = map_to_reg_reg_op (ins->opcode);
3609 break;
3610 case OP_STORER4_MEMBASE_REG:
3611 case OP_STORER8_MEMBASE_REG:
3612 if (arm_is_fpimm8 (ins->inst_offset))
3613 break;
3614 low_imm = ins->inst_offset & 0x1ff;
3615 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3616 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3617 temp->inst_imm = ins->inst_offset & ~0x1ff;
3618 temp->sreg1 = ins->inst_destbasereg;
3619 temp->dreg = mono_alloc_ireg (cfg);
3620 ins->inst_destbasereg = temp->dreg;
3621 ins->inst_offset = low_imm;
3622 } else {
3623 MonoInst *add_ins;
3624
3625 ADD_NEW_INS (cfg, temp, OP_ICONST);
3626 temp->inst_c0 = ins->inst_offset;
3627 temp->dreg = mono_alloc_ireg (cfg);
3628
3629 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3630 add_ins->sreg1 = ins->inst_destbasereg;
3631 add_ins->sreg2 = temp->dreg;
3632 add_ins->dreg = mono_alloc_ireg (cfg);
3633
3634 ins->inst_destbasereg = add_ins->dreg;
3635 ins->inst_offset = 0;
3636 }
3637 break;
3638 case OP_STORE_MEMBASE_IMM:
3639 case OP_STOREI1_MEMBASE_IMM:
3640 case OP_STOREI2_MEMBASE_IMM:
3641 case OP_STOREI4_MEMBASE_IMM:
3642 ADD_NEW_INS (cfg, temp, OP_ICONST);
3643 temp->inst_c0 = ins->inst_imm;
3644 temp->dreg = mono_alloc_ireg (cfg);
3645 ins->sreg1 = temp->dreg;
3646 ins->opcode = map_to_reg_reg_op (ins->opcode);
3647 last_ins = temp;
3648 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3649 case OP_FCOMPARE:
3650 case OP_RCOMPARE: {
3651 gboolean swap = FALSE;
3652 int reg;
3653
3654 if (!ins->next) {
3655 /* Optimized away */
3656 NULLIFY_INS (ins);
3657 break;
3658 }
3659
3660 /* Some fp compares require swapped operands */
3661 switch (ins->next->opcode) {
3662 case OP_FBGT:
3663 ins->next->opcode = OP_FBLT;
3664 swap = TRUE;
3665 break;
3666 case OP_FBGT_UN:
3667 ins->next->opcode = OP_FBLT_UN;
3668 swap = TRUE;
3669 break;
3670 case OP_FBLE:
3671 ins->next->opcode = OP_FBGE;
3672 swap = TRUE;
3673 break;
3674 case OP_FBLE_UN:
3675 ins->next->opcode = OP_FBGE_UN;
3676 swap = TRUE;
3677 break;
3678 default:
3679 break;
3680 }
3681 if (swap) {
3682 reg = ins->sreg1;
3683 ins->sreg1 = ins->sreg2;
3684 ins->sreg2 = reg;
3685 }
3686 break;
3687 }
3688 }
3689
3690 last_ins = ins;
3691 }
3692 bb->last_ins = last_ins;
3693 bb->max_vreg = cfg->next_vreg;
3694 }
3695
3696 void
3697 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3698 {
3699 MonoInst *ins;
3700
3701 if (long_ins->opcode == OP_LNEG) {
3702 ins = long_ins;
3703 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3704 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3705 NULLIFY_INS (ins);
3706 }
3707 }
3708
3709 static guchar*
3710 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3711 {
3712 /* sreg is a float, dreg is an integer reg */
3713 if (IS_VFP) {
3714 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3715 if (is_signed)
3716 ARM_TOSIZD (code, vfp_scratch1, sreg);
3717 else
3718 ARM_TOUIZD (code, vfp_scratch1, sreg);
3719 ARM_FMRS (code, dreg, vfp_scratch1);
3720 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3721 }
3722 if (!is_signed) {
3723 if (size == 1)
3724 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3725 else if (size == 2) {
3726 ARM_SHL_IMM (code, dreg, dreg, 16);
3727 ARM_SHR_IMM (code, dreg, dreg, 16);
3728 }
3729 } else {
3730 if (size == 1) {
3731 ARM_SHL_IMM (code, dreg, dreg, 24);
3732 ARM_SAR_IMM (code, dreg, dreg, 24);
3733 } else if (size == 2) {
3734 ARM_SHL_IMM (code, dreg, dreg, 16);
3735 ARM_SAR_IMM (code, dreg, dreg, 16);
3736 }
3737 }
3738 return code;
3739 }
3740
3741 static guchar*
3742 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3743 {
3744 /* sreg is a float, dreg is an integer reg */
3745 g_assert (IS_VFP);
3746 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3747 if (is_signed)
3748 ARM_TOSIZS (code, vfp_scratch1, sreg);
3749 else
3750 ARM_TOUIZS (code, vfp_scratch1, sreg);
3751 ARM_FMRS (code, dreg, vfp_scratch1);
3752 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3753
3754 if (!is_signed) {
3755 if (size == 1)
3756 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3757 else if (size == 2) {
3758 ARM_SHL_IMM (code, dreg, dreg, 16);
3759 ARM_SHR_IMM (code, dreg, dreg, 16);
3760 }
3761 } else {
3762 if (size == 1) {
3763 ARM_SHL_IMM (code, dreg, dreg, 24);
3764 ARM_SAR_IMM (code, dreg, dreg, 24);
3765 } else if (size == 2) {
3766 ARM_SHL_IMM (code, dreg, dreg, 16);
3767 ARM_SAR_IMM (code, dreg, dreg, 16);
3768 }
3769 }
3770 return code;
3771 }
3772
3773 #endif /* #ifndef DISABLE_JIT */
3774
3775 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3776
3777 static void
3778 emit_thunk (guint8 *code, gconstpointer target)
3779 {
3780 guint8 *p = code;
3781
3782 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3783 if (thumb_supported)
3784 ARM_BX (code, ARMREG_IP);
3785 else
3786 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3787 *(guint32*)code = (guint32)target;
3788 code += 4;
3789 mono_arch_flush_icache (p, code - p);
3790 }
3791
3792 static void
3793 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3794 {
3795 MonoJitInfo *ji = NULL;
3796 MonoThunkJitInfo *info;
3797 guint8 *thunks, *p;
3798 int thunks_size;
3799 guint8 *orig_target;
3800 guint8 *target_thunk;
3801
3802 if (!domain)
3803 domain = mono_domain_get ();
3804
3805 if (cfg) {
3806 /*
3807 * This can be called multiple times during JITting,
3808 * save the current position in cfg->arch to avoid
3809 * doing a O(n^2) search.
3810 */
3811 if (!cfg->arch.thunks) {
3812 cfg->arch.thunks = cfg->thunks;
3813 cfg->arch.thunks_size = cfg->thunk_area;
3814 }
3815 thunks = cfg->arch.thunks;
3816 thunks_size = cfg->arch.thunks_size;
3817 if (!thunks_size) {
3818 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3819 g_assert_not_reached ();
3820 }
3821
3822 g_assert (*(guint32*)thunks == 0);
3823 emit_thunk (thunks, target);
3824 arm_patch (code, thunks);
3825
3826 cfg->arch.thunks += THUNK_SIZE;
3827 cfg->arch.thunks_size -= THUNK_SIZE;
3828 } else {
3829 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3830 g_assert (ji);
3831 info = mono_jit_info_get_thunk_info (ji);
3832 g_assert (info);
3833
3834 thunks = (guint8*)ji->code_start + info->thunks_offset;
3835 thunks_size = info->thunks_size;
3836
3837 orig_target = mono_arch_get_call_target (code + 4);
3838
3839 mono_mini_arch_lock ();
3840
3841 target_thunk = NULL;
3842 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3843 /* The call already points to a thunk, because of trampolines etc. */
3844 target_thunk = orig_target;
3845 } else {
3846 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3847 if (((guint32*)p) [0] == 0) {
3848 /* Free entry */
3849 target_thunk = p;
3850 break;
3851 } else if (((guint32*)p) [2] == (guint32)target) {
3852 /* Thunk already points to target */
3853 target_thunk = p;
3854 break;
3855 }
3856 }
3857 }
3858
3859 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3860
3861 if (!target_thunk) {
3862 mono_mini_arch_unlock ();
3863 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3864 g_assert_not_reached ();
3865 }
3866
3867 emit_thunk (target_thunk, target);
3868 arm_patch (code, target_thunk);
3869 mono_arch_flush_icache (code, 4);
3870
3871 mono_mini_arch_unlock ();
3872 }
3873 }
3874
3875 static void
3876 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3877 {
3878 guint32 *code32 = (void*)code;
3879 guint32 ins = *code32;
3880 guint32 prim = (ins >> 25) & 7;
3881 guint32 tval = GPOINTER_TO_UINT (target);
3882
3883 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3884 if (prim == 5) { /* 101b */
3885 /* the diff starts 8 bytes from the branch opcode */
3886 gint diff = target - code - 8;
3887 gint tbits;
3888 gint tmask = 0xffffffff;
3889 if (tval & 1) { /* entering thumb mode */
3890 diff = target - 1 - code - 8;
3891 g_assert (thumb_supported);
3892 tbits = 0xf << 28; /* bl->blx bit pattern */
3893 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3894 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3895 if (diff & 2) {
3896 tbits |= 1 << 24;
3897 }
3898 tmask = ~(1 << 24); /* clear the link bit */
3899 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3900 } else {
3901 tbits = 0;
3902 }
3903 if (diff >= 0) {
3904 if (diff <= 33554431) {
3905 diff >>= 2;
3906 ins = (ins & 0xff000000) | diff;
3907 ins &= tmask;
3908 *code32 = ins | tbits;
3909 return;
3910 }
3911 } else {
3912 /* diff between 0 and -33554432 */
3913 if (diff >= -33554432) {
3914 diff >>= 2;
3915 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3916 ins &= tmask;
3917 *code32 = ins | tbits;
3918 return;
3919 }
3920 }
3921
3922 handle_thunk (cfg, domain, code, target);
3923 return;
3924 }
3925
3926 #ifdef USE_JUMP_TABLES
3927 {
3928 gpointer *jte = mono_jumptable_get_entry (code);
3929 g_assert (jte);
3930 jte [0] = (gpointer) target;
3931 }
3932 #else
3933 /*
3934 * The alternative call sequences looks like this:
3935 *
3936 * ldr ip, [pc] // loads the address constant
3937 * b 1f // jumps around the constant
3938 * address constant embedded in the code
3939 * 1f:
3940 * mov lr, pc
3941 * mov pc, ip
3942 *
3943 * There are two cases for patching:
3944 * a) at the end of method emission: in this case code points to the start
3945 * of the call sequence
3946 * b) during runtime patching of the call site: in this case code points
3947 * to the mov pc, ip instruction
3948 *
3949 * We have to handle also the thunk jump code sequence:
3950 *
3951 * ldr ip, [pc]
3952 * mov pc, ip
3953 * address constant // execution never reaches here
3954 */
3955 if ((ins & 0x0ffffff0) == 0x12fff10) {
3956 /* Branch and exchange: the address is constructed in a reg
3957 * We can patch BX when the code sequence is the following:
3958 * ldr ip, [pc, #0] ; 0x8
3959 * b 0xc
3960 * .word code_ptr
3961 * mov lr, pc
3962 * bx ips
3963 * */
3964 guint32 ccode [4];
3965 guint8 *emit = (guint8*)ccode;
3966 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3967 ARM_B (emit, 0);
3968 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3969 ARM_BX (emit, ARMREG_IP);
3970
3971 /*patching from magic trampoline*/
3972 if (ins == ccode [3]) {
3973 g_assert (code32 [-4] == ccode [0]);
3974 g_assert (code32 [-3] == ccode [1]);
3975 g_assert (code32 [-1] == ccode [2]);
3976 code32 [-2] = (guint32)target;
3977 return;
3978 }
3979 /*patching from JIT*/
3980 if (ins == ccode [0]) {
3981 g_assert (code32 [1] == ccode [1]);
3982 g_assert (code32 [3] == ccode [2]);
3983 g_assert (code32 [4] == ccode [3]);
3984 code32 [2] = (guint32)target;
3985 return;
3986 }
3987 g_assert_not_reached ();
3988 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3989 /*
3990 * ldr ip, [pc, #0]
3991 * b 0xc
3992 * .word code_ptr
3993 * blx ip
3994 */
3995 guint32 ccode [4];
3996 guint8 *emit = (guint8*)ccode;
3997 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3998 ARM_B (emit, 0);
3999 ARM_BLX_REG (emit, ARMREG_IP);
4000
4001 g_assert (code32 [-3] == ccode [0]);
4002 g_assert (code32 [-2] == ccode [1]);
4003 g_assert (code32 [0] == ccode [2]);
4004
4005 code32 [-1] = (guint32)target;
4006 } else {
4007 guint32 ccode [4];
4008 guint32 *tmp = ccode;
4009 guint8 *emit = (guint8*)tmp;
4010 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4011 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4012 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4013 ARM_BX (emit, ARMREG_IP);
4014 if (ins == ccode [2]) {
4015 g_assert_not_reached (); // should be -2 ...
4016 code32 [-1] = (guint32)target;
4017 return;
4018 }
4019 if (ins == ccode [0]) {
4020 /* handles both thunk jump code and the far call sequence */
4021 code32 [2] = (guint32)target;
4022 return;
4023 }
4024 g_assert_not_reached ();
4025 }
4026 // g_print ("patched with 0x%08x\n", ins);
4027 #endif
4028 }
4029
4030 void
4031 arm_patch (guchar *code, const guchar *target)
4032 {
4033 arm_patch_general (NULL, NULL, code, target);
4034 }
4035
4036 /*
4037 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4038 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4039 * to be used with the emit macros.
4040 * Return -1 otherwise.
4041 */
4042 int
4043 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4044 {
4045 guint32 res, i;
4046 for (i = 0; i < 31; i+= 2) {
4047 res = (val << (32 - i)) | (val >> i);
4048 if (res & ~0xff)
4049 continue;
4050 *rot_amount = i? 32 - i: 0;
4051 return res;
4052 }
4053 return -1;
4054 }
4055
4056 /*
4057 * Emits in code a sequence of instructions that load the value 'val'
4058 * into the dreg register. Uses at most 4 instructions.
4059 */
4060 guint8*
4061 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4062 {
4063 int imm8, rot_amount;
4064 #if 0
4065 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4066 /* skip the constant pool */
4067 ARM_B (code, 0);
4068 *(int*)code = val;
4069 code += 4;
4070 return code;
4071 #endif
4072 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4073 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4074 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4075 return code;
4076 }
4077
4078 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4079 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4080 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4081 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4082 } else {
4083 if (v7_supported) {
4084 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4085 if (val >> 16)
4086 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4087 return code;
4088 }
4089 if (val & 0xFF) {
4090 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4091 if (val & 0xFF00) {
4092 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4093 }
4094 if (val & 0xFF0000) {
4095 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4096 }
4097 if (val & 0xFF000000) {
4098 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4099 }
4100 } else if (val & 0xFF00) {
4101 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4102 if (val & 0xFF0000) {
4103 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4104 }
4105 if (val & 0xFF000000) {
4106 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4107 }
4108 } else if (val & 0xFF0000) {
4109 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4110 if (val & 0xFF000000) {
4111 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4112 }
4113 }
4114 //g_assert_not_reached ();
4115 }
4116 return code;
4117 }
4118
4119 gboolean
4120 mono_arm_thumb_supported (void)
4121 {
4122 return thumb_supported;
4123 }
4124
4125 #ifndef DISABLE_JIT
4126
4127 static guint8*
4128 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4129 {
4130 CallInfo *cinfo;
4131 MonoCallInst *call;
4132
4133 call = (MonoCallInst*)ins;
4134 cinfo = call->call_info;
4135
4136 switch (cinfo->ret.storage) {
4137 case RegTypeHFA: {
4138 MonoInst *loc = cfg->arch.vret_addr_loc;
4139 int i;
4140
4141 /* Load the destination address */
4142 g_assert (loc && loc->opcode == OP_REGOFFSET);
4143
4144 if (arm_is_imm12 (loc->inst_offset)) {
4145 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4146 } else {
4147 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4148 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4149 }
4150 for (i = 0; i < cinfo->ret.nregs; ++i) {
4151 if (cinfo->ret.esize == 4)
4152 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4153 else
4154 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4155 }
4156 return code;
4157 }
4158 default:
4159 break;
4160 }
4161
4162 switch (ins->opcode) {
4163 case OP_FCALL:
4164 case OP_FCALL_REG:
4165 case OP_FCALL_MEMBASE:
4166 if (IS_VFP) {
4167 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4168 if (sig_ret->type == MONO_TYPE_R4) {
4169 if (IS_HARD_FLOAT) {
4170 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4171 } else {
4172 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4173 ARM_CVTS (code, ins->dreg, ins->dreg);
4174 }
4175 } else {
4176 if (IS_HARD_FLOAT) {
4177 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4178 } else {
4179 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4180 }
4181 }
4182 }
4183 break;
4184 case OP_RCALL:
4185 case OP_RCALL_REG:
4186 case OP_RCALL_MEMBASE: {
4187 MonoType *sig_ret;
4188
4189 g_assert (IS_VFP);
4190
4191 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4192 g_assert (sig_ret->type == MONO_TYPE_R4);
4193 if (IS_HARD_FLOAT) {
4194 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4195 } else {
4196 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4197 ARM_CPYS (code, ins->dreg, ins->dreg);
4198 }
4199 break;
4200 }
4201 default:
4202 break;
4203 }
4204
4205 return code;
4206 }
4207
4208 void
4209 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4210 {
4211 MonoInst *ins;
4212 MonoCallInst *call;
4213 guint offset;
4214 guint8 *code = cfg->native_code + cfg->code_len;
4215 MonoInst *last_ins = NULL;
4216 guint last_offset = 0;
4217 int max_len, cpos;
4218 int imm8, rot_amount;
4219
4220 /* we don't align basic blocks of loops on arm */
4221
4222 if (cfg->verbose_level > 2)
4223 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4224
4225 cpos = bb->max_offset;
4226
4227 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4228 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4229 //g_assert (!mono_compile_aot);
4230 //cpos += 6;
4231 //if (bb->cil_code)
4232 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4233 /* this is not thread save, but good enough */
4234 /* fixme: howto handle overflows? */
4235 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4236 }
4237
4238 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4239 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4240 (gpointer)"mono_break");
4241 code = emit_call_seq (cfg, code);
4242 }
4243
4244 MONO_BB_FOR_EACH_INS (bb, ins) {
4245 offset = code - cfg->native_code;
4246
4247 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4248
4249 if (offset > (cfg->code_size - max_len - 16)) {
4250 cfg->code_size *= 2;
4251 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4252 code = cfg->native_code + offset;
4253 }
4254 // if (ins->cil_code)
4255 // g_print ("cil code\n");
4256 mono_debug_record_line_number (cfg, ins, offset);
4257
4258 switch (ins->opcode) {
4259 case OP_MEMORY_BARRIER:
4260 if (v6_supported) {
4261 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4262 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4263 }
4264 break;
4265 case OP_TLS_GET:
4266 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4267 break;
4268 case OP_TLS_GET_REG:
4269 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4270 break;
4271 case OP_TLS_SET:
4272 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4273 break;
4274 case OP_TLS_SET_REG:
4275 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4276 break;
4277 case OP_ATOMIC_EXCHANGE_I4:
4278 case OP_ATOMIC_CAS_I4:
4279 case OP_ATOMIC_ADD_I4: {
4280 int tmpreg;
4281 guint8 *buf [16];
4282
4283 g_assert (v7_supported);
4284
4285 /* Free up a reg */
4286 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4287 tmpreg = ARMREG_IP;
4288 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4289 tmpreg = ARMREG_R0;
4290 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4291 tmpreg = ARMREG_R1;
4292 else
4293 tmpreg = ARMREG_R2;
4294 g_assert (cfg->arch.atomic_tmp_offset != -1);
4295 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4296
4297 switch (ins->opcode) {
4298 case OP_ATOMIC_EXCHANGE_I4:
4299 buf [0] = code;
4300 ARM_DMB (code, ARM_DMB_SY);
4301 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4302 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4303 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4304 buf [1] = code;
4305 ARM_B_COND (code, ARMCOND_NE, 0);
4306 arm_patch (buf [1], buf [0]);
4307 break;
4308 case OP_ATOMIC_CAS_I4:
4309 ARM_DMB (code, ARM_DMB_SY);
4310 buf [0] = code;
4311 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4312 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4313 buf [1] = code;
4314 ARM_B_COND (code, ARMCOND_NE, 0);
4315 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4316 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4317 buf [2] = code;
4318 ARM_B_COND (code, ARMCOND_NE, 0);
4319 arm_patch (buf [2], buf [0]);
4320 arm_patch (buf [1], code);
4321 break;
4322 case OP_ATOMIC_ADD_I4:
4323 buf [0] = code;
4324 ARM_DMB (code, ARM_DMB_SY);
4325 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4326 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4327 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4328 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4329 buf [1] = code;
4330 ARM_B_COND (code, ARMCOND_NE, 0);
4331 arm_patch (buf [1], buf [0]);
4332 break;
4333 default:
4334 g_assert_not_reached ();
4335 }
4336
4337 ARM_DMB (code, ARM_DMB_SY);
4338 if (tmpreg != ins->dreg)
4339 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4340 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4341 break;
4342 }
4343 case OP_ATOMIC_LOAD_I1:
4344 case OP_ATOMIC_LOAD_U1:
4345 case OP_ATOMIC_LOAD_I2:
4346 case OP_ATOMIC_LOAD_U2:
4347 case OP_ATOMIC_LOAD_I4:
4348 case OP_ATOMIC_LOAD_U4:
4349 case OP_ATOMIC_LOAD_R4:
4350 case OP_ATOMIC_LOAD_R8: {
4351 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4352 ARM_DMB (code, ARM_DMB_SY);
4353
4354 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4355
4356 switch (ins->opcode) {
4357 case OP_ATOMIC_LOAD_I1:
4358 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4359 break;
4360 case OP_ATOMIC_LOAD_U1:
4361 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4362 break;
4363 case OP_ATOMIC_LOAD_I2:
4364 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4365 break;
4366 case OP_ATOMIC_LOAD_U2:
4367 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4368 break;
4369 case OP_ATOMIC_LOAD_I4:
4370 case OP_ATOMIC_LOAD_U4:
4371 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4372 break;
4373 case OP_ATOMIC_LOAD_R4:
4374 if (cfg->r4fp) {
4375 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4376 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4377 } else {
4378 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4379 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4380 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4381 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4382 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4383 }
4384 break;
4385 case OP_ATOMIC_LOAD_R8:
4386 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4387 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4388 break;
4389 }
4390
4391 ARM_DMB (code, ARM_DMB_SY);
4392 break;
4393 }
4394 case OP_ATOMIC_STORE_I1:
4395 case OP_ATOMIC_STORE_U1:
4396 case OP_ATOMIC_STORE_I2:
4397 case OP_ATOMIC_STORE_U2:
4398 case OP_ATOMIC_STORE_I4:
4399 case OP_ATOMIC_STORE_U4:
4400 case OP_ATOMIC_STORE_R4:
4401 case OP_ATOMIC_STORE_R8: {
4402 ARM_DMB (code, ARM_DMB_SY);
4403
4404 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4405
4406 switch (ins->opcode) {
4407 case OP_ATOMIC_STORE_I1:
4408 case OP_ATOMIC_STORE_U1:
4409 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4410 break;
4411 case OP_ATOMIC_STORE_I2:
4412 case OP_ATOMIC_STORE_U2:
4413 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4414 break;
4415 case OP_ATOMIC_STORE_I4:
4416 case OP_ATOMIC_STORE_U4:
4417 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4418 break;
4419 case OP_ATOMIC_STORE_R4:
4420 if (cfg->r4fp) {
4421 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4422 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4423 } else {
4424 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4425 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4426 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4427 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4428 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4429 }
4430 break;
4431 case OP_ATOMIC_STORE_R8:
4432 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4433 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4434 break;
4435 }
4436
4437 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4438 ARM_DMB (code, ARM_DMB_SY);
4439 break;
4440 }
4441 /*case OP_BIGMUL:
4442 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4443 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4444 break;
4445 case OP_BIGMUL_UN:
4446 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4447 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4448 break;*/
4449 case OP_STOREI1_MEMBASE_IMM:
4450 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4451 g_assert (arm_is_imm12 (ins->inst_offset));
4452 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4453 break;
4454 case OP_STOREI2_MEMBASE_IMM:
4455 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4456 g_assert (arm_is_imm8 (ins->inst_offset));
4457 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4458 break;
4459 case OP_STORE_MEMBASE_IMM:
4460 case OP_STOREI4_MEMBASE_IMM:
4461 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4462 g_assert (arm_is_imm12 (ins->inst_offset));
4463 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4464 break;
4465 case OP_STOREI1_MEMBASE_REG:
4466 g_assert (arm_is_imm12 (ins->inst_offset));
4467 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4468 break;
4469 case OP_STOREI2_MEMBASE_REG:
4470 g_assert (arm_is_imm8 (ins->inst_offset));
4471 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4472 break;
4473 case OP_STORE_MEMBASE_REG:
4474 case OP_STOREI4_MEMBASE_REG:
4475 /* this case is special, since it happens for spill code after lowering has been called */
4476 if (arm_is_imm12 (ins->inst_offset)) {
4477 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4478 } else {
4479 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4480 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4481 }
4482 break;
4483 case OP_STOREI1_MEMINDEX:
4484 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4485 break;
4486 case OP_STOREI2_MEMINDEX:
4487 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4488 break;
4489 case OP_STORE_MEMINDEX:
4490 case OP_STOREI4_MEMINDEX:
4491 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4492 break;
4493 case OP_LOADU4_MEM:
4494 g_assert_not_reached ();
4495 break;
4496 case OP_LOAD_MEMINDEX:
4497 case OP_LOADI4_MEMINDEX:
4498 case OP_LOADU4_MEMINDEX:
4499 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4500 break;
4501 case OP_LOADI1_MEMINDEX:
4502 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4503 break;
4504 case OP_LOADU1_MEMINDEX:
4505 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4506 break;
4507 case OP_LOADI2_MEMINDEX:
4508 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4509 break;
4510 case OP_LOADU2_MEMINDEX:
4511 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4512 break;
4513 case OP_LOAD_MEMBASE:
4514 case OP_LOADI4_MEMBASE:
4515 case OP_LOADU4_MEMBASE:
4516 /* this case is special, since it happens for spill code after lowering has been called */
4517 if (arm_is_imm12 (ins->inst_offset)) {
4518 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4519 } else {
4520 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4521 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4522 }
4523 break;
4524 case OP_LOADI1_MEMBASE:
4525 g_assert (arm_is_imm8 (ins->inst_offset));
4526 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4527 break;
4528 case OP_LOADU1_MEMBASE:
4529 g_assert (arm_is_imm12 (ins->inst_offset));
4530 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4531 break;
4532 case OP_LOADU2_MEMBASE:
4533 g_assert (arm_is_imm8 (ins->inst_offset));
4534 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4535 break;
4536 case OP_LOADI2_MEMBASE:
4537 g_assert (arm_is_imm8 (ins->inst_offset));
4538 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4539 break;
4540 case OP_ICONV_TO_I1:
4541 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4542 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4543 break;
4544 case OP_ICONV_TO_I2:
4545 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4546 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4547 break;
4548 case OP_ICONV_TO_U1:
4549 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4550 break;
4551 case OP_ICONV_TO_U2:
4552 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4553 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4554 break;
4555 case OP_COMPARE:
4556 case OP_ICOMPARE:
4557 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4558 break;
4559 case OP_COMPARE_IMM:
4560 case OP_ICOMPARE_IMM:
4561 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4562 g_assert (imm8 >= 0);
4563 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4564 break;
4565 case OP_BREAK:
4566 /*
4567 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4568 * So instead of emitting a trap, we emit a call a C function and place a
4569 * breakpoint there.
4570 */
4571 //*(int*)code = 0xef9f0001;
4572 //code += 4;
4573 //ARM_DBRK (code);
4574 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4575 (gpointer)"mono_break");
4576 code = emit_call_seq (cfg, code);
4577 break;
4578 case OP_RELAXED_NOP:
4579 ARM_NOP (code);
4580 break;
4581 case OP_NOP:
4582 case OP_DUMMY_USE:
4583 case OP_DUMMY_STORE:
4584 case OP_DUMMY_ICONST:
4585 case OP_DUMMY_R8CONST:
4586 case OP_NOT_REACHED:
4587 case OP_NOT_NULL:
4588 break;
4589 case OP_IL_SEQ_POINT:
4590 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4591 break;
4592 case OP_SEQ_POINT: {
4593 int i;
4594 MonoInst *info_var = cfg->arch.seq_point_info_var;
4595 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4596 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4597 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4598 MonoInst *var;
4599 int dreg = ARMREG_LR;
4600
4601 if (cfg->soft_breakpoints) {
4602 g_assert (!cfg->compile_aot);
4603 }
4604
4605 /*
4606 * For AOT, we use one got slot per method, which will point to a
4607 * SeqPointInfo structure, containing all the information required
4608 * by the code below.
4609 */
4610 if (cfg->compile_aot) {
4611 g_assert (info_var);
4612 g_assert (info_var->opcode == OP_REGOFFSET);
4613 g_assert (arm_is_imm12 (info_var->inst_offset));
4614 }
4615
4616 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4617 /*
4618 * Read from the single stepping trigger page. This will cause a
4619 * SIGSEGV when single stepping is enabled.
4620 * We do this _before_ the breakpoint, so single stepping after
4621 * a breakpoint is hit will step to the next IL offset.
4622 */
4623 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4624 }
4625
4626 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4627 if (cfg->soft_breakpoints) {
4628 /* Load the address of the sequence point method variable. */
4629 var = ss_method_var;
4630 g_assert (var);
4631 g_assert (var->opcode == OP_REGOFFSET);
4632 g_assert (arm_is_imm12 (var->inst_offset));
4633 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4634
4635 /* Read the value and check whether it is non-zero. */
4636 ARM_LDR_IMM (code, dreg, dreg, 0);
4637 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4638 /* Call it conditionally. */
4639 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4640 } else {
4641 if (cfg->compile_aot) {
4642 /* Load the trigger page addr from the variable initialized in the prolog */
4643 var = ss_trigger_page_var;
4644 g_assert (var);
4645 g_assert (var->opcode == OP_REGOFFSET);
4646 g_assert (arm_is_imm12 (var->inst_offset));
4647 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4648 } else {
4649 #ifdef USE_JUMP_TABLES
4650 gpointer *jte = mono_jumptable_add_entry ();
4651 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4652 jte [0] = ss_trigger_page;
4653 #else
4654 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4655 ARM_B (code, 0);
4656 *(int*)code = (int)ss_trigger_page;
4657 code += 4;
4658 #endif
4659 }
4660 ARM_LDR_IMM (code, dreg, dreg, 0);
4661 }
4662 }
4663
4664 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4665
4666 if (cfg->soft_breakpoints) {
4667 /* Load the address of the breakpoint method into ip. */
4668 var = bp_method_var;
4669 g_assert (var);
4670 g_assert (var->opcode == OP_REGOFFSET);
4671 g_assert (arm_is_imm12 (var->inst_offset));
4672 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4673
4674 /*
4675 * A placeholder for a possible breakpoint inserted by
4676 * mono_arch_set_breakpoint ().
4677 */
4678 ARM_NOP (code);
4679 } else if (cfg->compile_aot) {
4680 guint32 offset = code - cfg->native_code;
4681 guint32 val;
4682
4683 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4684 /* Add the offset */
4685 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4686 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4687 if (arm_is_imm12 ((int)val)) {
4688 ARM_LDR_IMM (code, dreg, dreg, val);
4689 } else {
4690 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4691 if (val & 0xFF00)
4692 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4693 if (val & 0xFF0000)
4694 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4695 g_assert (!(val & 0xFF000000));
4696
4697 ARM_LDR_IMM (code, dreg, dreg, 0);
4698 }
4699 /* What is faster, a branch or a load ? */
4700 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4701 /* The breakpoint instruction */
4702 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4703 } else {
4704 /*
4705 * A placeholder for a possible breakpoint inserted by
4706 * mono_arch_set_breakpoint ().
4707 */
4708 for (i = 0; i < 4; ++i)
4709 ARM_NOP (code);
4710 }
4711
4712 /*
4713 * Add an additional nop so skipping the bp doesn't cause the ip to point
4714 * to another IL offset.
4715 */
4716
4717 ARM_NOP (code);
4718 break;
4719 }
4720 case OP_ADDCC:
4721 case OP_IADDCC:
4722 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 break;
4724 case OP_IADD:
4725 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 break;
4727 case OP_ADC:
4728 case OP_IADC:
4729 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 break;
4731 case OP_ADDCC_IMM:
4732 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4733 g_assert (imm8 >= 0);
4734 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4735 break;
4736 case OP_ADD_IMM:
4737 case OP_IADD_IMM:
4738 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4739 g_assert (imm8 >= 0);
4740 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4741 break;
4742 case OP_ADC_IMM:
4743 case OP_IADC_IMM:
4744 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4745 g_assert (imm8 >= 0);
4746 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 break;
4748 case OP_IADD_OVF:
4749 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4751 break;
4752 case OP_IADD_OVF_UN:
4753 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4754 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4755 break;
4756 case OP_ISUB_OVF:
4757 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4759 break;
4760 case OP_ISUB_OVF_UN:
4761 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4762 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4763 break;
4764 case OP_ADD_OVF_CARRY:
4765 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4766 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4767 break;
4768 case OP_ADD_OVF_UN_CARRY:
4769 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4770 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4771 break;
4772 case OP_SUB_OVF_CARRY:
4773 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4774 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4775 break;
4776 case OP_SUB_OVF_UN_CARRY:
4777 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4779 break;
4780 case OP_SUBCC:
4781 case OP_ISUBCC:
4782 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4783 break;
4784 case OP_SUBCC_IMM:
4785 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4786 g_assert (imm8 >= 0);
4787 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4788 break;
4789 case OP_ISUB:
4790 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 break;
4792 case OP_SBB:
4793 case OP_ISBB:
4794 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4795 break;
4796 case OP_SUB_IMM:
4797 case OP_ISUB_IMM:
4798 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4799 g_assert (imm8 >= 0);
4800 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4801 break;
4802 case OP_SBB_IMM:
4803 case OP_ISBB_IMM:
4804 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4805 g_assert (imm8 >= 0);
4806 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4807 break;
4808 case OP_ARM_RSBS_IMM:
4809 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4810 g_assert (imm8 >= 0);
4811 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4812 break;
4813 case OP_ARM_RSC_IMM:
4814 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4815 g_assert (imm8 >= 0);
4816 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4817 break;
4818 case OP_IAND:
4819 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 break;
4821 case OP_AND_IMM:
4822 case OP_IAND_IMM:
4823 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4824 g_assert (imm8 >= 0);
4825 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4826 break;
4827 case OP_IDIV:
4828 g_assert (v7s_supported || v7k_supported);
4829 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4830 break;
4831 case OP_IDIV_UN:
4832 g_assert (v7s_supported || v7k_supported);
4833 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 break;
4835 case OP_IREM:
4836 g_assert (v7s_supported || v7k_supported);
4837 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4838 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4839 break;
4840 case OP_IREM_UN:
4841 g_assert (v7s_supported || v7k_supported);
4842 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4843 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4844 break;
4845 case OP_DIV_IMM:
4846 case OP_REM_IMM:
4847 g_assert_not_reached ();
4848 case OP_IOR:
4849 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 break;
4851 case OP_OR_IMM:
4852 case OP_IOR_IMM:
4853 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4854 g_assert (imm8 >= 0);
4855 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4856 break;
4857 case OP_IXOR:
4858 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 break;
4860 case OP_XOR_IMM:
4861 case OP_IXOR_IMM:
4862 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4863 g_assert (imm8 >= 0);
4864 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4865 break;
4866 case OP_ISHL:
4867 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4868 break;
4869 case OP_SHL_IMM:
4870 case OP_ISHL_IMM:
4871 if (ins->inst_imm)
4872 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4873 else if (ins->dreg != ins->sreg1)
4874 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4875 break;
4876 case OP_ISHR:
4877 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4878 break;
4879 case OP_SHR_IMM:
4880 case OP_ISHR_IMM:
4881 if (ins->inst_imm)
4882 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4883 else if (ins->dreg != ins->sreg1)
4884 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4885 break;
4886 case OP_SHR_UN_IMM:
4887 case OP_ISHR_UN_IMM:
4888 if (ins->inst_imm)
4889 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4890 else if (ins->dreg != ins->sreg1)
4891 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4892 break;
4893 case OP_ISHR_UN:
4894 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4895 break;
4896 case OP_INOT:
4897 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4898 break;
4899 case OP_INEG:
4900 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4901 break;
4902 case OP_IMUL:
4903 if (ins->dreg == ins->sreg2)
4904 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4905 else
4906 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4907 break;
4908 case OP_MUL_IMM:
4909 g_assert_not_reached ();
4910 break;
4911 case OP_IMUL_OVF:
4912 /* FIXME: handle ovf/ sreg2 != dreg */
4913 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4914 /* FIXME: MUL doesn't set the C/O flags on ARM */
4915 break;
4916 case OP_IMUL_OVF_UN:
4917 /* FIXME: handle ovf/ sreg2 != dreg */
4918 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4919 /* FIXME: MUL doesn't set the C/O flags on ARM */
4920 break;
4921 case OP_ICONST:
4922 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4923 break;
4924 case OP_AOTCONST:
4925 /* Load the GOT offset */
4926 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4927 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4928 ARM_B (code, 0);
4929 *(gpointer*)code = NULL;
4930 code += 4;
4931 /* Load the value from the GOT */
4932 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4933 break;
4934 case OP_OBJC_GET_SELECTOR:
4935 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4936 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4937 ARM_B (code, 0);
4938 *(gpointer*)code = NULL;
4939 code += 4;
4940 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4941 break;
4942 case OP_ICONV_TO_I4:
4943 case OP_ICONV_TO_U4:
4944 case OP_MOVE:
4945 if (ins->dreg != ins->sreg1)
4946 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4947 break;
4948 case OP_SETLRET: {
4949 int saved = ins->sreg2;
4950 if (ins->sreg2 == ARM_LSW_REG) {
4951 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4952 saved = ARMREG_LR;
4953 }
4954 if (ins->sreg1 != ARM_LSW_REG)
4955 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4956 if (saved != ARM_MSW_REG)
4957 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4958 break;
4959 }
4960 case OP_FMOVE:
4961 if (IS_VFP && ins->dreg != ins->sreg1)
4962 ARM_CPYD (code, ins->dreg, ins->sreg1);
4963 break;
4964 case OP_RMOVE:
4965 if (IS_VFP && ins->dreg != ins->sreg1)
4966 ARM_CPYS (code, ins->dreg, ins->sreg1);
4967 break;
4968 case OP_MOVE_F_TO_I4:
4969 if (cfg->r4fp) {
4970 ARM_FMRS (code, ins->dreg, ins->sreg1);
4971 } else {
4972 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4973 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4974 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4975 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4976 }
4977 break;
4978 case OP_MOVE_I4_TO_F:
4979 if (cfg->r4fp) {
4980 ARM_FMSR (code, ins->dreg, ins->sreg1);
4981 } else {
4982 ARM_FMSR (code, ins->dreg, ins->sreg1);
4983 ARM_CVTS (code, ins->dreg, ins->dreg);
4984 }
4985 break;
4986 case OP_FCONV_TO_R4:
4987 if (IS_VFP) {
4988 if (cfg->r4fp) {
4989 ARM_CVTD (code, ins->dreg, ins->sreg1);
4990 } else {
4991 ARM_CVTD (code, ins->dreg, ins->sreg1);
4992 ARM_CVTS (code, ins->dreg, ins->dreg);
4993 }
4994 }
4995 break;
4996 case OP_TAILCALL: {
4997 MonoCallInst *call = (MonoCallInst*)ins;
4998
4999 /*
5000 * The stack looks like the following:
5001 * <caller argument area>
5002 * <saved regs etc>
5003 * <rest of frame>
5004 * <callee argument area>
5005 * Need to copy the arguments from the callee argument area to
5006 * the caller argument area, and pop the frame.
5007 */
5008 if (call->stack_usage) {
5009 int i, prev_sp_offset = 0;
5010
5011 /* Compute size of saved registers restored below */
5012 if (iphone_abi)
5013 prev_sp_offset = 2 * 4;
5014 else
5015 prev_sp_offset = 1 * 4;
5016 for (i = 0; i < 16; ++i) {
5017 if (cfg->used_int_regs & (1 << i))
5018 prev_sp_offset += 4;
5019 }
5020
5021 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5022
5023 /* Copy arguments on the stack to our argument area */
5024 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5025 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5026 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5027 }
5028 }
5029
5030 /*
5031 * Keep in sync with mono_arch_emit_epilog
5032 */
5033 g_assert (!cfg->method->save_lmf);
5034
5035 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5036 if (iphone_abi) {
5037 if (cfg->used_int_regs)
5038 ARM_POP (code, cfg->used_int_regs);
5039 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5040 } else {
5041 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5042 }
5043
5044 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5045 if (cfg->compile_aot) {
5046 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5047 ARM_B (code, 0);
5048 *(gpointer*)code = NULL;
5049 code += 4;
5050 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5051 } else {
5052 code = mono_arm_patchable_b (code, ARMCOND_AL);
5053 cfg->thunk_area += THUNK_SIZE;
5054 }
5055 break;
5056 }
5057 case OP_CHECK_THIS:
5058 /* ensure ins->sreg1 is not NULL */
5059 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5060 break;
5061 case OP_ARGLIST: {
5062 g_assert (cfg->sig_cookie < 128);
5063 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5064 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5065 break;
5066 }
5067 case OP_FCALL:
5068 case OP_RCALL:
5069 case OP_LCALL:
5070 case OP_VCALL:
5071 case OP_VCALL2:
5072 case OP_VOIDCALL:
5073 case OP_CALL:
5074 call = (MonoCallInst*)ins;
5075
5076 if (IS_HARD_FLOAT)
5077 code = emit_float_args (cfg, call, code, &max_len, &offset);
5078
5079 if (ins->flags & MONO_INST_HAS_METHOD)
5080 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5081 else
5082 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5083 code = emit_call_seq (cfg, code);
5084 ins->flags |= MONO_INST_GC_CALLSITE;
5085 ins->backend.pc_offset = code - cfg->native_code;
5086 code = emit_move_return_value (cfg, ins, code);
5087 break;
5088 case OP_FCALL_REG:
5089 case OP_RCALL_REG:
5090 case OP_LCALL_REG:
5091 case OP_VCALL_REG:
5092 case OP_VCALL2_REG:
5093 case OP_VOIDCALL_REG:
5094 case OP_CALL_REG:
5095 if (IS_HARD_FLOAT)
5096 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5097
5098 code = emit_call_reg (code, ins->sreg1);
5099 ins->flags |= MONO_INST_GC_CALLSITE;
5100 ins->backend.pc_offset = code - cfg->native_code;
5101 code = emit_move_return_value (cfg, ins, code);
5102 break;
5103 case OP_FCALL_MEMBASE:
5104 case OP_RCALL_MEMBASE:
5105 case OP_LCALL_MEMBASE:
5106 case OP_VCALL_MEMBASE:
5107 case OP_VCALL2_MEMBASE:
5108 case OP_VOIDCALL_MEMBASE:
5109 case OP_CALL_MEMBASE: {
5110 g_assert (ins->sreg1 != ARMREG_LR);
5111 call = (MonoCallInst*)ins;
5112
5113 if (IS_HARD_FLOAT)
5114 code = emit_float_args (cfg, call, code, &max_len, &offset);
5115 if (!arm_is_imm12 (ins->inst_offset)) {
5116 /* sreg1 might be IP */
5117 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5118 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5119 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5120 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5121 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5122 } else {
5123 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5124 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5125 }
5126 ins->flags |= MONO_INST_GC_CALLSITE;
5127 ins->backend.pc_offset = code - cfg->native_code;
5128 code = emit_move_return_value (cfg, ins, code);
5129 break;
5130 }
5131 case OP_GENERIC_CLASS_INIT: {
5132 static int byte_offset = -1;
5133 static guint8 bitmask;
5134 guint32 imm8;
5135 guint8 *jump;
5136
5137 if (byte_offset < 0)
5138 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5139
5140 g_assert (arm_is_imm8 (byte_offset));
5141 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5142 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5143 g_assert (imm8 >= 0);
5144 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5145 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5146 jump = code;
5147 ARM_B_COND (code, ARMCOND_NE, 0);
5148
5149 /* Uninitialized case */
5150 g_assert (ins->sreg1 == ARMREG_R0);
5151
5152 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5153 (gpointer)"mono_generic_class_init");
5154 code = emit_call_seq (cfg, code);
5155
5156 /* Initialized case */
5157 arm_patch (jump, code);
5158 break;
5159 }
5160 case OP_LOCALLOC: {
5161 /* round the size to 8 bytes */
5162 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5163 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5164 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5165 /* memzero the area: dreg holds the size, sp is the pointer */
5166 if (ins->flags & MONO_INST_INIT) {
5167 guint8 *start_loop, *branch_to_cond;
5168 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5169 branch_to_cond = code;
5170 ARM_B (code, 0);
5171 start_loop = code;
5172 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5173 arm_patch (branch_to_cond, code);
5174 /* decrement by 4 and set flags */
5175 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5176 ARM_B_COND (code, ARMCOND_GE, 0);
5177 arm_patch (code - 4, start_loop);
5178 }
5179 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5180 if (cfg->param_area)
5181 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5182 break;
5183 }
5184 case OP_DYN_CALL: {
5185 int i;
5186 MonoInst *var = cfg->dyn_call_var;
5187
5188 g_assert (var->opcode == OP_REGOFFSET);
5189 g_assert (arm_is_imm12 (var->inst_offset));
5190
5191 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5192 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5193 /* ip = ftn */
5194 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5195
5196 /* Save args buffer */
5197 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5198
5199 /* Set stack slots using R0 as scratch reg */
5200 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5201 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5202 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5203 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5204 }
5205
5206 /* Set argument registers */
5207 for (i = 0; i < PARAM_REGS; ++i)
5208 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5209
5210 /* Make the call */
5211 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5212 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5213
5214 /* Save result */
5215 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5216 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5217 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5218 break;
5219 }
5220 case OP_THROW: {
5221 if (ins->sreg1 != ARMREG_R0)
5222 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5223 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5224 (gpointer)"mono_arch_throw_exception");
5225 code = emit_call_seq (cfg, code);
5226 break;
5227 }
5228 case OP_RETHROW: {
5229 if (ins->sreg1 != ARMREG_R0)
5230 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5231 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5232 (gpointer)"mono_arch_rethrow_exception");
5233 code = emit_call_seq (cfg, code);
5234 break;
5235 }
5236 case OP_START_HANDLER: {
5237 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5238 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5239 int i, rot_amount;
5240
5241 /* Reserve a param area, see filter-stack.exe */
5242 if (param_area) {
5243 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5244 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5245 } else {
5246 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5247 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5248 }
5249 }
5250
5251 if (arm_is_imm12 (spvar->inst_offset)) {
5252 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5253 } else {
5254 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5255 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5256 }
5257 break;
5258 }
5259 case OP_ENDFILTER: {
5260 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5261 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5262 int i, rot_amount;
5263
5264 /* Free the param area */
5265 if (param_area) {
5266 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5267 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5268 } else {
5269 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5270 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5271 }
5272 }
5273
5274 if (ins->sreg1 != ARMREG_R0)
5275 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5276 if (arm_is_imm12 (spvar->inst_offset)) {
5277 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5278 } else {
5279 g_assert (ARMREG_IP != spvar->inst_basereg);
5280 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5281 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5282 }
5283 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5284 break;
5285 }
5286 case OP_ENDFINALLY: {
5287 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5288 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5289 int i, rot_amount;
5290
5291 /* Free the param area */
5292 if (param_area) {
5293 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5294 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5295 } else {
5296 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5297 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5298 }
5299 }
5300
5301 if (arm_is_imm12 (spvar->inst_offset)) {
5302 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5303 } else {
5304 g_assert (ARMREG_IP != spvar->inst_basereg);
5305 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5306 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5307 }
5308 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5309 break;
5310 }
5311 case OP_CALL_HANDLER:
5312 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5313 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5314 cfg->thunk_area += THUNK_SIZE;
5315 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5316 break;
5317 case OP_GET_EX_OBJ:
5318 if (ins->dreg != ARMREG_R0)
5319 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5320 break;
5321
5322 case OP_LABEL:
5323 ins->inst_c0 = code - cfg->native_code;
5324 break;
5325 case OP_BR:
5326 /*if (ins->inst_target_bb->native_offset) {
5327 ARM_B (code, 0);
5328 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5329 } else*/ {
5330 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5331 code = mono_arm_patchable_b (code, ARMCOND_AL);
5332 }
5333 break;
5334 case OP_BR_REG:
5335 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5336 break;
5337 case OP_SWITCH:
5338 /*
5339 * In the normal case we have:
5340 * ldr pc, [pc, ins->sreg1 << 2]
5341 * nop
5342 * If aot, we have:
5343 * ldr lr, [pc, ins->sreg1 << 2]
5344 * add pc, pc, lr
5345 * After follows the data.
5346 * FIXME: add aot support.
5347 */
5348 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5349 #ifdef USE_JUMP_TABLES
5350 {
5351 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5352 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5353 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5354 }
5355 #else
5356
5357 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5358 if (offset + max_len > (cfg->code_size - 16)) {
5359 cfg->code_size += max_len;
5360 cfg->code_size *= 2;
5361 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5362 code = cfg->native_code + offset;
5363 }
5364 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5365 ARM_NOP (code);
5366 code += 4 * GPOINTER_TO_INT (ins->klass);
5367 #endif
5368 break;
5369 case OP_CEQ:
5370 case OP_ICEQ:
5371 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5372 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5373 break;
5374 case OP_CLT:
5375 case OP_ICLT:
5376 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5377 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5378 break;
5379 case OP_CLT_UN:
5380 case OP_ICLT_UN:
5381 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5382 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5383 break;
5384 case OP_CGT:
5385 case OP_ICGT:
5386 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5387 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5388 break;
5389 case OP_CGT_UN:
5390 case OP_ICGT_UN:
5391 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5393 break;
5394 case OP_ICNEQ:
5395 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5396 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5397 break;
5398 case OP_ICGE:
5399 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5400 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5401 break;
5402 case OP_ICLE:
5403 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5404 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5405 break;
5406 case OP_ICGE_UN:
5407 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5408 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5409 break;
5410 case OP_ICLE_UN:
5411 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5412 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5413 break;
5414 case OP_COND_EXC_EQ:
5415 case OP_COND_EXC_NE_UN:
5416 case OP_COND_EXC_LT:
5417 case OP_COND_EXC_LT_UN:
5418 case OP_COND_EXC_GT:
5419 case OP_COND_EXC_GT_UN:
5420 case OP_COND_EXC_GE:
5421 case OP_COND_EXC_GE_UN:
5422 case OP_COND_EXC_LE:
5423 case OP_COND_EXC_LE_UN:
5424 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5425 break;
5426 case OP_COND_EXC_IEQ:
5427 case OP_COND_EXC_INE_UN:
5428 case OP_COND_EXC_ILT:
5429 case OP_COND_EXC_ILT_UN:
5430 case OP_COND_EXC_IGT:
5431 case OP_COND_EXC_IGT_UN:
5432 case OP_COND_EXC_IGE:
5433 case OP_COND_EXC_IGE_UN:
5434 case OP_COND_EXC_ILE:
5435 case OP_COND_EXC_ILE_UN:
5436 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5437 break;
5438 case OP_COND_EXC_C:
5439 case OP_COND_EXC_IC:
5440 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5441 break;
5442 case OP_COND_EXC_OV:
5443 case OP_COND_EXC_IOV:
5444 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5445 break;
5446 case OP_COND_EXC_NC:
5447 case OP_COND_EXC_INC:
5448 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5449 break;
5450 case OP_COND_EXC_NO:
5451 case OP_COND_EXC_INO:
5452 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5453 break;
5454 case OP_IBEQ:
5455 case OP_IBNE_UN:
5456 case OP_IBLT:
5457 case OP_IBLT_UN:
5458 case OP_IBGT:
5459 case OP_IBGT_UN:
5460 case OP_IBGE:
5461 case OP_IBGE_UN:
5462 case OP_IBLE:
5463 case OP_IBLE_UN:
5464 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5465 break;
5466
5467 /* floating point opcodes */
5468 case OP_R8CONST:
5469 if (cfg->compile_aot) {
5470 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5471 ARM_B (code, 1);
5472 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5473 code += 4;
5474 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5475 code += 4;
5476 } else {
5477 /* FIXME: we can optimize the imm load by dealing with part of
5478 * the displacement in LDFD (aligning to 512).
5479 */
5480 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5481 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5482 }
5483 break;
5484 case OP_R4CONST:
5485 if (cfg->compile_aot) {
5486 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5487 ARM_B (code, 0);
5488 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5489 code += 4;
5490 if (!cfg->r4fp)
5491 ARM_CVTS (code, ins->dreg, ins->dreg);
5492 } else {
5493 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5494 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5495 if (!cfg->r4fp)
5496 ARM_CVTS (code, ins->dreg, ins->dreg);
5497 }
5498 break;
5499 case OP_STORER8_MEMBASE_REG:
5500 /* This is generated by the local regalloc pass which runs after the lowering pass */
5501 if (!arm_is_fpimm8 (ins->inst_offset)) {
5502 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5503 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5504 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5505 } else {
5506 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5507 }
5508 break;
5509 case OP_LOADR8_MEMBASE:
5510 /* This is generated by the local regalloc pass which runs after the lowering pass */
5511 if (!arm_is_fpimm8 (ins->inst_offset)) {
5512 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5513 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5514 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5515 } else {
5516 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5517 }
5518 break;
5519 case OP_STORER4_MEMBASE_REG:
5520 g_assert (arm_is_fpimm8 (ins->inst_offset));
5521 if (cfg->r4fp) {
5522 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5523 } else {
5524 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5525 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5526 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5527 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5528 }
5529 break;
5530 case OP_LOADR4_MEMBASE:
5531 if (cfg->r4fp) {
5532 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5533 } else {
5534 g_assert (arm_is_fpimm8 (ins->inst_offset));
5535 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5536 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5537 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5538 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5539 }
5540 break;
5541 case OP_ICONV_TO_R_UN: {
5542 g_assert_not_reached ();
5543 break;
5544 }
5545 case OP_ICONV_TO_R4:
5546 if (cfg->r4fp) {
5547 ARM_FMSR (code, ins->dreg, ins->sreg1);
5548 ARM_FSITOS (code, ins->dreg, ins->dreg);
5549 } else {
5550 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5551 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5552 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5553 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5554 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5555 }
5556 break;
5557 case OP_ICONV_TO_R8:
5558 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5559 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5560 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5561 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5562 break;
5563
5564 case OP_SETFRET: {
5565 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5566 if (sig_ret->type == MONO_TYPE_R4) {
5567 if (cfg->r4fp) {
5568 g_assert (!IS_HARD_FLOAT);
5569 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5570 } else {
5571 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5572
5573 if (!IS_HARD_FLOAT)
5574 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5575 }
5576 } else {
5577 if (IS_HARD_FLOAT)
5578 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5579 else
5580 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5581 }
5582 break;
5583 }
5584 case OP_FCONV_TO_I1:
5585 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5586 break;
5587 case OP_FCONV_TO_U1:
5588 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5589 break;
5590 case OP_FCONV_TO_I2:
5591 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5592 break;
5593 case OP_FCONV_TO_U2:
5594 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5595 break;
5596 case OP_FCONV_TO_I4:
5597 case OP_FCONV_TO_I:
5598 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5599 break;
5600 case OP_FCONV_TO_U4:
5601 case OP_FCONV_TO_U:
5602 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5603 break;
5604 case OP_FCONV_TO_I8:
5605 case OP_FCONV_TO_U8:
5606 g_assert_not_reached ();
5607 /* Implemented as helper calls */
5608 break;
5609 case OP_LCONV_TO_R_UN:
5610 g_assert_not_reached ();
5611 /* Implemented as helper calls */
5612 break;
5613 case OP_LCONV_TO_OVF_I4_2: {
5614 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5615 /*
5616 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5617 */
5618
5619 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5620 high_bit_not_set = code;
5621 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5622
5623 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5624 valid_negative = code;
5625 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5626 invalid_negative = code;
5627 ARM_B_COND (code, ARMCOND_AL, 0);
5628
5629 arm_patch (high_bit_not_set, code);
5630
5631 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5632 valid_positive = code;
5633 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5634
5635 arm_patch (invalid_negative, code);
5636 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5637
5638 arm_patch (valid_negative, code);
5639 arm_patch (valid_positive, code);
5640
5641 if (ins->dreg != ins->sreg1)
5642 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5643 break;
5644 }
5645 case OP_FADD:
5646 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5647 break;
5648 case OP_FSUB:
5649 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5650 break;
5651 case OP_FMUL:
5652 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5653 break;
5654 case OP_FDIV:
5655 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5656 break;
5657 case OP_FNEG:
5658 ARM_NEGD (code, ins->dreg, ins->sreg1);
5659 break;
5660 case OP_FREM:
5661 /* emulated */
5662 g_assert_not_reached ();
5663 break;
5664 case OP_FCOMPARE:
5665 if (IS_VFP) {
5666 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5667 ARM_FMSTAT (code);
5668 }
5669 break;
5670 case OP_RCOMPARE:
5671 g_assert (IS_VFP);
5672 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5673 ARM_FMSTAT (code);
5674 break;
5675 case OP_FCEQ:
5676 if (IS_VFP) {
5677 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5678 ARM_FMSTAT (code);
5679 }
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5682 break;
5683 case OP_FCLT:
5684 if (IS_VFP) {
5685 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5686 ARM_FMSTAT (code);
5687 }
5688 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5689 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5690 break;
5691 case OP_FCLT_UN:
5692 if (IS_VFP) {
5693 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5694 ARM_FMSTAT (code);
5695 }
5696 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5697 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5698 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5699 break;
5700 case OP_FCGT:
5701 if (IS_VFP) {
5702 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5703 ARM_FMSTAT (code);
5704 }
5705 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5706 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5707 break;
5708 case OP_FCGT_UN:
5709 if (IS_VFP) {
5710 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5711 ARM_FMSTAT (code);
5712 }
5713 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5714 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5715 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5716 break;
5717 case OP_FCNEQ:
5718 if (IS_VFP) {
5719 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5720 ARM_FMSTAT (code);
5721 }
5722 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5723 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5724 break;
5725 case OP_FCGE:
5726 if (IS_VFP) {
5727 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5728 ARM_FMSTAT (code);
5729 }
5730 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5731 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5732 break;
5733 case OP_FCLE:
5734 if (IS_VFP) {
5735 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5736 ARM_FMSTAT (code);
5737 }
5738 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5739 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5740 break;
5741
5742 /* ARM FPA flags table:
5743 * N Less than ARMCOND_MI
5744 * Z Equal ARMCOND_EQ
5745 * C Greater Than or Equal ARMCOND_CS
5746 * V Unordered ARMCOND_VS
5747 */
5748 case OP_FBEQ:
5749 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5750 break;
5751 case OP_FBNE_UN:
5752 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5753 break;
5754 case OP_FBLT:
5755 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5756 break;
5757 case OP_FBLT_UN:
5758 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5759 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5760 break;
5761 case OP_FBGT:
5762 case OP_FBGT_UN:
5763 case OP_FBLE:
5764 case OP_FBLE_UN:
5765 g_assert_not_reached ();
5766 break;
5767 case OP_FBGE:
5768 if (IS_VFP) {
5769 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5770 } else {
5771 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5772 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5773 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5774 }
5775 break;
5776 case OP_FBGE_UN:
5777 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5778 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5779 break;
5780
5781 case OP_CKFINITE: {
5782 if (IS_VFP) {
5783 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5784 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5785
5786 #ifdef USE_JUMP_TABLES
5787 {
5788 gpointer *jte = mono_jumptable_add_entries (2);
5789 jte [0] = GUINT_TO_POINTER (0xffffffff);
5790 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5791 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5792 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5793 }
5794 #else
5795 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5796 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5797 ARM_B (code, 1);
5798 *(guint32*)code = 0xffffffff;
5799 code += 4;
5800 *(guint32*)code = 0x7fefffff;
5801 code += 4;
5802 #endif
5803 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5804 ARM_FMSTAT (code);
5805 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5806 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5807 ARM_FMSTAT (code);
5808 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5809 ARM_CPYD (code, ins->dreg, ins->sreg1);
5810
5811 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5812 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5813 }
5814 break;
5815 }
5816
5817 case OP_RCONV_TO_I1:
5818 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5819 break;
5820 case OP_RCONV_TO_U1:
5821 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5822 break;
5823 case OP_RCONV_TO_I2:
5824 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5825 break;
5826 case OP_RCONV_TO_U2:
5827 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5828 break;
5829 case OP_RCONV_TO_I4:
5830 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5831 break;
5832 case OP_RCONV_TO_U4:
5833 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5834 break;
5835 case OP_RCONV_TO_R4:
5836 g_assert (IS_VFP);
5837 if (ins->dreg != ins->sreg1)
5838 ARM_CPYS (code, ins->dreg, ins->sreg1);
5839 break;
5840 case OP_RCONV_TO_R8:
5841 g_assert (IS_VFP);
5842 ARM_CVTS (code, ins->dreg, ins->sreg1);
5843 break;
5844 case OP_RADD:
5845 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5846 break;
5847 case OP_RSUB:
5848 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5849 break;
5850 case OP_RMUL:
5851 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5852 break;
5853 case OP_RDIV:
5854 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5855 break;
5856 case OP_RNEG:
5857 ARM_NEGS (code, ins->dreg, ins->sreg1);
5858 break;
5859 case OP_RCEQ:
5860 if (IS_VFP) {
5861 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5862 ARM_FMSTAT (code);
5863 }
5864 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5865 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5866 break;
5867 case OP_RCLT:
5868 if (IS_VFP) {
5869 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5870 ARM_FMSTAT (code);
5871 }
5872 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5873 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5874 break;
5875 case OP_RCLT_UN:
5876 if (IS_VFP) {
5877 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5878 ARM_FMSTAT (code);
5879 }
5880 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5881 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5882 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5883 break;
5884 case OP_RCGT:
5885 if (IS_VFP) {
5886 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5887 ARM_FMSTAT (code);
5888 }
5889 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5890 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5891 break;
5892 case OP_RCGT_UN:
5893 if (IS_VFP) {
5894 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5895 ARM_FMSTAT (code);
5896 }
5897 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5898 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5899 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5900 break;
5901 case OP_RCNEQ:
5902 if (IS_VFP) {
5903 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5904 ARM_FMSTAT (code);
5905 }
5906 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5907 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5908 break;
5909 case OP_RCGE:
5910 if (IS_VFP) {
5911 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5912 ARM_FMSTAT (code);
5913 }
5914 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5915 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5916 break;
5917 case OP_RCLE:
5918 if (IS_VFP) {
5919 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5920 ARM_FMSTAT (code);
5921 }
5922 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5923 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5924 break;
5925
5926 case OP_GC_LIVENESS_DEF:
5927 case OP_GC_LIVENESS_USE:
5928 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5929 ins->backend.pc_offset = code - cfg->native_code;
5930 break;
5931 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5932 ins->backend.pc_offset = code - cfg->native_code;
5933 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5934 break;
5935 case OP_GC_SAFE_POINT: {
5936 const char *polling_func = NULL;
5937 guint8 *buf [1];
5938
5939 g_assert (mono_threads_is_coop_enabled ());
5940
5941 polling_func = "mono_threads_state_poll";
5942 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5943 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5944 buf [0] = code;
5945 ARM_B_COND (code, ARMCOND_EQ, 0);
5946 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5947 code = emit_call_seq (cfg, code);
5948 arm_patch (buf [0], code);
5949 break;
5950 }
5951
5952 default:
5953 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5954 g_assert_not_reached ();
5955 }
5956
5957 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5958 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5959 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5960 g_assert_not_reached ();
5961 }
5962
5963 cpos += max_len;
5964
5965 last_ins = ins;
5966 last_offset = offset;
5967 }
5968
5969 cfg->code_len = code - cfg->native_code;
5970 }
5971
5972 #endif /* DISABLE_JIT */
5973
5974 void
5975 mono_arch_register_lowlevel_calls (void)
5976 {
5977 /* The signature doesn't matter */
5978 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5979 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5980 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5981
5982 #ifndef MONO_CROSS_COMPILE
5983 if (mono_arm_have_tls_get ()) {
5984 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5985
5986 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5987 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5988
5989 if (tls_imp.get_tls_thunk_end) {
5990 mono_tramp_info_register (
5991 mono_tramp_info_create (
5992 "mono_get_tls_key",
5993 (guint8*)tls_imp.get_tls_thunk,
5994 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5995 NULL,
5996 mono_arch_get_cie_program ()
5997 ),
5998 NULL
5999 );
6000 mono_tramp_info_register (
6001 mono_tramp_info_create (
6002 "mono_set_tls_key",
6003 (guint8*)tls_imp.set_tls_thunk,
6004 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
6005 NULL,
6006 mono_arch_get_cie_program ()
6007 ),
6008 NULL
6009 );
6010 }
6011 }
6012 #endif
6013 }
6014
6015 #define patch_lis_ori(ip,val) do {\
6016 guint16 *__lis_ori = (guint16*)(ip); \
6017 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6018 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6019 } while (0)
6020
6021 void
6022 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6023 {
6024 unsigned char *ip = ji->ip.i + code;
6025
6026 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6027 }
6028
6029 switch (ji->type) {
6030 case MONO_PATCH_INFO_SWITCH: {
6031 #ifdef USE_JUMP_TABLES
6032 gpointer *jt = mono_jumptable_get_entry (ip);
6033 #else
6034 gpointer *jt = (gpointer*)(ip + 8);
6035 #endif
6036 int i;
6037 /* jt is the inlined jump table, 2 instructions after ip
6038 * In the normal case we store the absolute addresses,
6039 * otherwise the displacements.
6040 */
6041 for (i = 0; i < ji->data.table->table_size; i++)
6042 jt [i] = code + (int)ji->data.table->table [i];
6043 break;
6044 }
6045 case MONO_PATCH_INFO_IP:
6046 g_assert_not_reached ();
6047 patch_lis_ori (ip, ip);
6048 break;
6049 case MONO_PATCH_INFO_METHOD_REL:
6050 g_assert_not_reached ();
6051 *((gpointer *)(ip)) = target;
6052 break;
6053 case MONO_PATCH_INFO_METHODCONST:
6054 case MONO_PATCH_INFO_CLASS:
6055 case MONO_PATCH_INFO_IMAGE:
6056 case MONO_PATCH_INFO_FIELD:
6057 case MONO_PATCH_INFO_VTABLE:
6058 case MONO_PATCH_INFO_IID:
6059 case MONO_PATCH_INFO_SFLDA:
6060 case MONO_PATCH_INFO_LDSTR:
6061 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6062 case MONO_PATCH_INFO_LDTOKEN:
6063 g_assert_not_reached ();
6064 /* from OP_AOTCONST : lis + ori */
6065 patch_lis_ori (ip, target);
6066 break;
6067 case MONO_PATCH_INFO_R4:
6068 case MONO_PATCH_INFO_R8:
6069 g_assert_not_reached ();
6070 *((gconstpointer *)(ip + 2)) = target;
6071 break;
6072 case MONO_PATCH_INFO_EXC_NAME:
6073 g_assert_not_reached ();
6074 *((gconstpointer *)(ip + 1)) = target;
6075 break;
6076 case MONO_PATCH_INFO_NONE:
6077 case MONO_PATCH_INFO_BB_OVF:
6078 case MONO_PATCH_INFO_EXC_OVF:
6079 /* everything is dealt with at epilog output time */
6080 break;
6081 default:
6082 arm_patch_general (cfg, domain, ip, target);
6083 break;
6084 }
6085 }
6086
6087 void
6088 mono_arm_unaligned_stack (MonoMethod *method)
6089 {
6090 g_assert_not_reached ();
6091 }
6092
6093 #ifndef DISABLE_JIT
6094
6095 /*
6096 * Stack frame layout:
6097 *
6098 * ------------------- fp
6099 * MonoLMF structure or saved registers
6100 * -------------------
6101 * locals
6102 * -------------------
6103 * spilled regs
6104 * -------------------
6105 * optional 8 bytes for tracing
6106 * -------------------
6107 * param area size is cfg->param_area
6108 * ------------------- sp
6109 */
6110 guint8 *
6111 mono_arch_emit_prolog (MonoCompile *cfg)
6112 {
6113 MonoMethod *method = cfg->method;
6114 MonoBasicBlock *bb;
6115 MonoMethodSignature *sig;
6116 MonoInst *inst;
6117 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6118 guint8 *code;
6119 CallInfo *cinfo;
6120 int tracing = 0;
6121 int lmf_offset = 0;
6122 int prev_sp_offset, reg_offset;
6123
6124 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6125 tracing = 1;
6126
6127 sig = mono_method_signature (method);
6128 cfg->code_size = 256 + sig->param_count * 64;
6129 code = cfg->native_code = g_malloc (cfg->code_size);
6130
6131 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6132
6133 alloc_size = cfg->stack_offset;
6134 pos = 0;
6135 prev_sp_offset = 0;
6136
6137 if (iphone_abi) {
6138 /*
6139 * The iphone uses R7 as the frame pointer, and it points at the saved
6140 * r7+lr:
6141 * <lr>
6142 * r7 -> <r7>
6143 * <rest of frame>
6144 * We can't use r7 as a frame pointer since it points into the middle of
6145 * the frame, so we keep using our own frame pointer.
6146 * FIXME: Optimize this.
6147 */
6148 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6149 prev_sp_offset += 8; /* r7 and lr */
6150 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6151 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6152 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6153 }
6154
6155 if (!method->save_lmf) {
6156 if (iphone_abi) {
6157 /* No need to push LR again */
6158 if (cfg->used_int_regs)
6159 ARM_PUSH (code, cfg->used_int_regs);
6160 } else {
6161 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6162 prev_sp_offset += 4;
6163 }
6164 for (i = 0; i < 16; ++i) {
6165 if (cfg->used_int_regs & (1 << i))
6166 prev_sp_offset += 4;
6167 }
6168 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6169 reg_offset = 0;
6170 for (i = 0; i < 16; ++i) {
6171 if ((cfg->used_int_regs & (1 << i))) {
6172 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6173 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6174 reg_offset += 4;
6175 }
6176 }
6177 if (iphone_abi) {
6178 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6179 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6180 } else {
6181 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6182 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6183 }
6184 } else {
6185 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6186 ARM_PUSH (code, 0x5ff0);
6187 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6188 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6189 reg_offset = 0;
6190 for (i = 0; i < 16; ++i) {
6191 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6192 /* The original r7 is saved at the start */
6193 if (!(iphone_abi && i == ARMREG_R7))
6194 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6195 reg_offset += 4;
6196 }
6197 }
6198 g_assert (reg_offset == 4 * 10);
6199 pos += sizeof (MonoLMF) - (4 * 10);
6200 lmf_offset = pos;
6201 }
6202 alloc_size += pos;
6203 orig_alloc_size = alloc_size;
6204 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6205 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6206 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6207 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6208 }
6209
6210 /* the stack used in the pushed regs */
6211 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6212 cfg->stack_usage = alloc_size;
6213 if (alloc_size) {
6214 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6215 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6216 } else {
6217 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6218 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6219 }
6220 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6221 }
6222 if (cfg->frame_reg != ARMREG_SP) {
6223 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6224 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6225 }
6226 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6227 prev_sp_offset += alloc_size;
6228
6229 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6230 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6231
6232 /* compute max_offset in order to use short forward jumps
6233 * we could skip do it on arm because the immediate displacement
6234 * for jumps is large enough, it may be useful later for constant pools
6235 */
6236 max_offset = 0;
6237 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6238 MonoInst *ins = bb->code;
6239 bb->max_offset = max_offset;
6240
6241 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6242 max_offset += 6;
6243
6244 MONO_BB_FOR_EACH_INS (bb, ins)
6245 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6246 }
6247
6248 /* stack alignment check */
6249 /*
6250 {
6251 guint8 *buf [16];
6252 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6253 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6254 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6255 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6256 buf [0] = code;
6257 ARM_B_COND (code, ARMCOND_EQ, 0);
6258 if (cfg->compile_aot)
6259 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6260 else
6261 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6262 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6263 code = emit_call_seq (cfg, code);
6264 arm_patch (buf [0], code);
6265 }
6266 */
6267
6268 /* store runtime generic context */
6269 if (cfg->rgctx_var) {
6270 MonoInst *ins = cfg->rgctx_var;
6271
6272 g_assert (ins->opcode == OP_REGOFFSET);
6273
6274 if (arm_is_imm12 (ins->inst_offset)) {
6275 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6276 } else {
6277 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6278 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6279 }
6280 }
6281
6282 /* load arguments allocated to register from the stack */
6283 pos = 0;
6284
6285 cinfo = get_call_info (NULL, sig);
6286
6287 if (cinfo->ret.storage == RegTypeStructByAddr) {
6288 ArgInfo *ainfo = &cinfo->ret;
6289 inst = cfg->vret_addr;
6290 g_assert (arm_is_imm12 (inst->inst_offset));
6291 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6292 }
6293
6294 if (sig->call_convention == MONO_CALL_VARARG) {
6295 ArgInfo *cookie = &cinfo->sig_cookie;
6296
6297 /* Save the sig cookie address */
6298 g_assert (cookie->storage == RegTypeBase);
6299
6300 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6301 g_assert (arm_is_imm12 (cfg->sig_cookie));
6302 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6303 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6304 }
6305
6306 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6307 ArgInfo *ainfo = cinfo->args + i;
6308 inst = cfg->args [pos];
6309
6310 if (cfg->verbose_level > 2)
6311 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6312
6313 if (inst->opcode == OP_REGVAR) {
6314 if (ainfo->storage == RegTypeGeneral)
6315 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6316 else if (ainfo->storage == RegTypeFP) {
6317 g_assert_not_reached ();
6318 } else if (ainfo->storage == RegTypeBase) {
6319 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6320 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6321 } else {
6322 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6323 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6324 }
6325 } else
6326 g_assert_not_reached ();
6327
6328 if (cfg->verbose_level > 2)
6329 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6330 } else {
6331 switch (ainfo->storage) {
6332 case RegTypeHFA:
6333 for (part = 0; part < ainfo->nregs; part ++) {
6334 if (ainfo->esize == 4)
6335 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6336 else
6337 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6338 }
6339 break;
6340 case RegTypeGeneral:
6341 case RegTypeIRegPair:
6342 case RegTypeGSharedVtInReg:
6343 switch (ainfo->size) {
6344 case 1:
6345 if (arm_is_imm12 (inst->inst_offset))
6346 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6347 else {
6348 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6349 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6350 }
6351 break;
6352 case 2:
6353 if (arm_is_imm8 (inst->inst_offset)) {
6354 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6355 } else {
6356 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6357 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6358 }
6359 break;
6360 case 8:
6361 if (arm_is_imm12 (inst->inst_offset)) {
6362 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6363 } else {
6364 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6365 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6366 }
6367 if (arm_is_imm12 (inst->inst_offset + 4)) {
6368 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6369 } else {
6370 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6371 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6372 }
6373 break;
6374 default:
6375 if (arm_is_imm12 (inst->inst_offset)) {
6376 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6377 } else {
6378 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6379 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6380 }
6381 break;
6382 }
6383 break;
6384 case RegTypeBaseGen:
6385 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6386 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6387 } else {
6388 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6389 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6390 }
6391 if (arm_is_imm12 (inst->inst_offset + 4)) {
6392 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6393 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6394 } else {
6395 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6396 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6397 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6398 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6399 }
6400 break;
6401 case RegTypeBase:
6402 case RegTypeGSharedVtOnStack:
6403 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6404 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6405 } else {
6406 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6407 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6408 }
6409
6410 switch (ainfo->size) {
6411 case 1:
6412 if (arm_is_imm8 (inst->inst_offset)) {
6413 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6414 } else {
6415 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6416 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6417 }
6418 break;
6419 case 2:
6420 if (arm_is_imm8 (inst->inst_offset)) {
6421 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6422 } else {
6423 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6424 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6425 }
6426 break;
6427 case 8:
6428 if (arm_is_imm12 (inst->inst_offset)) {
6429 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6430 } else {
6431 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6432 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6433 }
6434 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6435 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6436 } else {
6437 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6438 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6439 }
6440 if (arm_is_imm12 (inst->inst_offset + 4)) {
6441 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6442 } else {
6443 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6444 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6445 }
6446 break;
6447 default:
6448 if (arm_is_imm12 (inst->inst_offset)) {
6449 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6450 } else {
6451 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6452 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6453 }
6454 break;
6455 }
6456 break;
6457 case RegTypeFP: {
6458 int imm8, rot_amount;
6459
6460 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6461 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6462 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6463 } else
6464 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6465
6466 if (ainfo->size == 8)
6467 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6468 else
6469 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6470 break;
6471 }
6472 case RegTypeStructByVal: {
6473 int doffset = inst->inst_offset;
6474 int soffset = 0;
6475 int cur_reg;
6476 int size = 0;
6477 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6478 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6479 if (arm_is_imm12 (doffset)) {
6480 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6481 } else {
6482 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6483 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6484 }
6485 soffset += sizeof (gpointer);
6486 doffset += sizeof (gpointer);
6487 }
6488 if (ainfo->vtsize) {
6489 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6490 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6491 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6492 }
6493 break;
6494 }
6495 case RegTypeStructByAddr:
6496 g_assert_not_reached ();
6497 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6498 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6499 default:
6500 g_assert_not_reached ();
6501 break;
6502 }
6503 }
6504 pos++;
6505 }
6506
6507 if (method->save_lmf)
6508 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6509
6510 if (tracing)
6511 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6512
6513 if (cfg->arch.seq_point_info_var) {
6514 MonoInst *ins = cfg->arch.seq_point_info_var;
6515
6516 /* Initialize the variable from a GOT slot */
6517 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6518 #ifdef USE_JUMP_TABLES
6519 {
6520 gpointer *jte = mono_jumptable_add_entry ();
6521 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6522 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6523 }
6524 /** XXX: is it correct? */
6525 #else
6526 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6527 ARM_B (code, 0);
6528 *(gpointer*)code = NULL;
6529 code += 4;
6530 #endif
6531 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6532
6533 g_assert (ins->opcode == OP_REGOFFSET);
6534
6535 if (arm_is_imm12 (ins->inst_offset)) {
6536 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6537 } else {
6538 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6539 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6540 }
6541 }
6542
6543 /* Initialize ss_trigger_page_var */
6544 if (!cfg->soft_breakpoints) {
6545 MonoInst *info_var = cfg->arch.seq_point_info_var;
6546 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6547 int dreg = ARMREG_LR;
6548
6549 if (info_var) {
6550 g_assert (info_var->opcode == OP_REGOFFSET);
6551 g_assert (arm_is_imm12 (info_var->inst_offset));
6552
6553 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6554 /* Load the trigger page addr */
6555 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6556 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6557 }
6558 }
6559
6560 if (cfg->arch.seq_point_ss_method_var) {
6561 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6562 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6563 #ifdef USE_JUMP_TABLES
6564 gpointer *jte;
6565 #endif
6566 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6567 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6568 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6569 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6570
6571 #ifdef USE_JUMP_TABLES
6572 jte = mono_jumptable_add_entries (3);
6573 jte [0] = &single_step_tramp;
6574 jte [1] = breakpoint_tramp;
6575 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6576 #else
6577 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6578 ARM_B (code, 1);
6579 *(gpointer*)code = &single_step_tramp;
6580 code += 4;
6581 *(gpointer*)code = breakpoint_tramp;
6582 code += 4;
6583 #endif
6584
6585 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6586 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6587 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6588 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6589 }
6590
6591 cfg->code_len = code - cfg->native_code;
6592 g_assert (cfg->code_len < cfg->code_size);
6593 g_free (cinfo);
6594
6595 return code;
6596 }
6597
6598 void
6599 mono_arch_emit_epilog (MonoCompile *cfg)
6600 {
6601 MonoMethod *method = cfg->method;
6602 int pos, i, rot_amount;
6603 int max_epilog_size = 16 + 20*4;
6604 guint8 *code;
6605 CallInfo *cinfo;
6606
6607 if (cfg->method->save_lmf)
6608 max_epilog_size += 128;
6609
6610 if (mono_jit_trace_calls != NULL)
6611 max_epilog_size += 50;
6612
6613 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6614 max_epilog_size += 50;
6615
6616 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6617 cfg->code_size *= 2;
6618 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6619 cfg->stat_code_reallocs++;
6620 }
6621
6622 /*
6623 * Keep in sync with OP_JMP
6624 */
6625 code = cfg->native_code + cfg->code_len;
6626
6627 /* Save the uwind state which is needed by the out-of-line code */
6628 mono_emit_unwind_op_remember_state (cfg, code);
6629
6630 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6631 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6632 }
6633 pos = 0;
6634
6635 /* Load returned vtypes into registers if needed */
6636 cinfo = cfg->arch.cinfo;
6637 switch (cinfo->ret.storage) {
6638 case RegTypeStructByVal: {
6639 MonoInst *ins = cfg->ret;
6640
6641 if (arm_is_imm12 (ins->inst_offset)) {
6642 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6643 } else {
6644 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6645 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6646 }
6647 break;
6648 }
6649 case RegTypeHFA: {
6650 MonoInst *ins = cfg->ret;
6651
6652 for (i = 0; i < cinfo->ret.nregs; ++i) {
6653 if (cinfo->ret.esize == 4)
6654 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6655 else
6656 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6657 }
6658 break;
6659 }
6660 default:
6661 break;
6662 }
6663
6664 if (method->save_lmf) {
6665 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6666 /* all but r0-r3, sp and pc */
6667 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6668 lmf_offset = pos;
6669
6670 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6671
6672 /* This points to r4 inside MonoLMF->iregs */
6673 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6674 reg = ARMREG_R4;
6675 regmask = 0x9ff0; /* restore lr to pc */
6676 /* Skip caller saved registers not used by the method */
6677 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6678 regmask &= ~(1 << reg);
6679 sp_adj += 4;
6680 reg ++;
6681 }
6682 if (iphone_abi)
6683 /* Restored later */
6684 regmask &= ~(1 << ARMREG_PC);
6685 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6686 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6687 for (i = 0; i < 16; i++) {
6688 if (regmask & (1 << i))
6689 nused_int_regs ++;
6690 }
6691 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6692 /* restore iregs */
6693 ARM_POP (code, regmask);
6694 if (iphone_abi) {
6695 for (i = 0; i < 16; i++) {
6696 if (regmask & (1 << i))
6697 mono_emit_unwind_op_same_value (cfg, code, i);
6698 }
6699 /* Restore saved r7, restore LR to PC */
6700 /* Skip lr from the lmf */
6701 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6702 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6703 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6704 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6705 }
6706 } else {
6707 int i, nused_int_regs = 0;
6708
6709 for (i = 0; i < 16; i++) {
6710 if (cfg->used_int_regs & (1 << i))
6711 nused_int_regs ++;
6712 }
6713
6714 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6715 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6716 } else {
6717 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6718 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6719 }
6720
6721 if (cfg->frame_reg != ARMREG_SP) {
6722 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6723 }
6724
6725 if (iphone_abi) {
6726 /* Restore saved gregs */
6727 if (cfg->used_int_regs) {
6728 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6729 ARM_POP (code, cfg->used_int_regs);
6730 for (i = 0; i < 16; i++) {
6731 if (cfg->used_int_regs & (1 << i))
6732 mono_emit_unwind_op_same_value (cfg, code, i);
6733 }
6734 }
6735 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6736 /* Restore saved r7, restore LR to PC */
6737 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6738 } else {
6739 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6740 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6741 }
6742 }
6743
6744 /* Restore the unwind state to be the same as before the epilog */
6745 mono_emit_unwind_op_restore_state (cfg, code);
6746
6747 cfg->code_len = code - cfg->native_code;
6748
6749 g_assert (cfg->code_len < cfg->code_size);
6750
6751 }
6752
6753 void
6754 mono_arch_emit_exceptions (MonoCompile *cfg)
6755 {
6756 MonoJumpInfo *patch_info;
6757 int i;
6758 guint8 *code;
6759 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6760 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6761 int max_epilog_size = 50;
6762
6763 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6764 exc_throw_pos [i] = NULL;
6765 exc_throw_found [i] = 0;
6766 }
6767
6768 /* count the number of exception infos */
6769
6770 /*
6771 * make sure we have enough space for exceptions
6772 */
6773 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6774 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6775 i = mini_exception_id_by_name (patch_info->data.target);
6776 if (!exc_throw_found [i]) {
6777 max_epilog_size += 32;
6778 exc_throw_found [i] = TRUE;
6779 }
6780 }
6781 }
6782
6783 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6784 cfg->code_size *= 2;
6785 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6786 cfg->stat_code_reallocs++;
6787 }
6788
6789 code = cfg->native_code + cfg->code_len;
6790
6791 /* add code to raise exceptions */
6792 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6793 switch (patch_info->type) {
6794 case MONO_PATCH_INFO_EXC: {
6795 MonoClass *exc_class;
6796 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6797
6798 i = mini_exception_id_by_name (patch_info->data.target);
6799 if (exc_throw_pos [i]) {
6800 arm_patch (ip, exc_throw_pos [i]);
6801 patch_info->type = MONO_PATCH_INFO_NONE;
6802 break;
6803 } else {
6804 exc_throw_pos [i] = code;
6805 }
6806 arm_patch (ip, code);
6807
6808 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6809
6810 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6811 #ifdef USE_JUMP_TABLES
6812 {
6813 gpointer *jte = mono_jumptable_add_entries (2);
6814 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6815 patch_info->data.name = "mono_arch_throw_corlib_exception";
6816 patch_info->ip.i = code - cfg->native_code;
6817 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6818 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6819 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6820 ARM_BLX_REG (code, ARMREG_IP);
6821 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6822 }
6823 #else
6824 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6825 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6826 patch_info->data.name = "mono_arch_throw_corlib_exception";
6827 patch_info->ip.i = code - cfg->native_code;
6828 ARM_BL (code, 0);
6829 cfg->thunk_area += THUNK_SIZE;
6830 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6831 code += 4;
6832 #endif
6833 break;
6834 }
6835 default:
6836 /* do nothing */
6837 break;
6838 }
6839 }
6840
6841 cfg->code_len = code - cfg->native_code;
6842
6843 g_assert (cfg->code_len < cfg->code_size);
6844
6845 }
6846
6847 #endif /* #ifndef DISABLE_JIT */
6848
6849 void
6850 mono_arch_finish_init (void)
6851 {
6852 }
6853
6854 void
6855 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6856 {
6857 }
6858
6859 MonoInst*
6860 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6861 {
6862 /* FIXME: */
6863 return NULL;
6864 }
6865
6866 gboolean
6867 mono_arch_print_tree (MonoInst *tree, int arity)
6868 {
6869 return 0;
6870 }
6871
6872 #ifndef DISABLE_JIT
6873
6874 #endif
6875
6876 guint32
6877 mono_arch_get_patch_offset (guint8 *code)
6878 {
6879 /* OP_AOTCONST */
6880 return 8;
6881 }
6882
6883 void
6884 mono_arch_flush_register_windows (void)
6885 {
6886 }
6887
6888 MonoMethod*
6889 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6890 {
6891 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6892 }
6893
6894 MonoVTable*
6895 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6896 {
6897 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6898 }
6899
6900 GSList*
6901 mono_arch_get_cie_program (void)
6902 {
6903 GSList *l = NULL;
6904
6905 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6906
6907 return l;
6908 }
6909
6910 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6911 #define BASE_SIZE (6 * 4)
6912 #define BSEARCH_ENTRY_SIZE (4 * 4)
6913 #define CMP_SIZE (3 * 4)
6914 #define BRANCH_SIZE (1 * 4)
6915 #define CALL_SIZE (2 * 4)
6916 #define WMC_SIZE (8 * 4)
6917 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6918
6919 #ifdef USE_JUMP_TABLES
6920 static void
6921 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6922 {
6923 g_assert (base [index] == NULL);
6924 base [index] = value;
6925 }
6926 static arminstr_t *
6927 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6928 {
6929 if (arm_is_imm12 (jti * 4)) {
6930 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6931 } else {
6932 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6933 if ((jti * 4) >> 16)
6934 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6935 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6936 }
6937 return code;
6938 }
6939 #else
6940 static arminstr_t *
6941 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6942 {
6943 guint32 delta = DISTANCE (target, code);
6944 delta -= 8;
6945 g_assert (delta >= 0 && delta <= 0xFFF);
6946 *target = *target | delta;
6947 *code = value;
6948 return code + 1;
6949 }
6950 #endif
6951
6952 #ifdef ENABLE_WRONG_METHOD_CHECK
6953 static void
6954 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6955 {
6956 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6957 g_assert (0);
6958 }
6959 #endif
6960
6961 gpointer
6962 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6963 gpointer fail_tramp)
6964 {
6965 int size, i;
6966 arminstr_t *code, *start;
6967 #ifdef USE_JUMP_TABLES
6968 gpointer *jte;
6969 #else
6970 gboolean large_offsets = FALSE;
6971 guint32 **constant_pool_starts;
6972 arminstr_t *vtable_target = NULL;
6973 int extra_space = 0;
6974 #endif
6975 #ifdef ENABLE_WRONG_METHOD_CHECK
6976 char * cond;
6977 #endif
6978 GSList *unwind_ops;
6979
6980 size = BASE_SIZE;
6981 #ifdef USE_JUMP_TABLES
6982 for (i = 0; i < count; ++i) {
6983 MonoIMTCheckItem *item = imt_entries [i];
6984 item->chunk_size += 4 * 16;
6985 if (!item->is_equals)
6986 imt_entries [item->check_target_idx]->compare_done = TRUE;
6987 size += item->chunk_size;
6988 }
6989 #else
6990 constant_pool_starts = g_new0 (guint32*, count);
6991
6992 for (i = 0; i < count; ++i) {
6993 MonoIMTCheckItem *item = imt_entries [i];
6994 if (item->is_equals) {
6995 gboolean fail_case = !item->check_target_idx && fail_tramp;
6996
6997 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6998 item->chunk_size += 32;
6999 large_offsets = TRUE;
7000 }
7001
7002 if (item->check_target_idx || fail_case) {
7003 if (!item->compare_done || fail_case)
7004 item->chunk_size += CMP_SIZE;
7005 item->chunk_size += BRANCH_SIZE;
7006 } else {
7007 #ifdef ENABLE_WRONG_METHOD_CHECK
7008 item->chunk_size += WMC_SIZE;
7009 #endif
7010 }
7011 if (fail_case) {
7012 item->chunk_size += 16;
7013 large_offsets = TRUE;
7014 }
7015 item->chunk_size += CALL_SIZE;
7016 } else {
7017 item->chunk_size += BSEARCH_ENTRY_SIZE;
7018 imt_entries [item->check_target_idx]->compare_done = TRUE;
7019 }
7020 size += item->chunk_size;
7021 }
7022
7023 if (large_offsets)
7024 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7025 #endif
7026
7027 if (fail_tramp)
7028 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7029 else
7030 code = mono_domain_code_reserve (domain, size);
7031 start = code;
7032
7033 unwind_ops = mono_arch_get_cie_program ();
7034
7035 #ifdef DEBUG_IMT
7036 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7037 for (i = 0; i < count; ++i) {
7038 MonoIMTCheckItem *item = imt_entries [i];
7039 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7040 }
7041 #endif
7042
7043 #ifdef USE_JUMP_TABLES
7044 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7045 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7046 #define VTABLE_JTI 0
7047 #define IMT_METHOD_OFFSET 0
7048 #define TARGET_CODE_OFFSET 1
7049 #define JUMP_CODE_OFFSET 2
7050 #define RECORDS_PER_ENTRY 3
7051 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7052 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7053 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7054
7055 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7056 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7057 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7058 set_jumptable_element (jte, VTABLE_JTI, vtable);
7059 #else
7060 if (large_offsets) {
7061 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7062 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7063 } else {
7064 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7065 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7066 }
7067 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7068 vtable_target = code;
7069 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7070 #endif
7071 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7072
7073 for (i = 0; i < count; ++i) {
7074 MonoIMTCheckItem *item = imt_entries [i];
7075 #ifdef USE_JUMP_TABLES
7076 guint32 imt_method_jti = 0, target_code_jti = 0;
7077 #else
7078 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7079 #endif
7080 gint32 vtable_offset;
7081
7082 item->code_target = (guint8*)code;
7083
7084 if (item->is_equals) {
7085 gboolean fail_case = !item->check_target_idx && fail_tramp;
7086
7087 if (item->check_target_idx || fail_case) {
7088 if (!item->compare_done || fail_case) {
7089 #ifdef USE_JUMP_TABLES
7090 imt_method_jti = IMT_METHOD_JTI (i);
7091 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7092 #else
7093 imt_method = code;
7094 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7095 #endif
7096 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7097 }
7098 #ifdef USE_JUMP_TABLES
7099 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7100 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7101 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7102 #else
7103 item->jmp_code = (guint8*)code;
7104 ARM_B_COND (code, ARMCOND_NE, 0);
7105 #endif
7106 } else {
7107 /*Enable the commented code to assert on wrong method*/
7108 #ifdef ENABLE_WRONG_METHOD_CHECK
7109 #ifdef USE_JUMP_TABLES
7110 imt_method_jti = IMT_METHOD_JTI (i);
7111 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7112 #else
7113 imt_method = code;
7114 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7115 #endif
7116 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7117 cond = code;
7118 ARM_B_COND (code, ARMCOND_EQ, 0);
7119
7120 /* Define this if your system is so bad that gdb is failing. */
7121 #ifdef BROKEN_DEV_ENV
7122 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7123 ARM_BL (code, 0);
7124 arm_patch (code - 1, mini_dump_bad_imt);
7125 #else
7126 ARM_DBRK (code);
7127 #endif
7128 arm_patch (cond, code);
7129 #endif
7130 }
7131
7132 if (item->has_target_code) {
7133 /* Load target address */
7134 #ifdef USE_JUMP_TABLES
7135 target_code_jti = TARGET_CODE_JTI (i);
7136 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7137 /* Restore registers */
7138 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7139 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7140 /* And branch */
7141 ARM_BX (code, ARMREG_R1);
7142 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7143 #else
7144 target_code_ins = code;
7145 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7146 /* Save it to the fourth slot */
7147 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7148 /* Restore registers and branch */
7149 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7150
7151 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7152 #endif
7153 } else {
7154 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7155 if (!arm_is_imm12 (vtable_offset)) {
7156 /*
7157 * We need to branch to a computed address but we don't have
7158 * a free register to store it, since IP must contain the
7159 * vtable address. So we push the two values to the stack, and
7160 * load them both using LDM.
7161 */
7162 /* Compute target address */
7163 #ifdef USE_JUMP_TABLES
7164 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7165 if (vtable_offset >> 16)
7166 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7167 /* IP had vtable base. */
7168 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7169 /* Restore registers and branch */
7170 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7171 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7172 ARM_BX (code, ARMREG_IP);
7173 #else
7174 vtable_offset_ins = code;
7175 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7176 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7177 /* Save it to the fourth slot */
7178 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7179 /* Restore registers and branch */
7180 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7181
7182 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7183 #endif
7184 } else {
7185 #ifdef USE_JUMP_TABLES
7186 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7187 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7188 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7189 ARM_BX (code, ARMREG_IP);
7190 #else
7191 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7192 if (large_offsets) {
7193 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7194 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7195 }
7196 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7197 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7198 #endif
7199 }
7200 }
7201
7202 if (fail_case) {
7203 #ifdef USE_JUMP_TABLES
7204 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7205 target_code_jti = TARGET_CODE_JTI (i);
7206 /* Load target address */
7207 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7208 /* Restore registers */
7209 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7210 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7211 /* And branch */
7212 ARM_BX (code, ARMREG_R1);
7213 set_jumptable_element (jte, target_code_jti, fail_tramp);
7214 #else
7215 arm_patch (item->jmp_code, (guchar*)code);
7216
7217 target_code_ins = code;
7218 /* Load target address */
7219 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7220 /* Save it to the fourth slot */
7221 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7222 /* Restore registers and branch */
7223 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7224
7225 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7226 #endif
7227 item->jmp_code = NULL;
7228 }
7229
7230 #ifdef USE_JUMP_TABLES
7231 if (imt_method_jti)
7232 set_jumptable_element (jte, imt_method_jti, item->key);
7233 #else
7234 if (imt_method)
7235 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7236
7237 /*must emit after unconditional branch*/
7238 if (vtable_target) {
7239 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7240 item->chunk_size += 4;
7241 vtable_target = NULL;
7242 }
7243
7244 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7245 constant_pool_starts [i] = code;
7246 if (extra_space) {
7247 code += extra_space;
7248 extra_space = 0;
7249 }
7250 #endif
7251 } else {
7252 #ifdef USE_JUMP_TABLES
7253 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7254 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7255 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7256 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7257 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7258 #else
7259 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7260 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7261
7262 item->jmp_code = (guint8*)code;
7263 ARM_B_COND (code, ARMCOND_HS, 0);
7264 ++extra_space;
7265 #endif
7266 }
7267 }
7268
7269 for (i = 0; i < count; ++i) {
7270 MonoIMTCheckItem *item = imt_entries [i];
7271 if (item->jmp_code) {
7272 if (item->check_target_idx)
7273 #ifdef USE_JUMP_TABLES
7274 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7275 #else
7276 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7277 #endif
7278 }
7279 if (i > 0 && item->is_equals) {
7280 int j;
7281 #ifdef USE_JUMP_TABLES
7282 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7283 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7284 #else
7285 arminstr_t *space_start = constant_pool_starts [i];
7286 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7287 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7288 }
7289 #endif
7290 }
7291 }
7292
7293 #ifdef DEBUG_IMT
7294 {
7295 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7296 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7297 g_free (buff);
7298 }
7299 #endif
7300
7301 #ifndef USE_JUMP_TABLES
7302 g_free (constant_pool_starts);
7303 #endif
7304
7305 mono_arch_flush_icache ((guint8*)start, size);
7306 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7307 mono_stats.imt_thunks_size += code - start;
7308
7309 g_assert (DISTANCE (start, code) <= size);
7310
7311 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7312
7313 return start;
7314 }
7315
7316 mgreg_t
7317 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7318 {
7319 return ctx->regs [reg];
7320 }
7321
7322 void
7323 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7324 {
7325 ctx->regs [reg] = val;
7326 }
7327
7328 /*
7329 * mono_arch_get_trampolines:
7330 *
7331 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7332 * for AOT.
7333 */
7334 GSList *
7335 mono_arch_get_trampolines (gboolean aot)
7336 {
7337 return mono_arm_get_exception_trampolines (aot);
7338 }
7339
7340 gpointer
7341 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7342 {
7343 gpointer *lr_loc;
7344 char *old_value;
7345 char *bp;
7346
7347 /*Load the spvar*/
7348 bp = MONO_CONTEXT_GET_BP (ctx);
7349 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7350
7351 old_value = *lr_loc;
7352 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7353 return old_value;
7354
7355 *lr_loc = new_value;
7356
7357 return old_value;
7358 }
7359
7360 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7361 /*
7362 * mono_arch_set_breakpoint:
7363 *
7364 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7365 * The location should contain code emitted by OP_SEQ_POINT.
7366 */
7367 void
7368 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7369 {
7370 guint8 *code = ip;
7371 guint32 native_offset = ip - (guint8*)ji->code_start;
7372 MonoDebugOptions *opt = mini_get_debug_options ();
7373
7374 if (opt->soft_breakpoints) {
7375 g_assert (!ji->from_aot);
7376 code += 4;
7377 ARM_BLX_REG (code, ARMREG_LR);
7378 mono_arch_flush_icache (code - 4, 4);
7379 } else if (ji->from_aot) {
7380 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7381
7382 g_assert (native_offset % 4 == 0);
7383 g_assert (info->bp_addrs [native_offset / 4] == 0);
7384 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7385 } else {
7386 int dreg = ARMREG_LR;
7387
7388 /* Read from another trigger page */
7389 #ifdef USE_JUMP_TABLES
7390 gpointer *jte = mono_jumptable_add_entry ();
7391 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7392 jte [0] = bp_trigger_page;
7393 #else
7394 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7395 ARM_B (code, 0);
7396 *(int*)code = (int)bp_trigger_page;
7397 code += 4;
7398 #endif
7399 ARM_LDR_IMM (code, dreg, dreg, 0);
7400
7401 mono_arch_flush_icache (code - 16, 16);
7402
7403 #if 0
7404 /* This is currently implemented by emitting an SWI instruction, which
7405 * qemu/linux seems to convert to a SIGILL.
7406 */
7407 *(int*)code = (0xef << 24) | 8;
7408 code += 4;
7409 mono_arch_flush_icache (code - 4, 4);
7410 #endif
7411 }
7412 }
7413
7414 /*
7415 * mono_arch_clear_breakpoint:
7416 *
7417 * Clear the breakpoint at IP.
7418 */
7419 void
7420 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7421 {
7422 MonoDebugOptions *opt = mini_get_debug_options ();
7423 guint8 *code = ip;
7424 int i;
7425
7426 if (opt->soft_breakpoints) {
7427 g_assert (!ji->from_aot);
7428 code += 4;
7429 ARM_NOP (code);
7430 mono_arch_flush_icache (code - 4, 4);
7431 } else if (ji->from_aot) {
7432 guint32 native_offset = ip - (guint8*)ji->code_start;
7433 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7434
7435 g_assert (native_offset % 4 == 0);
7436 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7437 info->bp_addrs [native_offset / 4] = 0;
7438 } else {
7439 for (i = 0; i < 4; ++i)
7440 ARM_NOP (code);
7441
7442 mono_arch_flush_icache (ip, code - ip);
7443 }
7444 }
7445
7446 /*
7447 * mono_arch_start_single_stepping:
7448 *
7449 * Start single stepping.
7450 */
7451 void
7452 mono_arch_start_single_stepping (void)
7453 {
7454 if (ss_trigger_page)
7455 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7456 else
7457 single_step_tramp = mini_get_single_step_trampoline ();
7458 }
7459
7460 /*
7461 * mono_arch_stop_single_stepping:
7462 *
7463 * Stop single stepping.
7464 */
7465 void
7466 mono_arch_stop_single_stepping (void)
7467 {
7468 if (ss_trigger_page)
7469 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7470 else
7471 single_step_tramp = NULL;
7472 }
7473
7474 #if __APPLE__
7475 #define DBG_SIGNAL SIGBUS
7476 #else
7477 #define DBG_SIGNAL SIGSEGV
7478 #endif
7479
7480 /*
7481 * mono_arch_is_single_step_event:
7482 *
7483 * Return whenever the machine state in SIGCTX corresponds to a single
7484 * step event.
7485 */
7486 gboolean
7487 mono_arch_is_single_step_event (void *info, void *sigctx)
7488 {
7489 siginfo_t *sinfo = info;
7490
7491 if (!ss_trigger_page)
7492 return FALSE;
7493
7494 /* Sometimes the address is off by 4 */
7495 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7496 return TRUE;
7497 else
7498 return FALSE;
7499 }
7500
7501 /*
7502 * mono_arch_is_breakpoint_event:
7503 *
7504 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7505 */
7506 gboolean
7507 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7508 {
7509 siginfo_t *sinfo = info;
7510
7511 if (!ss_trigger_page)
7512 return FALSE;
7513
7514 if (sinfo->si_signo == DBG_SIGNAL) {
7515 /* Sometimes the address is off by 4 */
7516 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7517 return TRUE;
7518 else
7519 return FALSE;
7520 } else {
7521 return FALSE;
7522 }
7523 }
7524
7525 /*
7526 * mono_arch_skip_breakpoint:
7527 *
7528 * See mini-amd64.c for docs.
7529 */
7530 void
7531 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7532 {
7533 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7534 }
7535
7536 /*
7537 * mono_arch_skip_single_step:
7538 *
7539 * See mini-amd64.c for docs.
7540 */
7541 void
7542 mono_arch_skip_single_step (MonoContext *ctx)
7543 {
7544 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7545 }
7546
7547 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7548
7549 /*
7550 * mono_arch_get_seq_point_info:
7551 *
7552 * See mini-amd64.c for docs.
7553 */
7554 gpointer
7555 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7556 {
7557 SeqPointInfo *info;
7558 MonoJitInfo *ji;
7559
7560 // FIXME: Add a free function
7561
7562 mono_domain_lock (domain);
7563 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7564 code);
7565 mono_domain_unlock (domain);
7566
7567 if (!info) {
7568 ji = mono_jit_info_table_find (domain, (char*)code);
7569 g_assert (ji);
7570
7571 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7572
7573 info->ss_trigger_page = ss_trigger_page;
7574 info->bp_trigger_page = bp_trigger_page;
7575
7576 mono_domain_lock (domain);
7577 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7578 code, info);
7579 mono_domain_unlock (domain);
7580 }
7581
7582 return info;
7583 }
7584
7585 void
7586 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7587 {
7588 ext->lmf.previous_lmf = prev_lmf;
7589 /* Mark that this is a MonoLMFExt */
7590 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7591 ext->lmf.sp = (gssize)ext;
7592 }
7593
7594 /*
7595 * mono_arch_set_target:
7596 *
7597 * Set the target architecture the JIT backend should generate code for, in the form
7598 * of a GNU target triplet. Only used in AOT mode.
7599 */
7600 void
7601 mono_arch_set_target (char *mtriple)
7602 {
7603 /* The GNU target triple format is not very well documented */
7604 if (strstr (mtriple, "armv7")) {
7605 v5_supported = TRUE;
7606 v6_supported = TRUE;
7607 v7_supported = TRUE;
7608 }
7609 if (strstr (mtriple, "armv6")) {
7610 v5_supported = TRUE;
7611 v6_supported = TRUE;
7612 }
7613 if (strstr (mtriple, "armv7s")) {
7614 v7s_supported = TRUE;
7615 }
7616 if (strstr (mtriple, "armv7k")) {
7617 v7k_supported = TRUE;
7618 }
7619 if (strstr (mtriple, "thumbv7s")) {
7620 v5_supported = TRUE;
7621 v6_supported = TRUE;
7622 v7_supported = TRUE;
7623 v7s_supported = TRUE;
7624 thumb_supported = TRUE;
7625 thumb2_supported = TRUE;
7626 }
7627 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7628 v5_supported = TRUE;
7629 v6_supported = TRUE;
7630 thumb_supported = TRUE;
7631 iphone_abi = TRUE;
7632 }
7633 if (strstr (mtriple, "gnueabi"))
7634 eabi_supported = TRUE;
7635 }
7636
7637 gboolean
7638 mono_arch_opcode_supported (int opcode)
7639 {
7640 switch (opcode) {
7641 case OP_ATOMIC_ADD_I4:
7642 case OP_ATOMIC_EXCHANGE_I4:
7643 case OP_ATOMIC_CAS_I4:
7644 case OP_ATOMIC_LOAD_I1:
7645 case OP_ATOMIC_LOAD_I2:
7646 case OP_ATOMIC_LOAD_I4:
7647 case OP_ATOMIC_LOAD_U1:
7648 case OP_ATOMIC_LOAD_U2:
7649 case OP_ATOMIC_LOAD_U4:
7650 case OP_ATOMIC_STORE_I1:
7651 case OP_ATOMIC_STORE_I2:
7652 case OP_ATOMIC_STORE_I4:
7653 case OP_ATOMIC_STORE_U1:
7654 case OP_ATOMIC_STORE_U2:
7655 case OP_ATOMIC_STORE_U4:
7656 return v7_supported;
7657 case OP_ATOMIC_LOAD_R4:
7658 case OP_ATOMIC_LOAD_R8:
7659 case OP_ATOMIC_STORE_R4:
7660 case OP_ATOMIC_STORE_R8:
7661 return v7_supported && IS_VFP;
7662 default:
7663 return FALSE;
7664 }
7665 }
7666
7667 #if defined(ENABLE_GSHAREDVT)
7668
7669 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7670
7671 #endif /* !MONOTOUCH */
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