1 # powerpc cpu description file
2 # this file is read by genmdesc to pruduce a table with all the relevant information
3 # about the cpu instructions that may be used by the regsiter allocator, the scheduler
4 # and other parts of the arch-dependent part of mini.
6 # An opcode name is followed by a colon and optional specifiers.
7 # A specifier has a name, a colon and a value. Specifiers are separated by white space.
8 # Here is a description of the specifiers valid for this file and their possible values.
10 # dest:register describes the destination register of an instruction
11 # src1:register describes the first source register of an instruction
12 # src2:register describes the second source register of an instruction
14 # register may have the following values:
16 # a r3 register (output from calls)
17 # b base register (used in address references)
18 # f floating point register
20 # len:number describe the maximun length in bytes of the instruction
21 # number is a positive integer
23 # cost:number describe how many cycles are needed to complete the instruction (unused)
25 # clob:spec describe if the instruction clobbers registers or has special needs
27 # spec can be one of the following characters:
28 # c clobbers caller-save registers
29 # r 'reserves' the destination register until a later instruction unreserves it
30 # used mostly to set output registers in function calls
32 # flags:spec describe if the instruction uses or sets the flags (unused)
34 # spec can be one of the following chars:
37 # m uses and modifies the flags
39 # res:spec describe what units are used in the processor (unused)
41 # delay: describe delay slots (unused)
43 # the required specifiers are: len, clob (if registers are clobbered), the registers
44 # specifiers if the registers are actually used, flags (when scheduling is implemented).
46 # See the code in mini-x86.c for more details on how the specifiers are used.
48 tailcall: len:124 clob:c
56 call: dest:a clob:c len:36
59 rethrow: src1:i len:40
60 ckfinite: dest:f src1:f
61 ppc_check_finite: src1:i len:16
62 add_ovf_carry: dest:i src1:i src2:i len:16
63 sub_ovf_carry: dest:i src1:i src2:i len:16
64 add_ovf_un_carry: dest:i src1:i src2:i len:16
65 sub_ovf_un_carry: dest:i src1:i src2:i len:16
73 localloc: dest:i src1:i len:60
74 compare: src1:i src2:i len:4
75 compare_imm: src1:i len:12
76 fcompare: src1:f src2:f len:12
77 oparglist: src1:i len:12
78 setlret: src1:i src2:i len:12
79 checkthis: src1:b len:4
80 voidcall: len:36 clob:c
81 voidcall_reg: src1:i len:16 clob:c
82 voidcall_membase: src1:b len:16 clob:c
83 fcall: dest:g len:36 clob:c
84 fcall_reg: dest:g src1:i len:16 clob:c
85 fcall_membase: dest:g src1:b len:16 clob:c
86 lcall: dest:a len:36 clob:c
87 lcall_reg: dest:a src1:i len:16 clob:c
88 lcall_membase: dest:a src1:b len:16 clob:c
90 vcall_reg: src1:i len:16 clob:c
91 vcall_membase: src1:b len:12 clob:c
92 call_reg: dest:a src1:i len:16 clob:c
93 call_membase: dest:a src1:b len:16 clob:c
95 i8const: dest:i len:20
96 r4const: dest:f len:12
97 r8const: dest:f len:24
99 store_membase_reg: dest:b src1:i len:12
100 storei1_membase_reg: dest:b src1:i len:12
101 storei2_membase_reg: dest:b src1:i len:12
102 storei4_membase_reg: dest:b src1:i len:12
103 storei8_membase_reg: dest:b src1:i len:12
104 storer4_membase_reg: dest:b src1:f len:16
105 storer8_membase_reg: dest:b src1:f len:12
106 load_membase: dest:i src1:b len:12
107 loadi1_membase: dest:i src1:b len:16
108 loadu1_membase: dest:i src1:b len:12
109 loadi2_membase: dest:i src1:b len:12
110 loadu2_membase: dest:i src1:b len:12
111 loadi4_membase: dest:i src1:b len:12
112 loadu4_membase: dest:i src1:b len:12
113 loadi8_membase: dest:i src1:b len:12
114 loadr4_membase: dest:f src1:b len:12
115 loadr8_membase: dest:f src1:b len:12
116 load_memindex: dest:i src1:b src2:i len:4
117 loadi1_memindex: dest:i src1:b src2:i len:8
118 loadu1_memindex: dest:i src1:b src2:i len:4
119 loadi2_memindex: dest:i src1:b src2:i len:4
120 loadu2_memindex: dest:i src1:b src2:i len:4
121 loadi4_memindex: dest:i src1:b src2:i len:4
122 loadu4_memindex: dest:i src1:b src2:i len:4
123 loadi8_memindex: dest:i src1:b src2:i len:4
124 loadr4_memindex: dest:f src1:b src2:i len:4
125 loadr8_memindex: dest:f src1:b src2:i len:4
126 store_memindex: dest:b src1:i src2:i len:4
127 storei1_memindex: dest:b src1:i src2:i len:4
128 storei2_memindex: dest:b src1:i src2:i len:4
129 storei4_memindex: dest:b src1:i src2:i len:4
130 storei8_memindex: dest:b src1:i src2:i len:4
131 storer4_memindex: dest:b src1:i src2:i len:8
132 storer8_memindex: dest:b src1:i src2:i len:4
133 loadu4_mem: dest:i len:8
134 move: dest:i src1:i len:4
135 fmove: dest:f src1:f len:4
136 add_imm: dest:i src1:i len:4
137 sub_imm: dest:i src1:i len:4
138 mul_imm: dest:i src1:i len:4
139 # there is no actual support for division or reminder by immediate
140 # we simulate them, though (but we need to change the burg rules
141 # to allocate a symbolic reg for src2)
142 div_imm: dest:i src1:i src2:i len:20
143 div_un_imm: dest:i src1:i src2:i len:12
144 rem_imm: dest:i src1:i src2:i len:28
145 rem_un_imm: dest:i src1:i src2:i len:16
146 and_imm: dest:i src1:i len:4
147 or_imm: dest:i src1:i len:4
148 xor_imm: dest:i src1:i len:4
149 shl_imm: dest:i src1:i len:4
150 shr_imm: dest:i src1:i len:4
151 shr_un_imm: dest:i src1:i len:4
153 cond_exc_ne_un: len:8
155 cond_exc_lt_un: len:8
157 cond_exc_gt_un: len:8
159 cond_exc_ge_un: len:8
161 cond_exc_le_un: len:8
166 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
168 long_conv_to_r_un: dest:f src1:i src2:i len:37
179 float_add: dest:f src1:f src2:f len:4
180 float_sub: dest:f src1:f src2:f len:4
181 float_mul: dest:f src1:f src2:f len:4
182 float_div: dest:f src1:f src2:f len:4
183 float_div_un: dest:f src1:f src2:f len:4
184 float_rem: dest:f src1:f src2:f len:16
185 float_rem_un: dest:f src1:f src2:f len:16
186 float_neg: dest:f src1:f len:4
187 float_not: dest:f src1:f len:4
188 float_conv_to_i1: dest:i src1:f len:40
189 float_conv_to_i2: dest:i src1:f len:40
190 float_conv_to_i4: dest:i src1:f len:40
191 float_conv_to_i8: dest:i src1:f len:40
192 float_conv_to_r4: dest:f src1:f len:4
193 float_conv_to_u4: dest:i src1:f len:40
194 float_conv_to_u8: dest:i src1:f len:40
195 float_conv_to_u2: dest:i src1:f len:40
196 float_conv_to_u1: dest:i src1:f len:40
197 float_conv_to_i: dest:i src1:f len:40
198 float_ceq: dest:i src1:f src2:f len:16
199 float_cgt: dest:i src1:f src2:f len:16
200 float_cgt_un: dest:i src1:f src2:f len:20
201 float_clt: dest:i src1:f src2:f len:16
202 float_clt_un: dest:i src1:f src2:f len:20
203 float_conv_to_u: dest:i src1:f len:36
204 call_handler: len:12 clob:c
205 endfilter: src1:i len:20
206 aot_const: dest:i len:8
207 load_gotaddr: dest:i len:32
208 got_entry: dest:i src1:b len:32
209 sqrt: dest:f src1:f len:4
210 adc: dest:i src1:i src2:i len:4
211 addcc: dest:i src1:i src2:i len:4
212 subcc: dest:i src1:i src2:i len:4
213 addcc_imm: dest:i src1:i len:4
214 sbb: dest:i src1:i src2:i len:4
216 ppc_subfic: dest:i src1:i len:4
217 ppc_subfze: dest:i src1:i len:4
218 bigmul: len:12 dest:i src1:i src2:i
219 bigmul_un: len:12 dest:i src1:i src2:i
220 tls_get: len:8 dest:i
223 dummy_use: src1:i len:0
226 not_null: src1:i len:0
229 int_add: dest:i src1:i src2:i len:4
230 int_sub: dest:i src1:i src2:i len:4
231 int_mul: dest:i src1:i src2:i len:4
232 int_div: dest:i src1:i src2:i len:40
233 int_div_un: dest:i src1:i src2:i len:16
234 int_rem: dest:i src1:i src2:i len:48
235 int_rem_un: dest:i src1:i src2:i len:24
236 int_and: dest:i src1:i src2:i len:4
237 int_or: dest:i src1:i src2:i len:4
238 int_xor: dest:i src1:i src2:i len:4
239 int_shl: dest:i src1:i src2:i len:4
240 int_shr: dest:i src1:i src2:i len:4
241 int_shr_un: dest:i src1:i src2:i len:4
242 int_neg: dest:i src1:i len:4
243 int_not: dest:i src1:i len:4
244 int_conv_to_i1: dest:i src1:i len:8
245 int_conv_to_i2: dest:i src1:i len:8
246 int_conv_to_i4: dest:i src1:i len:4
247 sext_i4: dest:i src1:i len:4
248 int_conv_to_r4: dest:f src1:i len:20
249 int_conv_to_r8: dest:f src1:i len:16
250 int_conv_to_u4: dest:i src1:i len:4
251 int_conv_to_u2: dest:i src1:i len:8
252 int_conv_to_u1: dest:i src1:i len:4
263 int_add_ovf: dest:i src1:i src2:i len:16
264 int_add_ovf_un: dest:i src1:i src2:i len:16
265 int_mul_ovf: dest:i src1:i src2:i len:16
266 int_mul_ovf_un: dest:i src1:i src2:i len:16
267 int_sub_ovf: dest:i src1:i src2:i len:16
268 int_sub_ovf_un: dest:i src1:i src2:i len:16
270 int_adc: dest:i src1:i src2:i len:4
271 int_addcc: dest:i src1:i src2:i len:4
272 int_subcc: dest:i src1:i src2:i len:4
273 int_sbb: dest:i src1:i src2:i len:4
274 int_adc_imm: dest:i src1:i len:12
275 int_sbb_imm: dest:i src1:i len:12
277 int_add_imm: dest:i src1:i len:4
278 int_sub_imm: dest:i src1:i len:12
279 int_mul_imm: dest:i src1:i len:12
280 int_div_imm: dest:i src1:i len:20
281 int_div_un_imm: dest:i src1:i len:12
282 int_rem_imm: dest:i src1:i len:28
283 int_rem_un_imm: dest:i src1:i len:16
284 int_and_imm: dest:i src1:i len:12
285 int_or_imm: dest:i src1:i len:12
286 int_xor_imm: dest:i src1:i len:12
287 int_shl_imm: dest:i src1:i len:8
288 int_shr_imm: dest:i src1:i len:8
289 int_shr_un_imm: dest:i src1:i len:8
291 int_ceq: dest:i len:12
292 int_cgt: dest:i len:12
293 int_cgt_un: dest:i len:12
294 int_clt: dest:i len:12
295 int_clt_un: dest:i len:12
298 cond_exc_ine_un: len:8
300 cond_exc_ilt_un: len:8
302 cond_exc_igt_un: len:8
304 cond_exc_ige_un: len:8
306 cond_exc_ile_un: len:8
312 icompare: src1:i src2:i len:4
313 icompare_imm: src1:i len:12
316 long_add: dest:i src1:i src2:i len:4
317 long_sub: dest:i src1:i src2:i len:4
318 long_mul: dest:i src1:i src2:i len:4
319 long_mul_imm: dest:i src1:i len:4
320 long_div: dest:i src1:i src2:i len:40
321 long_div_un: dest:i src1:i src2:i len:16
322 long_rem: dest:i src1:i src2:i len:48
323 long_rem_un: dest:i src1:i src2:i len:24
324 long_and: dest:i src1:i src2:i len:4
325 long_or: dest:i src1:i src2:i len:4
326 long_xor: dest:i src1:i src2:i len:4
327 long_shl: dest:i src1:i src2:i len:4
328 long_shl_imm: dest:i src1:i len:4
329 long_shr: dest:i src1:i src2:i len:4
330 long_shr_un: dest:i src1:i src2:i len:4
331 long_shr_imm: dest:i src1:i len:4
332 long_shr_un_imm: dest:i src1:i len:4
333 long_neg: dest:i src1:i len:4
334 long_not: dest:i src1:i len:4
335 long_conv_to_i1: dest:i src1:i len:4
336 long_conv_to_i2: dest:i src1:i len:4
337 long_conv_to_i4: dest:i src1:i len:4
338 long_conv_to_r4: dest:f src1:i len:16
339 long_conv_to_r8: dest:f src1:i len:12
340 long_conv_to_u4: dest:i src1:i
341 long_conv_to_u2: dest:i src1:i len:4
342 long_conv_to_u1: dest:i src1:i len:4
343 zext_i4: dest:i src1:i len:4
355 long_add_ovf: dest:i src1:i src2:i len:16
356 long_add_ovf_un: dest:i src1:i src2:i len:16
357 long_mul_ovf: dest:i src1:i src2:i len:16
358 long_mul_ovf_un: dest:i src1:i src2:i len:16
359 long_sub_ovf: dest:i src1:i src2:i len:16
360 long_sub_ovf_un: dest:i src1:i src2:i len:16
362 long_ceq: dest:i len:12
363 long_cgt: dest:i len:12
364 long_cgt_un: dest:i len:12
365 long_clt: dest:i len:12
366 long_clt_un: dest:i len:12
368 long_add_imm: dest:i src1:i clob:1 len:4
369 long_sub_imm: dest:i src1:i clob:1 len:4
370 long_and_imm: dest:i src1:i clob:1 len:4
371 long_or_imm: dest:i src1:i clob:1 len:4
372 long_xor_imm: dest:i src1:i clob:1 len:4
374 lcompare: src1:i src2:i len:4
375 lcompare_imm: src1:i len:12
377 #long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30
379 vcall2: len:36 clob:c
380 vcall2_reg: src1:i len:16 clob:c
381 vcall2_membase: src1:b len:16 clob:c
383 jump_table: dest:i len:20
385 atomic_add_i4: src1:b src2:i dest:i len:28
386 atomic_add_i8: src1:b src2:i dest:i len:28
387 atomic_cas_i4: src1:b src2:i src3:i dest:i len:38
388 atomic_cas_i8: src1:b src2:i src3:i dest:i len:38