| blob | 51de55d7117b12eeb54a6c606b8c1f155c22b115 |
1 /**
2 * \file
3 * AMD64 backend for the Mono code generator
4 *
5 * Based on mini-x86.c.
6 *
7 * Authors:
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
10 * Patrik Torstensson
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
13 *
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
18 */
20 #include <string.h>
21 #include <math.h>
22 #include <assert.h>
23 #ifdef HAVE_UNISTD_H
24 #include <unistd.h>
25 #endif
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
40 #include <mono/utils/unlocked.h>
52 #ifdef MONO_XEN_OPT
54 #else
55 #define optimize_for_xen 0
56 #endif
61 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
63 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
65 /* The single step trampoline */
68 /* The breakpoint trampoline */
71 /* Offset between fp and the first argument in the callee */
72 #define ARGS_OFFSET 16
73 #define GP_SCRATCH_REG AMD64_R11
75 /* Max number of bblocks before we bail from using more advanced branch placement code */
76 #define MAX_BBLOCKS_FOR_BRANCH_OPTS 800
78 /*
79 * AMD64 register usage:
80 * - callee saved registers are used for global register allocation
81 * - %r11 is used for materializing 64 bit constants in opcodes
82 * - the rest is used for local allocation
83 */
85 /*
86 * Floating point comparison results:
87 * ZF PF CF
88 * A > B 0 0 0
89 * A < B 0 0 1
90 * A = B 1 0 0
91 * A > B 0 0 0
92 * UNORDERED 1 1 1
93 */
97 {
115 }
117 }
122 };
127 };
131 {
134 else
136 }
140 {
143 else
145 }
147 static gboolean
149 {
150 #if 0
152 #else
154 #endif
155 }
157 static gboolean
159 {
160 /* Skip REX */
165 }
167 static gboolean
169 {
174 }
176 void
178 {
180 }
182 static void
184 {
185 // NOTE: Sometimes code has just been generated, is not running yet,
186 // and has no alignment requirements. Sometimes it could be running while we patch it,
187 // and there are alignment requirements.
188 // FIXME Assert alignment.
192 /* Skip REX */
196 }
199 /* amd64_set_reg_template */
201 }
202 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
203 /* mov 0(%rip), %dreg */
208 }
210 /* call or jmp *<OFFSET>(%rip) */
211 // Patch the data, not the code.
214 }
215 else
217 }
219 void
221 {
223 }
225 #define DEBUG(a) if (cfg->verbose_level > 1) a
229 {
235 /* Since the same stack slot size is used for all arg */
236 /* types, it needs to be big enough to hold them all */
238 }
243 }
244 }
248 {
254 /* Since the same stack slot size is used for both float */
255 /* types, it needs to be big enough to hold them both */
257 }
259 /* A double register */
262 else
266 }
267 }
270 ARG_CLASS_NO_CLASS,
271 ARG_CLASS_MEMORY,
272 ARG_CLASS_INTEGER,
273 ARG_CLASS_SSE
276 static ArgumentClass
278 {
301 #ifdef TARGET_WIN32
303 #else
305 #endif
315 }
316 /* fall through */
324 }
326 }
329 }
331 /* Merge */
333 ;
340 else
344 }
351 /*
352 * collect_field_info_nested:
353 *
354 * Collect field info from KLASS recursively into FIELDS.
355 */
356 static void
357 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
358 {
367 collect_field_info_nested (mono_class_from_mono_type_internal (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
369 guint32 align;
370 StructFieldInfo f;
378 /* This can happen with .pack directives eg. 'fixed' arrays */
380 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
385 }
389 }
392 }
393 }
394 }
396 gpointer iter;
404 collect_field_info_nested (mono_class_from_mono_type_internal (field->type), fields_array, field->offset - MONO_ABI_SIZEOF (MonoObject), pinvoke, unicode);
407 StructFieldInfo f;
414 }
415 }
416 }
417 }
419 #ifdef TARGET_WIN32
421 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
422 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
424 static gboolean
425 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, const AMD64_Reg_No int_regs [], int int_reg_count, const AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
426 {
429 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
439 /* Pass parameter in integer register. */
445 /* Pass parameter in float register. */
446 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
450 }
455 }
458 }
460 static gboolean
461 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
462 {
463 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
464 }
466 static gboolean
467 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
468 {
469 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
470 }
472 static void
473 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
475 {
476 /* Windows x64 value type ABI.
477 *
478 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
479 *
480 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
481 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
482 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
483 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
484 *
485 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
486 *
487 * Integers/Float types smaller than or equal to 8 bytes
488 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
489 * Properly sized struct/unions (1,2,4,8)
490 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
491 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
492 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
493 */
495 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
499 /* Parameter cases. */
503 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
505 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
506 /* No more registers, fallback passing parameter on stack as value. */
507 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
509 /* Passing value directly on stack, so use size of value. */
515 }
517 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
519 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
520 /* No more registers, fallback passing address to parameter on stack. */
521 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
523 /* Passing an address to value on stack, so use size of register as argument size. */
529 }
530 }
532 /* Return value cases. */
536 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
538 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
540 /* Only RAX/XMM0 should be used to return valuetype. */
541 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
543 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
545 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
547 /* Only RAX should be used to return valuetype address. */
553 }
554 }
555 }
557 static void
558 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
559 {
563 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
566 /* Calculate argument class type and size of marshalled type. */
570 /* Calculate argument class type and size of managed type. */
572 }
574 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
578 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
580 }
582 /*
583 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
584 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
585 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
586 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
587 * it must be represented in call and cannot be dropped.
588 */
593 }
596 }
598 static void
601 {
604 ArgumentClass arg_class;
606 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
611 /* Only drop value type if its not an empty struct as input that must be represented in call */
612 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_info->pass_empty_struct && is_return)) {
616 /* Alocate storage for value type. */
617 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
618 }
619 }
623 static void
625 gboolean is_return,
627 {
628 #ifdef TARGET_WIN32
630 #else
632 /* Keep track of the size used in each quad so we can */
633 /* use the right size when copying args/return vars. */
646 /* We pass and return vtypes of size 8 in a register */
649 }
651 /* If this struct can't be split up naturally into 8-byte */
652 /* chunks (registers), pass it on the stack. */
659 }
660 /*
661 * Collect field information recursively to be able to
662 * handle nested structures.
663 */
673 }
674 }
680 }
683 /* Allways pass in memory */
692 }
696 else
705 /* Always pass in 1 or 2 integer registers */
708 /* Only the simplest cases are supported */
712 }
714 /*
715 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
716 * The X87 and SSEUP stuff is left out since there are no such types in
717 * the CLR.
718 */
723 }
734 }
739 ArgumentClass class1;
743 else
747 /* Unaligned field */
748 NOT_IMPLEMENTED;
749 }
751 /* Skip fields in other quad */
757 /* How far into this quad this data extends.*/
758 /* (8 is size of quad) */
762 }
763 /* Empty structs have a nonzero size, causing this assert to be hit */
767 }
768 }
772 /* Post merger cleanup */
776 /* Allocate registers */
777 {
783 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
802 else
805 }
816 }
824 }
825 }
829 /* Revert possible register assignments */
836 else
842 }
843 }
845 }
847 /*
848 * get_call_info:
849 *
850 * Obtain information about a call according to the calling convention.
851 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
852 * Draft Version 0.23" document for more information.
853 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
854 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
855 */
858 {
868 else
877 #ifdef TARGET_WIN32
878 /* Reserve space where the callee can save the argument registers */
880 #endif
882 /* return value */
917 }
921 }
922 /* fall through */
930 }
940 }
943 /*
944 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
945 * the first argument, allowing 'this' to be always passed in the first arg reg.
946 * Also do this if the first argument is a reference type, since virtual calls
947 * are sometimes made using calli without sig->hasthis set, like in the delegate
948 * invoke wrappers.
949 */
951 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
957 }
962 /* this */
969 }
970 }
976 /* Emit the signature cookie just before the implicit arguments */
978 }
984 #ifdef TARGET_WIN32
985 /* The float param registers and other param registers must be the same index on Windows x64.*/
990 #endif
993 /* We allways pass the sig cookie on the stack for simplicity */
994 /*
995 * Prevent implicit arguments + the sig cookie from being passed
996 * in registers.
997 */
1001 /* Emit the signature cookie just before the implicit arguments */
1003 }
1036 }
1038 /* gsharedvt arguments are passed by ref */
1042 else
1045 }
1046 /* fall through */
1064 /* gsharedvt arguments are passed by ref */
1069 else
1074 }
1075 }
1077 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1081 /* Emit the signature cookie just before the implicit arguments */
1083 }
1089 }
1091 static int
1093 {
1094 // Value types using one register doesn't need temp.
1098 }
1100 static gpointer
1102 {
1113 // Empty struct
1116 // Value type using one register can be stored
1117 // directly in its context gregs/fregs slot.
1127 }
1133 }
1134 }
1136 static void
1138 {
1142 /* Reconstruct the value type */
1156 }
1157 dest_cast++;
1158 }
1159 }
1161 static void
1163 {
1180 }
1181 src_cast++;
1182 }
1183 }
1185 void
1186 mono_arch_set_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1187 {
1190 gpointer storage;
1204 }
1205 }
1216 }
1222 else
1228 }
1231 }
1233 void
1234 mono_arch_set_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1235 {
1238 gpointer storage;
1253 else
1259 }
1260 #ifdef TARGET_WIN32
1261 // Windows x64 ABI ainfo implementation includes info on how to return value type address.
1262 // back to caller.
1266 }
1267 #endif
1270 }
1272 void
1273 mono_arch_get_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1274 {
1277 gpointer storage;
1285 }
1286 }
1295 }
1304 }
1307 }
1310 }
1312 void
1313 mono_arch_get_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1314 {
1318 gpointer storage;
1320 /* No return value */
1328 /* The return values were stored directly at address passed in reg */
1337 }
1339 }
1342 }
1344 /*
1345 * mono_arch_get_argument_info:
1346 * @csig: a method signature
1347 * @param_count: the number of parameters to consider
1348 * @arg_info: an array to store the result infos
1349 *
1350 * Gathers information on parameters such as size, alignment and
1351 * padding. arg_info should be large enought to hold param_count + 1 entries.
1352 *
1353 * Returns the size of the argument area on the stack.
1354 */
1355 int
1356 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1357 {
1362 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1365 }
1369 /* FIXME: */
1371 }
1376 }
1378 #ifndef DISABLE_JIT
1379 gboolean
1380 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
1381 {
1387 // Limit stack_usage to 1G. Assume 32bit limits when we move parameters.
1391 // valuetype parameters are address of local
1397 }
1403 }
1406 /*
1407 * Initialize the cpu to execute managed code.
1408 */
1409 void
1411 {
1412 #ifndef _MSC_VER
1413 guint16 fpcw;
1415 /* spec compliance requires running with double precision */
1421 #else
1422 /* TODO: This is crashing on Win64 right now.
1423 * _control87 (_PC_53, MCW_PC);
1424 */
1425 #endif
1426 }
1428 /*
1429 * Initialize architecture specific code.
1430 */
1431 void
1433 {
1436 }
1438 /*
1439 * Cleanup architecture specific code.
1440 */
1441 void
1443 {
1444 }
1446 /*
1447 * This function returns the optimizations supported on this cpu.
1448 */
1449 guint32
1451 {
1461 else
1465 }
1468 }
1470 /*
1471 * This function test for all SSE functions supported.
1472 *
1473 * Returns a bitmask corresponding to all supported versions.
1474 *
1475 */
1476 guint32
1478 {
1503 }
1505 MonoCPUFeatures
1507 {
1517 }
1519 #ifndef DISABLE_JIT
1521 GList *
1523 {
1531 /* unused vars */
1543 }
1544 }
1549 }
1551 /**
1552 * mono_arch_compute_omit_fp:
1553 * Determine whether the frame pointer can be eliminated.
1554 */
1555 static void
1557 {
1574 /*
1575 * FIXME: Remove some of the restrictions.
1576 */
1585 /*
1586 if (cfg->method->save_lmf)
1587 cfg->arch.omit_fp = FALSE;
1588 */
1600 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1601 /*
1602 * The stack offset can only be determined when the frame
1603 * size is known.
1604 */
1606 }
1607 }
1615 }
1616 }
1618 GList *
1620 {
1628 /* We use the callee saved registers for global allocation */
1634 #ifdef TARGET_WIN32
1637 #endif
1640 }
1642 /*
1643 * mono_arch_regalloc_cost:
1644 *
1645 * Return the cost, in number of memory references, of the action of
1646 * allocating the variable VMV into a register during global register
1647 * allocation.
1648 */
1649 guint32
1651 {
1655 /* The register is already saved */
1656 /* substract 1 for the invisible store in the prolog */
1658 else
1659 /* push+pop */
1661 }
1663 /*
1664 * mono_arch_fill_argument_info:
1665 *
1666 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1667 * of the method.
1668 */
1669 void
1671 {
1681 /*
1682 * Contrary to mono_arch_allocate_vars (), the information should describe
1683 * where the arguments are at the beginning of the method, not where they can be
1684 * accessed during the execution of the method. The later makes no sense for the
1685 * global register allocator, since a variable can be in more than one location.
1686 */
1703 }
1723 /* Dummy */
1728 }
1729 }
1730 }
1732 void
1734 {
1750 /*
1751 * We use the ABI calling conventions for managed code as well.
1752 * Exception: valuetypes are only sometimes passed or returned in registers.
1753 */
1755 /*
1756 * The stack looks like this:
1757 * <incoming arguments passed on the stack>
1758 * <return value>
1759 * <lmf/caller saved registers>
1760 * <locals>
1761 * <spill area>
1762 * <localloc area> -> grows dynamically
1763 * <params area>
1764 */
1771 /* Locals are allocated backwards from %fp */
1774 }
1778 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1781 }
1785 /* Reserve space for callee saved registers */
1789 }
1804 /* The register is volatile */
1813 }
1817 }
1820 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1829 }
1833 }
1834 }
1836 /* Allocate locals */
1837 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1841 }
1848 }
1857 else
1859 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1860 }
1861 }
1868 }
1876 /* FIXME: Allocate volatile arguments to registers */
1880 /*
1881 * Under AMD64, all registers used to pass arguments to functions
1882 * are volatile across calls.
1883 * FIXME: Optimize this.
1884 */
1885 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1898 }
1913 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1922 }
1926 }
1932 }
1934 NOT_IMPLEMENTED;
1935 }
1937 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1940 /* These arguments are saved to the stack in the prolog */
1944 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (target_mgreg_t) : sizeof (target_mgreg_t);
1945 // Arguments are yet supported by the stack map creation code
1946 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1948 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (target_mgreg_t) : sizeof (target_mgreg_t);
1950 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1951 }
1952 }
1953 }
1954 }
1957 }
1959 void
1961 {
1974 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1979 }
1980 }
1989 }
1997 }
2004 }
2005 }
2007 static void
2008 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2009 {
2039 }
2040 }
2042 static int
2044 {
2047 #if defined(MONO_ARCH_ILP32)
2049 #else
2051 #endif
2058 }
2061 }
2063 static void
2065 {
2070 NOT_IMPLEMENTED;
2074 /*
2075 * mono_ArgIterator_Setup assumes the signature cookie is
2076 * passed first and all the arguments which were before it are
2077 * passed on the stack after the signature. So compensate by
2078 * passing a different signature.
2079 */
2080 tmp_sig = mono_metadata_signature_dup_full (m_class_get_image (cfg->method->klass), call->signature);
2083 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2088 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2089 }
2091 #ifdef ENABLE_LLVM
2092 static LLVMArgStorage
2094 {
2106 }
2107 }
2109 LLVMCallInfo*
2111 {
2124 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2126 /*
2127 * LLVM always uses the native ABI while we use our own ABI, the
2128 * only difference is the handling of vtypes:
2129 * - we only pass/receive them in registers in some cases, and only
2130 * in 1 or 2 integer registers.
2131 */
2145 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2146 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2150 }
2156 }
2159 /* Vtype returned using a hidden argument */
2166 }
2173 else
2190 else
2195 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2196 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2200 }
2204 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2218 }
2219 }
2222 }
2223 #endif
2225 void
2227 {
2240 /* We shouldn't be called in the llvm case */
2243 }
2245 /*
2246 * Emit all arguments which are passed on the stack to prevent register
2247 * allocation problems.
2248 */
2257 else
2261 //XXX what about ArgGSharedVtOnStack here?
2262 // FIXME tailcall is not always yet initialized.
2269 else
2273 }
2278 }
2279 }
2280 }
2282 /*
2283 * Emit all parameters passed in registers in non-reverse order for better readability
2284 * and to help the optimization in emit_prolog ().
2285 */
2293 }
2304 else
2310 /* Already done */
2322 // FIXME tailcall is not always yet initialized.
2324 /* Already emitted above */
2326 //FIXME what about ArgGSharedVtOnStack ?
2327 // FIXME tailcall is not always yet initialized.
2333 }
2335 guint32 align;
2336 guint32 size;
2341 /*
2342 * Other backends use mono_type_stack_size (), but that
2343 * aligns the size to 8, which is larger than the size of
2344 * the source, leading to reads of invalid memory if the
2345 * source is at the end of address space.
2346 */
2348 }
2351 /* Avoid asserts in emit_memcpy () */
2352 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2353 /* Continue normally */
2354 }
2366 }
2368 }
2371 }
2374 /* Emit the signature cookie just before the implicit arguments */
2376 }
2378 /* Handle the case where there are no implicit arguments */
2385 /*
2386 * Tell the JIT to use a more efficient calling convention: call using
2387 * OP_CALL, compute the result location after the call, and save the
2388 * result there.
2389 */
2391 /*
2392 * Nullify the instruction computing the vret addr to enable
2393 * future optimizations.
2394 */
2399 NOT_IMPLEMENTED;
2400 /*
2401 * The valuetype is in RAX:RDX after the call, need to be copied to
2402 * the stack. Push the address here, so the call instruction can
2403 * access it.
2404 */
2407 /* Prevent it from being register allocated or optimized away */
2409 }
2412 }
2424 }
2427 }
2432 }
2435 }
2437 void
2439 {
2455 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2457 }
2473 }
2474 }
2479 }
2481 }
2486 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2510 }
2512 }
2514 /* Pass by addr */
2529 // FIXME: Code growth
2531 }
2535 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, m_class_get_byval_arg (ins->klass));
2536 }
2537 }
2538 }
2540 void
2542 {
2548 else
2554 }
2557 }
2561 #define EMIT_COND_BRANCH(ins,cond,sign) \
2562 if (ins->inst_true_bb->native_offset) { \
2563 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2564 } else { \
2565 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2566 if (optimize_branch_pred && \
2567 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2568 x86_branch8 (code, cond, 0, sign); \
2569 else \
2570 x86_branch32 (code, cond, 0, sign); \
2571 }
2579 static gboolean
2581 {
2594 }
2609 }
2610 }
2613 }
2615 /*
2616 * mono_arch_dyn_call_prepare:
2617 *
2618 * Return a pointer to an arch-specific structure which contains information
2619 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2620 * supported for SIG.
2621 * This function is equivalent to ffi_prep_cif in libffi.
2622 */
2623 MonoDynCallInfo*
2625 {
2635 }
2638 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2648 info->nstack_args = MAX (info->nstack_args, (ainfo->offset / sizeof (target_mgreg_t)) + (ainfo->arg_size / sizeof (target_mgreg_t)));
2652 }
2653 }
2664 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type_internal (t))) {
2669 /* Nullables need a temporary buffer, its stored at the end of DynCallArgs.regs after the stack args */
2672 }
2673 }
2677 }
2678 }
2682 /* Align to 16 bytes */
2687 }
2689 /*
2690 * mono_arch_dyn_call_free:
2691 *
2692 * Free a MonoDynCallInfo structure.
2693 */
2694 void
2696 {
2701 }
2703 int
2705 {
2708 /* Extend the 'regs' field dynamically */
2709 return sizeof (DynCallArgs) + (ainfo->nstack_args * sizeof (target_mgreg_t)) + ainfo->nullable_area;
2710 }
2712 #define PTR_TO_GREG(ptr) ((host_mgreg_t)(ptr))
2713 #define GREG_TO_PTR(greg) ((gpointer)(greg))
2715 /*
2716 * mono_arch_get_start_dyn_call:
2717 *
2718 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2719 * store the result into BUF.
2720 * ARGS should be an array of pointers pointing to the arguments.
2721 * RET should point to a memory buffer large enought to hold the result of the
2722 * call.
2723 * This function should be as fast as possible, any work which does not depend
2724 * on the actual values of the arguments should be done in
2725 * mono_arch_dyn_call_prepare ().
2726 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2727 * libffi.
2728 */
2729 void
2731 {
2752 }
2762 /* Stored after the stack arguments */
2769 }
2771 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2789 }
2794 }
2801 #if !defined(MONO_ARCH_ILP32)
2804 #endif
2807 #if defined(MONO_ARCH_ILP32)
2812 #endif
2840 }
2842 }
2849 }
2855 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type_internal (t))) {
2867 }
2869 /* The argument pointed to by arg is either a boxed vtype or null */
2873 /* Fall though */
2876 /* Fall through */
2877 }
2896 }
2905 }
2906 }
2910 // In DYNCALL use case value types are already copied when included in parameter array.
2911 // Currently no need to make an extra temporary value type on stack for this use case.
2921 }
2923 }
2926 }
2927 }
2928 }
2930 /*
2931 * mono_arch_finish_dyn_call:
2932 *
2933 * Store the result of a dyn call into the return value buffer passed to
2934 * start_dyn_call ().
2935 * This function should be as fast as possible, any work which does not depend
2936 * on the actual values of the arguments should be done in
2937 * mono_arch_dyn_call_prepare ().
2938 */
2939 void
2941 {
2995 /* Fall through */
2996 }
2998 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2999 /* Nothing to do */
3018 }
3019 }
3020 }
3024 }
3025 }
3027 #undef PTR_TO_GREG
3028 #undef GREG_TO_PTR
3030 /* emit an exception if condition is fail */
3031 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
3032 do { \
3033 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3034 if (tins == NULL) { \
3035 mono_add_patch_info (cfg, code - cfg->native_code, \
3036 MONO_PATCH_INFO_EXC, exc_name); \
3037 x86_branch32 (code, cond, 0, signed); \
3038 } else { \
3039 EMIT_COND_BRANCH (tins, cond, signed); \
3040 } \
3041 } while (0);
3043 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3044 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3045 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3046 amd64_ ##op (code); \
3047 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3048 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3049 } while (0);
3051 #ifndef DISABLE_JIT
3054 {
3056 MonoJumpInfoTarget patch;
3058 // FIXME? This is similar to mono_call_to_patch, except it favors MONO_PATCH_INFO_ABS over call->jit_icall_id.
3070 }
3072 /*
3073 * FIXME: Add support for thunks
3074 */
3075 {
3078 /*
3079 * Indirect calls are expensive so try to make a near call if possible.
3080 * The caller memory is allocated by the code manager so it is
3081 * guaranteed to be at a 32 bit offset.
3082 */
3086 /* The target is in memory allocated using the code manager */
3094 /* The callee might be an AOT method */
3097 /* The target is in malloc-ed memory */
3100 /*
3101 * The call might go directly to a native function without
3102 * the wrapper.
3103 */
3108 }
3122 /*
3123 * This is not really an optimization, but required because the
3124 * generic class init trampolines use R11 to pass the vtable.
3125 */
3127 }
3134 // Change patch from MONO_PATCH_INFO_ABS to MONO_PATCH_INFO_JIT_ICALL_ID.
3139 /* No wrapper */
3143 /* ?See the comment in mono_codegen ()? */
3145 }
3146 }
3150 }
3151 }
3152 }
3155 /* These methods are allocated using malloc */
3158 #ifdef MONO_ARCH_NOMAP32BIT
3160 #endif
3161 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3168 }
3171 /*
3172 * Align the call displacement to an address divisible by 4 so it does
3173 * not span cache lines. This is required for code patching to work on SMP
3174 * systems.
3175 */
3179 }
3182 }
3188 }
3192 }
3193 }
3198 }
3200 static int
3202 {
3210 }
3213 }
3216 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3218 /*
3219 * mono_arch_peephole_pass_1:
3220 *
3221 * Perform peephole opts which should/can be performed before local regalloc
3222 */
3223 void
3225 {
3236 /*
3237 * X86_LEA is like ADD, but doesn't have the
3238 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3239 * its operand to 64 bit.
3240 */
3243 }
3250 /*
3251 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3252 * the latter has length 2-3 instead of 6 (reverse constant
3253 * propagation). These instruction sequences are very common
3254 * in the initlocals bblock.
3255 */
3257 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3260 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3261 /* Continue */
3262 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3264 /* Continue */
3266 /* Continue */
3269 }
3270 }
3271 }
3275 /* OP_COMPARE_IMM (reg, 0)
3276 * -->
3277 * OP_AMD64_TEST_NULL (reg)
3278 */
3287 /*
3288 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3289 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3290 * -->
3291 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3292 * OP_COMPARE_IMM reg, imm
3293 *
3294 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3295 */
3302 /* check if we can remove cmp reg,0 with test null */
3305 }
3308 }
3311 }
3312 }
3314 void
3316 {
3324 /* reg = 0 -> XOR (reg, reg) */
3325 /* XOR sets cflags on x86, so we cant do it always */
3330 /* Fall through */
3333 }
3334 }
3336 /*
3337 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3338 * 0 result into 64 bits.
3339 */
3342 }
3343 /* Fall through */
3348 /*
3349 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3350 * the latter has length 2-3 instead of 6 (reverse constant
3351 * propagation). These instruction sequences are very common
3352 * in the initlocals bblock.
3353 */
3355 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3358 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3359 /* Continue */
3360 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3362 /* Continue */
3364 /* Continue */
3367 }
3368 }
3369 }
3379 }
3382 }
3383 }
3385 #define NEW_INS(cfg,ins,dest,op) do { \
3386 MONO_INST_NEW ((cfg), (dest), (op)); \
3387 (dest)->cil_code = (ins)->cil_code; \
3388 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3389 } while (0)
3391 #define NEW_SIMD_INS(cfg,ins,dest,op,d,s1,s2) do { \
3392 MONO_INST_NEW ((cfg), (dest), (op)); \
3393 (dest)->cil_code = (ins)->cil_code; \
3394 (dest)->dreg = d; \
3395 (dest)->sreg1 = s1; \
3396 (dest)->sreg2 = s2; \
3397 (dest)->type = STACK_VTYPE; \
3398 (dest)->klass = ins->klass; \
3399 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3400 } while (0)
3402 static int
3404 {
3421 }
3422 }
3424 static int
3426 {
3443 }
3444 }
3446 static int
3448 {
3462 }
3463 }
3465 static int
3467 {
3484 }
3485 }
3487 static int
3489 {
3497 //case MONO_TYPE_U8:
3498 // return OP_PMAXQ_UN; // AVX
3502 }
3503 }
3505 static int
3507 {
3524 }
3525 }
3527 static int
3529 {
3543 // case MONO_TYPE_I8: // AVX
3544 // case MONO_TYPE_U8:
3548 }
3549 }
3551 static int
3553 {
3567 // case MONO_TYPE_I8: // AVX
3568 // case MONO_TYPE_U8:
3572 }
3573 }
3575 static void
3576 emit_simd_comp_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3577 {
3580 if (!mono_hwcap_x86_has_sse42 && (ins->inst_c1 == MONO_TYPE_I8 || ins->inst_c1 == MONO_TYPE_U8)) {
3590 }
3591 }
3593 static void
3594 emit_simd_gt_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2);
3596 static void
3597 emit_simd_gt_un_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3598 {
3609 USE_MAX: {
3610 // dreg = max(sreg1, sreg2) != sreg2
3621 }
3624 USE_SIGNED_GT: {
3625 // convert to signed integer by subtracting (1 << (size - 1)) from each operand
3626 // and then use signed comparison
3640 }
3641 }
3642 }
3644 static void
3645 emit_simd_gt_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3646 {
3650 // Decompose 64-bit greater than to 32-bit
3651 //
3652 // t = (v1 > v2)
3653 // u = (v1 == v2)
3654 // v = (v1 > v2) unsigned
3655 //
3656 // z = shuffle(t, (3, 3, 1, 1))
3657 // t1 = shuffle(v, (2, 2, 0, 0))
3658 // u1 = shuffle(u, (3, 3, 1, 1))
3659 // w = and(t1, u1)
3660 // result = bitwise_or(z, w)
3683 }
3684 }
3686 static void
3687 emit_simd_min_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3688 {
3692 // SSE2, so always available
3695 // Decompose to t = (s1 > s2), d = (s1 & !t) | (s2 & t)
3701 else
3707 // SSE 4.1 has byte- and dword- operations
3709 }
3710 }
3712 static void
3713 emit_simd_max_op (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst *ins, int type, int dreg, int sreg1, int sreg2)
3714 {
3718 // SSE2, so always available
3721 // Decompose to t = (s1 > s2), d = (s1 & t) | (s2 & !t)
3727 else
3733 // SSE 4.1 has byte- and dword- operations
3735 }
3736 }
3738 /*
3739 * mono_arch_lowering_pass:
3740 *
3741 * Converts complex opcodes into simpler ones so that each IR instruction
3742 * corresponds to one machine instruction.
3743 */
3744 void
3746 {
3749 /*
3750 * FIXME: Need to add more instructions, but the current machine
3751 * description can't model some parts of the composite instructions like
3752 * cdq.
3753 */
3773 }
3775 #ifndef MONO_ARCH_ILP32
3777 #endif
3779 /* Don't generate memindex opcodes (to simplify */
3780 /* read sandboxing) */
3787 }
3789 #ifndef MONO_ARCH_ILP32
3791 #endif
3799 }
3801 #ifdef MONO_ARCH_SIMD_INTRINSICS
3823 }
3840 }
3846 {
3862 }
3887 }
3897 NEW_SIMD_INS (cfg, ins, temp, simd_type_to_max_un_op (ins->inst_c1), temp_reg1, ins->sreg1, ins->sreg2);
3909 }
3920 }
3925 }
3930 }
3936 {
3946 }
3949 }
3954 }
3958 {
4003 }
4005 }
4011 // TODO
4014 }
4015 #endif
4018 }
4019 }
4022 }
4024 static const int
4025 branch_cc_table [] = {
4029 };
4031 /* Maps CMP_... constants to X86_CC_... constants */
4032 static const int
4033 cc_table [] = {
4036 };
4038 static const int
4039 cc_signed_table [] = {
4042 };
4044 /*#include "cprop.c"*/
4047 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
4048 {
4049 // Use 8 as register size to get Nan/Inf conversion to uint result truncated to 0
4052 else
4060 }
4064 {
4068 #if defined(TARGET_WIN32)
4070 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4073 #endif
4078 /*
4079 * Under Windows:
4080 * If requested stack size is larger than one page,
4081 * perform stack-touch operation
4082 */
4083 /*
4084 * Generate stack probe code.
4085 * Under Windows, it is necessary to allocate one page at a time,
4086 * "touching" stack after each successful sub-allocation. This is
4087 * because of the way stack growth is implemented - there is a
4088 * guard page before the lowest stack page that is currently commited.
4089 * Stack normally grows sequentially so OS traps access to the
4090 * guard page and commits more pages when needed.
4091 */
4112 }
4113 else
4121 }
4125 }
4129 }
4149 }
4151 }
4155 {
4157 guint32 quad;
4159 /* Move return value to the target register */
4160 /* FIXME: do this in the local reg allocator */
4176 }
4180 }
4182 }
4199 /* Load the destination address */
4201 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
4206 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof (target_mgreg_t)), cinfo->ret.pair_regs [quad], sizeof (target_mgreg_t));
4217 NOT_IMPLEMENTED;
4218 }
4219 }
4220 }
4222 }
4225 }
4229 #ifdef TARGET_MACH
4231 #endif
4233 gboolean
4235 {
4236 #ifdef TARGET_MACH
4249 /*
4250 * We're looking for these two instructions:
4251 *
4252 * mov %gs:[offset](,%rdi,8),%rax
4253 * retq
4254 */
4267 /*
4268 * Apple now loads a different version of pthread_getspecific when launched from Xcode
4269 * For that version we're looking for these instructions:
4270 *
4271 * pushq %rbp
4272 * movq %rsp, %rbp
4273 * mov %gs:[offset](,%rdi,8),%rax
4274 * popq %rbp
4275 * retq
4276 */
4294 }
4298 #elif defined(TARGET_ANDROID)
4300 #else
4304 #endif
4305 }
4307 int
4309 {
4310 #ifdef TARGET_OSX
4312 #else
4315 #endif
4316 }
4318 /*
4319 * \param code buffer to store code to
4320 * \param dreg hard register where to place the result
4321 * \param tls_offset offset info
4322 * \return a pointer to the end of the stored code
4323 *
4324 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
4325 * the dreg register the item in the thread local storage identified
4326 * by tls_offset.
4327 */
4330 {
4331 #ifdef TARGET_WIN32
4339 /* Load TEB->TlsExpansionSlots */
4347 }
4348 #elif defined(TARGET_MACH)
4351 #else
4359 }
4360 #endif
4362 }
4366 {
4367 #ifdef TARGET_WIN32
4369 #elif defined(TARGET_MACH)
4372 #else
4376 #endif
4378 }
4380 /*
4381 * emit_setup_lmf:
4382 *
4383 * Emit code to initialize an LMF structure at LMF_OFFSET.
4384 */
4387 {
4388 /*
4389 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4390 */
4391 /*
4392 * sp is saved right before calls but we need to save it here too so
4393 * async stack walks would work.
4394 */
4395 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4396 /* Save rbp */
4397 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4399 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
4401 /* These can't contain refs */
4402 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
4403 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
4404 /* These are handled automatically by the stack marking code */
4405 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
4408 }
4410 #ifdef TARGET_WIN32
4412 #define TEB_LAST_ERROR_OFFSET 0x68
4416 {
4417 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
4421 }
4423 #else
4427 {
4429 }
4431 #endif
4433 /* benchmark and set based on cpu */
4434 #define LOOP_ALIGNMENT 8
4435 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
4437 #ifndef DISABLE_JIT
4441 {
4442 #ifndef TARGET_WIN32
4445 else
4447 #endif
4449 }
4452 amd64_handle_varargs_call (MonoCompile *cfg, guint8 *code, MonoCallInst *call, gboolean free_rax)
4453 {
4454 #ifdef TARGET_WIN32
4456 #else
4457 /*
4458 * The AMD64 ABI forces callers to know about varargs.
4459 */
4462 // deliberatly nothing -- but nreg = 0 and do not return
4463 } else if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE && m_class_get_image (cfg->method->klass) != mono_defaults.corlib) {
4464 /*
4465 * Since the unmanaged calling convention doesn't contain a
4466 * 'vararg' entry, we have to treat every pinvoke call as a
4467 * potential vararg call.
4468 */
4473 }
4478 }
4480 #endif
4481 }
4483 void
4485 {
4490 /* Fix max_offset estimate for each successor bb */
4491 gboolean optimize_branch_pred = (cfg->opt & MONO_OPT_BRANCH) && (cfg->max_block_num < MAX_BBLOCKS_FOR_BRANCH_OPTS);
4499 }
4500 }
4504 /* set alignment depending on cpu */
4507 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
4511 }
4512 }
4521 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4559 /* In AMD64 NaCl, pointers are 4 bytes, */
4560 /* so STORE_* != STOREI8_*. Likewise below. */
4562 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4571 /* In NaCl, this could be a PCONST type, which could */
4572 /* mean a pointer type was copied directly into the */
4573 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4574 /* the value would be 0x00000000FFFFFFFF which is */
4575 /* not proper for an imm32 unless you cast it. */
4577 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4584 #ifdef MONO_ARCH_ILP32
4585 /* In ILP32, pointers are 4 bytes, so separate these */
4586 /* cases, use literal 8 below where we really want 8 */
4590 #endif
4592 // FIXME: Decompose this earlier
4598 }
4605 // FIXME: Decompose this earlier
4611 }
4618 /* For NaCl, pointers are 4 bytes, so separate these */
4619 /* cases, use literal 8 below where we really want 8 */
4625 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4628 /* Use literal 8 instead of sizeof pointer or */
4629 /* register, we really want 8 for this opcode */
4640 /* The cpu zero extends the result into 64 bits */
4641 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4647 /* The cpu zero extends the result into 64 bits */
4648 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4675 /* Clean out the upper word */
4686 #if defined(MONO_ARCH_ILP32)
4687 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4691 #endif
4723 /* FIXME: Make a 64 version too */
4724 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4728 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4732 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4736 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4740 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4743 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4746 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4749 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4755 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4774 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4777 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4780 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4784 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4787 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4813 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4816 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4819 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4825 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4830 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4834 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4838 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4842 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4846 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4876 /* Load ss_tramp_var */
4877 /* This is equal to &ss_trampoline */
4879 /* Load the trampoline address */
4881 /* Call it if it is non-null */
4887 }
4889 /*
4890 * This is the address which is saved in seq points,
4891 */
4896 guint32 val;
4900 /* Load info var */
4903 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4908 /* Call the trampoline */
4915 /*
4916 * Emit a test+branch against a constant, the constant will be overwritten
4917 * by mono_arch_set_breakpoint () to cause the test to fail.
4918 */
4926 /* Load bp_tramp_var */
4927 /* This is equal to &bp_trampoline */
4929 /* Call the trampoline */
4932 }
4933 /*
4934 * Add an additional nop so skipping the bp doesn't cause the ip to point
4935 * to another IL offset.
4936 */
4939 }
4992 /* MOV r1, r2 */
4993 /* ADD r1, r1 */
4999 /* LEA r1, [r2 + r2*2] */
5003 /* LEA r1, [r2 + r2*4] */
5007 /* LEA r1, [r2 + r2*2] */
5008 /* ADD r1, r1 */
5013 /* LEA r1, [r2 + r2*8] */
5017 /* LEA r1, [r2 + r2*4] */
5018 /* ADD r1, r1 */
5023 /* LEA r1, [r2 + r2*2] */
5024 /* SHL r1, 2 */
5029 /* LEA r1, [r2 + r2*4] */
5030 /* LEA r1, [r1 + r1*4] */
5035 /* LEA r1, [r2 + r2*4] */
5036 /* SHL r1, 2 */
5037 /* LEA r1, [r1 + r1*4] */
5045 }
5047 }
5050 /* Regalloc magic makes the div/rem cases the same */
5058 }
5069 }
5080 }
5091 }
5224 /* the mul operation and the exception check should most likely be split */
5227 /*g_assert (ins->sreg2 == X86_EAX);
5228 g_assert (ins->dreg == X86_EAX);*/
5234 /* no need to save since we're going to store to it anyway */
5238 }
5241 }
5246 }
5250 }
5252 /* save before the check since pop and mov don't change the flags */
5261 }
5288 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5312 /* This needs to operate on 64 bit values */
5313 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
5327 else
5348 }
5350 }
5355 }
5358 // This opcode helps compute sizes, i.e.
5359 // of the subsequent OP_TAILCALL, but contributes no code.
5377 // FIXME hardcoding RAX here is not ideal.
5393 // FIXME Patch data instead of code.
5399 }
5400 }
5402 /* Restore callee saved registers */
5408 }
5413 // FIXME:
5415 NOT_IMPLEMENTED;
5418 /* Copy arguments on the stack to our argument area */
5419 // FIXME use rep mov for constant code size, before nonvolatiles
5420 // restored, first saving rsi, rdi into volatiles
5424 }
5426 #ifdef TARGET_WIN32
5430 #else
5432 #endif
5433 }
5435 #ifdef TARGET_WIN32
5436 // Redundant REX byte indicates a tailcall to the native unwinder. It means nothing to the processor.
5437 // https://github.com/dotnet/coreclr/blob/966dabb5bb3c4bf1ea885e1e8dc6528e8c64dc4f/src/unwinder/amd64/unwinder_amd64.cpp#L1394
5438 // FIXME This should be jmp rip+32 for AOT direct to same assembly.
5439 // FIXME This should be jmp [rip+32] for AOT direct to not-same assembly (through data).
5440 // FIXME This should be jmp [rip+32] for JIT direct -- patch data instead of code.
5441 // This is only close to ideal for tailcall_membase, and even then it should
5442 // have a more dynamic register allocation.
5445 #else
5446 // NT does not have varargs rax use, and NT ABI does not have red zone.
5447 // Use red-zone mov/jmp instead of push/ret to preserve call/ret speculation stack.
5448 // FIXME Just like NT the direct cases are are not ideal.
5452 #endif
5456 }
5458 /* ensure ins->sreg1 is not NULL */
5465 }
5493 }
5523 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5525 /* r10 = ftn */
5528 /* Save args buffer */
5531 /* Set fp arg regs */
5532 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (target_mgreg_t));
5537 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
5540 /* Allocate param area */
5541 /* This doesn't need to be freed since OP_DYN_CALL is never called in a loop */
5542 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
5545 /* Set stack args */
5546 /* rax/rcx/rdx/r8/r9 is scratch */
5551 amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
5553 amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof (target_mgreg_t)));
5569 /* Set argument registers */
5571 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof (target_mgreg_t)), sizeof (target_mgreg_t));
5573 /* Make the call */
5579 /* Save result */
5582 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5583 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
5585 }
5588 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5590 }
5615 else
5626 }
5632 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
5642 }
5645 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5657 /* keep alignment */
5685 }
5689 }
5693 }
5700 }
5707 }
5709 /* Align stack */
5713 /*
5714 * ins->inst_eh_blocks and bb->clause_holes are part of same GList.
5715 * Holes from bb->clause_holes will be added separately for the entire
5716 * basic block. Add only the rest of them.
5717 */
5720 /* Restore stack alignment */
5724 /* Even though we're saving RSP, use sizeof */
5725 /* gpointer because spvar is of type IntPtr */
5726 /* see: mono_create_spvar_for_region */
5728 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5734 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5735 }
5737 }
5740 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5743 }
5746 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5747 /* The local allocator will put the result into RAX */
5750 }
5759 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5760 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5761 //break;
5769 else
5771 }
5797 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5820 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5837 /* floating point opcodes */
5843 }
5847 }
5849 }
5856 else
5858 }
5864 }
5866 }
5877 /* This requires a double->single conversion */
5879 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5880 }
5888 }
5896 }
5907 }
5918 }
5963 // Use 8 as register size to get Nan/Inf conversion result truncated to 0
5981 /* Based on gcc code */
5985 /* Positive case */
5990 /* Negative case */
5991 /* Save to the red zone */
6001 /* Restore */
6006 }
6031 }
6064 }
6073 }
6099 }
6152 /*
6153 * The two arguments are swapped because the fbranch instructions
6154 * depend on this for the non-sse case to work.
6155 */
6159 /*
6160 * FIXME: Get rid of this.
6161 * The two arguments are swapped because the fbranch instructions
6162 * depend on this for the non-sse case to work.
6163 */
6168 /* zeroing the register at the start results in
6169 * shorter and faster code (we can also remove the widening op)
6170 */
6189 }
6191 }
6194 /* zeroing the register at the start results in
6195 * shorter and faster code (we can also remove the widening op)
6196 */
6211 }
6213 }
6223 }
6226 /* zeroing the register at the start results in
6227 * shorter and faster code (we can also remove the widening op)
6228 */
6240 }
6242 }
6252 }
6283 }
6308 }
6315 }
6317 }
6343 }
6365 }
6367 }
6374 }
6376 /* Branch if C013 != 100 */
6377 /* branch if !ZF or (PF|CF) */
6394 /* skip branch if C1=1 */
6397 /* branch if (C0 | C3) = 1 */
6403 }
6406 /* Branch if C013 == 100 or 001 */
6409 /* skip branch if C1=1 */
6412 /* branch if (C0 | C3) = 1 */
6416 }
6418 /* Branch if C013 == 000 */
6422 /* Branch if C013=000 or 100 */
6425 /* skip branch if C1=1 */
6428 /* branch if C0=0 */
6432 }
6434 /* Branch if C013 != 001 */
6439 /* Transfer value to the fp stack */
6457 }
6461 }
6466 }
6478 /* dreg contains the old value, add with sreg2 value */
6485 }
6490 /* LOCK prefix is implied. */
6495 }
6498 guint32 size;
6502 else
6505 /*
6506 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
6507 * an explanation of how this works.
6508 */
6519 }
6523 }
6527 }
6531 }
6535 }
6539 }
6543 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
6545 }
6552 }
6554 }
6558 }
6586 }
6593 }
6599 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6600 }
6605 }
6616 }
6622 gpointer card_table_mask;
6629 /*If either point to the stack we can simply avoid the WB. This happens due to
6630 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6631 */
6635 /*
6636 * We need one register we can clobber, we choose EDX and make sreg1
6637 * fixed EAX to work around limitations in the local register allocator.
6638 * sreg2 might get allocated to EDX, but that is not a problem since
6639 * we use it before clobbering EDX.
6640 */
6643 /*
6644 * This is the code we produce:
6645 *
6646 * edx = value
6647 * edx >>= nursery_shift
6648 * cmp edx, (nursery_start >> nursery_shift)
6649 * jne done
6650 * edx = ptr
6651 * edx >>= card_table_shift
6652 * edx += cardtable
6653 * [edx] = 1
6654 * done:
6655 */
6662 /*
6663 * The value we need to compare against is 64 bits, so we need
6664 * another spare register. We use RBX, which we save and
6665 * restore.
6666 */
6673 }
6675 }
6681 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6689 }
6690 #ifdef MONO_ARCH_SIMD_INTRINSICS
6691 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
7084 /*TODO: This is appart of the sse spec but not added
7085 case OP_PSARQ:
7086 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
7087 break;
7088 case OP_PSARQ_REG:
7089 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
7090 break;
7091 */
7136 }
7147 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
7148 if (ins->inst_c0)
7149 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
7156 else
7166 /*sreg1 is the extracted ireg (scratch)
7167 /sreg2 is the to be inserted ireg (scratch)
7168 /dreg is the xreg to receive the value*/
7170 /*clear the bits from the extracted word*/
7172 /*shift the value to insert if needed*/
7175 /*join them together*/
7188 else
7197 else
7204 else
7212 else
7220 else
7224 }
7229 else
7253 /*FIXME the peephole pass should have killed this*/
7288 }
7310 }
7320 #endif
7337 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
7340 }
7343 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
7346 }
7355 }
7372 amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (target_mgreg_t), i, sizeof (target_mgreg_t));
7377 }
7382 }
7385 }
7389 G_BEGIN_DECLS
7392 G_END_DECLS
7394 void
7396 {
7397 /* The signature doesn't matter */
7400 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
7401 #if _MSC_VER
7402 mono_register_jit_icall_info (&mono_get_jit_icall_info ()->mono_chkstk_win64, __chkstk, "mono_chkstk_win64", NULL, TRUE, "__chkstk");
7403 #else
7404 mono_register_jit_icall_info (&mono_get_jit_icall_info ()->mono_chkstk_win64, ___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, "___chkstk_ms");
7405 #endif
7406 #endif
7407 }
7409 void
7410 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
7411 {
7414 /*
7415 * Debug code to help track down problems where the target of a near call is
7416 * is not valid.
7417 */
7433 }
7434 }
7435 }
7438 }
7440 #ifndef DISABLE_JIT
7442 static int
7444 {
7453 }
7455 /*
7456 * This macro is used for testing whenever the unwinder works correctly at every point
7457 * where an async exception can happen.
7458 */
7459 /* This will generate a SIGSEGV at the given point in the code */
7460 #define async_exc_point(code) do { \
7461 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
7462 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
7463 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
7464 cfg->arch.async_point_count ++; \
7465 } \
7466 } while (0)
7468 #ifdef TARGET_WIN32
7470 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
7471 {
7474 /* Allocate windows stack frame using stack probing method */
7480 }
7487 }
7489 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
7490 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
7491 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
7492 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
7493 // that will retrieve the expected results.
7496 }
7501 }
7504 guint8 *
7506 {
7521 /* Amount of stack space allocated by register saving code */
7524 /* Offset between RSP and the CFA */
7527 /*
7528 * The prolog consists of the following parts:
7529 * FP present:
7530 * - push rbp
7531 * - mov rbp, rsp
7532 * - save callee saved regs using moves
7533 * - allocate frame
7534 * - save rgctx if needed
7535 * - save lmf if needed
7536 * FP not present:
7537 * - allocate frame
7538 * - save rgctx if needed
7539 * - save lmf if needed
7540 * - save callee saved regs using moves
7541 */
7543 // CFA = sp + 8
7546 // IP saved at CFA - 8
7557 /* These are handled automatically by the stack marking code */
7564 }
7566 /* The param area is always at offset 0 from sp */
7567 /* This needs to be allocated here, since it has to come after the spill area */
7570 // FIXME:
7573 }
7576 /*
7577 * On enter, the stack is misaligned by the pushing of the return
7578 * address. It is either made aligned by the pushing of %rbp, or by
7579 * this.
7580 */
7584 /* Mark the padding slot as NOREF */
7586 }
7590 /* Mark the padding slot as NOREF */
7592 }
7595 }
7601 /* Allocate stack frame */
7602 #ifdef TARGET_WIN32
7604 #else
7606 /* See mono_emit_stack_alloc */
7607 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7610 /* Use a loop for large sizes */
7624 }
7628 }
7630 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7638 }
7643 }
7650 }
7651 }
7652 #else
7658 }
7659 #endif
7660 }
7661 #endif
7663 /* Stack alignment check */
7664 #if 0
7665 {
7675 }
7676 #endif
7679 /* Fill the stack frame with a dummy value to force deterministic behavior */
7681 /* Save registers to the red zone */
7687 MONO_RESTORE_WARNING
7698 }
7700 /* Save LMF */
7704 /* Save callee saved registers */
7707 /* Save caller saved registers after sp is adjusted */
7708 /* The registers are saved at the bottom of the frame */
7709 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7711 /* The registers are saved just below the saved rbp */
7713 }
7721 /* These are handled automatically by the stack marking code */
7725 // FIXME: GC
7726 }
7730 }
7731 }
7733 /* store runtime generic context */
7738 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7740 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7741 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7742 }
7744 /* compute max_length in order to use short forward jumps */
7751 /* max alignment for loops */
7757 }
7759 /* Take prolog and epilog instrumentation into account */
7764 }
7765 }
7773 /* Save volatile arguments to the stack */
7775 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7776 }
7778 /* Keep this in sync with emit_load_volatile_arguments */
7785 /* Unused arguments */
7788 /* Save volatile arguments to the stack */
7794 /* FIXME: I1 etc */
7795 /*
7796 if (stack_offset & 0x1)
7797 size = 1;
7798 else if (stack_offset & 0x2)
7799 size = 2;
7800 else if (stack_offset & 0x4)
7801 size = 4;
7802 else
7803 size = 8;
7804 */
7807 /*
7808 * Save the original location of 'this',
7809 * get_generic_info_from_stack_frame () needs this to properly look up
7810 * the argument value during the handling of async exceptions.
7811 */
7814 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7815 }
7817 }
7828 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad], sizeof (target_mgreg_t));
7831 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad]);
7834 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_regs [quad]);
7840 }
7841 }
7845 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (target_mgreg_t));
7854 }
7856 /* Argument allocated to (non-volatile) register */
7866 }
7872 }
7873 }
7874 }
7879 /*
7880 * Optimize the common case of the first bblock making a call with the same
7881 * arguments as the method. This works because the arguments are still in their
7882 * original argument registers.
7883 * FIXME: Generalize this
7884 */
7894 }
7907 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7914 /* Only continue if the instruction doesn't change argument regs */
7917 }
7918 }
7920 }
7923 }
7925 /* Argument allocated to (non-volatile) register */
7931 }
7935 }
7936 }
7940 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7943 }
7944 }
7945 }
7950 /* Initialize seq_point_info_var */
7952 /* Initialize the variable from a GOT slot */
7953 /* Same as OP_AOTCONST */
7954 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7958 }
7961 /* Initialize ss_tramp_var */
7966 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7969 /* Initialize ss_tramp_var */
7976 /* Initialize bp_tramp_var */
7982 }
7983 }
7988 }
7990 void
7992 {
8007 /* Mark the start of the epilog */
8010 /* Save the uwind state which is needed by the out-of-line code */
8013 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
8017 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
8019 /*
8020 * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
8021 * since its stack slot will become invalid.
8022 */
8024 }
8026 /* Restore callee saved regs */
8029 /* Restore only used_int_regs, not arch.saved_iregs */
8030 #if defined(MONO_SUPPORT_TASKLETS)
8032 #else
8034 #endif
8039 }
8041 }
8042 }
8044 /* Load returned vtypes into registers if needed */
8053 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)), ainfo->pair_size [quad]);
8056 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)));
8059 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (target_mgreg_t)));
8065 }
8066 }
8067 }
8072 }
8074 #ifdef TARGET_WIN32
8078 #else
8081 #endif
8082 }
8087 /* Restore the unwind state to be the same as before the epilog */
8091 }
8093 void
8095 {
8103 /* Compute needed space */
8113 }
8117 /* add code to raise exceptions */
8124 guint32 throw_ip;
8131 //x86_breakpoint (code);
8132 /* Find a throw sequence for the same exception class */
8140 }
8149 }
8150 amd64_mov_reg_imm (code, AMD64_ARG_REG1, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
8162 nthrows ++;
8163 }
8164 }
8166 }
8168 /* do nothing */
8170 }
8172 }
8174 /* Handle relocations with RIP relative addressing */
8183 guint32 target_pos;
8185 /* The SSE opcodes require a 16 byte alignment */
8192 }
8196 }
8204 }
8210 }
8217 /*loading is faster against aligned addresses.*/
8223 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
8226 else
8234 }
8237 }
8246 ;
8248 }
8249 }
8251 }
8254 }
8258 MONO_NEVER_INLINE
8259 void
8261 {
8262 /* call/ret required (or likely other control transfer) */
8263 }
8265 void
8267 {
8268 }
8270 gboolean
8272 {
8274 }
8276 /*
8277 * Determine whenever the trap whose info is in SIGINFO is caused by
8278 * integer overflow.
8279 */
8280 gboolean
8282 {
8283 MonoContext ctx;
8286 gint64 value;
8294 rip ++;
8295 }
8296 else
8299 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
8300 /* idiv REG */
8307 }
8310 }
8312 guint32
8314 {
8316 }
8318 /**
8319 * \return TRUE if no sw breakpoint was present.
8320 *
8321 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
8322 * breakpoints in the original code, they are removed in the copy.
8323 */
8324 gboolean
8325 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
8326 {
8327 /*
8328 * If method_start is non-NULL we need to perform bound checks, since we access memory
8329 * at code - offset we could go before the start of the method and end up in a different
8330 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
8331 * instead.
8332 */
8339 }
8341 }
8343 int
8345 {
8347 }
8349 gpointer
8351 {
8353 }
8355 #define MAX_ARCH_DELEGATE_PARAMS 10
8357 static gpointer
8359 {
8368 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8372 /* Replace the this argument with the target */
8374 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8381 /* We have to shift the arguments left */
8384 #ifdef TARGET_WIN32
8387 else
8389 #else
8391 #endif
8392 }
8395 }
8396 }
8399 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8404 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8409 }
8415 else
8420 }
8421 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
8424 }
8426 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8428 static gpointer
8430 {
8439 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8443 /* Replace the this argument with the target */
8445 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8448 /* Load the IMT reg */
8449 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8450 }
8452 /* Load the vtable */
8453 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8458 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
8465 }
8467 /*
8468 * mono_arch_get_delegate_invoke_impls:
8469 *
8470 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8471 * trampolines.
8472 */
8473 GSList*
8475 {
8486 }
8491 }
8498 }
8501 }
8503 gpointer
8505 {
8512 /* FIXME: Support more cases */
8528 }
8553 }
8558 }
8561 }
8563 gpointer
8564 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8565 {
8567 gpointer code;
8573 }
8575 void
8577 {
8578 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8580 #endif
8581 }
8583 #define CMP_SIZE (6 + 1)
8584 #define CMP_REG_REG_SIZE (4 + 1)
8585 #define BR_SMALL_SIZE 2
8586 #define BR_LARGE_SIZE 6
8587 #define MOV_REG_IMM_SIZE 10
8588 #define MOV_REG_IMM_32BIT_SIZE 6
8589 #define JUMP_REG_SIZE (2 + 1)
8591 static int
8593 {
8598 }
8600 /*
8601 * LOCKING: called with the domain lock held
8602 */
8603 gpointer
8604 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8605 gpointer fail_tramp)
8606 {
8620 else
8622 }
8628 else
8630 }
8639 else
8642 /* with assert below:
8643 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8644 */
8645 }
8646 }
8650 else
8654 }
8656 }
8658 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8659 else
8674 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8678 }
8679 }
8686 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8688 }
8695 }
8697 /* enable the commented code to assert on wrong method */
8698 #if 0
8700 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8704 }
8707 /* See the comment below about R10 */
8708 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8713 #else
8714 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8715 needs to be preserved. R10 needs
8716 to be preserved for calls which
8717 require a runtime generic context,
8718 but interface calls don't. */
8719 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8721 #endif
8722 }
8725 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (target_mgreg_t));
8729 }
8733 else
8735 }
8736 g_assertf (code - item->code_target <= item->chunk_size, "%X %X", (guint)(code - item->code_target), (guint)item->chunk_size);
8737 }
8738 /* patch the branches to get to the target items */
8744 }
8745 }
8746 }
8751 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8753 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8755 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8758 }
8760 MonoMethod*
8762 {
8764 }
8766 MonoVTable*
8768 {
8770 }
8772 GSList*
8774 {
8781 }
8783 #ifndef DISABLE_JIT
8785 MonoInst*
8786 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8787 {
8796 }
8804 }
8826 }
8827 }
8836 }
8838 #if 0
8839 /* OP_FREM is not IEEE compatible */
8844 }
8845 #endif
8847 if ((mini_get_cpu_features (cfg) & MONO_CPU_X86_SSE41) != 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
8863 }
8864 }
8865 }
8868 }
8869 #endif
8871 host_mgreg_t
8873 {
8875 }
8877 void
8879 {
8881 }
8883 /*
8884 * mono_arch_emit_load_aotconst:
8885 *
8886 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8887 * TARGET from the mscorlib GOT in full-aot code.
8888 * On AMD64, the result is placed into R11.
8889 */
8890 guint8*
8891 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8892 {
8897 }
8899 /*
8900 * mono_arch_get_trampolines:
8901 *
8902 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8903 * for AOT.
8904 */
8905 GSList *
8907 {
8909 }
8911 /* Soft Debug support */
8912 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8914 /*
8915 * mono_arch_set_breakpoint:
8916 *
8917 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8918 * The location should contain code emitted by OP_SEQ_POINT.
8919 */
8920 void
8922 {
8927 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8932 /* ip points to a mov r11, 0 */
8936 }
8937 }
8939 /*
8940 * mono_arch_clear_breakpoint:
8941 *
8942 * Clear the breakpoint at IP.
8943 */
8944 void
8946 {
8951 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8956 }
8957 }
8959 gboolean
8961 {
8962 /* We use soft breakpoints on amd64 */
8964 }
8966 /*
8967 * mono_arch_skip_breakpoint:
8968 *
8969 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8970 * we resume, the instruction is not executed again.
8971 */
8972 void
8974 {
8976 }
8978 /*
8979 * mono_arch_start_single_stepping:
8980 *
8981 * Start single stepping.
8982 */
8983 void
8985 {
8987 }
8989 /*
8990 * mono_arch_stop_single_stepping:
8991 *
8992 * Stop single stepping.
8993 */
8994 void
8996 {
8998 }
9000 /*
9001 * mono_arch_is_single_step_event:
9002 *
9003 * Return whenever the machine state in SIGCTX corresponds to a single
9004 * step event.
9005 */
9006 gboolean
9008 {
9009 /* We use soft breakpoints on amd64 */
9011 }
9013 /*
9014 * mono_arch_skip_single_step:
9015 *
9016 * Modify CTX so the ip is placed after the single step trigger instruction,
9017 * we resume, the instruction is not executed again.
9018 */
9019 void
9021 {
9023 }
9025 /*
9026 * mono_arch_create_seq_point_info:
9027 *
9028 * Return a pointer to a data structure which is used by the sequence
9029 * point implementation in AOTed code.
9030 */
9031 SeqPointInfo*
9033 {
9037 // FIXME: Add a free function
9041 code);
9048 // FIXME: Optimize the size
9049 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
9057 }
9060 }
9062 #endif
9064 gboolean
9066 {
9097 }
9098 }
9100 CallInfo*
9102 {
9104 }
9106 gpointer
9108 {
9111 #undef MONO_AOT_ICALL
9112 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
9119 }
9121 }