| blob | 977286f5440f058c26df657eaf4d0193f9b79354 |
1 /**
2 * \file
3 * AMD64 backend for the Mono code generator
4 *
5 * Based on mini-x86.c.
6 *
7 * Authors:
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
10 * Patrik Torstensson
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
13 *
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
18 */
20 #include <string.h>
21 #include <math.h>
22 #include <assert.h>
23 #ifdef HAVE_UNISTD_H
24 #include <unistd.h>
25 #endif
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
40 #include <mono/utils/unlocked.h>
53 #ifdef MONO_XEN_OPT
55 #else
56 #define optimize_for_xen 0
57 #endif
59 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
61 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
63 #ifdef TARGET_WIN32
64 /* Under windows, the calling convention is never stdcall */
65 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
66 #else
67 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
68 #endif
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
75 /* The single step trampoline */
78 /* The breakpoint trampoline */
81 /* Offset between fp and the first argument in the callee */
82 #define ARGS_OFFSET 16
83 #define GP_SCRATCH_REG AMD64_R11
85 /* Max number of bblocks before we bail from using more advanced branch placement code */
86 #define MAX_BBLOCKS_FOR_BRANCH_OPTS 800
88 /*
89 * AMD64 register usage:
90 * - callee saved registers are used for global register allocation
91 * - %r11 is used for materializing 64 bit constants in opcodes
92 * - the rest is used for local allocation
93 */
95 /*
96 * Floating point comparison results:
97 * ZF PF CF
98 * A > B 0 0 0
99 * A < B 0 0 1
100 * A = B 1 0 0
101 * A > B 0 0 0
102 * UNORDERED 1 1 1
103 */
107 {
125 }
127 }
132 };
137 };
141 {
144 else
146 }
150 {
153 else
155 }
157 static gboolean
159 {
160 #if 0
162 #else
164 #endif
165 }
169 {
170 /* Skip REX */
175 }
179 {
184 }
186 static void
188 {
189 // NOTE: Sometimes code has just been generated, is not running yet,
190 // and has no alignment requirements. Sometimes it could be running while we patch it,
191 // and there are alignment requirements.
192 // FIXME Assert alignment.
196 /* Skip REX */
200 }
203 /* amd64_set_reg_template */
205 }
206 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
207 /* mov 0(%rip), %dreg */
209 }
211 /* call or jmp *<OFFSET>(%rip) */
213 }
215 /* call or jmp <DISP> */
219 }
220 else
222 }
224 void
226 {
228 }
230 #define DEBUG(a) if (cfg->verbose_level > 1) a
234 {
240 /* Since the same stack slot size is used for all arg */
241 /* types, it needs to be big enough to hold them all */
243 }
248 }
249 }
253 {
259 /* Since the same stack slot size is used for both float */
260 /* types, it needs to be big enough to hold them both */
262 }
264 /* A double register */
267 else
271 }
272 }
275 ARG_CLASS_NO_CLASS,
276 ARG_CLASS_MEMORY,
277 ARG_CLASS_INTEGER,
278 ARG_CLASS_SSE
281 static ArgumentClass
283 {
306 #ifdef TARGET_WIN32
308 #else
310 #endif
320 }
321 /* fall through */
329 }
331 }
334 }
336 /* Merge */
338 ;
345 else
349 }
356 /*
357 * collect_field_info_nested:
358 *
359 * Collect field info from KLASS recursively into FIELDS.
360 */
361 static void
362 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
363 {
372 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
374 guint32 align;
375 StructFieldInfo f;
383 /* This can happen with .pack directives eg. 'fixed' arrays */
385 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
390 }
394 }
397 }
398 }
399 }
401 gpointer iter;
409 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - MONO_ABI_SIZEOF (MonoObject), pinvoke, unicode);
412 StructFieldInfo f;
419 }
420 }
421 }
422 }
424 #ifdef TARGET_WIN32
426 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
427 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
429 static gboolean
430 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, const AMD64_Reg_No int_regs [], int int_reg_count, const AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
431 {
434 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
444 /* Pass parameter in integer register. */
450 /* Pass parameter in float register. */
451 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
455 }
460 }
463 }
466 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
467 {
468 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
469 }
472 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
473 {
474 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
475 }
477 static void
478 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
480 {
481 /* Windows x64 value type ABI.
482 *
483 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
484 *
485 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
486 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
487 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
488 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
489 *
490 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
491 *
492 * Integers/Float types smaller than or equal to 8 bytes
493 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
494 * Properly sized struct/unions (1,2,4,8)
495 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
496 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
497 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
498 */
500 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
504 /* Parameter cases. */
508 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
510 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
511 /* No more registers, fallback passing parameter on stack as value. */
512 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
514 /* Passing value directly on stack, so use size of value. */
520 }
522 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
524 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
525 /* No more registers, fallback passing address to parameter on stack. */
526 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
528 /* Passing an address to value on stack, so use size of register as argument size. */
534 }
535 }
537 /* Return value cases. */
541 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
543 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
545 /* Only RAX/XMM0 should be used to return valuetype. */
546 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
548 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
550 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
552 /* Only RAX should be used to return valuetype address. */
558 }
559 }
560 }
562 static void
563 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
564 {
568 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
571 /* Calculate argument class type and size of marshalled type. */
575 /* Calculate argument class type and size of managed type. */
577 }
579 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
583 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
585 }
587 /*
588 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
589 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
590 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
591 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
592 * it must be represented in call and cannot be dropped.
593 */
598 }
601 }
603 static void
606 {
609 ArgumentClass arg_class;
611 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
616 /* Only drop value type if its not an empty struct as input that must be represented in call */
617 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_info->pass_empty_struct && is_return)) {
621 /* Alocate storage for value type. */
622 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
623 }
624 }
628 static void
630 gboolean is_return,
632 {
633 #ifdef TARGET_WIN32
635 #else
637 /* Keep track of the size used in each quad so we can */
638 /* use the right size when copying args/return vars. */
651 /* We pass and return vtypes of size 8 in a register */
654 }
656 /* If this struct can't be split up naturally into 8-byte */
657 /* chunks (registers), pass it on the stack. */
664 }
665 /*
666 * Collect field information recursively to be able to
667 * handle nested structures.
668 */
678 }
679 }
685 }
688 /* Allways pass in memory */
697 }
701 else
710 /* Always pass in 1 or 2 integer registers */
713 /* Only the simplest cases are supported */
717 }
719 /*
720 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
721 * The X87 and SSEUP stuff is left out since there are no such types in
722 * the CLR.
723 */
728 }
739 }
744 ArgumentClass class1;
748 else
752 /* Unaligned field */
753 NOT_IMPLEMENTED;
754 }
756 /* Skip fields in other quad */
762 /* How far into this quad this data extends.*/
763 /* (8 is size of quad) */
767 }
768 /* Empty structs have a nonzero size, causing this assert to be hit */
772 }
773 }
777 /* Post merger cleanup */
781 /* Allocate registers */
782 {
788 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
807 else
810 }
821 }
829 }
830 }
834 /* Revert possible register assignments */
841 else
847 }
848 }
850 }
852 /*
853 * get_call_info:
854 *
855 * Obtain information about a call according to the calling convention.
856 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
857 * Draft Version 0.23" document for more information.
858 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
859 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
860 */
863 {
873 else
882 #ifdef TARGET_WIN32
883 /* Reserve space where the callee can save the argument registers */
885 #endif
887 /* return value */
922 }
926 }
927 /* fall through */
935 }
945 }
948 /*
949 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
950 * the first argument, allowing 'this' to be always passed in the first arg reg.
951 * Also do this if the first argument is a reference type, since virtual calls
952 * are sometimes made using calli without sig->hasthis set, like in the delegate
953 * invoke wrappers.
954 */
956 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
962 }
967 /* this */
974 }
975 }
981 /* Emit the signature cookie just before the implicit arguments */
983 }
989 #ifdef TARGET_WIN32
990 /* The float param registers and other param registers must be the same index on Windows x64.*/
995 #endif
998 /* We allways pass the sig cookie on the stack for simplicity */
999 /*
1000 * Prevent implicit arguments + the sig cookie from being passed
1001 * in registers.
1002 */
1006 /* Emit the signature cookie just before the implicit arguments */
1008 }
1038 }
1040 /* gsharedvt arguments are passed by ref */
1044 else
1047 }
1048 /* fall through */
1066 /* gsharedvt arguments are passed by ref */
1071 else
1076 }
1077 }
1079 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1083 /* Emit the signature cookie just before the implicit arguments */
1085 }
1091 }
1093 void
1094 mono_arch_set_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1095 {
1107 gpointer ret_storage = interp_cb->frame_arg_to_storage ((MonoInterpFrameHandle)frame, sig, -1);
1109 }
1110 }
1114 gpointer storage;
1121 }
1126 }
1130 }
1132 // FIXME? Alloca in a loop.
1135 }
1138 }
1141 /* Split up the value type into the reg pairs */
1155 }
1157 }
1158 }
1159 }
1162 }
1164 void
1165 mono_arch_get_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1166 {
1170 /* No return value */
1176 /* The return values were stored directly at address passed in reg */
1181 gpointer storage;
1188 }
1193 }
1197 /* Reconstruct the value type */
1211 }
1212 storage_tmp++;
1213 }
1215 }
1218 }
1220 done:
1222 }
1224 /*
1225 * mono_arch_get_argument_info:
1226 * @csig: a method signature
1227 * @param_count: the number of parameters to consider
1228 * @arg_info: an array to store the result infos
1229 *
1230 * Gathers information on parameters such as size, alignment and
1231 * padding. arg_info should be large enought to hold param_count + 1 entries.
1232 *
1233 * Returns the size of the argument area on the stack.
1234 */
1235 int
1236 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1237 {
1242 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1245 }
1249 /* FIXME: */
1251 }
1256 }
1258 gboolean
1259 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1260 {
1266 // Limit stack_usage to 1G. Assume 32bit limits when we move parameters.
1270 // valuetype parameters are address of local
1276 }
1282 }
1284 /*
1285 * Initialize the cpu to execute managed code.
1286 */
1287 void
1289 {
1290 #ifndef _MSC_VER
1291 guint16 fpcw;
1293 /* spec compliance requires running with double precision */
1299 #else
1300 /* TODO: This is crashing on Win64 right now.
1301 * _control87 (_PC_53, MCW_PC);
1302 */
1303 #endif
1304 }
1306 /*
1307 * Initialize architecture specific code.
1308 */
1309 void
1311 {
1315 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1318 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1319 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1320 #endif
1324 }
1326 /*
1327 * Cleanup architecture specific code.
1328 */
1329 void
1331 {
1333 }
1335 /*
1336 * This function returns the optimizations supported on this cpu.
1337 */
1338 guint32
1340 {
1350 else
1354 }
1357 }
1359 /*
1360 * This function test for all SSE functions supported.
1361 *
1362 * Returns a bitmask corresponding to all supported versions.
1363 *
1364 */
1365 guint32
1367 {
1392 }
1394 #ifndef DISABLE_JIT
1396 GList *
1398 {
1406 /* unused vars */
1418 }
1419 }
1424 }
1426 /**
1427 * mono_arch_compute_omit_fp:
1428 * Determine whether the frame pointer can be eliminated.
1429 */
1430 static void
1432 {
1449 /*
1450 * FIXME: Remove some of the restrictions.
1451 */
1460 /*
1461 if (cfg->method->save_lmf)
1462 cfg->arch.omit_fp = FALSE;
1463 */
1477 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1478 /*
1479 * The stack offset can only be determined when the frame
1480 * size is known.
1481 */
1483 }
1484 }
1492 }
1493 }
1495 GList *
1497 {
1505 /* We use the callee saved registers for global allocation */
1511 #ifdef TARGET_WIN32
1514 #endif
1517 }
1519 /*
1520 * mono_arch_regalloc_cost:
1521 *
1522 * Return the cost, in number of memory references, of the action of
1523 * allocating the variable VMV into a register during global register
1524 * allocation.
1525 */
1526 guint32
1528 {
1532 /* The register is already saved */
1533 /* substract 1 for the invisible store in the prolog */
1535 else
1536 /* push+pop */
1538 }
1540 /*
1541 * mono_arch_fill_argument_info:
1542 *
1543 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1544 * of the method.
1545 */
1546 void
1548 {
1560 /*
1561 * Contrary to mono_arch_allocate_vars (), the information should describe
1562 * where the arguments are at the beginning of the method, not where they can be
1563 * accessed during the execution of the method. The later makes no sense for the
1564 * global register allocator, since a variable can be in more than one location.
1565 */
1582 }
1602 /* Dummy */
1607 }
1608 }
1609 }
1611 void
1613 {
1629 /*
1630 * We use the ABI calling conventions for managed code as well.
1631 * Exception: valuetypes are only sometimes passed or returned in registers.
1632 */
1634 /*
1635 * The stack looks like this:
1636 * <incoming arguments passed on the stack>
1637 * <return value>
1638 * <lmf/caller saved registers>
1639 * <locals>
1640 * <spill area>
1641 * <localloc area> -> grows dynamically
1642 * <params area>
1643 */
1650 /* Locals are allocated backwards from %fp */
1653 }
1657 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1660 }
1664 /* Reserve space for callee saved registers */
1668 }
1683 /* The register is volatile */
1692 }
1696 }
1699 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1708 }
1712 }
1713 }
1715 /* Allocate locals */
1716 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1720 }
1727 }
1736 else
1738 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1739 }
1740 }
1747 }
1755 /* FIXME: Allocate volatile arguments to registers */
1759 /*
1760 * Under AMD64, all registers used to pass arguments to functions
1761 * are volatile across calls.
1762 * FIXME: Optimize this.
1763 */
1764 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1777 }
1792 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1801 }
1805 }
1811 }
1813 NOT_IMPLEMENTED;
1814 }
1816 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1819 /* These arguments are saved to the stack in the prolog */
1823 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1824 // Arguments are yet supported by the stack map creation code
1825 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1827 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1829 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1830 }
1831 }
1832 }
1833 }
1836 }
1838 void
1840 {
1855 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1860 }
1861 }
1870 }
1878 }
1885 }
1886 }
1888 static void
1889 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1890 {
1920 }
1921 }
1923 static int
1925 {
1928 #if defined(__mono_ilp32__)
1930 #else
1932 #endif
1939 }
1942 }
1944 static void
1946 {
1951 NOT_IMPLEMENTED;
1955 /*
1956 * mono_ArgIterator_Setup assumes the signature cookie is
1957 * passed first and all the arguments which were before it are
1958 * passed on the stack after the signature. So compensate by
1959 * passing a different signature.
1960 */
1961 tmp_sig = mono_metadata_signature_dup_full (m_class_get_image (cfg->method->klass), call->signature);
1964 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1969 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1970 }
1972 #ifdef ENABLE_LLVM
1975 {
1987 }
1988 }
1990 LLVMCallInfo*
1992 {
2005 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2007 /*
2008 * LLVM always uses the native ABI while we use our own ABI, the
2009 * only difference is the handling of vtypes:
2010 * - we only pass/receive them in registers in some cases, and only
2011 * in 1 or 2 integer registers.
2012 */
2026 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2027 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2031 }
2037 }
2040 /* Vtype returned using a hidden argument */
2047 }
2054 else
2071 else
2076 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2077 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2081 }
2085 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2095 }
2096 }
2099 }
2100 #endif
2102 void
2104 {
2120 /* We shouldn't be called in the llvm case */
2123 }
2125 /*
2126 * Emit all arguments which are passed on the stack to prevent register
2127 * allocation problems.
2128 */
2137 else
2141 //XXX what about ArgGSharedVtOnStack here?
2142 // FIXME tailcall is not always yet initialized.
2149 else
2153 }
2158 }
2159 }
2160 }
2162 /*
2163 * Emit all parameters passed in registers in non-reverse order for better readability
2164 * and to help the optimization in emit_prolog ().
2165 */
2173 }
2184 else
2190 /* Already done */
2202 // FIXME tailcall is not always yet initialized.
2204 /* Already emitted above */
2206 //FIXME what about ArgGSharedVtOnStack ?
2207 // FIXME tailcall is not always yet initialized.
2213 }
2215 guint32 align;
2216 guint32 size;
2221 /*
2222 * Other backends use mono_type_stack_size (), but that
2223 * aligns the size to 8, which is larger than the size of
2224 * the source, leading to reads of invalid memory if the
2225 * source is at the end of address space.
2226 */
2228 }
2231 /* Avoid asserts in emit_memcpy () */
2232 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2233 /* Continue normally */
2234 }
2246 }
2248 }
2251 }
2254 /* Emit the signature cookie just before the implicit arguments */
2256 }
2258 /* Handle the case where there are no implicit arguments */
2265 /*
2266 * Tell the JIT to use a more efficient calling convention: call using
2267 * OP_CALL, compute the result location after the call, and save the
2268 * result there.
2269 */
2271 /*
2272 * Nullify the instruction computing the vret addr to enable
2273 * future optimizations.
2274 */
2279 NOT_IMPLEMENTED;
2280 /*
2281 * The valuetype is in RAX:RDX after the call, need to be copied to
2282 * the stack. Push the address here, so the call instruction can
2283 * access it.
2284 */
2287 /* Prevent it from being register allocated or optimized away */
2289 }
2292 }
2304 }
2307 }
2312 }
2315 }
2317 void
2319 {
2335 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2337 }
2353 }
2354 }
2359 }
2361 }
2366 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2390 }
2392 }
2394 /* Pass by addr */
2409 // FIXME: Code growth
2411 }
2415 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, m_class_get_byval_arg (ins->klass));
2416 }
2417 }
2418 }
2420 void
2422 {
2428 else
2434 }
2437 }
2441 #define EMIT_COND_BRANCH(ins,cond,sign) \
2442 if (ins->inst_true_bb->native_offset) { \
2443 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2444 } else { \
2445 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2446 if (optimize_branch_pred && \
2447 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2448 x86_branch8 (code, cond, 0, sign); \
2449 else \
2450 x86_branch32 (code, cond, 0, sign); \
2451 }
2459 static gboolean
2461 {
2474 }
2489 }
2490 }
2493 }
2495 /*
2496 * mono_arch_dyn_call_prepare:
2497 *
2498 * Return a pointer to an arch-specific structure which contains information
2499 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2500 * supported for SIG.
2501 * This function is equivalent to ffi_prep_cif in libffi.
2502 */
2503 MonoDynCallInfo*
2505 {
2515 }
2518 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2528 info->nstack_args = MAX (info->nstack_args, (ainfo->offset / sizeof (mgreg_t)) + (ainfo->arg_size / sizeof (mgreg_t)));
2532 }
2533 }
2534 /* Align to 16 bytes */
2539 }
2541 /*
2542 * mono_arch_dyn_call_free:
2543 *
2544 * Free a MonoDynCallInfo structure.
2545 */
2546 void
2548 {
2553 }
2555 int
2557 {
2560 /* Extend the 'regs' field dynamically */
2562 }
2564 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2565 #define GREG_TO_PTR(greg) (gpointer)(greg)
2567 /*
2568 * mono_arch_get_start_dyn_call:
2569 *
2570 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2571 * store the result into BUF.
2572 * ARGS should be an array of pointers pointing to the arguments.
2573 * RET should point to a memory buffer large enought to hold the result of the
2574 * call.
2575 * This function should be as fast as possible, any work which does not depend
2576 * on the actual values of the arguments should be done in
2577 * mono_arch_dyn_call_prepare ().
2578 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2579 * libffi.
2580 */
2581 void
2583 {
2603 }
2617 }
2619 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2637 }
2642 }
2649 #if !defined(__mono_ilp32__)
2652 #endif
2655 #if defined(__mono_ilp32__)
2660 #endif
2688 }
2690 }
2697 }
2703 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2713 /* The argument pointed to by arg is either a boxed vtype or null */
2717 /* Fall though */
2720 /* Fall through */
2721 }
2740 }
2749 }
2750 }
2754 // In DYNCALL use case value types are already copied when included in parameter array.
2755 // Currently no need to make an extra temporary value type on stack for this use case.
2765 }
2767 }
2770 }
2771 }
2772 }
2774 /*
2775 * mono_arch_finish_dyn_call:
2776 *
2777 * Store the result of a dyn call into the return value buffer passed to
2778 * start_dyn_call ().
2779 * This function should be as fast as possible, any work which does not depend
2780 * on the actual values of the arguments should be done in
2781 * mono_arch_dyn_call_prepare ().
2782 */
2783 void
2785 {
2839 /* Fall through */
2840 }
2842 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2843 /* Nothing to do */
2862 }
2863 }
2864 }
2868 }
2869 }
2871 /* emit an exception if condition is fail */
2872 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2873 do { \
2874 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2875 if (tins == NULL) { \
2876 mono_add_patch_info (cfg, code - cfg->native_code, \
2877 MONO_PATCH_INFO_EXC, exc_name); \
2878 x86_branch32 (code, cond, 0, signed); \
2879 } else { \
2880 EMIT_COND_BRANCH (tins, cond, signed); \
2881 } \
2882 } while (0);
2884 #define EMIT_FPCOMPARE(code) do { \
2885 amd64_fcompp (code); \
2886 amd64_fnstsw (code); \
2887 } while (0);
2889 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2890 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2891 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2892 amd64_ ##op (code); \
2893 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2894 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2895 } while (0);
2898 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2899 {
2902 /*
2903 * FIXME: Add support for thunks
2904 */
2905 {
2908 /*
2909 * Indirect calls are expensive so try to make a near call if possible.
2910 * The caller memory is allocated by the code manager so it is
2911 * guaranteed to be at a 32 bit offset.
2912 */
2915 /* The target is in memory allocated using the code manager */
2920 /* The callee might be an AOT method */
2923 /* The target is in malloc-ed memory */
2925 }
2928 /*
2929 * The call might go directly to a native function without
2930 * the wrapper.
2931 */
2937 }
2938 }
2939 }
2952 /*
2953 * This is not really an optimization, but required because the
2954 * generic class init trampolines use R11 to pass the vtable.
2955 */
2957 }
2962 /* No wrapper */
2965 }
2967 /* See the comment in mono_codegen () */
2968 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2970 }
2971 }
2975 }
2976 }
2977 }
2980 /* These methods are allocated using malloc */
2983 #ifdef MONO_ARCH_NOMAP32BIT
2985 #endif
2986 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2993 }
2996 /*
2997 * Align the call displacement to an address divisible by 4 so it does
2998 * not span cache lines. This is required for code patching to work on SMP
2999 * systems.
3000 */
3004 }
3007 }
3013 }
3017 }
3018 }
3023 }
3026 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3027 {
3028 #ifdef TARGET_WIN32
3031 #endif
3033 #ifdef TARGET_WIN32
3036 #endif
3041 }
3045 {
3053 }
3056 }
3058 #ifndef DISABLE_JIT
3060 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3062 /*
3063 * mono_arch_peephole_pass_1:
3064 *
3065 * Perform peephole opts which should/can be performed before local regalloc
3066 */
3067 void
3069 {
3080 /*
3081 * X86_LEA is like ADD, but doesn't have the
3082 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3083 * its operand to 64 bit.
3084 */
3087 }
3094 /*
3095 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3096 * the latter has length 2-3 instead of 6 (reverse constant
3097 * propagation). These instruction sequences are very common
3098 * in the initlocals bblock.
3099 */
3101 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3104 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3105 /* Continue */
3106 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3108 /* Continue */
3110 /* Continue */
3113 }
3114 }
3115 }
3119 /* OP_COMPARE_IMM (reg, 0)
3120 * -->
3121 * OP_AMD64_TEST_NULL (reg)
3122 */
3131 /*
3132 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3133 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3134 * -->
3135 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3136 * OP_COMPARE_IMM reg, imm
3137 *
3138 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3139 */
3146 /* check if we can remove cmp reg,0 with test null */
3149 }
3152 }
3155 }
3156 }
3158 void
3160 {
3168 /* reg = 0 -> XOR (reg, reg) */
3169 /* XOR sets cflags on x86, so we cant do it always */
3174 /* Fall through */
3177 }
3178 }
3180 /*
3181 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3182 * 0 result into 64 bits.
3183 */
3186 }
3187 /* Fall through */
3192 /*
3193 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3194 * the latter has length 2-3 instead of 6 (reverse constant
3195 * propagation). These instruction sequences are very common
3196 * in the initlocals bblock.
3197 */
3199 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3202 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3203 /* Continue */
3204 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3206 /* Continue */
3208 /* Continue */
3211 }
3212 }
3213 }
3223 }
3226 }
3227 }
3229 #define NEW_INS(cfg,ins,dest,op) do { \
3230 MONO_INST_NEW ((cfg), (dest), (op)); \
3231 (dest)->cil_code = (ins)->cil_code; \
3232 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3233 } while (0)
3235 /*
3236 * mono_arch_lowering_pass:
3237 *
3238 * Converts complex opcodes into simpler ones so that each IR instruction
3239 * corresponds to one machine instruction.
3240 */
3241 void
3243 {
3246 /*
3247 * FIXME: Need to add more instructions, but the current machine
3248 * description can't model some parts of the composite instructions like
3249 * cdq.
3250 */
3270 }
3272 #ifndef __mono_ilp32__
3274 #endif
3276 /* Don't generate memindex opcodes (to simplify */
3277 /* read sandboxing) */
3284 }
3286 #ifndef __mono_ilp32__
3288 #endif
3296 }
3298 #ifdef MONO_ARCH_SIMD_INTRINSICS
3319 }
3321 #endif
3324 }
3325 }
3328 }
3330 static const int
3331 branch_cc_table [] = {
3335 };
3337 /* Maps CMP_... constants to X86_CC_... constants */
3338 static const int
3339 cc_table [] = {
3342 };
3344 static const int
3345 cc_signed_table [] = {
3348 };
3350 /*#include "cprop.c"*/
3353 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3354 {
3357 else
3365 }
3369 {
3373 #if defined(TARGET_WIN32)
3375 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3378 #endif
3383 /*
3384 * Under Windows:
3385 * If requested stack size is larger than one page,
3386 * perform stack-touch operation
3387 */
3388 /*
3389 * Generate stack probe code.
3390 * Under Windows, it is necessary to allocate one page at a time,
3391 * "touching" stack after each successful sub-allocation. This is
3392 * because of the way stack growth is implemented - there is a
3393 * guard page before the lowest stack page that is currently commited.
3394 * Stack normally grows sequentially so OS traps access to the
3395 * guard page and commits more pages when needed.
3396 */
3417 }
3418 else
3426 }
3430 }
3434 }
3454 }
3456 }
3460 {
3462 guint32 quad;
3464 /* Move return value to the target register */
3465 /* FIXME: do this in the local reg allocator */
3481 }
3485 }
3487 }
3504 /* Load the destination address */
3506 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3511 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3522 NOT_IMPLEMENTED;
3523 }
3524 }
3525 }
3527 }
3530 }
3534 #ifdef TARGET_MACH
3536 #endif
3538 gboolean
3540 {
3541 #ifdef TARGET_MACH
3554 /*
3555 * We're looking for these two instructions:
3556 *
3557 * mov %gs:[offset](,%rdi,8),%rax
3558 * retq
3559 */
3572 /*
3573 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3574 * For that version we're looking for these instructions:
3575 *
3576 * pushq %rbp
3577 * movq %rsp, %rbp
3578 * mov %gs:[offset](,%rdi,8),%rax
3579 * popq %rbp
3580 * retq
3581 */
3599 }
3603 #elif defined(TARGET_ANDROID)
3605 #else
3609 #endif
3610 }
3612 int
3614 {
3615 #ifdef TARGET_OSX
3617 #else
3620 #endif
3621 }
3623 /*
3624 * \param code buffer to store code to
3625 * \param dreg hard register where to place the result
3626 * \param tls_offset offset info
3627 * \return a pointer to the end of the stored code
3628 *
3629 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3630 * the dreg register the item in the thread local storage identified
3631 * by tls_offset.
3632 */
3635 {
3636 #ifdef TARGET_WIN32
3644 /* Load TEB->TlsExpansionSlots */
3652 }
3653 #elif defined(TARGET_MACH)
3656 #else
3664 }
3665 #endif
3667 }
3671 {
3672 #ifdef TARGET_WIN32
3674 #elif defined(TARGET_MACH)
3677 #else
3681 #endif
3683 }
3685 /*
3686 * emit_setup_lmf:
3687 *
3688 * Emit code to initialize an LMF structure at LMF_OFFSET.
3689 */
3692 {
3693 /*
3694 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3695 */
3696 /*
3697 * sp is saved right before calls but we need to save it here too so
3698 * async stack walks would work.
3699 */
3700 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3701 /* Save rbp */
3702 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3704 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3706 /* These can't contain refs */
3707 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3708 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3709 /* These are handled automatically by the stack marking code */
3710 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3713 }
3715 #ifdef TARGET_WIN32
3717 #define TEB_LAST_ERROR_OFFSET 0x068
3721 {
3722 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3727 }
3729 #else
3733 {
3735 }
3737 #endif
3739 /* benchmark and set based on cpu */
3740 #define LOOP_ALIGNMENT 8
3741 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3743 #ifndef DISABLE_JIT
3747 {
3748 #ifndef TARGET_WIN32
3751 else
3753 #endif
3755 }
3758 amd64_handle_varargs_call (MonoCompile *cfg, guint8 *code, MonoCallInst *call, gboolean free_rax)
3759 {
3760 #ifdef TARGET_WIN32
3762 #else
3763 /*
3764 * The AMD64 ABI forces callers to know about varargs.
3765 */
3768 // deliberatly nothing -- but nreg = 0 and do not return
3769 } else if (cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE && m_class_get_image (cfg->method->klass) != mono_defaults.corlib) {
3770 /*
3771 * Since the unmanaged calling convention doesn't contain a
3772 * 'vararg' entry, we have to treat every pinvoke call as a
3773 * potential vararg call.
3774 */
3779 }
3784 }
3786 #endif
3787 }
3789 void
3791 {
3796 /* Fix max_offset estimate for each successor bb */
3797 gboolean optimize_branch_pred = (cfg->opt & MONO_OPT_BRANCH) && (cfg->max_block_num < MAX_BBLOCKS_FOR_BRANCH_OPTS);
3805 }
3806 }
3810 /* set alignment depending on cpu */
3813 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3817 }
3818 }
3827 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3864 /* In AMD64 NaCl, pointers are 4 bytes, */
3865 /* so STORE_* != STOREI8_*. Likewise below. */
3867 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3876 /* In NaCl, this could be a PCONST type, which could */
3877 /* mean a pointer type was copied directly into the */
3878 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3879 /* the value would be 0x00000000FFFFFFFF which is */
3880 /* not proper for an imm32 unless you cast it. */
3882 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3889 #ifdef __mono_ilp32__
3890 /* In ILP32, pointers are 4 bytes, so separate these */
3891 /* cases, use literal 8 below where we really want 8 */
3895 #endif
3897 // FIXME: Decompose this earlier
3903 }
3910 // FIXME: Decompose this earlier
3916 }
3923 /* For NaCl, pointers are 4 bytes, so separate these */
3924 /* cases, use literal 8 below where we really want 8 */
3930 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3933 /* Use literal 8 instead of sizeof pointer or */
3934 /* register, we really want 8 for this opcode */
3945 /* The cpu zero extends the result into 64 bits */
3946 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3952 /* The cpu zero extends the result into 64 bits */
3953 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3980 /* Clean out the upper word */
3991 #if defined(__mono_ilp32__)
3992 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3996 #endif
4028 /* FIXME: Make a 64 version too */
4029 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4037 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4045 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4048 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4051 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4054 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4060 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4079 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4082 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4085 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4089 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4118 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4121 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4130 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4135 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4139 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4143 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4147 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4151 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4181 /* Load ss_tramp_var */
4182 /* This is equal to &ss_trampoline */
4184 /* Load the trampoline address */
4186 /* Call it if it is non-null */
4192 }
4194 /*
4195 * This is the address which is saved in seq points,
4196 */
4201 guint32 val;
4205 /* Load info var */
4208 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4213 /* Call the trampoline */
4220 /*
4221 * Emit a test+branch against a constant, the constant will be overwritten
4222 * by mono_arch_set_breakpoint () to cause the test to fail.
4223 */
4231 /* Load bp_tramp_var */
4232 /* This is equal to &bp_trampoline */
4234 /* Call the trampoline */
4237 }
4238 /*
4239 * Add an additional nop so skipping the bp doesn't cause the ip to point
4240 * to another IL offset.
4241 */
4244 }
4297 /* MOV r1, r2 */
4298 /* ADD r1, r1 */
4304 /* LEA r1, [r2 + r2*2] */
4308 /* LEA r1, [r2 + r2*4] */
4312 /* LEA r1, [r2 + r2*2] */
4313 /* ADD r1, r1 */
4318 /* LEA r1, [r2 + r2*8] */
4322 /* LEA r1, [r2 + r2*4] */
4323 /* ADD r1, r1 */
4328 /* LEA r1, [r2 + r2*2] */
4329 /* SHL r1, 2 */
4334 /* LEA r1, [r2 + r2*4] */
4335 /* LEA r1, [r1 + r1*4] */
4340 /* LEA r1, [r2 + r2*4] */
4341 /* SHL r1, 2 */
4342 /* LEA r1, [r1 + r1*4] */
4350 }
4352 }
4355 /* Regalloc magic makes the div/rem cases the same */
4363 }
4374 }
4385 }
4396 }
4529 /* the mul operation and the exception check should most likely be split */
4532 /*g_assert (ins->sreg2 == X86_EAX);
4533 g_assert (ins->dreg == X86_EAX);*/
4539 /* no need to save since we're going to store to it anyway */
4543 }
4546 }
4551 }
4555 }
4557 /* save before the check since pop and mov don't change the flags */
4566 }
4593 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4617 /* This needs to operate on 64 bit values */
4618 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4632 else
4653 }
4655 }
4660 }
4663 // This opcode helps compute sizes, i.e.
4664 // of the subsequent OP_TAILCALL, but contributes no code.
4682 // FIXME hardcoding RAX here is not ideal.
4698 // FIXME Patch data instead of code.
4704 }
4705 }
4707 /* Restore callee saved registers */
4713 }
4718 // FIXME:
4720 NOT_IMPLEMENTED;
4723 /* Copy arguments on the stack to our argument area */
4724 // FIXME use rep mov for constant code size, before nonvolatiles
4725 // restored, first saving rsi, rdi into volatiles
4729 }
4731 #ifdef TARGET_WIN32
4735 #else
4737 #endif
4738 }
4740 #ifdef TARGET_WIN32
4741 // Redundant REX byte indicates a tailcall to the native unwinder. It means nothing to the processor.
4742 // https://github.com/dotnet/coreclr/blob/966dabb5bb3c4bf1ea885e1e8dc6528e8c64dc4f/src/unwinder/amd64/unwinder_amd64.cpp#L1394
4743 // FIXME This should be jmp rip+32 for AOT direct to same assembly.
4744 // FIXME This should be jmp [rip+32] for AOT direct to not-same assembly (through data).
4745 // FIXME This should be jmp [rip+32] for JIT direct -- patch data instead of code.
4746 // This is only close to ideal for tailcall_membase, and even then it should
4747 // have a more dynamic register allocation.
4750 #else
4751 // NT does not have varargs rax use, and NT ABI does not have red zone.
4752 // Use red-zone mov/jmp instead of push/ret to preserve call/ret speculation stack.
4753 // FIXME Just like NT the direct cases are are not ideal.
4757 #endif
4761 }
4763 /* ensure ins->sreg1 is not NULL */
4770 }
4783 else
4801 }
4831 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4833 /* r10 = ftn */
4836 /* Save args buffer */
4839 /* Set fp arg regs */
4840 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4845 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4848 /* Allocate param area */
4849 /* This doesn't need to be freed since OP_DYN_CALL is never called in a loop */
4850 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4853 /* Set stack args */
4854 /* rax/rcx/rdx/r8/r9 is scratch */
4859 amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4861 amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof(mgreg_t)));
4877 /* Set argument registers */
4879 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof(mgreg_t)), sizeof(mgreg_t));
4881 /* Make the call */
4887 /* Save result */
4890 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4891 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4893 }
4896 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4898 }
4923 else
4934 }
4940 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4944 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4950 }
4953 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4962 /* keep alignment */
4990 }
4994 }
4998 }
5006 }
5014 }
5016 /* Align stack */
5020 /*
5021 * ins->inst_eh_blocks and bb->clause_holes are part of same GList.
5022 * Holes from bb->clause_holes will be added separately for the entire
5023 * basic block. Add only the rest of them.
5024 */
5027 /* Restore stack alignment */
5031 /* Even though we're saving RSP, use sizeof */
5032 /* gpointer because spvar is of type IntPtr */
5033 /* see: mono_create_spvar_for_region */
5035 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5040 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5041 }
5043 }
5046 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5049 }
5052 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5053 /* The local allocator will put the result into RAX */
5056 }
5065 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5066 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5067 //break;
5075 else
5077 }
5103 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5126 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5143 /* floating point opcodes */
5149 }
5153 }
5155 }
5162 else
5164 }
5170 }
5172 }
5183 /* This requires a double->single conversion */
5185 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5186 }
5194 }
5202 }
5213 }
5224 }
5286 /* Based on gcc code */
5290 /* Positive case */
5295 /* Negative case */
5296 /* Save to the red zone */
5306 /* Restore */
5311 }
5336 }
5369 }
5384 }
5410 }
5463 /*
5464 * The two arguments are swapped because the fbranch instructions
5465 * depend on this for the non-sse case to work.
5466 */
5470 /*
5471 * FIXME: Get rid of this.
5472 * The two arguments are swapped because the fbranch instructions
5473 * depend on this for the non-sse case to work.
5474 */
5479 /* zeroing the register at the start results in
5480 * shorter and faster code (we can also remove the widening op)
5481 */
5500 }
5502 }
5505 /* zeroing the register at the start results in
5506 * shorter and faster code (we can also remove the widening op)
5507 */
5522 }
5524 }
5534 }
5537 /* zeroing the register at the start results in
5538 * shorter and faster code (we can also remove the widening op)
5539 */
5551 }
5553 }
5563 }
5597 }
5622 }
5629 }
5631 }
5657 }
5679 }
5681 }
5688 }
5690 /* Branch if C013 != 100 */
5691 /* branch if !ZF or (PF|CF) */
5708 /* skip branch if C1=1 */
5711 /* branch if (C0 | C3) = 1 */
5717 }
5720 /* Branch if C013 == 100 or 001 */
5723 /* skip branch if C1=1 */
5726 /* branch if (C0 | C3) = 1 */
5730 }
5732 /* Branch if C013 == 000 */
5736 /* Branch if C013=000 or 100 */
5739 /* skip branch if C1=1 */
5742 /* branch if C0=0 */
5746 }
5748 /* Branch if C013 != 001 */
5753 /* Transfer value to the fp stack */
5771 }
5775 }
5780 }
5792 /* dreg contains the old value, add with sreg2 value */
5799 }
5804 /* LOCK prefix is implied. */
5809 }
5812 guint32 size;
5816 else
5819 /*
5820 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5821 * an explanation of how this works.
5822 */
5833 }
5837 }
5841 }
5845 }
5849 }
5853 }
5857 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5859 }
5866 }
5868 }
5872 }
5900 }
5907 }
5913 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5914 }
5919 }
5930 }
5936 gpointer card_table_mask;
5943 /*If either point to the stack we can simply avoid the WB. This happens due to
5944 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5945 */
5949 /*
5950 * We need one register we can clobber, we choose EDX and make sreg1
5951 * fixed EAX to work around limitations in the local register allocator.
5952 * sreg2 might get allocated to EDX, but that is not a problem since
5953 * we use it before clobbering EDX.
5954 */
5957 /*
5958 * This is the code we produce:
5959 *
5960 * edx = value
5961 * edx >>= nursery_shift
5962 * cmp edx, (nursery_start >> nursery_shift)
5963 * jne done
5964 * edx = ptr
5965 * edx >>= card_table_shift
5966 * edx += cardtable
5967 * [edx] = 1
5968 * done:
5969 */
5976 /*
5977 * The value we need to compare against is 64 bits, so we need
5978 * another spare register. We use RBX, which we save and
5979 * restore.
5980 */
5987 }
5989 }
5995 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6003 }
6004 #ifdef MONO_ARCH_SIMD_INTRINSICS
6005 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6395 /*TODO: This is appart of the sse spec but not added
6396 case OP_PSARQ:
6397 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6398 break;
6399 case OP_PSARQ_REG:
6400 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6401 break;
6402 */
6447 }
6458 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6459 if (ins->inst_c0)
6460 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6467 else
6477 /*sreg1 is the extracted ireg (scratch)
6478 /sreg2 is the to be inserted ireg (scratch)
6479 /dreg is the xreg to receive the value*/
6481 /*clear the bits from the extracted word*/
6483 /*shift the value to insert if needed*/
6486 /*join them together*/
6499 else
6508 else
6515 else
6523 else
6531 else
6535 }
6540 else
6564 /*FIXME the peephole pass should have killed this*/
6599 }
6621 }
6628 #endif
6631 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6634 }
6637 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6640 }
6648 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6651 }
6668 amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (mgreg_t), i, sizeof (mgreg_t));
6673 }
6679 }
6680 }
6683 }
6687 void
6689 {
6690 /* The signature doesn't matter */
6691 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6693 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6694 #if _MSC_VER
6697 #else
6700 #endif
6701 #endif
6702 }
6704 void
6705 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6706 {
6709 /*
6710 * Debug code to help track down problems where the target of a near call is
6711 * is not valid.
6712 */
6728 }
6729 }
6730 }
6733 }
6735 #ifndef DISABLE_JIT
6737 static int
6739 {
6751 }
6753 /*
6754 * This macro is used for testing whenever the unwinder works correctly at every point
6755 * where an async exception can happen.
6756 */
6757 /* This will generate a SIGSEGV at the given point in the code */
6758 #define async_exc_point(code) do { \
6759 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6760 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6761 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6762 cfg->arch.async_point_count ++; \
6763 } \
6764 } while (0)
6766 #ifdef TARGET_WIN32
6768 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6769 {
6772 /* Allocate windows stack frame using stack probing method */
6778 }
6785 }
6787 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6788 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6789 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6790 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6791 // that will retrieve the expected results.
6794 }
6799 }
6802 guint8 *
6804 {
6823 /* Amount of stack space allocated by register saving code */
6826 /* Offset between RSP and the CFA */
6829 /*
6830 * The prolog consists of the following parts:
6831 * FP present:
6832 * - push rbp
6833 * - mov rbp, rsp
6834 * - save callee saved regs using moves
6835 * - allocate frame
6836 * - save rgctx if needed
6837 * - save lmf if needed
6838 * FP not present:
6839 * - allocate frame
6840 * - save rgctx if needed
6841 * - save lmf if needed
6842 * - save callee saved regs using moves
6843 */
6845 // CFA = sp + 8
6848 // IP saved at CFA - 8
6859 /* These are handled automatically by the stack marking code */
6866 }
6868 /* The param area is always at offset 0 from sp */
6869 /* This needs to be allocated here, since it has to come after the spill area */
6872 // FIXME:
6875 }
6878 /*
6879 * On enter, the stack is misaligned by the pushing of the return
6880 * address. It is either made aligned by the pushing of %rbp, or by
6881 * this.
6882 */
6886 /* Mark the padding slot as NOREF */
6888 }
6892 /* Mark the padding slot as NOREF */
6894 }
6897 }
6903 /* Allocate stack frame */
6904 #ifdef TARGET_WIN32
6906 #else
6908 /* See mono_emit_stack_alloc */
6909 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6912 /* Use a loop for large sizes */
6926 }
6930 }
6932 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6940 }
6945 }
6952 }
6953 }
6954 #else
6960 }
6961 #endif
6962 }
6963 #endif
6965 /* Stack alignment check */
6966 #if 0
6967 {
6977 }
6978 #endif
6981 /* Fill the stack frame with a dummy value to force deterministic behavior */
6983 /* Save registers to the red zone */
6997 }
6999 /* Save LMF */
7003 /* Save callee saved registers */
7006 /* Save caller saved registers after sp is adjusted */
7007 /* The registers are saved at the bottom of the frame */
7008 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7010 /* The registers are saved just below the saved rbp */
7012 }
7020 /* These are handled automatically by the stack marking code */
7024 // FIXME: GC
7025 }
7029 }
7030 }
7032 /* store runtime generic context */
7037 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7039 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7040 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7041 }
7043 /* compute max_length in order to use short forward jumps */
7050 /* max alignment for loops */
7056 }
7058 /* Take prolog and epilog instrumentation into account */
7063 }
7064 }
7072 /* Save volatile arguments to the stack */
7074 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7075 }
7077 /* Keep this in sync with emit_load_volatile_arguments */
7084 /* Unused arguments */
7087 /* Save volatile arguments to the stack */
7093 /* FIXME: I1 etc */
7094 /*
7095 if (stack_offset & 0x1)
7096 size = 1;
7097 else if (stack_offset & 0x2)
7098 size = 2;
7099 else if (stack_offset & 0x4)
7100 size = 4;
7101 else
7102 size = 8;
7103 */
7106 /*
7107 * Save the original location of 'this',
7108 * get_generic_info_from_stack_frame () needs this to properly look up
7109 * the argument value during the handling of async exceptions.
7110 */
7113 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7114 }
7116 }
7127 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7130 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7133 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7139 }
7140 }
7144 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7153 }
7155 /* Argument allocated to (non-volatile) register */
7165 }
7170 }
7171 }
7172 }
7180 }
7182 /*
7183 * Optimize the common case of the first bblock making a call with the same
7184 * arguments as the method. This works because the arguments are still in their
7185 * original argument registers.
7186 * FIXME: Generalize this
7187 */
7197 }
7210 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7217 /* Only continue if the instruction doesn't change argument regs */
7220 }
7221 }
7223 }
7226 }
7228 /* Argument allocated to (non-volatile) register */
7234 }
7238 }
7239 }
7243 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7246 }
7247 }
7248 }
7253 /* Initialize seq_point_info_var */
7255 /* Initialize the variable from a GOT slot */
7256 /* Same as OP_AOTCONST */
7257 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7261 }
7264 /* Initialize ss_tramp_var */
7269 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7272 /* Initialize ss_tramp_var */
7279 /* Initialize bp_tramp_var */
7285 }
7286 }
7291 }
7293 void
7295 {
7310 /* Mark the start of the epilog */
7313 /* Save the uwind state which is needed by the out-of-line code */
7319 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7323 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7325 /*
7326 * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
7327 * since its stack slot will become invalid.
7328 */
7330 }
7332 /* Restore callee saved regs */
7335 /* Restore only used_int_regs, not arch.saved_iregs */
7336 #if defined(MONO_SUPPORT_TASKLETS)
7338 #else
7340 #endif
7345 }
7347 }
7348 }
7350 /* Load returned vtypes into registers if needed */
7359 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7362 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7365 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7371 }
7372 }
7373 }
7378 }
7380 #ifdef TARGET_WIN32
7384 #else
7387 #endif
7388 }
7393 /* Restore the unwind state to be the same as before the epilog */
7397 }
7399 void
7401 {
7409 /* Compute needed space */
7419 }
7423 /* add code to raise exceptions */
7430 guint32 throw_ip;
7437 //x86_breakpoint (code);
7438 /* Find a throw sequence for the same exception class */
7446 }
7455 }
7456 amd64_mov_reg_imm (code, AMD64_ARG_REG1, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
7460 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7468 nthrows ++;
7469 }
7470 }
7472 }
7474 /* do nothing */
7476 }
7478 }
7480 /* Handle relocations with RIP relative addressing */
7489 guint32 target_pos;
7491 /* The SSE opcodes require a 16 byte alignment */
7498 }
7502 }
7510 }
7516 }
7523 /*loading is faster against aligned addresses.*/
7529 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7532 else
7540 }
7543 }
7552 ;
7554 }
7555 }
7557 }
7560 }
7566 {
7572 /* Keep this in sync with mono_arch_get_argument_info */
7575 /* Allocate a new area on the stack and save arguments there */
7594 }
7595 }
7596 }
7609 }
7612 SAVE_NONE,
7613 SAVE_STRUCT,
7614 SAVE_EAX,
7615 SAVE_EAX_EDX,
7616 SAVE_XMM
7617 };
7621 {
7629 /* special case string .ctor icall */
7632 else
7647 }
7648 /* Fall through */
7655 }
7657 /* Save the result and copy it into the proper argument register */
7661 /* Align stack */
7667 /* FIXME: */
7674 /* Align stack */
7676 /*
7677 * The result is already in the proper argument register so no copying
7678 * needed.
7679 */
7685 }
7687 /* Set %al since this is a varargs call */
7693 /* Restore result */
7700 /* FIXME: */
7711 }
7716 }
7718 MONO_NEVER_INLINE
7719 void
7721 {
7722 /* call/ret required (or likely other control transfer) */
7723 }
7725 void
7727 {
7728 }
7730 gboolean
7732 {
7734 }
7736 /*
7737 * Determine whenever the trap whose info is in SIGINFO is caused by
7738 * integer overflow.
7739 */
7740 gboolean
7742 {
7743 MonoContext ctx;
7746 gint64 value;
7754 rip ++;
7755 }
7756 else
7759 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7760 /* idiv REG */
7767 }
7770 }
7772 guint32
7774 {
7776 }
7778 /**
7779 * \return TRUE if no sw breakpoint was present.
7780 *
7781 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7782 * breakpoints in the original code, they are removed in the copy.
7783 */
7784 gboolean
7785 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7786 {
7787 /*
7788 * If method_start is non-NULL we need to perform bound checks, since we access memory
7789 * at code - offset we could go before the start of the method and end up in a different
7790 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7791 * instead.
7792 */
7799 }
7801 }
7803 int
7805 {
7807 }
7809 gpointer
7811 {
7813 }
7815 #define MAX_ARCH_DELEGATE_PARAMS 10
7817 static gpointer
7819 {
7827 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7829 /* Replace the this argument with the target */
7831 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7835 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7837 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7842 /* We have to shift the arguments left */
7845 #ifdef TARGET_WIN32
7848 else
7850 #else
7852 #endif
7853 }
7856 }
7858 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7859 }
7864 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7869 }
7875 else
7880 }
7881 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7884 }
7886 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7888 static gpointer
7890 {
7899 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7903 /* Replace the this argument with the target */
7905 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7908 /* Load the IMT reg */
7909 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7910 }
7912 /* Load the vtable */
7913 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7915 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7922 }
7924 /*
7925 * mono_arch_get_delegate_invoke_impls:
7926 *
7927 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7928 * trampolines.
7929 */
7930 GSList*
7932 {
7943 }
7948 }
7955 }
7958 }
7960 gpointer
7962 {
7969 /* FIXME: Support more cases */
7985 }
8010 }
8015 }
8018 }
8020 gpointer
8021 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8022 {
8024 gpointer code;
8030 }
8032 void
8034 {
8035 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8037 #endif
8038 }
8040 void
8042 {
8043 }
8045 #define CMP_SIZE (6 + 1)
8046 #define CMP_REG_REG_SIZE (4 + 1)
8047 #define BR_SMALL_SIZE 2
8048 #define BR_LARGE_SIZE 6
8049 #define MOV_REG_IMM_SIZE 10
8050 #define MOV_REG_IMM_32BIT_SIZE 6
8051 #define JUMP_REG_SIZE (2 + 1)
8053 static int
8055 {
8060 }
8062 /*
8063 * LOCKING: called with the domain lock held
8064 */
8065 gpointer
8066 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8067 gpointer fail_tramp)
8068 {
8082 else
8084 }
8090 else
8092 }
8101 else
8104 /* with assert below:
8105 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8106 */
8107 }
8108 }
8112 else
8116 }
8118 }
8120 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
8121 else
8136 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8140 }
8141 }
8148 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8150 }
8157 }
8159 /* enable the commented code to assert on wrong method */
8160 #if 0
8162 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8166 }
8169 /* See the comment below about R10 */
8170 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8175 #else
8176 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8177 needs to be preserved. R10 needs
8178 to be preserved for calls which
8179 require a runtime generic context,
8180 but interface calls don't. */
8181 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8183 #endif
8184 }
8187 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8191 }
8195 else
8197 }
8199 }
8200 /* patch the branches to get to the target items */
8206 }
8207 }
8208 }
8213 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8215 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8217 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8220 }
8222 MonoMethod*
8224 {
8226 }
8228 MonoVTable*
8230 {
8232 }
8234 GSList*
8236 {
8243 }
8245 #ifndef DISABLE_JIT
8247 MonoInst*
8248 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8249 {
8262 }
8270 }
8292 }
8293 }
8302 }
8304 #if 0
8305 /* OP_FREM is not IEEE compatible */
8310 }
8311 #endif
8312 }
8315 }
8316 #endif
8318 mgreg_t
8320 {
8322 }
8324 void
8326 {
8328 }
8330 /*
8331 * mono_arch_emit_load_aotconst:
8332 *
8333 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8334 * TARGET from the mscorlib GOT in full-aot code.
8335 * On AMD64, the result is placed into R11.
8336 */
8337 guint8*
8338 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8339 {
8344 }
8346 /*
8347 * mono_arch_get_trampolines:
8348 *
8349 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8350 * for AOT.
8351 */
8352 GSList *
8354 {
8356 }
8358 /* Soft Debug support */
8359 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8361 /*
8362 * mono_arch_set_breakpoint:
8363 *
8364 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8365 * The location should contain code emitted by OP_SEQ_POINT.
8366 */
8367 void
8369 {
8374 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8379 /* ip points to a mov r11, 0 */
8383 }
8384 }
8386 /*
8387 * mono_arch_clear_breakpoint:
8388 *
8389 * Clear the breakpoint at IP.
8390 */
8391 void
8393 {
8398 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8403 }
8404 }
8406 gboolean
8408 {
8409 /* We use soft breakpoints on amd64 */
8411 }
8413 /*
8414 * mono_arch_skip_breakpoint:
8415 *
8416 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8417 * we resume, the instruction is not executed again.
8418 */
8419 void
8421 {
8423 }
8425 /*
8426 * mono_arch_start_single_stepping:
8427 *
8428 * Start single stepping.
8429 */
8430 void
8432 {
8434 }
8436 /*
8437 * mono_arch_stop_single_stepping:
8438 *
8439 * Stop single stepping.
8440 */
8441 void
8443 {
8445 }
8447 /*
8448 * mono_arch_is_single_step_event:
8449 *
8450 * Return whenever the machine state in SIGCTX corresponds to a single
8451 * step event.
8452 */
8453 gboolean
8455 {
8456 /* We use soft breakpoints on amd64 */
8458 }
8460 /*
8461 * mono_arch_skip_single_step:
8462 *
8463 * Modify CTX so the ip is placed after the single step trigger instruction,
8464 * we resume, the instruction is not executed again.
8465 */
8466 void
8468 {
8470 }
8472 /*
8473 * mono_arch_create_seq_point_info:
8474 *
8475 * Return a pointer to a data structure which is used by the sequence
8476 * point implementation in AOTed code.
8477 */
8478 SeqPointInfo*
8480 {
8484 // FIXME: Add a free function
8488 code);
8495 // FIXME: Optimize the size
8496 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8504 }
8507 }
8509 #endif
8511 gboolean
8513 {
8544 }
8545 }
8547 CallInfo*
8549 {
8551 }