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[jit] Disable fast tls on osx if MONO_HAVE_FAST_TLS is not defined.
[mono-project.git] / mono / mini / mini-x86.c
blob1268643dd135d67a5e94200611b9b22d862095f8
1 /*
2 * mini-x86.c: x86 backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 * Patrik Torstensson
8 *
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
12 */
13 #include "mini.h"
14 #include <string.h>
15 #include <math.h>
16 #ifdef HAVE_UNISTD_H
17 #include <unistd.h>
18 #endif
19
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
33
34 #include "trace.h"
35 #include "mini-x86.h"
36 #include "cpu-x86.h"
37 #include "ir-emit.h"
38 #include "mini-gc.h"
39
40 #ifndef TARGET_WIN32
41 #ifdef MONO_XEN_OPT
42 static gboolean optimize_for_xen = TRUE;
43 #else
44 #define optimize_for_xen 0
45 #endif
46 #endif
47
48 /* This mutex protects architecture specific caches */
49 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
50 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
51 static mono_mutex_t mini_arch_mutex;
52
53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54
55 #define ARGS_OFFSET 8
56
57 #ifdef TARGET_WIN32
58 /* Under windows, the default pinvoke calling convention is stdcall */
59 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #else
61 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
62 #endif
63
64 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
65
66 MonoBreakpointInfo
67 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68
69 static guint8*
70 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71
72 #ifdef __native_client_codegen__
73
74 /* Default alignment for Native Client is 32-byte. */
75 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76
77 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
78 /* Check that alignment doesn't cross an alignment boundary. */
79 guint8 *
80 mono_arch_nacl_pad (guint8 *code, int pad)
81 {
82 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83
84 if (pad == 0) return code;
85 /* assertion: alignment cannot cross a block boundary */
86 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
87 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
88 while (pad >= kMaxPadding) {
89 x86_padding (code, kMaxPadding);
90 pad -= kMaxPadding;
91 }
92 if (pad != 0) x86_padding (code, pad);
93 return code;
94 }
95
96 guint8 *
97 mono_arch_nacl_skip_nops (guint8 *code)
98 {
99 x86_skip_nops (code);
100 return code;
101 }
102
103 #endif /* __native_client_codegen__ */
104
105 /*
106 * The code generated for sequence points reads from this location, which is
107 * made read-only when single stepping is enabled.
108 */
109 static gpointer ss_trigger_page;
110
111 /* Enabled breakpoints read from this trigger page */
112 static gpointer bp_trigger_page;
113
114 const char*
115 mono_arch_regname (int reg)
116 {
117 switch (reg) {
118 case X86_EAX: return "%eax";
119 case X86_EBX: return "%ebx";
120 case X86_ECX: return "%ecx";
121 case X86_EDX: return "%edx";
122 case X86_ESP: return "%esp";
123 case X86_EBP: return "%ebp";
124 case X86_EDI: return "%edi";
125 case X86_ESI: return "%esi";
126 }
127 return "unknown";
128 }
129
130 const char*
131 mono_arch_fregname (int reg)
132 {
133 switch (reg) {
134 case 0:
135 return "%fr0";
136 case 1:
137 return "%fr1";
138 case 2:
139 return "%fr2";
140 case 3:
141 return "%fr3";
142 case 4:
143 return "%fr4";
144 case 5:
145 return "%fr5";
146 case 6:
147 return "%fr6";
148 case 7:
149 return "%fr7";
150 default:
151 return "unknown";
152 }
153 }
154
155 const char *
156 mono_arch_xregname (int reg)
157 {
158 switch (reg) {
159 case 0:
160 return "%xmm0";
161 case 1:
162 return "%xmm1";
163 case 2:
164 return "%xmm2";
165 case 3:
166 return "%xmm3";
167 case 4:
168 return "%xmm4";
169 case 5:
170 return "%xmm5";
171 case 6:
172 return "%xmm6";
173 case 7:
174 return "%xmm7";
175 default:
176 return "unknown";
177 }
178 }
179
180 void
181 mono_x86_patch (unsigned char* code, gpointer target)
182 {
183 x86_patch (code, (unsigned char*)target);
184 }
185
186 typedef enum {
187 ArgInIReg,
188 ArgInFloatSSEReg,
189 ArgInDoubleSSEReg,
190 ArgOnStack,
191 ArgValuetypeInReg,
192 ArgOnFloatFpStack,
193 ArgOnDoubleFpStack,
194 /* gsharedvt argument passed by addr */
195 ArgGSharedVt,
196 ArgNone
197 } ArgStorage;
198
199 typedef struct {
200 gint16 offset;
201 gint8 reg;
202 ArgStorage storage;
203 int nslots;
204 gboolean is_pair;
205
206 /* Only if storage == ArgValuetypeInReg */
207 ArgStorage pair_storage [2];
208 gint8 pair_regs [2];
209 } ArgInfo;
210
211 typedef struct {
212 int nargs;
213 guint32 stack_usage;
214 guint32 reg_usage;
215 guint32 freg_usage;
216 gboolean need_stack_align;
217 guint32 stack_align_amount;
218 gboolean vtype_retaddr;
219 /* The index of the vret arg in the argument list */
220 int vret_arg_index;
221 int vret_arg_offset;
222 /* Argument space popped by the callee */
223 int callee_stack_pop;
224 ArgInfo ret;
225 ArgInfo sig_cookie;
226 ArgInfo args [1];
227 } CallInfo;
228
229 #define FLOAT_PARAM_REGS 0
230
231 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232
233 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 {
235 if (!sig->pinvoke)
236 return NULL;
237
238 switch (sig->call_convention) {
239 case MONO_CALL_THISCALL:
240 return thiscall_param_regs;
241 default:
242 return NULL;
243 }
244 }
245
246 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
247 #define SMALL_STRUCTS_IN_REGS
248 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
249 #endif
250
251 static void inline
252 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 {
254 ainfo->offset = *stack_size;
255
256 if (!param_regs || param_regs [*gr] == X86_NREG) {
257 ainfo->storage = ArgOnStack;
258 ainfo->nslots = 1;
259 (*stack_size) += sizeof (gpointer);
260 }
261 else {
262 ainfo->storage = ArgInIReg;
263 ainfo->reg = param_regs [*gr];
264 (*gr) ++;
265 }
266 }
267
268 static void inline
269 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 {
271 ainfo->offset = *stack_size;
272
273 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274
275 ainfo->storage = ArgOnStack;
276 (*stack_size) += sizeof (gpointer) * 2;
277 ainfo->nslots = 2;
278 }
279
280 static void inline
281 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 {
283 ainfo->offset = *stack_size;
284
285 if (*gr >= FLOAT_PARAM_REGS) {
286 ainfo->storage = ArgOnStack;
287 (*stack_size) += is_double ? 8 : 4;
288 ainfo->nslots = is_double ? 2 : 1;
289 }
290 else {
291 /* A double register */
292 if (is_double)
293 ainfo->storage = ArgInDoubleSSEReg;
294 else
295 ainfo->storage = ArgInFloatSSEReg;
296 ainfo->reg = *gr;
297 (*gr) += 1;
298 }
299 }
300
301
302 static void
303 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 gboolean is_return,
305 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 {
307 guint32 size;
308 MonoClass *klass;
309
310 klass = mono_class_from_mono_type (type);
311 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312
313 #ifdef SMALL_STRUCTS_IN_REGS
314 if (sig->pinvoke && is_return) {
315 MonoMarshalType *info;
316
317 /*
318 * the exact rules are not very well documented, the code below seems to work with the
319 * code generated by gcc 3.3.3 -mno-cygwin.
320 */
321 info = mono_marshal_load_type_info (klass);
322 g_assert (info);
323
324 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325
326 /* Special case structs with only a float member */
327 if (info->num_fields == 1) {
328 int ftype = mini_type_get_underlying_type (gsctx, info->fields [0].field->type)->type;
329 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
330 ainfo->storage = ArgValuetypeInReg;
331 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
332 return;
333 }
334 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
335 ainfo->storage = ArgValuetypeInReg;
336 ainfo->pair_storage [0] = ArgOnFloatFpStack;
337 return;
338 }
339 }
340 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
341 ainfo->storage = ArgValuetypeInReg;
342 ainfo->pair_storage [0] = ArgInIReg;
343 ainfo->pair_regs [0] = return_regs [0];
344 if (info->native_size > 4) {
345 ainfo->pair_storage [1] = ArgInIReg;
346 ainfo->pair_regs [1] = return_regs [1];
347 }
348 return;
349 }
350 }
351 #endif
352
353 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
354 g_assert (size <= 4);
355 ainfo->storage = ArgValuetypeInReg;
356 ainfo->reg = param_regs [*gr];
357 (*gr)++;
358 return;
359 }
360
361 ainfo->offset = *stack_size;
362 ainfo->storage = ArgOnStack;
363 *stack_size += ALIGN_TO (size, sizeof (gpointer));
364 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
365 }
366
367 /*
368 * get_call_info:
369 *
370 * Obtain information about a call according to the calling convention.
371 * For x86 ELF, see the "System V Application Binary Interface Intel386
372 * Architecture Processor Supplment, Fourth Edition" document for more
373 * information.
374 * For x86 win32, see ???.
375 */
376 static CallInfo*
377 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 {
379 guint32 i, gr, fr, pstart;
380 const guint32 *param_regs;
381 MonoType *ret_type;
382 int n = sig->hasthis + sig->param_count;
383 guint32 stack_size = 0;
384 gboolean is_pinvoke = sig->pinvoke;
385
386 gr = 0;
387 fr = 0;
388 cinfo->nargs = n;
389
390 param_regs = callconv_param_regs(sig);
391
392 /* return value */
393 {
394 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
395 switch (ret_type->type) {
396 case MONO_TYPE_I1:
397 case MONO_TYPE_U1:
398 case MONO_TYPE_I2:
399 case MONO_TYPE_U2:
400 case MONO_TYPE_I4:
401 case MONO_TYPE_U4:
402 case MONO_TYPE_I:
403 case MONO_TYPE_U:
404 case MONO_TYPE_PTR:
405 case MONO_TYPE_FNPTR:
406 case MONO_TYPE_CLASS:
407 case MONO_TYPE_OBJECT:
408 case MONO_TYPE_SZARRAY:
409 case MONO_TYPE_ARRAY:
410 case MONO_TYPE_STRING:
411 cinfo->ret.storage = ArgInIReg;
412 cinfo->ret.reg = X86_EAX;
413 break;
414 case MONO_TYPE_U8:
415 case MONO_TYPE_I8:
416 cinfo->ret.storage = ArgInIReg;
417 cinfo->ret.reg = X86_EAX;
418 cinfo->ret.is_pair = TRUE;
419 break;
420 case MONO_TYPE_R4:
421 cinfo->ret.storage = ArgOnFloatFpStack;
422 break;
423 case MONO_TYPE_R8:
424 cinfo->ret.storage = ArgOnDoubleFpStack;
425 break;
426 case MONO_TYPE_GENERICINST:
427 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
428 cinfo->ret.storage = ArgInIReg;
429 cinfo->ret.reg = X86_EAX;
430 break;
431 }
432 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
433 cinfo->ret.storage = ArgOnStack;
434 cinfo->vtype_retaddr = TRUE;
435 break;
436 }
437 /* Fall through */
438 case MONO_TYPE_VALUETYPE:
439 case MONO_TYPE_TYPEDBYREF: {
440 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
441
442 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
443 if (cinfo->ret.storage == ArgOnStack) {
444 cinfo->vtype_retaddr = TRUE;
445 /* The caller passes the address where the value is stored */
446 }
447 break;
448 }
449 case MONO_TYPE_VAR:
450 case MONO_TYPE_MVAR:
451 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
452 cinfo->ret.storage = ArgOnStack;
453 cinfo->vtype_retaddr = TRUE;
454 break;
455 case MONO_TYPE_VOID:
456 cinfo->ret.storage = ArgNone;
457 break;
458 default:
459 g_error ("Can't handle as return value 0x%x", ret_type->type);
460 }
461 }
462
463 pstart = 0;
464 /*
465 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
466 * the first argument, allowing 'this' to be always passed in the first arg reg.
467 * Also do this if the first argument is a reference type, since virtual calls
468 * are sometimes made using calli without sig->hasthis set, like in the delegate
469 * invoke wrappers.
470 */
471 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
472 if (sig->hasthis) {
473 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
474 } else {
475 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
476 pstart = 1;
477 }
478 cinfo->vret_arg_offset = stack_size;
479 add_general (&gr, NULL, &stack_size, &cinfo->ret);
480 cinfo->vret_arg_index = 1;
481 } else {
482 /* this */
483 if (sig->hasthis)
484 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
485
486 if (cinfo->vtype_retaddr)
487 add_general (&gr, NULL, &stack_size, &cinfo->ret);
488 }
489
490 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
491 fr = FLOAT_PARAM_REGS;
492
493 /* Emit the signature cookie just before the implicit arguments */
494 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
495 }
496
497 for (i = pstart; i < sig->param_count; ++i) {
498 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
499 MonoType *ptype;
500
501 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
502 /* We allways pass the sig cookie on the stack for simplicity */
503 /*
504 * Prevent implicit arguments + the sig cookie from being passed
505 * in registers.
506 */
507 fr = FLOAT_PARAM_REGS;
508
509 /* Emit the signature cookie just before the implicit arguments */
510 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
511 }
512
513 if (sig->params [i]->byref) {
514 add_general (&gr, param_regs, &stack_size, ainfo);
515 continue;
516 }
517 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
518 switch (ptype->type) {
519 case MONO_TYPE_I1:
520 case MONO_TYPE_U1:
521 add_general (&gr, param_regs, &stack_size, ainfo);
522 break;
523 case MONO_TYPE_I2:
524 case MONO_TYPE_U2:
525 add_general (&gr, param_regs, &stack_size, ainfo);
526 break;
527 case MONO_TYPE_I4:
528 case MONO_TYPE_U4:
529 add_general (&gr, param_regs, &stack_size, ainfo);
530 break;
531 case MONO_TYPE_I:
532 case MONO_TYPE_U:
533 case MONO_TYPE_PTR:
534 case MONO_TYPE_FNPTR:
535 case MONO_TYPE_CLASS:
536 case MONO_TYPE_OBJECT:
537 case MONO_TYPE_STRING:
538 case MONO_TYPE_SZARRAY:
539 case MONO_TYPE_ARRAY:
540 add_general (&gr, param_regs, &stack_size, ainfo);
541 break;
542 case MONO_TYPE_GENERICINST:
543 if (!mono_type_generic_inst_is_valuetype (ptype)) {
544 add_general (&gr, param_regs, &stack_size, ainfo);
545 break;
546 }
547 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
548 /* gsharedvt arguments are passed by ref */
549 add_general (&gr, param_regs, &stack_size, ainfo);
550 g_assert (ainfo->storage == ArgOnStack);
551 ainfo->storage = ArgGSharedVt;
552 break;
553 }
554 /* Fall through */
555 case MONO_TYPE_VALUETYPE:
556 case MONO_TYPE_TYPEDBYREF:
557 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
558 break;
559 case MONO_TYPE_U8:
560 case MONO_TYPE_I8:
561 add_general_pair (&gr, param_regs, &stack_size, ainfo);
562 break;
563 case MONO_TYPE_R4:
564 add_float (&fr, &stack_size, ainfo, FALSE);
565 break;
566 case MONO_TYPE_R8:
567 add_float (&fr, &stack_size, ainfo, TRUE);
568 break;
569 case MONO_TYPE_VAR:
570 case MONO_TYPE_MVAR:
571 /* gsharedvt arguments are passed by ref */
572 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
573 add_general (&gr, param_regs, &stack_size, ainfo);
574 g_assert (ainfo->storage == ArgOnStack);
575 ainfo->storage = ArgGSharedVt;
576 break;
577 default:
578 g_error ("unexpected type 0x%x", ptype->type);
579 g_assert_not_reached ();
580 }
581 }
582
583 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
584 fr = FLOAT_PARAM_REGS;
585
586 /* Emit the signature cookie just before the implicit arguments */
587 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
588 }
589
590 if (cinfo->vtype_retaddr) {
591 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
592 cinfo->callee_stack_pop = 4;
593 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
594 /* Have to compensate for the stack space popped by the native callee */
595 cinfo->callee_stack_pop = stack_size;
596 }
597
598 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
599 cinfo->need_stack_align = TRUE;
600 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
601 stack_size += cinfo->stack_align_amount;
602 }
603
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
607 return cinfo;
608 }
609
610 static CallInfo*
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
612 {
613 int n = sig->hasthis + sig->param_count;
614 CallInfo *cinfo;
615
616 if (mp)
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
618 else
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
620
621 return get_call_info_internal (gsctx, cinfo, sig);
622 }
623
624 /*
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
629 *
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
632 *
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
637 */
638 int
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
640 {
641 int len, k, args_size = 0;
642 int size, pad;
643 guint32 align;
644 int offset = 8;
645 CallInfo *cinfo;
646
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
651
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
653
654 arg_info [0].offset = offset;
655
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
658 offset += 4;
659 }
660
661 if (csig->hasthis) {
662 args_size += sizeof (gpointer);
663 offset += 4;
664 }
665
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
669 offset += 4;
670 }
671
672 arg_info [0].size = args_size;
673
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
676
677 /* ignore alignment for now */
678 align = 1;
679
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
682 args_size += size;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
685 offset += pad;
686 arg_info [k + 1].offset = offset;
687 offset += size;
688
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
692 offset += 4;
693 }
694 }
695
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
698 else
699 align = 4;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
702
703 return args_size;
704 }
705
706 gboolean
707 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
708 {
709 MonoType *callee_ret;
710 CallInfo *c1, *c2;
711 gboolean res;
712
713 if (cfg->compile_aot && !cfg->full_aot)
714 /* OP_TAILCALL doesn't work with AOT */
715 return FALSE;
716
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
719 /*
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
722 */
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
727 res = FALSE;
728
729 g_free (c1);
730 g_free (c2);
731
732 return res;
733 }
734
735 /*
736 * Initialize the cpu to execute managed code.
737 */
738 void
739 mono_arch_cpu_init (void)
740 {
741 /* spec compliance requires running with double precision */
742 #ifndef _MSC_VER
743 guint16 fpcw;
744
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
750 #else
751 _control87 (_PC_53, MCW_PC);
752 #endif
753 }
754
755 /*
756 * Initialize architecture specific code.
757 */
758 void
759 mono_arch_init (void)
760 {
761 mono_mutex_init_recursive (&mini_arch_mutex);
762
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
766
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(ENABLE_GSHAREDVT)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
771 #endif
772 }
773
774 /*
775 * Cleanup architecture specific code.
776 */
777 void
778 mono_arch_cleanup (void)
779 {
780 if (ss_trigger_page)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
782 if (bp_trigger_page)
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 mono_mutex_destroy (&mini_arch_mutex);
785 }
786
787 /*
788 * This function returns the optimizations supported on this cpu.
789 */
790 guint32
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
792 {
793 #if !defined(__native_client__)
794 guint32 opts = 0;
795
796 *exclude_mask = 0;
797
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
800
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
803 else
804 *exclude_mask |= MONO_OPT_FCMOV;
805 } else {
806 *exclude_mask |= MONO_OPT_CMOV;
807 }
808
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
811 else
812 *exclude_mask |= MONO_OPT_SSE2;
813
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
818 #endif
819
820 return opts;
821 #else
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
823 #endif
824 }
825
826 /*
827 * This function test for all SSE functions supported.
828 *
829 * Returns a bitmask corresponding to all supported versions.
830 *
831 */
832 guint32
833 mono_arch_cpu_enumerate_simd_versions (void)
834 {
835 guint32 sse_opts = 0;
836
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
839
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
842
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
845
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
848
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
851
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
854
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
857
858 return sse_opts;
859 }
860
861 /*
862 * Determine whenever the trap whose info is in SIGINFO is caused by
863 * integer overflow.
864 */
865 gboolean
866 mono_arch_is_int_overflow (void *sigctx, void *info)
867 {
868 MonoContext ctx;
869 guint8* ip;
870
871 mono_sigctx_to_monoctx (sigctx, &ctx);
872
873 ip = (guint8*)ctx.eip;
874
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
876 gint32 reg;
877
878 /* idiv REG */
879 switch (x86_modrm_rm (ip [1])) {
880 case X86_EAX:
881 reg = ctx.eax;
882 break;
883 case X86_ECX:
884 reg = ctx.ecx;
885 break;
886 case X86_EDX:
887 reg = ctx.edx;
888 break;
889 case X86_EBX:
890 reg = ctx.ebx;
891 break;
892 case X86_ESI:
893 reg = ctx.esi;
894 break;
895 case X86_EDI:
896 reg = ctx.edi;
897 break;
898 default:
899 g_assert_not_reached ();
900 reg = -1;
901 }
902
903 if (reg == -1)
904 return TRUE;
905 }
906
907 return FALSE;
908 }
909
910 GList *
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
912 {
913 GList *vars = NULL;
914 int i;
915
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
919
920 /* unused vars */
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
922 continue;
923
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
926 continue;
927
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
934 }
935 }
936
937 vars = mono_varlist_sort (cfg, vars, 0);
938
939 return vars;
940 }
941
942 GList *
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
944 {
945 GList *regs = NULL;
946
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
951
952 return regs;
953 }
954
955 /*
956 * mono_arch_regalloc_cost:
957 *
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
960 * allocation.
961 */
962 guint32
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
964 {
965 MonoInst *ins = cfg->varinfo [vmv->idx];
966
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
970 else
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
973 }
974
975 static void
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
977 {
978 static int inited = FALSE;
979 static int count = 0;
980
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
983 return;
984 }
985
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
988
989 if (flag)
990 return;
991
992 if (!inited) {
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
994 inited = TRUE;
995 }
996 ++count;
997
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
999 }
1000
1001 static gboolean
1002 needs_stack_frame (MonoCompile *cfg)
1003 {
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1007
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1010 return TRUE;
1011 #endif
1012
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1015
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1018
1019 if (cfg->disable_omit_fp)
1020 result = TRUE;
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1022 result = TRUE;
1023 else if (cfg->method->save_lmf)
1024 result = TRUE;
1025 else if (cfg->stack_offset)
1026 result = TRUE;
1027 else if (cfg->param_area)
1028 result = TRUE;
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1030 result = TRUE;
1031 else if (header->num_clauses)
1032 result = TRUE;
1033 else if (sig->param_count + sig->hasthis)
1034 result = TRUE;
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1036 result = TRUE;
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1039 result = TRUE;
1040
1041 set_needs_stack_frame (cfg, result);
1042
1043 return cfg->arch.need_stack_frame;
1044 }
1045
1046 /*
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1049 */
1050 void
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1052 {
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1055 MonoInst *inst;
1056 guint32 locals_stack_size, locals_stack_align;
1057 int i, offset;
1058 gint32 *offsets;
1059 CallInfo *cinfo;
1060
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1063
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1065
1066 cfg->frame_reg = X86_EBP;
1067 offset = 0;
1068
1069 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1070 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1071 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1072 }
1073
1074 /* Reserve space to save LMF and caller saved registers */
1075
1076 if (cfg->method->save_lmf) {
1077 /* The LMF var is allocated normally */
1078 } else {
1079 if (cfg->used_int_regs & (1 << X86_EBX)) {
1080 offset += 4;
1081 }
1082
1083 if (cfg->used_int_regs & (1 << X86_EDI)) {
1084 offset += 4;
1085 }
1086
1087 if (cfg->used_int_regs & (1 << X86_ESI)) {
1088 offset += 4;
1089 }
1090 }
1091
1092 switch (cinfo->ret.storage) {
1093 case ArgValuetypeInReg:
1094 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1095 offset += 8;
1096 cfg->ret->opcode = OP_REGOFFSET;
1097 cfg->ret->inst_basereg = X86_EBP;
1098 cfg->ret->inst_offset = - offset;
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 /* Allocate locals */
1105 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1106 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1107 char *mname = mono_method_full_name (cfg->method, TRUE);
1108 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1109 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1110 g_free (mname);
1111 return;
1112 }
1113 if (locals_stack_align) {
1114 int prev_offset = offset;
1115
1116 offset += (locals_stack_align - 1);
1117 offset &= ~(locals_stack_align - 1);
1118
1119 while (prev_offset < offset) {
1120 prev_offset += 4;
1121 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1122 }
1123 }
1124 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1125 cfg->locals_max_stack_offset = - offset;
1126 /*
1127 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1128 * have locals larger than 8 bytes we need to make sure that
1129 * they have the appropriate offset.
1130 */
1131 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1132 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1133 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1134 if (offsets [i] != -1) {
1135 MonoInst *inst = cfg->varinfo [i];
1136 inst->opcode = OP_REGOFFSET;
1137 inst->inst_basereg = X86_EBP;
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1140 }
1141 }
1142 offset += locals_stack_size;
1143
1144
1145 /*
1146 * Allocate arguments+return value
1147 */
1148
1149 switch (cinfo->ret.storage) {
1150 case ArgOnStack:
1151 if (cfg->vret_addr) {
1152 /*
1153 * In the new IR, the cfg->vret_addr variable represents the
1154 * vtype return value.
1155 */
1156 cfg->vret_addr->opcode = OP_REGOFFSET;
1157 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1158 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1160 printf ("vret_addr =");
1161 mono_print_ins (cfg->vret_addr);
1162 }
1163 } else {
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1167 }
1168 break;
1169 case ArgValuetypeInReg:
1170 break;
1171 case ArgInIReg:
1172 cfg->ret->opcode = OP_REGVAR;
1173 cfg->ret->inst_c0 = cinfo->ret.reg;
1174 cfg->ret->dreg = cinfo->ret.reg;
1175 break;
1176 case ArgNone:
1177 case ArgOnFloatFpStack:
1178 case ArgOnDoubleFpStack:
1179 break;
1180 default:
1181 g_assert_not_reached ();
1182 }
1183
1184 if (sig->call_convention == MONO_CALL_VARARG) {
1185 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1186 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1187 }
1188
1189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1190 ArgInfo *ainfo = &cinfo->args [i];
1191 inst = cfg->args [i];
1192 if (inst->opcode != OP_REGVAR) {
1193 inst->opcode = OP_REGOFFSET;
1194 inst->inst_basereg = X86_EBP;
1195 }
1196 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1197 }
1198
1199 cfg->stack_offset = offset;
1200 }
1201
1202 void
1203 mono_arch_create_vars (MonoCompile *cfg)
1204 {
1205 MonoType *sig_ret;
1206 MonoMethodSignature *sig;
1207 CallInfo *cinfo;
1208
1209 sig = mono_method_signature (cfg->method);
1210
1211 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1212 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1213
1214 if (cinfo->ret.storage == ArgValuetypeInReg)
1215 cfg->ret_var_is_local = TRUE;
1216 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1217 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1218 }
1219
1220 if (cfg->method->save_lmf) {
1221 cfg->create_lmf_var = TRUE;
1222 cfg->lmf_ir = TRUE;
1223 #ifndef HOST_WIN32
1224 cfg->lmf_ir_mono_lmf = TRUE;
1225 #endif
1226 }
1227
1228 cfg->arch_eh_jit_info = 1;
1229 }
1230
1231 /*
1232 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1233 * so we try to do it just once when we have multiple fp arguments in a row.
1234 * We don't use this mechanism generally because for int arguments the generated code
1235 * is slightly bigger and new generation cpus optimize away the dependency chains
1236 * created by push instructions on the esp value.
1237 * fp_arg_setup is the first argument in the execution sequence where the esp register
1238 * is modified.
1239 */
1240 static G_GNUC_UNUSED int
1241 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1242 {
1243 int fp_space = 0;
1244 MonoType *t;
1245
1246 for (; start_arg < sig->param_count; ++start_arg) {
1247 t = mini_replace_type (sig->params [start_arg]);
1248 if (!t->byref && t->type == MONO_TYPE_R8) {
1249 fp_space += sizeof (double);
1250 *fp_arg_setup = start_arg;
1251 } else {
1252 break;
1253 }
1254 }
1255 return fp_space;
1256 }
1257
1258 static void
1259 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1260 {
1261 MonoMethodSignature *tmp_sig;
1262 int sig_reg;
1263
1264 /*
1265 * mono_ArgIterator_Setup assumes the signature cookie is
1266 * passed first and all the arguments which were before it are
1267 * passed on the stack after the signature. So compensate by
1268 * passing a different signature.
1269 */
1270 tmp_sig = mono_metadata_signature_dup (call->signature);
1271 tmp_sig->param_count -= call->signature->sentinelpos;
1272 tmp_sig->sentinelpos = 0;
1273 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1274
1275 if (cfg->compile_aot) {
1276 sig_reg = mono_alloc_ireg (cfg);
1277 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1279 } else {
1280 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1281 }
1282 }
1283
1284 #ifdef ENABLE_LLVM
1285 LLVMCallInfo*
1286 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1287 {
1288 int i, n;
1289 CallInfo *cinfo;
1290 ArgInfo *ainfo;
1291 LLVMCallInfo *linfo;
1292 MonoType *t, *sig_ret;
1293
1294 n = sig->param_count + sig->hasthis;
1295
1296 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1297 sig_ret = sig->ret;
1298
1299 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1300
1301 /*
1302 * LLVM always uses the native ABI while we use our own ABI, the
1303 * only difference is the handling of vtypes:
1304 * - we only pass/receive them in registers in some cases, and only
1305 * in 1 or 2 integer registers.
1306 */
1307 if (cinfo->ret.storage == ArgValuetypeInReg) {
1308 if (sig->pinvoke) {
1309 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1310 cfg->disable_llvm = TRUE;
1311 return linfo;
1312 }
1313
1314 cfg->exception_message = g_strdup ("vtype ret in call");
1315 cfg->disable_llvm = TRUE;
1316 /*
1317 linfo->ret.storage = LLVMArgVtypeInReg;
1318 for (j = 0; j < 2; ++j)
1319 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1320 */
1321 }
1322
1323 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1324 /* Vtype returned using a hidden argument */
1325 linfo->ret.storage = LLVMArgVtypeRetAddr;
1326 linfo->vret_arg_index = cinfo->vret_arg_index;
1327 }
1328
1329 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1330 // FIXME:
1331 cfg->exception_message = g_strdup ("vtype ret in call");
1332 cfg->disable_llvm = TRUE;
1333 }
1334
1335 for (i = 0; i < n; ++i) {
1336 ainfo = cinfo->args + i;
1337
1338 if (i >= sig->hasthis)
1339 t = sig->params [i - sig->hasthis];
1340 else
1341 t = &mono_defaults.int_class->byval_arg;
1342
1343 linfo->args [i].storage = LLVMArgNone;
1344
1345 switch (ainfo->storage) {
1346 case ArgInIReg:
1347 linfo->args [i].storage = LLVMArgInIReg;
1348 break;
1349 case ArgInDoubleSSEReg:
1350 case ArgInFloatSSEReg:
1351 linfo->args [i].storage = LLVMArgInFPReg;
1352 break;
1353 case ArgOnStack:
1354 if (mini_type_is_vtype (cfg, t)) {
1355 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1356 /* LLVM seems to allocate argument space for empty structures too */
1357 linfo->args [i].storage = LLVMArgNone;
1358 else
1359 linfo->args [i].storage = LLVMArgVtypeByVal;
1360 } else {
1361 linfo->args [i].storage = LLVMArgInIReg;
1362 if (t->byref) {
1363 if (t->type == MONO_TYPE_R4)
1364 linfo->args [i].storage = LLVMArgInFPReg;
1365 else if (t->type == MONO_TYPE_R8)
1366 linfo->args [i].storage = LLVMArgInFPReg;
1367 }
1368 }
1369 break;
1370 case ArgValuetypeInReg:
1371 if (sig->pinvoke) {
1372 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1373 cfg->disable_llvm = TRUE;
1374 return linfo;
1375 }
1376
1377 cfg->exception_message = g_strdup ("vtype arg");
1378 cfg->disable_llvm = TRUE;
1379 /*
1380 linfo->args [i].storage = LLVMArgVtypeInReg;
1381 for (j = 0; j < 2; ++j)
1382 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1383 */
1384 break;
1385 case ArgGSharedVt:
1386 linfo->args [i].storage = LLVMArgGSharedVt;
1387 break;
1388 default:
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1391 break;
1392 }
1393 }
1394
1395 return linfo;
1396 }
1397 #endif
1398
1399 static void
1400 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1401 {
1402 if (cfg->compute_gc_maps) {
1403 MonoInst *def;
1404
1405 /* Needs checking if the feature will be enabled again */
1406 g_assert_not_reached ();
1407
1408 /* On x86, the offsets are from the sp value before the start of the call sequence */
1409 if (t == NULL)
1410 t = &mono_defaults.int_class->byval_arg;
1411 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 }
1413 }
1414
1415 void
1416 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1417 {
1418 MonoType *sig_ret;
1419 MonoInst *arg, *in;
1420 MonoMethodSignature *sig;
1421 int i, j, n;
1422 CallInfo *cinfo;
1423 int sentinelpos = 0, sp_offset = 0;
1424
1425 sig = call->signature;
1426 n = sig->param_count + sig->hasthis;
1427 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1428
1429 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1430 call->call_info = cinfo;
1431
1432 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1433 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1434
1435 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1436 if (cinfo->ret.storage == ArgValuetypeInReg) {
1437 /*
1438 * Tell the JIT to use a more efficient calling convention: call using
1439 * OP_CALL, compute the result location after the call, and save the
1440 * result there.
1441 */
1442 call->vret_in_reg = TRUE;
1443 #if defined(__APPLE__)
1444 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1445 call->vret_in_reg_fp = TRUE;
1446 #endif
1447 if (call->vret_var)
1448 NULLIFY_INS (call->vret_var);
1449 }
1450 }
1451
1452 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1453
1454 /* Handle the case where there are no implicit arguments */
1455 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1456 emit_sig_cookie (cfg, call, cinfo);
1457 sp_offset = cinfo->sig_cookie.offset;
1458 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1459 }
1460
1461 /* Arguments are pushed in the reverse order */
1462 for (i = n - 1; i >= 0; i --) {
1463 ArgInfo *ainfo = cinfo->args + i;
1464 MonoType *orig_type, *t;
1465 int argsize;
1466
1467 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1468 MonoInst *vtarg;
1469
1470 /* Push the vret arg before the first argument */
1471 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1472 vtarg->type = STACK_MP;
1473 vtarg->inst_destbasereg = X86_ESP;
1474 vtarg->sreg1 = call->vret_var->dreg;
1475 vtarg->inst_offset = cinfo->ret.offset;
1476 MONO_ADD_INS (cfg->cbb, vtarg);
1477 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1478 }
1479
1480 if (i >= sig->hasthis)
1481 t = sig->params [i - sig->hasthis];
1482 else
1483 t = &mono_defaults.int_class->byval_arg;
1484 orig_type = t;
1485 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1486
1487 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1488
1489 in = call->args [i];
1490 arg->cil_code = in->cil_code;
1491 arg->sreg1 = in->dreg;
1492 arg->type = in->type;
1493
1494 g_assert (in->dreg != -1);
1495
1496 if (ainfo->storage == ArgGSharedVt) {
1497 arg->opcode = OP_OUTARG_VT;
1498 arg->sreg1 = in->dreg;
1499 arg->klass = in->klass;
1500 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1501 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1502 sp_offset += 4;
1503 MONO_ADD_INS (cfg->cbb, arg);
1504 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1505 guint32 align;
1506 guint32 size;
1507
1508 g_assert (in->klass);
1509
1510 if (t->type == MONO_TYPE_TYPEDBYREF) {
1511 size = sizeof (MonoTypedRef);
1512 align = sizeof (gpointer);
1513 }
1514 else {
1515 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1516 }
1517
1518 if (size > 0) {
1519 arg->opcode = OP_OUTARG_VT;
1520 arg->sreg1 = in->dreg;
1521 arg->klass = in->klass;
1522 arg->backend.size = size;
1523 arg->inst_p0 = call;
1524 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1525 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1526
1527 MONO_ADD_INS (cfg->cbb, arg);
1528 if (ainfo->storage != ArgValuetypeInReg) {
1529 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1530 }
1531 }
1532 } else {
1533 switch (ainfo->storage) {
1534 case ArgOnStack:
1535 if (!t->byref) {
1536 if (t->type == MONO_TYPE_R4) {
1537 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 argsize = 4;
1539 } else if (t->type == MONO_TYPE_R8) {
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1541 argsize = 8;
1542 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1544 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1545 argsize = 4;
1546 } else {
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1548 argsize = 4;
1549 }
1550 } else {
1551 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 argsize = 4;
1553 }
1554 break;
1555 case ArgInIReg:
1556 arg->opcode = OP_MOVE;
1557 arg->dreg = ainfo->reg;
1558 MONO_ADD_INS (cfg->cbb, arg);
1559 argsize = 0;
1560 break;
1561 default:
1562 g_assert_not_reached ();
1563 }
1564
1565 if (cfg->compute_gc_maps) {
1566 if (argsize == 4) {
1567 /* FIXME: The == STACK_OBJ check might be fragile ? */
1568 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1569 /* this */
1570 if (call->need_unbox_trampoline)
1571 /* The unbox trampoline transforms this into a managed pointer */
1572 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1573 else
1574 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1575 } else {
1576 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1577 }
1578 } else {
1579 /* i8/r8 */
1580 for (j = 0; j < argsize; j += 4)
1581 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 }
1583 }
1584 }
1585
1586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1587 /* Emit the signature cookie just before the implicit arguments */
1588 emit_sig_cookie (cfg, call, cinfo);
1589 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1590 }
1591 }
1592
1593 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1594 MonoInst *vtarg;
1595
1596 if (cinfo->ret.storage == ArgValuetypeInReg) {
1597 /* Already done */
1598 }
1599 else if (cinfo->ret.storage == ArgInIReg) {
1600 NOT_IMPLEMENTED;
1601 /* The return address is passed in a register */
1602 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1603 vtarg->sreg1 = call->inst.dreg;
1604 vtarg->dreg = mono_alloc_ireg (cfg);
1605 MONO_ADD_INS (cfg->cbb, vtarg);
1606
1607 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1608 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1609 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1610 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1611 }
1612 }
1613
1614 call->stack_usage = cinfo->stack_usage;
1615 call->stack_align_amount = cinfo->stack_align_amount;
1616 }
1617
1618 void
1619 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1620 {
1621 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1622 ArgInfo *ainfo = ins->inst_p1;
1623 int size = ins->backend.size;
1624
1625 if (ainfo->storage == ArgValuetypeInReg) {
1626 int dreg = mono_alloc_ireg (cfg);
1627 switch (size) {
1628 case 1:
1629 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1630 break;
1631 case 2:
1632 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1633 break;
1634 case 4:
1635 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1636 break;
1637 case 3: /* FIXME */
1638 default:
1639 g_assert_not_reached ();
1640 }
1641 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1642 }
1643 else {
1644 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1645 /* Pass by addr */
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1647 } else if (size <= 4) {
1648 int dreg = mono_alloc_ireg (cfg);
1649 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1650 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1651 } else if (size <= 20) {
1652 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1653 } else {
1654 // FIXME: Code growth
1655 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1656 }
1657 }
1658 }
1659
1660 void
1661 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1662 {
1663 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1664
1665 if (!ret->byref) {
1666 if (ret->type == MONO_TYPE_R4) {
1667 if (COMPILE_LLVM (cfg))
1668 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1669 /* Nothing to do */
1670 return;
1671 } else if (ret->type == MONO_TYPE_R8) {
1672 if (COMPILE_LLVM (cfg))
1673 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1674 /* Nothing to do */
1675 return;
1676 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1677 if (COMPILE_LLVM (cfg))
1678 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1679 else {
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1681 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1682 }
1683 return;
1684 }
1685 }
1686
1687 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1688 }
1689
1690 /*
1691 * Allow tracing to work with this interface (with an optional argument)
1692 */
1693 void*
1694 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1695 {
1696 guchar *code = p;
1697
1698 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1699 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1700
1701 /* if some args are passed in registers, we need to save them here */
1702 x86_push_reg (code, X86_EBP);
1703
1704 if (cfg->compile_aot) {
1705 x86_push_imm (code, cfg->method);
1706 x86_mov_reg_imm (code, X86_EAX, func);
1707 x86_call_reg (code, X86_EAX);
1708 } else {
1709 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1710 x86_push_imm (code, cfg->method);
1711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1712 x86_call_code (code, 0);
1713 }
1714 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1715
1716 return code;
1717 }
1718
1719 enum {
1720 SAVE_NONE,
1721 SAVE_STRUCT,
1722 SAVE_EAX,
1723 SAVE_EAX_EDX,
1724 SAVE_FP
1725 };
1726
1727 void*
1728 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1729 {
1730 guchar *code = p;
1731 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1732 MonoMethod *method = cfg->method;
1733 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1734
1735 switch (ret_type->type) {
1736 case MONO_TYPE_VOID:
1737 /* special case string .ctor icall */
1738 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1739 save_mode = SAVE_EAX;
1740 stack_usage = enable_arguments ? 8 : 4;
1741 } else
1742 save_mode = SAVE_NONE;
1743 break;
1744 case MONO_TYPE_I8:
1745 case MONO_TYPE_U8:
1746 save_mode = SAVE_EAX_EDX;
1747 stack_usage = enable_arguments ? 16 : 8;
1748 break;
1749 case MONO_TYPE_R4:
1750 case MONO_TYPE_R8:
1751 save_mode = SAVE_FP;
1752 stack_usage = enable_arguments ? 16 : 8;
1753 break;
1754 case MONO_TYPE_GENERICINST:
1755 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1756 save_mode = SAVE_EAX;
1757 stack_usage = enable_arguments ? 8 : 4;
1758 break;
1759 }
1760 /* Fall through */
1761 case MONO_TYPE_VALUETYPE:
1762 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1763 save_mode = SAVE_STRUCT;
1764 stack_usage = enable_arguments ? 4 : 0;
1765 break;
1766 default:
1767 save_mode = SAVE_EAX;
1768 stack_usage = enable_arguments ? 8 : 4;
1769 break;
1770 }
1771
1772 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1773
1774 switch (save_mode) {
1775 case SAVE_EAX_EDX:
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1778 if (enable_arguments) {
1779 x86_push_reg (code, X86_EDX);
1780 x86_push_reg (code, X86_EAX);
1781 arg_size = 8;
1782 }
1783 break;
1784 case SAVE_EAX:
1785 x86_push_reg (code, X86_EAX);
1786 if (enable_arguments) {
1787 x86_push_reg (code, X86_EAX);
1788 arg_size = 4;
1789 }
1790 break;
1791 case SAVE_FP:
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1794 if (enable_arguments) {
1795 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1796 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 arg_size = 8;
1798 }
1799 break;
1800 case SAVE_STRUCT:
1801 if (enable_arguments) {
1802 x86_push_membase (code, X86_EBP, 8);
1803 arg_size = 4;
1804 }
1805 break;
1806 case SAVE_NONE:
1807 default:
1808 break;
1809 }
1810
1811 if (cfg->compile_aot) {
1812 x86_push_imm (code, method);
1813 x86_mov_reg_imm (code, X86_EAX, func);
1814 x86_call_reg (code, X86_EAX);
1815 } else {
1816 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1817 x86_push_imm (code, method);
1818 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1819 x86_call_code (code, 0);
1820 }
1821
1822 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1823
1824 switch (save_mode) {
1825 case SAVE_EAX_EDX:
1826 x86_pop_reg (code, X86_EAX);
1827 x86_pop_reg (code, X86_EDX);
1828 break;
1829 case SAVE_EAX:
1830 x86_pop_reg (code, X86_EAX);
1831 break;
1832 case SAVE_FP:
1833 x86_fld_membase (code, X86_ESP, 0, TRUE);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1835 break;
1836 case SAVE_NONE:
1837 default:
1838 break;
1839 }
1840
1841 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842
1843 return code;
1844 }
1845
1846 #define EMIT_COND_BRANCH(ins,cond,sign) \
1847 if (ins->inst_true_bb->native_offset) { \
1848 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1849 } else { \
1850 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1851 if ((cfg->opt & MONO_OPT_BRANCH) && \
1852 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1853 x86_branch8 (code, cond, 0, sign); \
1854 else \
1855 x86_branch32 (code, cond, 0, sign); \
1856 }
1857
1858 /*
1859 * Emit an exception if condition is fail and
1860 * if possible do a directly branch to target
1861 */
1862 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1863 do { \
1864 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1865 if (tins == NULL) { \
1866 mono_add_patch_info (cfg, code - cfg->native_code, \
1867 MONO_PATCH_INFO_EXC, exc_name); \
1868 x86_branch32 (code, cond, 0, signed); \
1869 } else { \
1870 EMIT_COND_BRANCH (tins, cond, signed); \
1871 } \
1872 } while (0);
1873
1874 #define EMIT_FPCOMPARE(code) do { \
1875 x86_fcompp (code); \
1876 x86_fnstsw (code); \
1877 } while (0);
1878
1879
1880 static guint8*
1881 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1882 {
1883 gboolean needs_paddings = TRUE;
1884 guint32 pad_size;
1885 MonoJumpInfo *jinfo = NULL;
1886
1887 if (cfg->abs_patches) {
1888 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1889 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1890 needs_paddings = FALSE;
1891 }
1892
1893 if (cfg->compile_aot)
1894 needs_paddings = FALSE;
1895 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1896 This is required for code patching to be safe on SMP machines.
1897 */
1898 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1899 #ifndef __native_client_codegen__
1900 if (needs_paddings && pad_size)
1901 x86_padding (code, 4 - pad_size);
1902 #endif
1903
1904 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1905 x86_call_code (code, 0);
1906
1907 return code;
1908 }
1909
1910 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1911
1912 /*
1913 * mono_peephole_pass_1:
1914 *
1915 * Perform peephole opts which should/can be performed before local regalloc
1916 */
1917 void
1918 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1919 {
1920 MonoInst *ins, *n;
1921
1922 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1923 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1924
1925 switch (ins->opcode) {
1926 case OP_IADD_IMM:
1927 case OP_ADD_IMM:
1928 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1929 /*
1930 * X86_LEA is like ADD, but doesn't have the
1931 * sreg1==dreg restriction.
1932 */
1933 ins->opcode = OP_X86_LEA_MEMBASE;
1934 ins->inst_basereg = ins->sreg1;
1935 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1936 ins->opcode = OP_X86_INC_REG;
1937 break;
1938 case OP_SUB_IMM:
1939 case OP_ISUB_IMM:
1940 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1941 ins->opcode = OP_X86_LEA_MEMBASE;
1942 ins->inst_basereg = ins->sreg1;
1943 ins->inst_imm = -ins->inst_imm;
1944 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1945 ins->opcode = OP_X86_DEC_REG;
1946 break;
1947 case OP_COMPARE_IMM:
1948 case OP_ICOMPARE_IMM:
1949 /* OP_COMPARE_IMM (reg, 0)
1950 * -->
1951 * OP_X86_TEST_NULL (reg)
1952 */
1953 if (!ins->inst_imm)
1954 ins->opcode = OP_X86_TEST_NULL;
1955 break;
1956 case OP_X86_COMPARE_MEMBASE_IMM:
1957 /*
1958 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1959 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1960 * -->
1961 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1962 * OP_COMPARE_IMM reg, imm
1963 *
1964 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1965 */
1966 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1967 ins->inst_basereg == last_ins->inst_destbasereg &&
1968 ins->inst_offset == last_ins->inst_offset) {
1969 ins->opcode = OP_COMPARE_IMM;
1970 ins->sreg1 = last_ins->sreg1;
1971
1972 /* check if we can remove cmp reg,0 with test null */
1973 if (!ins->inst_imm)
1974 ins->opcode = OP_X86_TEST_NULL;
1975 }
1976
1977 break;
1978 case OP_X86_PUSH_MEMBASE:
1979 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1980 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1981 ins->inst_basereg == last_ins->inst_destbasereg &&
1982 ins->inst_offset == last_ins->inst_offset) {
1983 ins->opcode = OP_X86_PUSH;
1984 ins->sreg1 = last_ins->sreg1;
1985 }
1986 break;
1987 }
1988
1989 mono_peephole_ins (bb, ins);
1990 }
1991 }
1992
1993 void
1994 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1995 {
1996 MonoInst *ins, *n;
1997
1998 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1999 switch (ins->opcode) {
2000 case OP_ICONST:
2001 /* reg = 0 -> XOR (reg, reg) */
2002 /* XOR sets cflags on x86, so we cant do it always */
2003 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2004 MonoInst *ins2;
2005
2006 ins->opcode = OP_IXOR;
2007 ins->sreg1 = ins->dreg;
2008 ins->sreg2 = ins->dreg;
2009
2010 /*
2011 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2012 * since it takes 3 bytes instead of 7.
2013 */
2014 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2015 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STORE_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2018 }
2019 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2020 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2021 ins2->sreg1 = ins->dreg;
2022 }
2023 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2024 /* Continue iteration */
2025 }
2026 else
2027 break;
2028 }
2029 }
2030 break;
2031 case OP_IADD_IMM:
2032 case OP_ADD_IMM:
2033 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2034 ins->opcode = OP_X86_INC_REG;
2035 break;
2036 case OP_ISUB_IMM:
2037 case OP_SUB_IMM:
2038 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2039 ins->opcode = OP_X86_DEC_REG;
2040 break;
2041 }
2042
2043 mono_peephole_ins (bb, ins);
2044 }
2045 }
2046
2047 /*
2048 * mono_arch_lowering_pass:
2049 *
2050 * Converts complex opcodes into simpler ones so that each IR instruction
2051 * corresponds to one machine instruction.
2052 */
2053 void
2054 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2055 {
2056 MonoInst *ins, *next;
2057
2058 /*
2059 * FIXME: Need to add more instructions, but the current machine
2060 * description can't model some parts of the composite instructions like
2061 * cdq.
2062 */
2063 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2064 switch (ins->opcode) {
2065 case OP_IREM_IMM:
2066 case OP_IDIV_IMM:
2067 case OP_IDIV_UN_IMM:
2068 case OP_IREM_UN_IMM:
2069 /*
2070 * Keep the cases where we could generated optimized code, otherwise convert
2071 * to the non-imm variant.
2072 */
2073 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2074 break;
2075 mono_decompose_op_imm (cfg, bb, ins);
2076 break;
2077 default:
2078 break;
2079 }
2080 }
2081
2082 bb->max_vreg = cfg->next_vreg;
2083 }
2084
2085 static const int
2086 branch_cc_table [] = {
2087 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2089 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2090 };
2091
2092 /* Maps CMP_... constants to X86_CC_... constants */
2093 static const int
2094 cc_table [] = {
2095 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2096 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2097 };
2098
2099 static const int
2100 cc_signed_table [] = {
2101 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2102 FALSE, FALSE, FALSE, FALSE
2103 };
2104
2105 static unsigned char*
2106 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2107 {
2108 #define XMM_TEMP_REG 0
2109 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2110 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2111 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2112 /* optimize by assigning a local var for this use so we avoid
2113 * the stack manipulations */
2114 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2115 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2116 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2117 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2118 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2119 if (size == 1)
2120 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2121 else if (size == 2)
2122 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2123 return code;
2124 }
2125 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2126 x86_fnstcw_membase(code, X86_ESP, 0);
2127 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2128 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2129 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2130 x86_fldcw_membase (code, X86_ESP, 2);
2131 if (size == 8) {
2132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2133 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2134 x86_pop_reg (code, dreg);
2135 /* FIXME: need the high register
2136 * x86_pop_reg (code, dreg_high);
2137 */
2138 } else {
2139 x86_push_reg (code, X86_EAX); // SP = SP - 4
2140 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2141 x86_pop_reg (code, dreg);
2142 }
2143 x86_fldcw_membase (code, X86_ESP, 0);
2144 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2145
2146 if (size == 1)
2147 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2148 else if (size == 2)
2149 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2150 return code;
2151 }
2152
2153 static unsigned char*
2154 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2155 {
2156 int sreg = tree->sreg1;
2157 int need_touch = FALSE;
2158
2159 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2160 need_touch = TRUE;
2161 #endif
2162
2163 if (need_touch) {
2164 guint8* br[5];
2165
2166 /*
2167 * Under Windows:
2168 * If requested stack size is larger than one page,
2169 * perform stack-touch operation
2170 */
2171 /*
2172 * Generate stack probe code.
2173 * Under Windows, it is necessary to allocate one page at a time,
2174 * "touching" stack after each successful sub-allocation. This is
2175 * because of the way stack growth is implemented - there is a
2176 * guard page before the lowest stack page that is currently commited.
2177 * Stack normally grows sequentially so OS traps access to the
2178 * guard page and commits more pages when needed.
2179 */
2180 x86_test_reg_imm (code, sreg, ~0xFFF);
2181 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2182
2183 br[2] = code; /* loop */
2184 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2185 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2186
2187 /*
2188 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2189 * that follows only initializes the last part of the area.
2190 */
2191 /* Same as the init code below with size==0x1000 */
2192 if (tree->flags & MONO_INST_INIT) {
2193 x86_push_reg (code, X86_EAX);
2194 x86_push_reg (code, X86_ECX);
2195 x86_push_reg (code, X86_EDI);
2196 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2197 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2198 if (cfg->param_area)
2199 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2200 else
2201 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2202 x86_cld (code);
2203 x86_prefix (code, X86_REP_PREFIX);
2204 x86_stosl (code);
2205 x86_pop_reg (code, X86_EDI);
2206 x86_pop_reg (code, X86_ECX);
2207 x86_pop_reg (code, X86_EAX);
2208 }
2209
2210 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2211 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2212 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2213 x86_patch (br[3], br[2]);
2214 x86_test_reg_reg (code, sreg, sreg);
2215 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2216 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2217
2218 br[1] = code; x86_jump8 (code, 0);
2219
2220 x86_patch (br[0], code);
2221 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2222 x86_patch (br[1], code);
2223 x86_patch (br[4], code);
2224 }
2225 else
2226 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2227
2228 if (tree->flags & MONO_INST_INIT) {
2229 int offset = 0;
2230 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2231 x86_push_reg (code, X86_EAX);
2232 offset += 4;
2233 }
2234 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2235 x86_push_reg (code, X86_ECX);
2236 offset += 4;
2237 }
2238 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2239 x86_push_reg (code, X86_EDI);
2240 offset += 4;
2241 }
2242
2243 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2244 if (sreg != X86_ECX)
2245 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2246 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2247
2248 if (cfg->param_area)
2249 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2250 else
2251 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2252 x86_cld (code);
2253 x86_prefix (code, X86_REP_PREFIX);
2254 x86_stosl (code);
2255
2256 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2257 x86_pop_reg (code, X86_EDI);
2258 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2259 x86_pop_reg (code, X86_ECX);
2260 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2261 x86_pop_reg (code, X86_EAX);
2262 }
2263 return code;
2264 }
2265
2266
2267 static guint8*
2268 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2269 {
2270 /* Move return value to the target register */
2271 switch (ins->opcode) {
2272 case OP_CALL:
2273 case OP_CALL_REG:
2274 case OP_CALL_MEMBASE:
2275 if (ins->dreg != X86_EAX)
2276 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2277 break;
2278 default:
2279 break;
2280 }
2281
2282 return code;
2283 }
2284
2285 #ifdef __APPLE__
2286 static int tls_gs_offset;
2287 #endif
2288
2289 gboolean
2290 mono_x86_have_tls_get (void)
2291 {
2292 #ifdef TARGET_MACH
2293 static gboolean have_tls_get = FALSE;
2294 static gboolean inited = FALSE;
2295 guint32 *ins;
2296
2297 if (inited)
2298 return have_tls_get;
2299
2300 #ifdef MONO_HAVE_FAST_TLS
2301 ins = (guint32*)pthread_getspecific;
2302 /*
2303 * We're looking for these two instructions:
2304 *
2305 * mov 0x4(%esp),%eax
2306 * mov %gs:[offset](,%eax,4),%eax
2307 */
2308 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2309 tls_gs_offset = ins [2];
2310 #endif
2311
2312 inited = TRUE;
2313
2314 return have_tls_get;
2315 #elif defined(TARGET_ANDROID)
2316 return FALSE;
2317 #else
2318 return TRUE;
2319 #endif
2320 }
2321
2322 static guint8*
2323 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2324 {
2325 #if defined(__APPLE__)
2326 x86_prefix (code, X86_GS_PREFIX);
2327 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2328 #elif defined(TARGET_WIN32)
2329 g_assert_not_reached ();
2330 #else
2331 x86_prefix (code, X86_GS_PREFIX);
2332 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2333 #endif
2334 return code;
2335 }
2336
2337 /*
2338 * mono_x86_emit_tls_get:
2339 * @code: buffer to store code to
2340 * @dreg: hard register where to place the result
2341 * @tls_offset: offset info
2342 *
2343 * mono_x86_emit_tls_get emits in @code the native code that puts in
2344 * the dreg register the item in the thread local storage identified
2345 * by tls_offset.
2346 *
2347 * Returns: a pointer to the end of the stored code
2348 */
2349 guint8*
2350 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2351 {
2352 #if defined(__APPLE__)
2353 x86_prefix (code, X86_GS_PREFIX);
2354 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2355 #elif defined(TARGET_WIN32)
2356 /*
2357 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2358 * Journal and/or a disassembly of the TlsGet () function.
2359 */
2360 x86_prefix (code, X86_FS_PREFIX);
2361 x86_mov_reg_mem (code, dreg, 0x18, 4);
2362 if (tls_offset < 64) {
2363 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2364 } else {
2365 guint8 *buf [16];
2366
2367 g_assert (tls_offset < 0x440);
2368 /* Load TEB->TlsExpansionSlots */
2369 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2370 x86_test_reg_reg (code, dreg, dreg);
2371 buf [0] = code;
2372 x86_branch (code, X86_CC_EQ, code, TRUE);
2373 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2374 x86_patch (buf [0], code);
2375 }
2376 #else
2377 if (optimize_for_xen) {
2378 x86_prefix (code, X86_GS_PREFIX);
2379 x86_mov_reg_mem (code, dreg, 0, 4);
2380 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2381 } else {
2382 x86_prefix (code, X86_GS_PREFIX);
2383 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2384 }
2385 #endif
2386 return code;
2387 }
2388
2389 static guint8*
2390 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2391 {
2392 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2393 #if defined(__APPLE__) || defined(__linux__)
2394 if (dreg != offset_reg)
2395 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2396 x86_prefix (code, X86_GS_PREFIX);
2397 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2398 #else
2399 g_assert_not_reached ();
2400 #endif
2401 return code;
2402 }
2403
2404 guint8*
2405 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2406 {
2407 return emit_tls_get_reg (code, dreg, offset_reg);
2408 }
2409
2410 static guint8*
2411 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2412 {
2413 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2414 #ifdef HOST_WIN32
2415 g_assert_not_reached ();
2416 #elif defined(__APPLE__) || defined(__linux__)
2417 x86_prefix (code, X86_GS_PREFIX);
2418 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2419 #else
2420 g_assert_not_reached ();
2421 #endif
2422 return code;
2423 }
2424
2425 /*
2426 * mono_arch_translate_tls_offset:
2427 *
2428 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2429 */
2430 int
2431 mono_arch_translate_tls_offset (int offset)
2432 {
2433 #ifdef __APPLE__
2434 return tls_gs_offset + (offset * 4);
2435 #else
2436 return offset;
2437 #endif
2438 }
2439
2440 /*
2441 * emit_setup_lmf:
2442 *
2443 * Emit code to initialize an LMF structure at LMF_OFFSET.
2444 */
2445 static guint8*
2446 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2447 {
2448 /* save all caller saved regs */
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2450 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2451 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2452 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2454 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2455 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2456
2457 /* save the current IP */
2458 if (cfg->compile_aot) {
2459 /* This pushes the current ip */
2460 x86_call_imm (code, 0);
2461 x86_pop_reg (code, X86_EAX);
2462 } else {
2463 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2464 x86_mov_reg_imm (code, X86_EAX, 0);
2465 }
2466 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2467
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2475 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2476 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2477
2478 return code;
2479 }
2480
2481 #define REAL_PRINT_REG(text,reg) \
2482 mono_assert (reg >= 0); \
2483 x86_push_reg (code, X86_EAX); \
2484 x86_push_reg (code, X86_EDX); \
2485 x86_push_reg (code, X86_ECX); \
2486 x86_push_reg (code, reg); \
2487 x86_push_imm (code, reg); \
2488 x86_push_imm (code, text " %d %p\n"); \
2489 x86_mov_reg_imm (code, X86_EAX, printf); \
2490 x86_call_reg (code, X86_EAX); \
2491 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2492 x86_pop_reg (code, X86_ECX); \
2493 x86_pop_reg (code, X86_EDX); \
2494 x86_pop_reg (code, X86_EAX);
2495
2496 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2497 #ifdef __native__client_codegen__
2498 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2499 #endif
2500
2501 /* benchmark and set based on cpu */
2502 #define LOOP_ALIGNMENT 8
2503 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2504
2505 #ifndef DISABLE_JIT
2506 void
2507 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2508 {
2509 MonoInst *ins;
2510 MonoCallInst *call;
2511 guint offset;
2512 guint8 *code = cfg->native_code + cfg->code_len;
2513 int max_len, cpos;
2514
2515 if (cfg->opt & MONO_OPT_LOOP) {
2516 int pad, align = LOOP_ALIGNMENT;
2517 /* set alignment depending on cpu */
2518 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2519 pad = align - pad;
2520 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2521 x86_padding (code, pad);
2522 cfg->code_len += pad;
2523 bb->native_offset = cfg->code_len;
2524 }
2525 }
2526 #ifdef __native_client_codegen__
2527 {
2528 /* For Native Client, all indirect call/jump targets must be */
2529 /* 32-byte aligned. Exception handler blocks are jumped to */
2530 /* indirectly as well. */
2531 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2532 (bb->flags & BB_EXCEPTION_HANDLER);
2533
2534 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2535 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2536 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2537 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2538 cfg->code_len += pad;
2539 bb->native_offset = cfg->code_len;
2540 }
2541 }
2542 #endif /* __native_client_codegen__ */
2543 if (cfg->verbose_level > 2)
2544 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2545
2546 cpos = bb->max_offset;
2547
2548 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2549 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2550 g_assert (!cfg->compile_aot);
2551 cpos += 6;
2552
2553 cov->data [bb->dfn].cil_code = bb->cil_code;
2554 /* this is not thread save, but good enough */
2555 x86_inc_mem (code, &cov->data [bb->dfn].count);
2556 }
2557
2558 offset = code - cfg->native_code;
2559
2560 mono_debug_open_block (cfg, bb, offset);
2561
2562 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2563 x86_breakpoint (code);
2564
2565 MONO_BB_FOR_EACH_INS (bb, ins) {
2566 offset = code - cfg->native_code;
2567
2568 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2569
2570 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2571
2572 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2573 cfg->code_size *= 2;
2574 cfg->native_code = mono_realloc_native_code(cfg);
2575 code = cfg->native_code + offset;
2576 cfg->stat_code_reallocs++;
2577 }
2578
2579 if (cfg->debug_info)
2580 mono_debug_record_line_number (cfg, ins, offset);
2581
2582 switch (ins->opcode) {
2583 case OP_BIGMUL:
2584 x86_mul_reg (code, ins->sreg2, TRUE);
2585 break;
2586 case OP_BIGMUL_UN:
2587 x86_mul_reg (code, ins->sreg2, FALSE);
2588 break;
2589 case OP_X86_SETEQ_MEMBASE:
2590 case OP_X86_SETNE_MEMBASE:
2591 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2592 ins->inst_basereg, ins->inst_offset, TRUE);
2593 break;
2594 case OP_STOREI1_MEMBASE_IMM:
2595 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2596 break;
2597 case OP_STOREI2_MEMBASE_IMM:
2598 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2599 break;
2600 case OP_STORE_MEMBASE_IMM:
2601 case OP_STOREI4_MEMBASE_IMM:
2602 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2603 break;
2604 case OP_STOREI1_MEMBASE_REG:
2605 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2606 break;
2607 case OP_STOREI2_MEMBASE_REG:
2608 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2609 break;
2610 case OP_STORE_MEMBASE_REG:
2611 case OP_STOREI4_MEMBASE_REG:
2612 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2613 break;
2614 case OP_STORE_MEM_IMM:
2615 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2616 break;
2617 case OP_LOADU4_MEM:
2618 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2619 break;
2620 case OP_LOAD_MEM:
2621 case OP_LOADI4_MEM:
2622 /* These are created by the cprop pass so they use inst_imm as the source */
2623 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2624 break;
2625 case OP_LOADU1_MEM:
2626 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2627 break;
2628 case OP_LOADU2_MEM:
2629 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2630 break;
2631 case OP_LOAD_MEMBASE:
2632 case OP_LOADI4_MEMBASE:
2633 case OP_LOADU4_MEMBASE:
2634 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2635 break;
2636 case OP_LOADU1_MEMBASE:
2637 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2638 break;
2639 case OP_LOADI1_MEMBASE:
2640 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2641 break;
2642 case OP_LOADU2_MEMBASE:
2643 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2644 break;
2645 case OP_LOADI2_MEMBASE:
2646 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2647 break;
2648 case OP_ICONV_TO_I1:
2649 case OP_SEXT_I1:
2650 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2651 break;
2652 case OP_ICONV_TO_I2:
2653 case OP_SEXT_I2:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2655 break;
2656 case OP_ICONV_TO_U1:
2657 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2658 break;
2659 case OP_ICONV_TO_U2:
2660 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2661 break;
2662 case OP_COMPARE:
2663 case OP_ICOMPARE:
2664 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2665 break;
2666 case OP_COMPARE_IMM:
2667 case OP_ICOMPARE_IMM:
2668 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2669 break;
2670 case OP_X86_COMPARE_MEMBASE_REG:
2671 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2672 break;
2673 case OP_X86_COMPARE_MEMBASE_IMM:
2674 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2675 break;
2676 case OP_X86_COMPARE_MEMBASE8_IMM:
2677 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2678 break;
2679 case OP_X86_COMPARE_REG_MEMBASE:
2680 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2681 break;
2682 case OP_X86_COMPARE_MEM_IMM:
2683 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2684 break;
2685 case OP_X86_TEST_NULL:
2686 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2687 break;
2688 case OP_X86_ADD_MEMBASE_IMM:
2689 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2690 break;
2691 case OP_X86_ADD_REG_MEMBASE:
2692 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2693 break;
2694 case OP_X86_SUB_MEMBASE_IMM:
2695 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2696 break;
2697 case OP_X86_SUB_REG_MEMBASE:
2698 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2699 break;
2700 case OP_X86_AND_MEMBASE_IMM:
2701 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2702 break;
2703 case OP_X86_OR_MEMBASE_IMM:
2704 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2705 break;
2706 case OP_X86_XOR_MEMBASE_IMM:
2707 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2708 break;
2709 case OP_X86_ADD_MEMBASE_REG:
2710 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2711 break;
2712 case OP_X86_SUB_MEMBASE_REG:
2713 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2714 break;
2715 case OP_X86_AND_MEMBASE_REG:
2716 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2717 break;
2718 case OP_X86_OR_MEMBASE_REG:
2719 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2720 break;
2721 case OP_X86_XOR_MEMBASE_REG:
2722 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2723 break;
2724 case OP_X86_INC_MEMBASE:
2725 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2726 break;
2727 case OP_X86_INC_REG:
2728 x86_inc_reg (code, ins->dreg);
2729 break;
2730 case OP_X86_DEC_MEMBASE:
2731 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2732 break;
2733 case OP_X86_DEC_REG:
2734 x86_dec_reg (code, ins->dreg);
2735 break;
2736 case OP_X86_MUL_REG_MEMBASE:
2737 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2738 break;
2739 case OP_X86_AND_REG_MEMBASE:
2740 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2741 break;
2742 case OP_X86_OR_REG_MEMBASE:
2743 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2744 break;
2745 case OP_X86_XOR_REG_MEMBASE:
2746 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2747 break;
2748 case OP_BREAK:
2749 x86_breakpoint (code);
2750 break;
2751 case OP_RELAXED_NOP:
2752 x86_prefix (code, X86_REP_PREFIX);
2753 x86_nop (code);
2754 break;
2755 case OP_HARD_NOP:
2756 x86_nop (code);
2757 break;
2758 case OP_NOP:
2759 case OP_DUMMY_USE:
2760 case OP_DUMMY_STORE:
2761 case OP_DUMMY_ICONST:
2762 case OP_DUMMY_R8CONST:
2763 case OP_NOT_REACHED:
2764 case OP_NOT_NULL:
2765 break;
2766 case OP_IL_SEQ_POINT:
2767 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2768 break;
2769 case OP_SEQ_POINT: {
2770 int i;
2771
2772 if (cfg->compile_aot)
2773 NOT_IMPLEMENTED;
2774
2775 /*
2776 * Read from the single stepping trigger page. This will cause a
2777 * SIGSEGV when single stepping is enabled.
2778 * We do this _before_ the breakpoint, so single stepping after
2779 * a breakpoint is hit will step to the next IL offset.
2780 */
2781 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2782 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2783
2784 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2785
2786 /*
2787 * A placeholder for a possible breakpoint inserted by
2788 * mono_arch_set_breakpoint ().
2789 */
2790 for (i = 0; i < 6; ++i)
2791 x86_nop (code);
2792 /*
2793 * Add an additional nop so skipping the bp doesn't cause the ip to point
2794 * to another IL offset.
2795 */
2796 x86_nop (code);
2797 break;
2798 }
2799 case OP_ADDCC:
2800 case OP_IADDCC:
2801 case OP_IADD:
2802 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2803 break;
2804 case OP_ADC:
2805 case OP_IADC:
2806 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2807 break;
2808 case OP_ADDCC_IMM:
2809 case OP_ADD_IMM:
2810 case OP_IADD_IMM:
2811 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2812 break;
2813 case OP_ADC_IMM:
2814 case OP_IADC_IMM:
2815 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2816 break;
2817 case OP_SUBCC:
2818 case OP_ISUBCC:
2819 case OP_ISUB:
2820 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2821 break;
2822 case OP_SBB:
2823 case OP_ISBB:
2824 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2825 break;
2826 case OP_SUBCC_IMM:
2827 case OP_SUB_IMM:
2828 case OP_ISUB_IMM:
2829 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2830 break;
2831 case OP_SBB_IMM:
2832 case OP_ISBB_IMM:
2833 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2834 break;
2835 case OP_IAND:
2836 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2837 break;
2838 case OP_AND_IMM:
2839 case OP_IAND_IMM:
2840 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2841 break;
2842 case OP_IDIV:
2843 case OP_IREM:
2844 #if defined( __native_client_codegen__ )
2845 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2846 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2847 #endif
2848 /*
2849 * The code is the same for div/rem, the allocator will allocate dreg
2850 * to RAX/RDX as appropriate.
2851 */
2852 if (ins->sreg2 == X86_EDX) {
2853 /* cdq clobbers this */
2854 x86_push_reg (code, ins->sreg2);
2855 x86_cdq (code);
2856 x86_div_membase (code, X86_ESP, 0, TRUE);
2857 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2858 } else {
2859 x86_cdq (code);
2860 x86_div_reg (code, ins->sreg2, TRUE);
2861 }
2862 break;
2863 case OP_IDIV_UN:
2864 case OP_IREM_UN:
2865 #if defined( __native_client_codegen__ )
2866 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2867 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2868 #endif
2869 if (ins->sreg2 == X86_EDX) {
2870 x86_push_reg (code, ins->sreg2);
2871 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2872 x86_div_membase (code, X86_ESP, 0, FALSE);
2873 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2874 } else {
2875 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2876 x86_div_reg (code, ins->sreg2, FALSE);
2877 }
2878 break;
2879 case OP_DIV_IMM:
2880 #if defined( __native_client_codegen__ )
2881 if (ins->inst_imm == 0) {
2882 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2883 x86_jump32 (code, 0);
2884 break;
2885 }
2886 #endif
2887 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2888 x86_cdq (code);
2889 x86_div_reg (code, ins->sreg2, TRUE);
2890 break;
2891 case OP_IREM_IMM: {
2892 int power = mono_is_power_of_two (ins->inst_imm);
2893
2894 g_assert (ins->sreg1 == X86_EAX);
2895 g_assert (ins->dreg == X86_EAX);
2896 g_assert (power >= 0);
2897
2898 if (power == 1) {
2899 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2900 x86_cdq (code);
2901 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2902 /*
2903 * If the divident is >= 0, this does not nothing. If it is positive, it
2904 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2905 */
2906 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2907 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2908 } else if (power == 0) {
2909 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2910 } else {
2911 /* Based on gcc code */
2912
2913 /* Add compensation for negative dividents */
2914 x86_cdq (code);
2915 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2916 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2917 /* Compute remainder */
2918 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2919 /* Remove compensation */
2920 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2921 }
2922 break;
2923 }
2924 case OP_IOR:
2925 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2926 break;
2927 case OP_OR_IMM:
2928 case OP_IOR_IMM:
2929 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2930 break;
2931 case OP_IXOR:
2932 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2933 break;
2934 case OP_XOR_IMM:
2935 case OP_IXOR_IMM:
2936 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2937 break;
2938 case OP_ISHL:
2939 g_assert (ins->sreg2 == X86_ECX);
2940 x86_shift_reg (code, X86_SHL, ins->dreg);
2941 break;
2942 case OP_ISHR:
2943 g_assert (ins->sreg2 == X86_ECX);
2944 x86_shift_reg (code, X86_SAR, ins->dreg);
2945 break;
2946 case OP_SHR_IMM:
2947 case OP_ISHR_IMM:
2948 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2949 break;
2950 case OP_SHR_UN_IMM:
2951 case OP_ISHR_UN_IMM:
2952 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2953 break;
2954 case OP_ISHR_UN:
2955 g_assert (ins->sreg2 == X86_ECX);
2956 x86_shift_reg (code, X86_SHR, ins->dreg);
2957 break;
2958 case OP_SHL_IMM:
2959 case OP_ISHL_IMM:
2960 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2961 break;
2962 case OP_LSHL: {
2963 guint8 *jump_to_end;
2964
2965 /* handle shifts below 32 bits */
2966 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2967 x86_shift_reg (code, X86_SHL, ins->sreg1);
2968
2969 x86_test_reg_imm (code, X86_ECX, 32);
2970 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2971
2972 /* handle shift over 32 bit */
2973 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2974 x86_clear_reg (code, ins->sreg1);
2975
2976 x86_patch (jump_to_end, code);
2977 }
2978 break;
2979 case OP_LSHR: {
2980 guint8 *jump_to_end;
2981
2982 /* handle shifts below 32 bits */
2983 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2984 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2985
2986 x86_test_reg_imm (code, X86_ECX, 32);
2987 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2988
2989 /* handle shifts over 31 bits */
2990 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2991 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2992
2993 x86_patch (jump_to_end, code);
2994 }
2995 break;
2996 case OP_LSHR_UN: {
2997 guint8 *jump_to_end;
2998
2999 /* handle shifts below 32 bits */
3000 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3001 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3002
3003 x86_test_reg_imm (code, X86_ECX, 32);
3004 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3005
3006 /* handle shifts over 31 bits */
3007 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3008 x86_clear_reg (code, ins->backend.reg3);
3009
3010 x86_patch (jump_to_end, code);
3011 }
3012 break;
3013 case OP_LSHL_IMM:
3014 if (ins->inst_imm >= 32) {
3015 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3016 x86_clear_reg (code, ins->sreg1);
3017 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3018 } else {
3019 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3020 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3021 }
3022 break;
3023 case OP_LSHR_IMM:
3024 if (ins->inst_imm >= 32) {
3025 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3026 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3027 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3028 } else {
3029 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3030 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3031 }
3032 break;
3033 case OP_LSHR_UN_IMM:
3034 if (ins->inst_imm >= 32) {
3035 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3036 x86_clear_reg (code, ins->backend.reg3);
3037 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3038 } else {
3039 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3040 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3041 }
3042 break;
3043 case OP_INOT:
3044 x86_not_reg (code, ins->sreg1);
3045 break;
3046 case OP_INEG:
3047 x86_neg_reg (code, ins->sreg1);
3048 break;
3049
3050 case OP_IMUL:
3051 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3052 break;
3053 case OP_MUL_IMM:
3054 case OP_IMUL_IMM:
3055 switch (ins->inst_imm) {
3056 case 2:
3057 /* MOV r1, r2 */
3058 /* ADD r1, r1 */
3059 if (ins->dreg != ins->sreg1)
3060 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3061 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3062 break;
3063 case 3:
3064 /* LEA r1, [r2 + r2*2] */
3065 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3066 break;
3067 case 5:
3068 /* LEA r1, [r2 + r2*4] */
3069 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3070 break;
3071 case 6:
3072 /* LEA r1, [r2 + r2*2] */
3073 /* ADD r1, r1 */
3074 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3075 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3076 break;
3077 case 9:
3078 /* LEA r1, [r2 + r2*8] */
3079 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3080 break;
3081 case 10:
3082 /* LEA r1, [r2 + r2*4] */
3083 /* ADD r1, r1 */
3084 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3085 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3086 break;
3087 case 12:
3088 /* LEA r1, [r2 + r2*2] */
3089 /* SHL r1, 2 */
3090 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3091 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3092 break;
3093 case 25:
3094 /* LEA r1, [r2 + r2*4] */
3095 /* LEA r1, [r1 + r1*4] */
3096 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3097 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3098 break;
3099 case 100:
3100 /* LEA r1, [r2 + r2*4] */
3101 /* SHL r1, 2 */
3102 /* LEA r1, [r1 + r1*4] */
3103 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3104 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3105 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3106 break;
3107 default:
3108 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3109 break;
3110 }
3111 break;
3112 case OP_IMUL_OVF:
3113 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3114 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3115 break;
3116 case OP_IMUL_OVF_UN: {
3117 /* the mul operation and the exception check should most likely be split */
3118 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3119 /*g_assert (ins->sreg2 == X86_EAX);
3120 g_assert (ins->dreg == X86_EAX);*/
3121 if (ins->sreg2 == X86_EAX) {
3122 non_eax_reg = ins->sreg1;
3123 } else if (ins->sreg1 == X86_EAX) {
3124 non_eax_reg = ins->sreg2;
3125 } else {
3126 /* no need to save since we're going to store to it anyway */
3127 if (ins->dreg != X86_EAX) {
3128 saved_eax = TRUE;
3129 x86_push_reg (code, X86_EAX);
3130 }
3131 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3132 non_eax_reg = ins->sreg2;
3133 }
3134 if (ins->dreg == X86_EDX) {
3135 if (!saved_eax) {
3136 saved_eax = TRUE;
3137 x86_push_reg (code, X86_EAX);
3138 }
3139 } else if (ins->dreg != X86_EAX) {
3140 saved_edx = TRUE;
3141 x86_push_reg (code, X86_EDX);
3142 }
3143 x86_mul_reg (code, non_eax_reg, FALSE);
3144 /* save before the check since pop and mov don't change the flags */
3145 if (ins->dreg != X86_EAX)
3146 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3147 if (saved_edx)
3148 x86_pop_reg (code, X86_EDX);
3149 if (saved_eax)
3150 x86_pop_reg (code, X86_EAX);
3151 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3152 break;
3153 }
3154 case OP_ICONST:
3155 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3156 break;
3157 case OP_AOTCONST:
3158 g_assert_not_reached ();
3159 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3160 x86_mov_reg_imm (code, ins->dreg, 0);
3161 break;
3162 case OP_JUMP_TABLE:
3163 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3164 x86_mov_reg_imm (code, ins->dreg, 0);
3165 break;
3166 case OP_LOAD_GOTADDR:
3167 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3168 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3169 break;
3170 case OP_GOT_ENTRY:
3171 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3172 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3173 break;
3174 case OP_X86_PUSH_GOT_ENTRY:
3175 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3176 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3177 break;
3178 case OP_MOVE:
3179 if (ins->dreg != ins->sreg1)
3180 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3181 break;
3182 case OP_TAILCALL: {
3183 MonoCallInst *call = (MonoCallInst*)ins;
3184 int pos = 0, i;
3185
3186 ins->flags |= MONO_INST_GC_CALLSITE;
3187 ins->backend.pc_offset = code - cfg->native_code;
3188
3189 /* reset offset to make max_len work */
3190 offset = code - cfg->native_code;
3191
3192 g_assert (!cfg->method->save_lmf);
3193
3194 /* restore callee saved registers */
3195 for (i = 0; i < X86_NREG; ++i)
3196 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3197 pos -= 4;
3198 if (cfg->used_int_regs & (1 << X86_ESI)) {
3199 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3200 pos += 4;
3201 }
3202 if (cfg->used_int_regs & (1 << X86_EDI)) {
3203 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3204 pos += 4;
3205 }
3206 if (cfg->used_int_regs & (1 << X86_EBX)) {
3207 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3208 pos += 4;
3209 }
3210
3211 /* Copy arguments on the stack to our argument area */
3212 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3213 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3214 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3215 }
3216
3217 /* restore ESP/EBP */
3218 x86_leave (code);
3219 offset = code - cfg->native_code;
3220 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3221 x86_jump32 (code, 0);
3222
3223 ins->flags |= MONO_INST_GC_CALLSITE;
3224 cfg->disable_aot = TRUE;
3225 break;
3226 }
3227 case OP_CHECK_THIS:
3228 /* ensure ins->sreg1 is not NULL
3229 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3230 * cmp DWORD PTR [eax], 0
3231 */
3232 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3233 break;
3234 case OP_ARGLIST: {
3235 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3236 x86_push_reg (code, hreg);
3237 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3238 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3239 x86_pop_reg (code, hreg);
3240 break;
3241 }
3242 case OP_FCALL:
3243 case OP_LCALL:
3244 case OP_VCALL:
3245 case OP_VCALL2:
3246 case OP_VOIDCALL:
3247 case OP_CALL:
3248 case OP_FCALL_REG:
3249 case OP_LCALL_REG:
3250 case OP_VCALL_REG:
3251 case OP_VCALL2_REG:
3252 case OP_VOIDCALL_REG:
3253 case OP_CALL_REG:
3254 case OP_FCALL_MEMBASE:
3255 case OP_LCALL_MEMBASE:
3256 case OP_VCALL_MEMBASE:
3257 case OP_VCALL2_MEMBASE:
3258 case OP_VOIDCALL_MEMBASE:
3259 case OP_CALL_MEMBASE: {
3260 CallInfo *cinfo;
3261
3262 call = (MonoCallInst*)ins;
3263 cinfo = (CallInfo*)call->call_info;
3264
3265 switch (ins->opcode) {
3266 case OP_FCALL:
3267 case OP_LCALL:
3268 case OP_VCALL:
3269 case OP_VCALL2:
3270 case OP_VOIDCALL:
3271 case OP_CALL:
3272 if (ins->flags & MONO_INST_HAS_METHOD)
3273 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3274 else
3275 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3276 break;
3277 case OP_FCALL_REG:
3278 case OP_LCALL_REG:
3279 case OP_VCALL_REG:
3280 case OP_VCALL2_REG:
3281 case OP_VOIDCALL_REG:
3282 case OP_CALL_REG:
3283 x86_call_reg (code, ins->sreg1);
3284 break;
3285 case OP_FCALL_MEMBASE:
3286 case OP_LCALL_MEMBASE:
3287 case OP_VCALL_MEMBASE:
3288 case OP_VCALL2_MEMBASE:
3289 case OP_VOIDCALL_MEMBASE:
3290 case OP_CALL_MEMBASE:
3291 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3292 break;
3293 default:
3294 g_assert_not_reached ();
3295 break;
3296 }
3297 ins->flags |= MONO_INST_GC_CALLSITE;
3298 ins->backend.pc_offset = code - cfg->native_code;
3299 if (cinfo->callee_stack_pop) {
3300 /* Have to compensate for the stack space popped by the callee */
3301 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3302 }
3303 code = emit_move_return_value (cfg, ins, code);
3304 break;
3305 }
3306 case OP_X86_LEA:
3307 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3308 break;
3309 case OP_X86_LEA_MEMBASE:
3310 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3311 break;
3312 case OP_X86_XCHG:
3313 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3314 break;
3315 case OP_LOCALLOC:
3316 /* keep alignment */
3317 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3318 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3319 code = mono_emit_stack_alloc (cfg, code, ins);
3320 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3321 if (cfg->param_area)
3322 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3323 break;
3324 case OP_LOCALLOC_IMM: {
3325 guint32 size = ins->inst_imm;
3326 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3327
3328 if (ins->flags & MONO_INST_INIT) {
3329 /* FIXME: Optimize this */
3330 x86_mov_reg_imm (code, ins->dreg, size);
3331 ins->sreg1 = ins->dreg;
3332
3333 code = mono_emit_stack_alloc (cfg, code, ins);
3334 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3335 } else {
3336 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3337 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3338 }
3339 if (cfg->param_area)
3340 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3341 break;
3342 }
3343 case OP_THROW: {
3344 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3345 x86_push_reg (code, ins->sreg1);
3346 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3347 (gpointer)"mono_arch_throw_exception");
3348 ins->flags |= MONO_INST_GC_CALLSITE;
3349 ins->backend.pc_offset = code - cfg->native_code;
3350 break;
3351 }
3352 case OP_RETHROW: {
3353 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3354 x86_push_reg (code, ins->sreg1);
3355 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3356 (gpointer)"mono_arch_rethrow_exception");
3357 ins->flags |= MONO_INST_GC_CALLSITE;
3358 ins->backend.pc_offset = code - cfg->native_code;
3359 break;
3360 }
3361 case OP_CALL_HANDLER:
3362 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3363 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3364 x86_call_imm (code, 0);
3365 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3366 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3367 break;
3368 case OP_START_HANDLER: {
3369 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3370 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3371 if (cfg->param_area)
3372 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3373 break;
3374 }
3375 case OP_ENDFINALLY: {
3376 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3377 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3378 x86_ret (code);
3379 break;
3380 }
3381 case OP_ENDFILTER: {
3382 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3383 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3384 /* The local allocator will put the result into EAX */
3385 x86_ret (code);
3386 break;
3387 }
3388 case OP_GET_EX_OBJ:
3389 if (ins->dreg != X86_EAX)
3390 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3391 break;
3392
3393 case OP_LABEL:
3394 ins->inst_c0 = code - cfg->native_code;
3395 break;
3396 case OP_BR:
3397 if (ins->inst_target_bb->native_offset) {
3398 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3399 } else {
3400 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3401 if ((cfg->opt & MONO_OPT_BRANCH) &&
3402 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3403 x86_jump8 (code, 0);
3404 else
3405 x86_jump32 (code, 0);
3406 }
3407 break;
3408 case OP_BR_REG:
3409 x86_jump_reg (code, ins->sreg1);
3410 break;
3411 case OP_ICNEQ:
3412 case OP_ICGE:
3413 case OP_ICLE:
3414 case OP_ICGE_UN:
3415 case OP_ICLE_UN:
3416
3417 case OP_CEQ:
3418 case OP_CLT:
3419 case OP_CLT_UN:
3420 case OP_CGT:
3421 case OP_CGT_UN:
3422 case OP_CNE:
3423 case OP_ICEQ:
3424 case OP_ICLT:
3425 case OP_ICLT_UN:
3426 case OP_ICGT:
3427 case OP_ICGT_UN:
3428 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3429 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3430 break;
3431 case OP_COND_EXC_EQ:
3432 case OP_COND_EXC_NE_UN:
3433 case OP_COND_EXC_LT:
3434 case OP_COND_EXC_LT_UN:
3435 case OP_COND_EXC_GT:
3436 case OP_COND_EXC_GT_UN:
3437 case OP_COND_EXC_GE:
3438 case OP_COND_EXC_GE_UN:
3439 case OP_COND_EXC_LE:
3440 case OP_COND_EXC_LE_UN:
3441 case OP_COND_EXC_IEQ:
3442 case OP_COND_EXC_INE_UN:
3443 case OP_COND_EXC_ILT:
3444 case OP_COND_EXC_ILT_UN:
3445 case OP_COND_EXC_IGT:
3446 case OP_COND_EXC_IGT_UN:
3447 case OP_COND_EXC_IGE:
3448 case OP_COND_EXC_IGE_UN:
3449 case OP_COND_EXC_ILE:
3450 case OP_COND_EXC_ILE_UN:
3451 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3452 break;
3453 case OP_COND_EXC_OV:
3454 case OP_COND_EXC_NO:
3455 case OP_COND_EXC_C:
3456 case OP_COND_EXC_NC:
3457 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3458 break;
3459 case OP_COND_EXC_IOV:
3460 case OP_COND_EXC_INO:
3461 case OP_COND_EXC_IC:
3462 case OP_COND_EXC_INC:
3463 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3464 break;
3465 case OP_IBEQ:
3466 case OP_IBNE_UN:
3467 case OP_IBLT:
3468 case OP_IBLT_UN:
3469 case OP_IBGT:
3470 case OP_IBGT_UN:
3471 case OP_IBGE:
3472 case OP_IBGE_UN:
3473 case OP_IBLE:
3474 case OP_IBLE_UN:
3475 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3476 break;
3477
3478 case OP_CMOV_IEQ:
3479 case OP_CMOV_IGE:
3480 case OP_CMOV_IGT:
3481 case OP_CMOV_ILE:
3482 case OP_CMOV_ILT:
3483 case OP_CMOV_INE_UN:
3484 case OP_CMOV_IGE_UN:
3485 case OP_CMOV_IGT_UN:
3486 case OP_CMOV_ILE_UN:
3487 case OP_CMOV_ILT_UN:
3488 g_assert (ins->dreg == ins->sreg1);
3489 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3490 break;
3491
3492 /* floating point opcodes */
3493 case OP_R8CONST: {
3494 double d = *(double *)ins->inst_p0;
3495
3496 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3497 x86_fldz (code);
3498 } else if (d == 1.0) {
3499 x86_fld1 (code);
3500 } else {
3501 if (cfg->compile_aot) {
3502 guint32 *val = (guint32*)&d;
3503 x86_push_imm (code, val [1]);
3504 x86_push_imm (code, val [0]);
3505 x86_fld_membase (code, X86_ESP, 0, TRUE);
3506 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3507 }
3508 else {
3509 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3510 x86_fld (code, NULL, TRUE);
3511 }
3512 }
3513 break;
3514 }
3515 case OP_R4CONST: {
3516 float f = *(float *)ins->inst_p0;
3517
3518 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3519 x86_fldz (code);
3520 } else if (f == 1.0) {
3521 x86_fld1 (code);
3522 } else {
3523 if (cfg->compile_aot) {
3524 guint32 val = *(guint32*)&f;
3525 x86_push_imm (code, val);
3526 x86_fld_membase (code, X86_ESP, 0, FALSE);
3527 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3528 }
3529 else {
3530 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3531 x86_fld (code, NULL, FALSE);
3532 }
3533 }
3534 break;
3535 }
3536 case OP_STORER8_MEMBASE_REG:
3537 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3538 break;
3539 case OP_LOADR8_MEMBASE:
3540 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3541 break;
3542 case OP_STORER4_MEMBASE_REG:
3543 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3544 break;
3545 case OP_LOADR4_MEMBASE:
3546 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3547 break;
3548 case OP_ICONV_TO_R4:
3549 x86_push_reg (code, ins->sreg1);
3550 x86_fild_membase (code, X86_ESP, 0, FALSE);
3551 /* Change precision */
3552 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3553 x86_fld_membase (code, X86_ESP, 0, FALSE);
3554 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3555 break;
3556 case OP_ICONV_TO_R8:
3557 x86_push_reg (code, ins->sreg1);
3558 x86_fild_membase (code, X86_ESP, 0, FALSE);
3559 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3560 break;
3561 case OP_ICONV_TO_R_UN:
3562 x86_push_imm (code, 0);
3563 x86_push_reg (code, ins->sreg1);
3564 x86_fild_membase (code, X86_ESP, 0, TRUE);
3565 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3566 break;
3567 case OP_X86_FP_LOAD_I8:
3568 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3569 break;
3570 case OP_X86_FP_LOAD_I4:
3571 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3572 break;
3573 case OP_FCONV_TO_R4:
3574 /* Change precision */
3575 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3576 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3577 x86_fld_membase (code, X86_ESP, 0, FALSE);
3578 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3579 break;
3580 case OP_FCONV_TO_I1:
3581 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3582 break;
3583 case OP_FCONV_TO_U1:
3584 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3585 break;
3586 case OP_FCONV_TO_I2:
3587 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3588 break;
3589 case OP_FCONV_TO_U2:
3590 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3591 break;
3592 case OP_FCONV_TO_I4:
3593 case OP_FCONV_TO_I:
3594 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3595 break;
3596 case OP_FCONV_TO_I8:
3597 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3598 x86_fnstcw_membase(code, X86_ESP, 0);
3599 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3600 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3601 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3602 x86_fldcw_membase (code, X86_ESP, 2);
3603 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3604 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3605 x86_pop_reg (code, ins->dreg);
3606 x86_pop_reg (code, ins->backend.reg3);
3607 x86_fldcw_membase (code, X86_ESP, 0);
3608 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3609 break;
3610 case OP_LCONV_TO_R8_2:
3611 x86_push_reg (code, ins->sreg2);
3612 x86_push_reg (code, ins->sreg1);
3613 x86_fild_membase (code, X86_ESP, 0, TRUE);
3614 /* Change precision */
3615 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3616 x86_fld_membase (code, X86_ESP, 0, TRUE);
3617 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3618 break;
3619 case OP_LCONV_TO_R4_2:
3620 x86_push_reg (code, ins->sreg2);
3621 x86_push_reg (code, ins->sreg1);
3622 x86_fild_membase (code, X86_ESP, 0, TRUE);
3623 /* Change precision */
3624 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3625 x86_fld_membase (code, X86_ESP, 0, FALSE);
3626 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3627 break;
3628 case OP_LCONV_TO_R_UN_2: {
3629 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3630 guint8 *br;
3631
3632 /* load 64bit integer to FP stack */
3633 x86_push_reg (code, ins->sreg2);
3634 x86_push_reg (code, ins->sreg1);
3635 x86_fild_membase (code, X86_ESP, 0, TRUE);
3636
3637 /* test if lreg is negative */
3638 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3639 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3640
3641 /* add correction constant mn */
3642 if (cfg->compile_aot) {
3643 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3644 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3645 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3646 x86_fld80_membase (code, X86_ESP, 2);
3647 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3648 } else {
3649 x86_fld80_mem (code, mn);
3650 }
3651 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3652
3653 x86_patch (br, code);
3654
3655 /* Change precision */
3656 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3657 x86_fld_membase (code, X86_ESP, 0, TRUE);
3658
3659 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3660
3661 break;
3662 }
3663 case OP_LCONV_TO_OVF_I:
3664 case OP_LCONV_TO_OVF_I4_2: {
3665 guint8 *br [3], *label [1];
3666 MonoInst *tins;
3667
3668 /*
3669 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3670 */
3671 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3672
3673 /* If the low word top bit is set, see if we are negative */
3674 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3675 /* We are not negative (no top bit set, check for our top word to be zero */
3676 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3677 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3678 label [0] = code;
3679
3680 /* throw exception */
3681 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3682 if (tins) {
3683 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3684 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3685 x86_jump8 (code, 0);
3686 else
3687 x86_jump32 (code, 0);
3688 } else {
3689 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3690 x86_jump32 (code, 0);
3691 }
3692
3693
3694 x86_patch (br [0], code);
3695 /* our top bit is set, check that top word is 0xfffffff */
3696 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3697
3698 x86_patch (br [1], code);
3699 /* nope, emit exception */
3700 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3701 x86_patch (br [2], label [0]);
3702
3703 if (ins->dreg != ins->sreg1)
3704 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3705 break;
3706 }
3707 case OP_FMOVE:
3708 /* Not needed on the fp stack */
3709 break;
3710 case OP_MOVE_F_TO_I4:
3711 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3712 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3713 break;
3714 case OP_MOVE_I4_TO_F:
3715 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3716 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3717 break;
3718 case OP_FADD:
3719 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3720 break;
3721 case OP_FSUB:
3722 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3723 break;
3724 case OP_FMUL:
3725 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3726 break;
3727 case OP_FDIV:
3728 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3729 break;
3730 case OP_FNEG:
3731 x86_fchs (code);
3732 break;
3733 case OP_SIN:
3734 x86_fsin (code);
3735 x86_fldz (code);
3736 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3737 break;
3738 case OP_COS:
3739 x86_fcos (code);
3740 x86_fldz (code);
3741 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3742 break;
3743 case OP_ABS:
3744 x86_fabs (code);
3745 break;
3746 case OP_TAN: {
3747 /*
3748 * it really doesn't make sense to inline all this code,
3749 * it's here just to show that things may not be as simple
3750 * as they appear.
3751 */
3752 guchar *check_pos, *end_tan, *pop_jump;
3753 x86_push_reg (code, X86_EAX);
3754 x86_fptan (code);
3755 x86_fnstsw (code);
3756 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3757 check_pos = code;
3758 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3759 x86_fstp (code, 0); /* pop the 1.0 */
3760 end_tan = code;
3761 x86_jump8 (code, 0);
3762 x86_fldpi (code);
3763 x86_fp_op (code, X86_FADD, 0);
3764 x86_fxch (code, 1);
3765 x86_fprem1 (code);
3766 x86_fstsw (code);
3767 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3768 pop_jump = code;
3769 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3770 x86_fstp (code, 1);
3771 x86_fptan (code);
3772 x86_patch (pop_jump, code);
3773 x86_fstp (code, 0); /* pop the 1.0 */
3774 x86_patch (check_pos, code);
3775 x86_patch (end_tan, code);
3776 x86_fldz (code);
3777 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3778 x86_pop_reg (code, X86_EAX);
3779 break;
3780 }
3781 case OP_ATAN:
3782 x86_fld1 (code);
3783 x86_fpatan (code);
3784 x86_fldz (code);
3785 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3786 break;
3787 case OP_SQRT:
3788 x86_fsqrt (code);
3789 break;
3790 case OP_ROUND:
3791 x86_frndint (code);
3792 break;
3793 case OP_IMIN:
3794 g_assert (cfg->opt & MONO_OPT_CMOV);
3795 g_assert (ins->dreg == ins->sreg1);
3796 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3797 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3798 break;
3799 case OP_IMIN_UN:
3800 g_assert (cfg->opt & MONO_OPT_CMOV);
3801 g_assert (ins->dreg == ins->sreg1);
3802 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3803 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3804 break;
3805 case OP_IMAX:
3806 g_assert (cfg->opt & MONO_OPT_CMOV);
3807 g_assert (ins->dreg == ins->sreg1);
3808 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3809 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3810 break;
3811 case OP_IMAX_UN:
3812 g_assert (cfg->opt & MONO_OPT_CMOV);
3813 g_assert (ins->dreg == ins->sreg1);
3814 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3815 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3816 break;
3817 case OP_X86_FPOP:
3818 x86_fstp (code, 0);
3819 break;
3820 case OP_X86_FXCH:
3821 x86_fxch (code, ins->inst_imm);
3822 break;
3823 case OP_FREM: {
3824 guint8 *l1, *l2;
3825
3826 x86_push_reg (code, X86_EAX);
3827 /* we need to exchange ST(0) with ST(1) */
3828 x86_fxch (code, 1);
3829
3830 /* this requires a loop, because fprem somtimes
3831 * returns a partial remainder */
3832 l1 = code;
3833 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3834 /* x86_fprem1 (code); */
3835 x86_fprem (code);
3836 x86_fnstsw (code);
3837 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3838 l2 = code;
3839 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3840 x86_patch (l2, l1);
3841
3842 /* pop result */
3843 x86_fstp (code, 1);
3844
3845 x86_pop_reg (code, X86_EAX);
3846 break;
3847 }
3848 case OP_FCOMPARE:
3849 if (cfg->opt & MONO_OPT_FCMOV) {
3850 x86_fcomip (code, 1);
3851 x86_fstp (code, 0);
3852 break;
3853 }
3854 /* this overwrites EAX */
3855 EMIT_FPCOMPARE(code);
3856 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3857 break;
3858 case OP_FCEQ:
3859 case OP_FCNEQ:
3860 if (cfg->opt & MONO_OPT_FCMOV) {
3861 /* zeroing the register at the start results in
3862 * shorter and faster code (we can also remove the widening op)
3863 */
3864 guchar *unordered_check;
3865 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3866 x86_fcomip (code, 1);
3867 x86_fstp (code, 0);
3868 unordered_check = code;
3869 x86_branch8 (code, X86_CC_P, 0, FALSE);
3870 if (ins->opcode == OP_FCEQ) {
3871 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3872 x86_patch (unordered_check, code);
3873 } else {
3874 guchar *jump_to_end;
3875 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3876 jump_to_end = code;
3877 x86_jump8 (code, 0);
3878 x86_patch (unordered_check, code);
3879 x86_inc_reg (code, ins->dreg);
3880 x86_patch (jump_to_end, code);
3881 }
3882
3883 break;
3884 }
3885 if (ins->dreg != X86_EAX)
3886 x86_push_reg (code, X86_EAX);
3887
3888 EMIT_FPCOMPARE(code);
3889 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3890 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3891 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3892 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3893
3894 if (ins->dreg != X86_EAX)
3895 x86_pop_reg (code, X86_EAX);
3896 break;
3897 case OP_FCLT:
3898 case OP_FCLT_UN:
3899 if (cfg->opt & MONO_OPT_FCMOV) {
3900 /* zeroing the register at the start results in
3901 * shorter and faster code (we can also remove the widening op)
3902 */
3903 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3904 x86_fcomip (code, 1);
3905 x86_fstp (code, 0);
3906 if (ins->opcode == OP_FCLT_UN) {
3907 guchar *unordered_check = code;
3908 guchar *jump_to_end;
3909 x86_branch8 (code, X86_CC_P, 0, FALSE);
3910 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3911 jump_to_end = code;
3912 x86_jump8 (code, 0);
3913 x86_patch (unordered_check, code);
3914 x86_inc_reg (code, ins->dreg);
3915 x86_patch (jump_to_end, code);
3916 } else {
3917 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3918 }
3919 break;
3920 }
3921 if (ins->dreg != X86_EAX)
3922 x86_push_reg (code, X86_EAX);
3923
3924 EMIT_FPCOMPARE(code);
3925 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3926 if (ins->opcode == OP_FCLT_UN) {
3927 guchar *is_not_zero_check, *end_jump;
3928 is_not_zero_check = code;
3929 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3930 end_jump = code;
3931 x86_jump8 (code, 0);
3932 x86_patch (is_not_zero_check, code);
3933 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3934
3935 x86_patch (end_jump, code);
3936 }
3937 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3938 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3939
3940 if (ins->dreg != X86_EAX)
3941 x86_pop_reg (code, X86_EAX);
3942 break;
3943 case OP_FCLE: {
3944 guchar *unordered_check;
3945 guchar *jump_to_end;
3946 if (cfg->opt & MONO_OPT_FCMOV) {
3947 /* zeroing the register at the start results in
3948 * shorter and faster code (we can also remove the widening op)
3949 */
3950 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3951 x86_fcomip (code, 1);
3952 x86_fstp (code, 0);
3953 unordered_check = code;
3954 x86_branch8 (code, X86_CC_P, 0, FALSE);
3955 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3956 x86_patch (unordered_check, code);
3957 break;
3958 }
3959 if (ins->dreg != X86_EAX)
3960 x86_push_reg (code, X86_EAX);
3961
3962 EMIT_FPCOMPARE(code);
3963 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3964 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3965 unordered_check = code;
3966 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3967
3968 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3969 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3970 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3971 jump_to_end = code;
3972 x86_jump8 (code, 0);
3973 x86_patch (unordered_check, code);
3974 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3975 x86_patch (jump_to_end, code);
3976
3977 if (ins->dreg != X86_EAX)
3978 x86_pop_reg (code, X86_EAX);
3979 break;
3980 }
3981 case OP_FCGT:
3982 case OP_FCGT_UN:
3983 if (cfg->opt & MONO_OPT_FCMOV) {
3984 /* zeroing the register at the start results in
3985 * shorter and faster code (we can also remove the widening op)
3986 */
3987 guchar *unordered_check;
3988 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3989 x86_fcomip (code, 1);
3990 x86_fstp (code, 0);
3991 if (ins->opcode == OP_FCGT) {
3992 unordered_check = code;
3993 x86_branch8 (code, X86_CC_P, 0, FALSE);
3994 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3995 x86_patch (unordered_check, code);
3996 } else {
3997 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3998 }
3999 break;
4000 }
4001 if (ins->dreg != X86_EAX)
4002 x86_push_reg (code, X86_EAX);
4003
4004 EMIT_FPCOMPARE(code);
4005 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4006 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4007 if (ins->opcode == OP_FCGT_UN) {
4008 guchar *is_not_zero_check, *end_jump;
4009 is_not_zero_check = code;
4010 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4011 end_jump = code;
4012 x86_jump8 (code, 0);
4013 x86_patch (is_not_zero_check, code);
4014 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4015
4016 x86_patch (end_jump, code);
4017 }
4018 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4019 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4020
4021 if (ins->dreg != X86_EAX)
4022 x86_pop_reg (code, X86_EAX);
4023 break;
4024 case OP_FCGE: {
4025 guchar *unordered_check;
4026 guchar *jump_to_end;
4027 if (cfg->opt & MONO_OPT_FCMOV) {
4028 /* zeroing the register at the start results in
4029 * shorter and faster code (we can also remove the widening op)
4030 */
4031 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4032 x86_fcomip (code, 1);
4033 x86_fstp (code, 0);
4034 unordered_check = code;
4035 x86_branch8 (code, X86_CC_P, 0, FALSE);
4036 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4037 x86_patch (unordered_check, code);
4038 break;
4039 }
4040 if (ins->dreg != X86_EAX)
4041 x86_push_reg (code, X86_EAX);
4042
4043 EMIT_FPCOMPARE(code);
4044 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4045 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4046 unordered_check = code;
4047 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4048
4049 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4050 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4051 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4052 jump_to_end = code;
4053 x86_jump8 (code, 0);
4054 x86_patch (unordered_check, code);
4055 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4056 x86_patch (jump_to_end, code);
4057
4058 if (ins->dreg != X86_EAX)
4059 x86_pop_reg (code, X86_EAX);
4060 break;
4061 }
4062 case OP_FBEQ:
4063 if (cfg->opt & MONO_OPT_FCMOV) {
4064 guchar *jump = code;
4065 x86_branch8 (code, X86_CC_P, 0, TRUE);
4066 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4067 x86_patch (jump, code);
4068 break;
4069 }
4070 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4071 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4072 break;
4073 case OP_FBNE_UN:
4074 /* Branch if C013 != 100 */
4075 if (cfg->opt & MONO_OPT_FCMOV) {
4076 /* branch if !ZF or (PF|CF) */
4077 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4078 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4079 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4080 break;
4081 }
4082 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4083 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4084 break;
4085 case OP_FBLT:
4086 if (cfg->opt & MONO_OPT_FCMOV) {
4087 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4088 break;
4089 }
4090 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4091 break;
4092 case OP_FBLT_UN:
4093 if (cfg->opt & MONO_OPT_FCMOV) {
4094 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4095 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4096 break;
4097 }
4098 if (ins->opcode == OP_FBLT_UN) {
4099 guchar *is_not_zero_check, *end_jump;
4100 is_not_zero_check = code;
4101 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4102 end_jump = code;
4103 x86_jump8 (code, 0);
4104 x86_patch (is_not_zero_check, code);
4105 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4106
4107 x86_patch (end_jump, code);
4108 }
4109 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4110 break;
4111 case OP_FBGT:
4112 case OP_FBGT_UN:
4113 if (cfg->opt & MONO_OPT_FCMOV) {
4114 if (ins->opcode == OP_FBGT) {
4115 guchar *br1;
4116
4117 /* skip branch if C1=1 */
4118 br1 = code;
4119 x86_branch8 (code, X86_CC_P, 0, FALSE);
4120 /* branch if (C0 | C3) = 1 */
4121 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4122 x86_patch (br1, code);
4123 } else {
4124 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4125 }
4126 break;
4127 }
4128 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4129 if (ins->opcode == OP_FBGT_UN) {
4130 guchar *is_not_zero_check, *end_jump;
4131 is_not_zero_check = code;
4132 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4133 end_jump = code;
4134 x86_jump8 (code, 0);
4135 x86_patch (is_not_zero_check, code);
4136 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4137
4138 x86_patch (end_jump, code);
4139 }
4140 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4141 break;
4142 case OP_FBGE:
4143 /* Branch if C013 == 100 or 001 */
4144 if (cfg->opt & MONO_OPT_FCMOV) {
4145 guchar *br1;
4146
4147 /* skip branch if C1=1 */
4148 br1 = code;
4149 x86_branch8 (code, X86_CC_P, 0, FALSE);
4150 /* branch if (C0 | C3) = 1 */
4151 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4152 x86_patch (br1, code);
4153 break;
4154 }
4155 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4156 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4157 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4158 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4159 break;
4160 case OP_FBGE_UN:
4161 /* Branch if C013 == 000 */
4162 if (cfg->opt & MONO_OPT_FCMOV) {
4163 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4164 break;
4165 }
4166 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4167 break;
4168 case OP_FBLE:
4169 /* Branch if C013=000 or 100 */
4170 if (cfg->opt & MONO_OPT_FCMOV) {
4171 guchar *br1;
4172
4173 /* skip branch if C1=1 */
4174 br1 = code;
4175 x86_branch8 (code, X86_CC_P, 0, FALSE);
4176 /* branch if C0=0 */
4177 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4178 x86_patch (br1, code);
4179 break;
4180 }
4181 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4182 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4183 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4184 break;
4185 case OP_FBLE_UN:
4186 /* Branch if C013 != 001 */
4187 if (cfg->opt & MONO_OPT_FCMOV) {
4188 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4189 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4190 break;
4191 }
4192 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4193 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4194 break;
4195 case OP_CKFINITE: {
4196 guchar *br1;
4197 x86_push_reg (code, X86_EAX);
4198 x86_fxam (code);
4199 x86_fnstsw (code);
4200 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4201 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4202 x86_pop_reg (code, X86_EAX);
4203
4204 /* Have to clean up the fp stack before throwing the exception */
4205 br1 = code;
4206 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4207
4208 x86_fstp (code, 0);
4209 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4210
4211 x86_patch (br1, code);
4212 break;
4213 }
4214 case OP_TLS_GET: {
4215 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4216 break;
4217 }
4218 case OP_TLS_GET_REG: {
4219 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4220 break;
4221 }
4222 case OP_TLS_SET: {
4223 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4224 break;
4225 }
4226 case OP_TLS_SET_REG: {
4227 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4228 break;
4229 }
4230 case OP_MEMORY_BARRIER: {
4231 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4232 x86_prefix (code, X86_LOCK_PREFIX);
4233 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4234 }
4235 break;
4236 }
4237 case OP_ATOMIC_ADD_I4: {
4238 int dreg = ins->dreg;
4239
4240 g_assert (cfg->has_atomic_add_i4);
4241
4242 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4243 if (ins->sreg2 == dreg) {
4244 if (dreg == X86_EBX) {
4245 dreg = X86_EDI;
4246 if (ins->inst_basereg == X86_EDI)
4247 dreg = X86_ESI;
4248 } else {
4249 dreg = X86_EBX;
4250 if (ins->inst_basereg == X86_EBX)
4251 dreg = X86_EDI;
4252 }
4253 } else if (ins->inst_basereg == dreg) {
4254 if (dreg == X86_EBX) {
4255 dreg = X86_EDI;
4256 if (ins->sreg2 == X86_EDI)
4257 dreg = X86_ESI;
4258 } else {
4259 dreg = X86_EBX;
4260 if (ins->sreg2 == X86_EBX)
4261 dreg = X86_EDI;
4262 }
4263 }
4264
4265 if (dreg != ins->dreg) {
4266 x86_push_reg (code, dreg);
4267 }
4268
4269 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4270 x86_prefix (code, X86_LOCK_PREFIX);
4271 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4272 /* dreg contains the old value, add with sreg2 value */
4273 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4274
4275 if (ins->dreg != dreg) {
4276 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4277 x86_pop_reg (code, dreg);
4278 }
4279
4280 break;
4281 }
4282 case OP_ATOMIC_EXCHANGE_I4: {
4283 guchar *br[2];
4284 int sreg2 = ins->sreg2;
4285 int breg = ins->inst_basereg;
4286
4287 g_assert (cfg->has_atomic_exchange_i4);
4288
4289 /* cmpxchg uses eax as comperand, need to make sure we can use it
4290 * hack to overcome limits in x86 reg allocator
4291 * (req: dreg == eax and sreg2 != eax and breg != eax)
4292 */
4293 g_assert (ins->dreg == X86_EAX);
4294
4295 /* We need the EAX reg for the cmpxchg */
4296 if (ins->sreg2 == X86_EAX) {
4297 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4298 x86_push_reg (code, sreg2);
4299 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4300 }
4301
4302 if (breg == X86_EAX) {
4303 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4304 x86_push_reg (code, breg);
4305 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4306 }
4307
4308 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4309
4310 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4311 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4312 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4313 x86_patch (br [1], br [0]);
4314
4315 if (breg != ins->inst_basereg)
4316 x86_pop_reg (code, breg);
4317
4318 if (ins->sreg2 != sreg2)
4319 x86_pop_reg (code, sreg2);
4320
4321 break;
4322 }
4323 case OP_ATOMIC_CAS_I4: {
4324 g_assert (ins->dreg == X86_EAX);
4325 g_assert (ins->sreg3 == X86_EAX);
4326 g_assert (ins->sreg1 != X86_EAX);
4327 g_assert (ins->sreg1 != ins->sreg2);
4328
4329 x86_prefix (code, X86_LOCK_PREFIX);
4330 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4331 break;
4332 }
4333 case OP_ATOMIC_LOAD_I1: {
4334 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4335 break;
4336 }
4337 case OP_ATOMIC_LOAD_U1: {
4338 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4339 break;
4340 }
4341 case OP_ATOMIC_LOAD_I2: {
4342 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4343 break;
4344 }
4345 case OP_ATOMIC_LOAD_U2: {
4346 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4347 break;
4348 }
4349 case OP_ATOMIC_LOAD_I4:
4350 case OP_ATOMIC_LOAD_U4: {
4351 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4352 break;
4353 }
4354 case OP_ATOMIC_LOAD_R4:
4355 case OP_ATOMIC_LOAD_R8: {
4356 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4357 break;
4358 }
4359 case OP_ATOMIC_STORE_I1:
4360 case OP_ATOMIC_STORE_U1:
4361 case OP_ATOMIC_STORE_I2:
4362 case OP_ATOMIC_STORE_U2:
4363 case OP_ATOMIC_STORE_I4:
4364 case OP_ATOMIC_STORE_U4: {
4365 int size;
4366
4367 switch (ins->opcode) {
4368 case OP_ATOMIC_STORE_I1:
4369 case OP_ATOMIC_STORE_U1:
4370 size = 1;
4371 break;
4372 case OP_ATOMIC_STORE_I2:
4373 case OP_ATOMIC_STORE_U2:
4374 size = 2;
4375 break;
4376 case OP_ATOMIC_STORE_I4:
4377 case OP_ATOMIC_STORE_U4:
4378 size = 4;
4379 break;
4380 }
4381
4382 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4383
4384 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4385 x86_mfence (code);
4386 break;
4387 }
4388 case OP_ATOMIC_STORE_R4:
4389 case OP_ATOMIC_STORE_R8: {
4390 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4391
4392 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4393 x86_mfence (code);
4394 break;
4395 }
4396 case OP_CARD_TABLE_WBARRIER: {
4397 int ptr = ins->sreg1;
4398 int value = ins->sreg2;
4399 guchar *br = NULL;
4400 int nursery_shift, card_table_shift;
4401 gpointer card_table_mask;
4402 size_t nursery_size;
4403 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4404 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4405 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4406
4407 /*
4408 * We need one register we can clobber, we choose EDX and make sreg1
4409 * fixed EAX to work around limitations in the local register allocator.
4410 * sreg2 might get allocated to EDX, but that is not a problem since
4411 * we use it before clobbering EDX.
4412 */
4413 g_assert (ins->sreg1 == X86_EAX);
4414
4415 /*
4416 * This is the code we produce:
4417 *
4418 * edx = value
4419 * edx >>= nursery_shift
4420 * cmp edx, (nursery_start >> nursery_shift)
4421 * jne done
4422 * edx = ptr
4423 * edx >>= card_table_shift
4424 * card_table[edx] = 1
4425 * done:
4426 */
4427
4428 if (card_table_nursery_check) {
4429 if (value != X86_EDX)
4430 x86_mov_reg_reg (code, X86_EDX, value, 4);
4431 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4432 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4433 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4434 }
4435 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4436 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4437 if (card_table_mask)
4438 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4439 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4440 if (card_table_nursery_check)
4441 x86_patch (br, code);
4442 break;
4443 }
4444 #ifdef MONO_ARCH_SIMD_INTRINSICS
4445 case OP_ADDPS:
4446 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4447 break;
4448 case OP_DIVPS:
4449 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4450 break;
4451 case OP_MULPS:
4452 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4453 break;
4454 case OP_SUBPS:
4455 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4456 break;
4457 case OP_MAXPS:
4458 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4459 break;
4460 case OP_MINPS:
4461 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4462 break;
4463 case OP_COMPPS:
4464 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4465 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4466 break;
4467 case OP_ANDPS:
4468 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4469 break;
4470 case OP_ANDNPS:
4471 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4472 break;
4473 case OP_ORPS:
4474 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4475 break;
4476 case OP_XORPS:
4477 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4478 break;
4479 case OP_SQRTPS:
4480 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4481 break;
4482 case OP_RSQRTPS:
4483 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4484 break;
4485 case OP_RCPPS:
4486 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4487 break;
4488 case OP_ADDSUBPS:
4489 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4490 break;
4491 case OP_HADDPS:
4492 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4493 break;
4494 case OP_HSUBPS:
4495 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4496 break;
4497 case OP_DUPPS_HIGH:
4498 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4499 break;
4500 case OP_DUPPS_LOW:
4501 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4502 break;
4503
4504 case OP_PSHUFLEW_HIGH:
4505 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4506 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4507 break;
4508 case OP_PSHUFLEW_LOW:
4509 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4510 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4511 break;
4512 case OP_PSHUFLED:
4513 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4514 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4515 break;
4516 case OP_SHUFPS:
4517 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4518 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4519 break;
4520 case OP_SHUFPD:
4521 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4522 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4523 break;
4524
4525 case OP_ADDPD:
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4527 break;
4528 case OP_DIVPD:
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4530 break;
4531 case OP_MULPD:
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4533 break;
4534 case OP_SUBPD:
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4536 break;
4537 case OP_MAXPD:
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4539 break;
4540 case OP_MINPD:
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4542 break;
4543 case OP_COMPPD:
4544 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4545 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4546 break;
4547 case OP_ANDPD:
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4549 break;
4550 case OP_ANDNPD:
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4552 break;
4553 case OP_ORPD:
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4555 break;
4556 case OP_XORPD:
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4558 break;
4559 case OP_SQRTPD:
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4561 break;
4562 case OP_ADDSUBPD:
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4564 break;
4565 case OP_HADDPD:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4567 break;
4568 case OP_HSUBPD:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4570 break;
4571 case OP_DUPPD:
4572 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4573 break;
4574
4575 case OP_EXTRACT_MASK:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4577 break;
4578
4579 case OP_PAND:
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4581 break;
4582 case OP_POR:
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4584 break;
4585 case OP_PXOR:
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4587 break;
4588
4589 case OP_PADDB:
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4591 break;
4592 case OP_PADDW:
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4594 break;
4595 case OP_PADDD:
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4597 break;
4598 case OP_PADDQ:
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4600 break;
4601
4602 case OP_PSUBB:
4603 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4604 break;
4605 case OP_PSUBW:
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4607 break;
4608 case OP_PSUBD:
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4610 break;
4611 case OP_PSUBQ:
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4613 break;
4614
4615 case OP_PMAXB_UN:
4616 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4617 break;
4618 case OP_PMAXW_UN:
4619 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4620 break;
4621 case OP_PMAXD_UN:
4622 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4623 break;
4624
4625 case OP_PMAXB:
4626 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4627 break;
4628 case OP_PMAXW:
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4630 break;
4631 case OP_PMAXD:
4632 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4633 break;
4634
4635 case OP_PAVGB_UN:
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4637 break;
4638 case OP_PAVGW_UN:
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4640 break;
4641
4642 case OP_PMINB_UN:
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4644 break;
4645 case OP_PMINW_UN:
4646 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4647 break;
4648 case OP_PMIND_UN:
4649 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4650 break;
4651
4652 case OP_PMINB:
4653 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4654 break;
4655 case OP_PMINW:
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4657 break;
4658 case OP_PMIND:
4659 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4660 break;
4661
4662 case OP_PCMPEQB:
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4664 break;
4665 case OP_PCMPEQW:
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4667 break;
4668 case OP_PCMPEQD:
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4670 break;
4671 case OP_PCMPEQQ:
4672 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4673 break;
4674
4675 case OP_PCMPGTB:
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4677 break;
4678 case OP_PCMPGTW:
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4680 break;
4681 case OP_PCMPGTD:
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4683 break;
4684 case OP_PCMPGTQ:
4685 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4686 break;
4687
4688 case OP_PSUM_ABS_DIFF:
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4690 break;
4691
4692 case OP_UNPACK_LOWB:
4693 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4694 break;
4695 case OP_UNPACK_LOWW:
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4697 break;
4698 case OP_UNPACK_LOWD:
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4700 break;
4701 case OP_UNPACK_LOWQ:
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4703 break;
4704 case OP_UNPACK_LOWPS:
4705 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4706 break;
4707 case OP_UNPACK_LOWPD:
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4709 break;
4710
4711 case OP_UNPACK_HIGHB:
4712 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4713 break;
4714 case OP_UNPACK_HIGHW:
4715 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4716 break;
4717 case OP_UNPACK_HIGHD:
4718 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4719 break;
4720 case OP_UNPACK_HIGHQ:
4721 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4722 break;
4723 case OP_UNPACK_HIGHPS:
4724 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4725 break;
4726 case OP_UNPACK_HIGHPD:
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4728 break;
4729
4730 case OP_PACKW:
4731 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4732 break;
4733 case OP_PACKD:
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4735 break;
4736 case OP_PACKW_UN:
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4738 break;
4739 case OP_PACKD_UN:
4740 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4741 break;
4742
4743 case OP_PADDB_SAT_UN:
4744 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4745 break;
4746 case OP_PSUBB_SAT_UN:
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4748 break;
4749 case OP_PADDW_SAT_UN:
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4751 break;
4752 case OP_PSUBW_SAT_UN:
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4754 break;
4755
4756 case OP_PADDB_SAT:
4757 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4758 break;
4759 case OP_PSUBB_SAT:
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4761 break;
4762 case OP_PADDW_SAT:
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4764 break;
4765 case OP_PSUBW_SAT:
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4767 break;
4768
4769 case OP_PMULW:
4770 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4771 break;
4772 case OP_PMULD:
4773 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4774 break;
4775 case OP_PMULQ:
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4777 break;
4778 case OP_PMULW_HIGH_UN:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4780 break;
4781 case OP_PMULW_HIGH:
4782 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4783 break;
4784
4785 case OP_PSHRW:
4786 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4787 break;
4788 case OP_PSHRW_REG:
4789 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4790 break;
4791
4792 case OP_PSARW:
4793 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4794 break;
4795 case OP_PSARW_REG:
4796 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4797 break;
4798
4799 case OP_PSHLW:
4800 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4801 break;
4802 case OP_PSHLW_REG:
4803 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4804 break;
4805
4806 case OP_PSHRD:
4807 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4808 break;
4809 case OP_PSHRD_REG:
4810 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4811 break;
4812
4813 case OP_PSARD:
4814 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4815 break;
4816 case OP_PSARD_REG:
4817 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4818 break;
4819
4820 case OP_PSHLD:
4821 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4822 break;
4823 case OP_PSHLD_REG:
4824 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4825 break;
4826
4827 case OP_PSHRQ:
4828 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4829 break;
4830 case OP_PSHRQ_REG:
4831 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4832 break;
4833
4834 case OP_PSHLQ:
4835 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4836 break;
4837 case OP_PSHLQ_REG:
4838 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4839 break;
4840
4841 case OP_ICONV_TO_X:
4842 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4843 break;
4844 case OP_EXTRACT_I4:
4845 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4846 break;
4847 case OP_EXTRACT_I1:
4848 case OP_EXTRACT_U1:
4849 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4850 if (ins->inst_c0)
4851 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4852 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4853 break;
4854 case OP_EXTRACT_I2:
4855 case OP_EXTRACT_U2:
4856 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4857 if (ins->inst_c0)
4858 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4859 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4860 break;
4861 case OP_EXTRACT_R8:
4862 if (ins->inst_c0)
4863 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4864 else
4865 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4866 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4867 break;
4868
4869 case OP_INSERT_I2:
4870 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4871 break;
4872 case OP_EXTRACTX_U2:
4873 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4874 break;
4875 case OP_INSERTX_U1_SLOW:
4876 /*sreg1 is the extracted ireg (scratch)
4877 /sreg2 is the to be inserted ireg (scratch)
4878 /dreg is the xreg to receive the value*/
4879
4880 /*clear the bits from the extracted word*/
4881 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4882 /*shift the value to insert if needed*/
4883 if (ins->inst_c0 & 1)
4884 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4885 /*join them together*/
4886 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4887 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4888 break;
4889 case OP_INSERTX_I4_SLOW:
4890 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4891 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4892 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4893 break;
4894
4895 case OP_INSERTX_R4_SLOW:
4896 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4897 /*TODO if inst_c0 == 0 use movss*/
4898 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4899 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4900 break;
4901 case OP_INSERTX_R8_SLOW:
4902 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4903 if (cfg->verbose_level)
4904 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4905 if (ins->inst_c0)
4906 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4907 else
4908 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4909 break;
4910
4911 case OP_STOREX_MEMBASE_REG:
4912 case OP_STOREX_MEMBASE:
4913 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4914 break;
4915 case OP_LOADX_MEMBASE:
4916 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4917 break;
4918 case OP_LOADX_ALIGNED_MEMBASE:
4919 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4920 break;
4921 case OP_STOREX_ALIGNED_MEMBASE_REG:
4922 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4923 break;
4924 case OP_STOREX_NTA_MEMBASE_REG:
4925 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4926 break;
4927 case OP_PREFETCH_MEMBASE:
4928 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4929
4930 break;
4931 case OP_XMOVE:
4932 /*FIXME the peephole pass should have killed this*/
4933 if (ins->dreg != ins->sreg1)
4934 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4935 break;
4936 case OP_XZERO:
4937 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4938 break;
4939
4940 case OP_FCONV_TO_R8_X:
4941 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4942 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4943 break;
4944
4945 case OP_XCONV_R8_TO_I4:
4946 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4947 switch (ins->backend.source_opcode) {
4948 case OP_FCONV_TO_I1:
4949 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4950 break;
4951 case OP_FCONV_TO_U1:
4952 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4953 break;
4954 case OP_FCONV_TO_I2:
4955 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4956 break;
4957 case OP_FCONV_TO_U2:
4958 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4959 break;
4960 }
4961 break;
4962
4963 case OP_EXPAND_I1:
4964 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4965 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4966 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4967 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4968 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4969 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4970 break;
4971 case OP_EXPAND_I2:
4972 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4973 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4974 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4975 break;
4976 case OP_EXPAND_I4:
4977 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4978 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4979 break;
4980 case OP_EXPAND_R4:
4981 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4982 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4983 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4984 break;
4985 case OP_EXPAND_R8:
4986 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4987 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4988 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4989 break;
4990
4991 case OP_CVTDQ2PD:
4992 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4993 break;
4994 case OP_CVTDQ2PS:
4995 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4996 break;
4997 case OP_CVTPD2DQ:
4998 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4999 break;
5000 case OP_CVTPD2PS:
5001 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5002 break;
5003 case OP_CVTPS2DQ:
5004 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5005 break;
5006 case OP_CVTPS2PD:
5007 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5008 break;
5009 case OP_CVTTPD2DQ:
5010 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5011 break;
5012 case OP_CVTTPS2DQ:
5013 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5014 break;
5015
5016 #endif
5017 case OP_LIVERANGE_START: {
5018 if (cfg->verbose_level > 1)
5019 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5020 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5021 break;
5022 }
5023 case OP_LIVERANGE_END: {
5024 if (cfg->verbose_level > 1)
5025 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5026 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5027 break;
5028 }
5029 case OP_GC_SAFE_POINT: {
5030 const char *polling_func = NULL;
5031 int compare_val = 0;
5032 guint8 *br [1];
5033
5034 #if defined (USE_COOP_GC)
5035 polling_func = "mono_threads_state_poll";
5036 compare_val = 1;
5037 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
5038 polling_func = "mono_nacl_gc";
5039 compare_val = 0xFFFFFFFF;
5040 #endif
5041 if (!polling_func)
5042 break;
5043
5044 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5045 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5046 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5047 x86_patch (br [0], code);
5048
5049 break;
5050 }
5051 case OP_GC_LIVENESS_DEF:
5052 case OP_GC_LIVENESS_USE:
5053 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5054 ins->backend.pc_offset = code - cfg->native_code;
5055 break;
5056 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5057 ins->backend.pc_offset = code - cfg->native_code;
5058 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5059 break;
5060 case OP_GET_SP:
5061 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5062 break;
5063 case OP_SET_SP:
5064 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5065 break;
5066 default:
5067 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5068 g_assert_not_reached ();
5069 }
5070
5071 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5072 #ifndef __native_client_codegen__
5073 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5074 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5075 g_assert_not_reached ();
5076 #endif /* __native_client_codegen__ */
5077 }
5078
5079 cpos += max_len;
5080 }
5081
5082 cfg->code_len = code - cfg->native_code;
5083 }
5084
5085 #endif /* DISABLE_JIT */
5086
5087 void
5088 mono_arch_register_lowlevel_calls (void)
5089 {
5090 }
5091
5092 void
5093 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5094 {
5095 unsigned char *ip = ji->ip.i + code;
5096
5097 switch (ji->type) {
5098 case MONO_PATCH_INFO_IP:
5099 *((gconstpointer *)(ip)) = target;
5100 break;
5101 case MONO_PATCH_INFO_CLASS_INIT: {
5102 guint8 *code = ip;
5103 /* Might already been changed to a nop */
5104 x86_call_code (code, 0);
5105 x86_patch (ip, (unsigned char*)target);
5106 break;
5107 }
5108 case MONO_PATCH_INFO_ABS:
5109 case MONO_PATCH_INFO_METHOD:
5110 case MONO_PATCH_INFO_METHOD_JUMP:
5111 case MONO_PATCH_INFO_INTERNAL_METHOD:
5112 case MONO_PATCH_INFO_BB:
5113 case MONO_PATCH_INFO_LABEL:
5114 case MONO_PATCH_INFO_RGCTX_FETCH:
5115 case MONO_PATCH_INFO_MONITOR_ENTER:
5116 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5117 case MONO_PATCH_INFO_MONITOR_EXIT:
5118 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5119 #if defined(__native_client_codegen__) && defined(__native_client__)
5120 if (nacl_is_code_address (code)) {
5121 /* For tail calls, code is patched after being installed */
5122 /* but not through the normal "patch callsite" method. */
5123 unsigned char buf[kNaClAlignment];
5124 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5125 unsigned char *_target = target;
5126 int ret;
5127 /* All patch targets modified in x86_patch */
5128 /* are IP relative. */
5129 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5130 memcpy (buf, aligned_code, kNaClAlignment);
5131 /* Patch a temp buffer of bundle size, */
5132 /* then install to actual location. */
5133 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5134 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5135 g_assert (ret == 0);
5136 }
5137 else {
5138 x86_patch (ip, (unsigned char*)target);
5139 }
5140 #else
5141 x86_patch (ip, (unsigned char*)target);
5142 #endif
5143 break;
5144 case MONO_PATCH_INFO_NONE:
5145 break;
5146 case MONO_PATCH_INFO_R4:
5147 case MONO_PATCH_INFO_R8: {
5148 guint32 offset = mono_arch_get_patch_offset (ip);
5149 *((gconstpointer *)(ip + offset)) = target;
5150 break;
5151 }
5152 default: {
5153 guint32 offset = mono_arch_get_patch_offset (ip);
5154 #if !defined(__native_client__)
5155 *((gconstpointer *)(ip + offset)) = target;
5156 #else
5157 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5158 #endif
5159 break;
5160 }
5161 }
5162 }
5163
5164 static G_GNUC_UNUSED void
5165 stack_unaligned (MonoMethod *m, gpointer caller)
5166 {
5167 printf ("%s\n", mono_method_full_name (m, TRUE));
5168 g_assert_not_reached ();
5169 }
5170
5171 guint8 *
5172 mono_arch_emit_prolog (MonoCompile *cfg)
5173 {
5174 MonoMethod *method = cfg->method;
5175 MonoBasicBlock *bb;
5176 MonoMethodSignature *sig;
5177 MonoInst *inst;
5178 int alloc_size, pos, max_offset, i, cfa_offset;
5179 guint8 *code;
5180 gboolean need_stack_frame;
5181 #ifdef __native_client_codegen__
5182 guint alignment_check;
5183 #endif
5184
5185 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5186
5187 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5188 cfg->code_size += 512;
5189
5190 #if defined(__default_codegen__)
5191 code = cfg->native_code = g_malloc (cfg->code_size);
5192 #elif defined(__native_client_codegen__)
5193 /* native_code_alloc is not 32-byte aligned, native_code is. */
5194 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5195 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5196
5197 /* Align native_code to next nearest kNaclAlignment byte. */
5198 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5199 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5200
5201 code = cfg->native_code;
5202
5203 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5204 g_assert(alignment_check == 0);
5205 #endif
5206
5207 #if 0
5208 {
5209 guint8 *br [16];
5210
5211 /* Check that the stack is aligned on osx */
5212 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5213 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5214 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5215 br [0] = code;
5216 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5217 x86_push_membase (code, X86_ESP, 0);
5218 x86_push_imm (code, cfg->method);
5219 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5220 x86_call_reg (code, X86_EAX);
5221 x86_patch (br [0], code);
5222 }
5223 #endif
5224
5225 /* Offset between RSP and the CFA */
5226 cfa_offset = 0;
5227
5228 // CFA = sp + 4
5229 cfa_offset = sizeof (gpointer);
5230 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5231 // IP saved at CFA - 4
5232 /* There is no IP reg on x86 */
5233 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5234 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5235
5236 need_stack_frame = needs_stack_frame (cfg);
5237
5238 if (need_stack_frame) {
5239 x86_push_reg (code, X86_EBP);
5240 cfa_offset += sizeof (gpointer);
5241 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5242 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5243 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5244 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5245 /* These are handled automatically by the stack marking code */
5246 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5247 } else {
5248 cfg->frame_reg = X86_ESP;
5249 }
5250
5251 cfg->stack_offset += cfg->param_area;
5252 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5253
5254 alloc_size = cfg->stack_offset;
5255 pos = 0;
5256
5257 if (!method->save_lmf) {
5258 if (cfg->used_int_regs & (1 << X86_EBX)) {
5259 x86_push_reg (code, X86_EBX);
5260 pos += 4;
5261 cfa_offset += sizeof (gpointer);
5262 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5263 /* These are handled automatically by the stack marking code */
5264 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5265 }
5266
5267 if (cfg->used_int_regs & (1 << X86_EDI)) {
5268 x86_push_reg (code, X86_EDI);
5269 pos += 4;
5270 cfa_offset += sizeof (gpointer);
5271 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5272 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5273 }
5274
5275 if (cfg->used_int_regs & (1 << X86_ESI)) {
5276 x86_push_reg (code, X86_ESI);
5277 pos += 4;
5278 cfa_offset += sizeof (gpointer);
5279 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5280 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5281 }
5282 }
5283
5284 alloc_size -= pos;
5285
5286 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5287 if (mono_do_x86_stack_align && need_stack_frame) {
5288 int tot = alloc_size + pos + 4; /* ret ip */
5289 if (need_stack_frame)
5290 tot += 4; /* ebp */
5291 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5292 if (tot) {
5293 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5294 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5295 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5296 }
5297 }
5298
5299 cfg->arch.sp_fp_offset = alloc_size + pos;
5300
5301 if (alloc_size) {
5302 /* See mono_emit_stack_alloc */
5303 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5304 guint32 remaining_size = alloc_size;
5305 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5306 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5307 guint32 offset = code - cfg->native_code;
5308 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5309 while (required_code_size >= (cfg->code_size - offset))
5310 cfg->code_size *= 2;
5311 cfg->native_code = mono_realloc_native_code(cfg);
5312 code = cfg->native_code + offset;
5313 cfg->stat_code_reallocs++;
5314 }
5315 while (remaining_size >= 0x1000) {
5316 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5317 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5318 remaining_size -= 0x1000;
5319 }
5320 if (remaining_size)
5321 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5322 #else
5323 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5324 #endif
5325
5326 g_assert (need_stack_frame);
5327 }
5328
5329 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5330 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5331 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5332 }
5333
5334 #if DEBUG_STACK_ALIGNMENT
5335 /* check the stack is aligned */
5336 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5337 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5338 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5339 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5340 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5341 x86_breakpoint (code);
5342 }
5343 #endif
5344
5345 /* compute max_offset in order to use short forward jumps */
5346 max_offset = 0;
5347 if (cfg->opt & MONO_OPT_BRANCH) {
5348 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5349 MonoInst *ins;
5350 bb->max_offset = max_offset;
5351
5352 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5353 max_offset += 6;
5354 /* max alignment for loops */
5355 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5356 max_offset += LOOP_ALIGNMENT;
5357 #ifdef __native_client_codegen__
5358 /* max alignment for native client */
5359 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5360 max_offset += kNaClAlignment;
5361 #endif
5362 MONO_BB_FOR_EACH_INS (bb, ins) {
5363 if (ins->opcode == OP_LABEL)
5364 ins->inst_c1 = max_offset;
5365 #ifdef __native_client_codegen__
5366 switch (ins->opcode)
5367 {
5368 case OP_FCALL:
5369 case OP_LCALL:
5370 case OP_VCALL:
5371 case OP_VCALL2:
5372 case OP_VOIDCALL:
5373 case OP_CALL:
5374 case OP_FCALL_REG:
5375 case OP_LCALL_REG:
5376 case OP_VCALL_REG:
5377 case OP_VCALL2_REG:
5378 case OP_VOIDCALL_REG:
5379 case OP_CALL_REG:
5380 case OP_FCALL_MEMBASE:
5381 case OP_LCALL_MEMBASE:
5382 case OP_VCALL_MEMBASE:
5383 case OP_VCALL2_MEMBASE:
5384 case OP_VOIDCALL_MEMBASE:
5385 case OP_CALL_MEMBASE:
5386 max_offset += kNaClAlignment;
5387 break;
5388 default:
5389 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5390 break;
5391 }
5392 #endif /* __native_client_codegen__ */
5393 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5394 }
5395 }
5396 }
5397
5398 /* store runtime generic context */
5399 if (cfg->rgctx_var) {
5400 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5401
5402 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5403 }
5404
5405 if (method->save_lmf)
5406 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5407
5408 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5409 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5410
5411 /* load arguments allocated to register from the stack */
5412 sig = mono_method_signature (method);
5413 pos = 0;
5414
5415 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5416 inst = cfg->args [pos];
5417 if (inst->opcode == OP_REGVAR) {
5418 g_assert (need_stack_frame);
5419 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5420 if (cfg->verbose_level > 2)
5421 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5422 }
5423 pos++;
5424 }
5425
5426 cfg->code_len = code - cfg->native_code;
5427
5428 g_assert (cfg->code_len < cfg->code_size);
5429
5430 return code;
5431 }
5432
5433 void
5434 mono_arch_emit_epilog (MonoCompile *cfg)
5435 {
5436 MonoMethod *method = cfg->method;
5437 MonoMethodSignature *sig = mono_method_signature (method);
5438 int i, quad, pos;
5439 guint32 stack_to_pop;
5440 guint8 *code;
5441 int max_epilog_size = 16;
5442 CallInfo *cinfo;
5443 gboolean need_stack_frame = needs_stack_frame (cfg);
5444
5445 if (cfg->method->save_lmf)
5446 max_epilog_size += 128;
5447
5448 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5449 cfg->code_size *= 2;
5450 cfg->native_code = mono_realloc_native_code(cfg);
5451 cfg->stat_code_reallocs++;
5452 }
5453
5454 code = cfg->native_code + cfg->code_len;
5455
5456 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5457 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5458
5459 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5460 pos = 0;
5461
5462 if (method->save_lmf) {
5463 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5464 guint8 *patch;
5465 gboolean supported = FALSE;
5466
5467 if (cfg->compile_aot) {
5468 #if defined(__APPLE__) || defined(__linux__)
5469 supported = TRUE;
5470 #endif
5471 } else if (mono_get_jit_tls_offset () != -1) {
5472 supported = TRUE;
5473 }
5474
5475 /* check if we need to restore protection of the stack after a stack overflow */
5476 if (supported) {
5477 if (cfg->compile_aot) {
5478 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5479
5480 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5481 } else {
5482 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5483 }
5484
5485 /* we load the value in a separate instruction: this mechanism may be
5486 * used later as a safer way to do thread interruption
5487 */
5488 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5489 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5490 patch = code;
5491 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5492 /* note that the call trampoline will preserve eax/edx */
5493 x86_call_reg (code, X86_ECX);
5494 x86_patch (patch, code);
5495 } else {
5496 /* FIXME: maybe save the jit tls in the prolog */
5497 }
5498
5499 /* restore caller saved regs */
5500 if (cfg->used_int_regs & (1 << X86_EBX)) {
5501 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5502 }
5503
5504 if (cfg->used_int_regs & (1 << X86_EDI)) {
5505 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5506 }
5507 if (cfg->used_int_regs & (1 << X86_ESI)) {
5508 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5509 }
5510
5511 /* EBP is restored by LEAVE */
5512 } else {
5513 for (i = 0; i < X86_NREG; ++i) {
5514 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5515 pos -= 4;
5516 }
5517 }
5518
5519 if (pos) {
5520 g_assert (need_stack_frame);
5521 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5522 }
5523
5524 if (pos) {
5525 g_assert (need_stack_frame);
5526 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5527 }
5528
5529 if (cfg->used_int_regs & (1 << X86_ESI)) {
5530 x86_pop_reg (code, X86_ESI);
5531 }
5532 if (cfg->used_int_regs & (1 << X86_EDI)) {
5533 x86_pop_reg (code, X86_EDI);
5534 }
5535 if (cfg->used_int_regs & (1 << X86_EBX)) {
5536 x86_pop_reg (code, X86_EBX);
5537 }
5538 }
5539
5540 /* Load returned vtypes into registers if needed */
5541 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5542 if (cinfo->ret.storage == ArgValuetypeInReg) {
5543 for (quad = 0; quad < 2; quad ++) {
5544 switch (cinfo->ret.pair_storage [quad]) {
5545 case ArgInIReg:
5546 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5547 break;
5548 case ArgOnFloatFpStack:
5549 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5550 break;
5551 case ArgOnDoubleFpStack:
5552 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5553 break;
5554 case ArgNone:
5555 break;
5556 default:
5557 g_assert_not_reached ();
5558 }
5559 }
5560 }
5561
5562 if (need_stack_frame)
5563 x86_leave (code);
5564
5565 if (CALLCONV_IS_STDCALL (sig)) {
5566 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5567
5568 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5569 } else if (cinfo->callee_stack_pop)
5570 stack_to_pop = cinfo->callee_stack_pop;
5571 else
5572 stack_to_pop = 0;
5573
5574 if (stack_to_pop) {
5575 g_assert (need_stack_frame);
5576 x86_ret_imm (code, stack_to_pop);
5577 } else {
5578 x86_ret (code);
5579 }
5580
5581 cfg->code_len = code - cfg->native_code;
5582
5583 g_assert (cfg->code_len < cfg->code_size);
5584 }
5585
5586 void
5587 mono_arch_emit_exceptions (MonoCompile *cfg)
5588 {
5589 MonoJumpInfo *patch_info;
5590 int nthrows, i;
5591 guint8 *code;
5592 MonoClass *exc_classes [16];
5593 guint8 *exc_throw_start [16], *exc_throw_end [16];
5594 guint32 code_size;
5595 int exc_count = 0;
5596
5597 /* Compute needed space */
5598 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5599 if (patch_info->type == MONO_PATCH_INFO_EXC)
5600 exc_count++;
5601 }
5602
5603 /*
5604 * make sure we have enough space for exceptions
5605 * 16 is the size of two push_imm instructions and a call
5606 */
5607 if (cfg->compile_aot)
5608 code_size = exc_count * 32;
5609 else
5610 code_size = exc_count * 16;
5611
5612 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5613 cfg->code_size *= 2;
5614 cfg->native_code = mono_realloc_native_code(cfg);
5615 cfg->stat_code_reallocs++;
5616 }
5617
5618 code = cfg->native_code + cfg->code_len;
5619
5620 nthrows = 0;
5621 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5622 switch (patch_info->type) {
5623 case MONO_PATCH_INFO_EXC: {
5624 MonoClass *exc_class;
5625 guint8 *buf, *buf2;
5626 guint32 throw_ip;
5627
5628 x86_patch (patch_info->ip.i + cfg->native_code, code);
5629
5630 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5631 g_assert (exc_class);
5632 throw_ip = patch_info->ip.i;
5633
5634 /* Find a throw sequence for the same exception class */
5635 for (i = 0; i < nthrows; ++i)
5636 if (exc_classes [i] == exc_class)
5637 break;
5638 if (i < nthrows) {
5639 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5640 x86_jump_code (code, exc_throw_start [i]);
5641 patch_info->type = MONO_PATCH_INFO_NONE;
5642 }
5643 else {
5644 guint32 size;
5645
5646 /* Compute size of code following the push <OFFSET> */
5647 #if defined(__default_codegen__)
5648 size = 5 + 5;
5649 #elif defined(__native_client_codegen__)
5650 code = mono_nacl_align (code);
5651 size = kNaClAlignment;
5652 #endif
5653 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5654
5655 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5656 /* Use the shorter form */
5657 buf = buf2 = code;
5658 x86_push_imm (code, 0);
5659 }
5660 else {
5661 buf = code;
5662 x86_push_imm (code, 0xf0f0f0f0);
5663 buf2 = code;
5664 }
5665
5666 if (nthrows < 16) {
5667 exc_classes [nthrows] = exc_class;
5668 exc_throw_start [nthrows] = code;
5669 }
5670
5671 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5672 patch_info->data.name = "mono_arch_throw_corlib_exception";
5673 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5674 patch_info->ip.i = code - cfg->native_code;
5675 x86_call_code (code, 0);
5676 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5677 while (buf < buf2)
5678 x86_nop (buf);
5679
5680 if (nthrows < 16) {
5681 exc_throw_end [nthrows] = code;
5682 nthrows ++;
5683 }
5684 }
5685 break;
5686 }
5687 default:
5688 /* do nothing */
5689 break;
5690 }
5691 }
5692
5693 cfg->code_len = code - cfg->native_code;
5694
5695 g_assert (cfg->code_len < cfg->code_size);
5696 }
5697
5698 void
5699 mono_arch_flush_icache (guint8 *code, gint size)
5700 {
5701 /* not needed */
5702 }
5703
5704 void
5705 mono_arch_flush_register_windows (void)
5706 {
5707 }
5708
5709 gboolean
5710 mono_arch_is_inst_imm (gint64 imm)
5711 {
5712 return TRUE;
5713 }
5714
5715 void
5716 mono_arch_finish_init (void)
5717 {
5718 if (!g_getenv ("MONO_NO_TLS")) {
5719 #ifndef TARGET_WIN32
5720 #if MONO_XEN_OPT
5721 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5722 #endif
5723 #endif
5724 }
5725 }
5726
5727 void
5728 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5729 {
5730 }
5731
5732 // Linear handler, the bsearch head compare is shorter
5733 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5734 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5735 // x86_patch(ins,target)
5736 //[1 + 5] x86_jump_mem(inst,mem)
5737
5738 #define CMP_SIZE 6
5739 #if defined(__default_codegen__)
5740 #define BR_SMALL_SIZE 2
5741 #define BR_LARGE_SIZE 5
5742 #elif defined(__native_client_codegen__)
5743 /* I suspect the size calculation below is actually incorrect. */
5744 /* TODO: fix the calculation that uses these sizes. */
5745 #define BR_SMALL_SIZE 16
5746 #define BR_LARGE_SIZE 12
5747 #endif /*__native_client_codegen__*/
5748 #define JUMP_IMM_SIZE 6
5749 #define ENABLE_WRONG_METHOD_CHECK 0
5750 #define DEBUG_IMT 0
5751
5752 static int
5753 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5754 {
5755 int i, distance = 0;
5756 for (i = start; i < target; ++i)
5757 distance += imt_entries [i]->chunk_size;
5758 return distance;
5759 }
5760
5761 /*
5762 * LOCKING: called with the domain lock held
5763 */
5764 gpointer
5765 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5766 gpointer fail_tramp)
5767 {
5768 int i;
5769 int size = 0;
5770 guint8 *code, *start;
5771
5772 for (i = 0; i < count; ++i) {
5773 MonoIMTCheckItem *item = imt_entries [i];
5774 if (item->is_equals) {
5775 if (item->check_target_idx) {
5776 if (!item->compare_done)
5777 item->chunk_size += CMP_SIZE;
5778 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5779 } else {
5780 if (fail_tramp) {
5781 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5782 } else {
5783 item->chunk_size += JUMP_IMM_SIZE;
5784 #if ENABLE_WRONG_METHOD_CHECK
5785 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5786 #endif
5787 }
5788 }
5789 } else {
5790 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5791 imt_entries [item->check_target_idx]->compare_done = TRUE;
5792 }
5793 size += item->chunk_size;
5794 }
5795 #if defined(__native_client__) && defined(__native_client_codegen__)
5796 /* In Native Client, we don't re-use thunks, allocate from the */
5797 /* normal code manager paths. */
5798 size = NACL_BUNDLE_ALIGN_UP (size);
5799 code = mono_domain_code_reserve (domain, size);
5800 #else
5801 if (fail_tramp)
5802 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5803 else
5804 code = mono_domain_code_reserve (domain, size);
5805 #endif
5806 start = code;
5807 for (i = 0; i < count; ++i) {
5808 MonoIMTCheckItem *item = imt_entries [i];
5809 item->code_target = code;
5810 if (item->is_equals) {
5811 if (item->check_target_idx) {
5812 if (!item->compare_done)
5813 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5814 item->jmp_code = code;
5815 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5816 if (item->has_target_code)
5817 x86_jump_code (code, item->value.target_code);
5818 else
5819 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5820 } else {
5821 if (fail_tramp) {
5822 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5823 item->jmp_code = code;
5824 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5825 if (item->has_target_code)
5826 x86_jump_code (code, item->value.target_code);
5827 else
5828 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5829 x86_patch (item->jmp_code, code);
5830 x86_jump_code (code, fail_tramp);
5831 item->jmp_code = NULL;
5832 } else {
5833 /* enable the commented code to assert on wrong method */
5834 #if ENABLE_WRONG_METHOD_CHECK
5835 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5836 item->jmp_code = code;
5837 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5838 #endif
5839 if (item->has_target_code)
5840 x86_jump_code (code, item->value.target_code);
5841 else
5842 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5843 #if ENABLE_WRONG_METHOD_CHECK
5844 x86_patch (item->jmp_code, code);
5845 x86_breakpoint (code);
5846 item->jmp_code = NULL;
5847 #endif
5848 }
5849 }
5850 } else {
5851 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5852 item->jmp_code = code;
5853 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5854 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5855 else
5856 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5857 }
5858 }
5859 /* patch the branches to get to the target items */
5860 for (i = 0; i < count; ++i) {
5861 MonoIMTCheckItem *item = imt_entries [i];
5862 if (item->jmp_code) {
5863 if (item->check_target_idx) {
5864 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5865 }
5866 }
5867 }
5868
5869 if (!fail_tramp)
5870 mono_stats.imt_thunks_size += code - start;
5871 g_assert (code - start <= size);
5872
5873 #if DEBUG_IMT
5874 {
5875 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5876 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5877 g_free (buff);
5878 }
5879 #endif
5880 if (mono_jit_map_is_enabled ()) {
5881 char *buff;
5882 if (vtable)
5883 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5884 else
5885 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5886 mono_emit_jit_tramp (start, code - start, buff);
5887 g_free (buff);
5888 }
5889
5890 nacl_domain_code_validate (domain, &start, size, &code);
5891 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5892
5893 return start;
5894 }
5895
5896 MonoMethod*
5897 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5898 {
5899 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5900 }
5901
5902 MonoVTable*
5903 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5904 {
5905 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5906 }
5907
5908 GSList*
5909 mono_arch_get_cie_program (void)
5910 {
5911 GSList *l = NULL;
5912
5913 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5914 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5915
5916 return l;
5917 }
5918
5919 MonoInst*
5920 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5921 {
5922 MonoInst *ins = NULL;
5923 int opcode = 0;
5924
5925 if (cmethod->klass == mono_defaults.math_class) {
5926 if (strcmp (cmethod->name, "Sin") == 0) {
5927 opcode = OP_SIN;
5928 } else if (strcmp (cmethod->name, "Cos") == 0) {
5929 opcode = OP_COS;
5930 } else if (strcmp (cmethod->name, "Tan") == 0) {
5931 opcode = OP_TAN;
5932 } else if (strcmp (cmethod->name, "Atan") == 0) {
5933 opcode = OP_ATAN;
5934 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5935 opcode = OP_SQRT;
5936 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5937 opcode = OP_ABS;
5938 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5939 opcode = OP_ROUND;
5940 }
5941
5942 if (opcode && fsig->param_count == 1) {
5943 MONO_INST_NEW (cfg, ins, opcode);
5944 ins->type = STACK_R8;
5945 ins->dreg = mono_alloc_freg (cfg);
5946 ins->sreg1 = args [0]->dreg;
5947 MONO_ADD_INS (cfg->cbb, ins);
5948 }
5949
5950 if (cfg->opt & MONO_OPT_CMOV) {
5951 opcode = 0;
5952
5953 if (strcmp (cmethod->name, "Min") == 0) {
5954 if (fsig->params [0]->type == MONO_TYPE_I4)
5955 opcode = OP_IMIN;
5956 } else if (strcmp (cmethod->name, "Max") == 0) {
5957 if (fsig->params [0]->type == MONO_TYPE_I4)
5958 opcode = OP_IMAX;
5959 }
5960
5961 if (opcode && fsig->param_count == 2) {
5962 MONO_INST_NEW (cfg, ins, opcode);
5963 ins->type = STACK_I4;
5964 ins->dreg = mono_alloc_ireg (cfg);
5965 ins->sreg1 = args [0]->dreg;
5966 ins->sreg2 = args [1]->dreg;
5967 MONO_ADD_INS (cfg->cbb, ins);
5968 }
5969 }
5970
5971 #if 0
5972 /* OP_FREM is not IEEE compatible */
5973 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5974 MONO_INST_NEW (cfg, ins, OP_FREM);
5975 ins->inst_i0 = args [0];
5976 ins->inst_i1 = args [1];
5977 }
5978 #endif
5979 }
5980
5981 return ins;
5982 }
5983
5984 gboolean
5985 mono_arch_print_tree (MonoInst *tree, int arity)
5986 {
5987 return 0;
5988 }
5989
5990 guint32
5991 mono_arch_get_patch_offset (guint8 *code)
5992 {
5993 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5994 return 2;
5995 else if (code [0] == 0xba)
5996 return 1;
5997 else if (code [0] == 0x68)
5998 /* push IMM */
5999 return 1;
6000 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6001 /* push <OFFSET>(<REG>) */
6002 return 2;
6003 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6004 /* call *<OFFSET>(<REG>) */
6005 return 2;
6006 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6007 /* fldl <ADDR> */
6008 return 2;
6009 else if ((code [0] == 0x58) && (code [1] == 0x05))
6010 /* pop %eax; add <OFFSET>, %eax */
6011 return 2;
6012 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6013 /* pop <REG>; add <OFFSET>, <REG> */
6014 return 3;
6015 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6016 /* mov <REG>, imm */
6017 return 1;
6018 else {
6019 g_assert_not_reached ();
6020 return -1;
6021 }
6022 }
6023
6024 /**
6025 * mono_breakpoint_clean_code:
6026 *
6027 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6028 * breakpoints in the original code, they are removed in the copy.
6029 *
6030 * Returns TRUE if no sw breakpoint was present.
6031 */
6032 gboolean
6033 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6034 {
6035 /*
6036 * If method_start is non-NULL we need to perform bound checks, since we access memory
6037 * at code - offset we could go before the start of the method and end up in a different
6038 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6039 * instead.
6040 */
6041 if (!method_start || code - offset >= method_start) {
6042 memcpy (buf, code - offset, size);
6043 } else {
6044 int diff = code - method_start;
6045 memset (buf, 0, size);
6046 memcpy (buf + offset - diff, method_start, diff + size - offset);
6047 }
6048 return TRUE;
6049 }
6050
6051 /*
6052 * mono_x86_get_this_arg_offset:
6053 *
6054 * Return the offset of the stack location where this is passed during a virtual
6055 * call.
6056 */
6057 guint32
6058 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6059 {
6060 return 0;
6061 }
6062
6063 gpointer
6064 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6065 {
6066 guint32 esp = regs [X86_ESP];
6067 gpointer res;
6068 int offset;
6069
6070 offset = 0;
6071
6072 /*
6073 * The stack looks like:
6074 * <other args>
6075 * <this=delegate>
6076 */
6077 res = ((MonoObject**)esp) [0];
6078 return res;
6079 }
6080
6081 #define MAX_ARCH_DELEGATE_PARAMS 10
6082
6083 static gpointer
6084 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6085 {
6086 guint8 *code, *start;
6087 int code_reserve = 64;
6088
6089 /*
6090 * The stack contains:
6091 * <delegate>
6092 * <return addr>
6093 */
6094
6095 if (has_target) {
6096 start = code = mono_global_codeman_reserve (code_reserve);
6097
6098 /* Replace the this argument with the target */
6099 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6100 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6101 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6102 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6103
6104 g_assert ((code - start) < code_reserve);
6105 } else {
6106 int i = 0;
6107 /* 8 for mov_reg and jump, plus 8 for each parameter */
6108 #ifdef __native_client_codegen__
6109 /* TODO: calculate this size correctly */
6110 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6111 #else
6112 code_reserve = 8 + (param_count * 8);
6113 #endif /* __native_client_codegen__ */
6114 /*
6115 * The stack contains:
6116 * <args in reverse order>
6117 * <delegate>
6118 * <return addr>
6119 *
6120 * and we need:
6121 * <args in reverse order>
6122 * <return addr>
6123 *
6124 * without unbalancing the stack.
6125 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6126 * and leaving original spot of first arg as placeholder in stack so
6127 * when callee pops stack everything works.
6128 */
6129
6130 start = code = mono_global_codeman_reserve (code_reserve);
6131
6132 /* store delegate for access to method_ptr */
6133 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6134
6135 /* move args up */
6136 for (i = 0; i < param_count; ++i) {
6137 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6138 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6139 }
6140
6141 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6142
6143 g_assert ((code - start) < code_reserve);
6144 }
6145
6146 nacl_global_codeman_validate (&start, code_reserve, &code);
6147
6148 if (code_len)
6149 *code_len = code - start;
6150
6151 if (mono_jit_map_is_enabled ()) {
6152 char *buff;
6153 if (has_target)
6154 buff = (char*)"delegate_invoke_has_target";
6155 else
6156 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6157 mono_emit_jit_tramp (start, code - start, buff);
6158 if (!has_target)
6159 g_free (buff);
6160 }
6161 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6162
6163 return start;
6164 }
6165
6166 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6167
6168 static gpointer
6169 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_size)
6170 {
6171 guint8 *code, *start;
6172 int size = 24;
6173
6174 /*
6175 * The stack contains:
6176 * <delegate>
6177 * <return addr>
6178 */
6179 start = code = mono_global_codeman_reserve (size);
6180
6181 /* Replace the this argument with the target */
6182 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6183 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6184 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6185
6186 if (load_imt_reg) {
6187 /* Load the IMT reg */
6188 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6189 }
6190
6191 /* Load the vtable */
6192 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6193 x86_jump_membase (code, X86_EAX, offset);
6194 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6195
6196 if (code_size)
6197 *code_size = code - start;
6198
6199 return start;
6200 }
6201
6202 GSList*
6203 mono_arch_get_delegate_invoke_impls (void)
6204 {
6205 GSList *res = NULL;
6206 guint8 *code;
6207 guint32 code_len;
6208 int i;
6209 char *tramp_name;
6210
6211 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6212 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6213
6214 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6215 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6216 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6217 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6218 g_free (tramp_name);
6219 }
6220
6221 for (i = 0; i < MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6222 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
6223 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
6224 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6225 g_free (tramp_name);
6226
6227 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
6228 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
6229 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6230 g_free (tramp_name);
6231 }
6232
6233 return res;
6234 }
6235
6236 gpointer
6237 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6238 {
6239 guint8 *code, *start;
6240
6241 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6242 return NULL;
6243
6244 /* FIXME: Support more cases */
6245 if (MONO_TYPE_ISSTRUCT (sig->ret))
6246 return NULL;
6247
6248 /*
6249 * The stack contains:
6250 * <delegate>
6251 * <return addr>
6252 */
6253
6254 if (has_target) {
6255 static guint8* cached = NULL;
6256 if (cached)
6257 return cached;
6258
6259 if (mono_aot_only)
6260 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6261 else
6262 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6263
6264 mono_memory_barrier ();
6265
6266 cached = start;
6267 } else {
6268 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6269 int i = 0;
6270
6271 for (i = 0; i < sig->param_count; ++i)
6272 if (!mono_is_regsize_var (sig->params [i]))
6273 return NULL;
6274
6275 code = cache [sig->param_count];
6276 if (code)
6277 return code;
6278
6279 if (mono_aot_only) {
6280 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6281 start = mono_aot_get_trampoline (name);
6282 g_free (name);
6283 } else {
6284 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6285 }
6286
6287 mono_memory_barrier ();
6288
6289 cache [sig->param_count] = start;
6290 }
6291
6292 return start;
6293 }
6294
6295 gpointer
6296 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6297 {
6298 return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
6299 }
6300
6301 mgreg_t
6302 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6303 {
6304 switch (reg) {
6305 case X86_EAX: return ctx->eax;
6306 case X86_EBX: return ctx->ebx;
6307 case X86_ECX: return ctx->ecx;
6308 case X86_EDX: return ctx->edx;
6309 case X86_ESP: return ctx->esp;
6310 case X86_EBP: return ctx->ebp;
6311 case X86_ESI: return ctx->esi;
6312 case X86_EDI: return ctx->edi;
6313 default:
6314 g_assert_not_reached ();
6315 return 0;
6316 }
6317 }
6318
6319 void
6320 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6321 {
6322 switch (reg) {
6323 case X86_EAX:
6324 ctx->eax = val;
6325 break;
6326 case X86_EBX:
6327 ctx->ebx = val;
6328 break;
6329 case X86_ECX:
6330 ctx->ecx = val;
6331 break;
6332 case X86_EDX:
6333 ctx->edx = val;
6334 break;
6335 case X86_ESP:
6336 ctx->esp = val;
6337 break;
6338 case X86_EBP:
6339 ctx->ebp = val;
6340 break;
6341 case X86_ESI:
6342 ctx->esi = val;
6343 break;
6344 case X86_EDI:
6345 ctx->edi = val;
6346 break;
6347 default:
6348 g_assert_not_reached ();
6349 }
6350 }
6351
6352 #ifdef MONO_ARCH_SIMD_INTRINSICS
6353
6354 static MonoInst*
6355 get_float_to_x_spill_area (MonoCompile *cfg)
6356 {
6357 if (!cfg->fconv_to_r8_x_var) {
6358 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6359 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6360 }
6361 return cfg->fconv_to_r8_x_var;
6362 }
6363
6364 /*
6365 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6366 */
6367 void
6368 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6369 {
6370 MonoInst *fconv;
6371 int dreg, src_opcode;
6372
6373 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6374 return;
6375
6376 switch (src_opcode = ins->opcode) {
6377 case OP_FCONV_TO_I1:
6378 case OP_FCONV_TO_U1:
6379 case OP_FCONV_TO_I2:
6380 case OP_FCONV_TO_U2:
6381 case OP_FCONV_TO_I4:
6382 case OP_FCONV_TO_I:
6383 break;
6384 default:
6385 return;
6386 }
6387
6388 /* dreg is the IREG and sreg1 is the FREG */
6389 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6390 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6391 fconv->sreg1 = ins->sreg1;
6392 fconv->dreg = mono_alloc_ireg (cfg);
6393 fconv->type = STACK_VTYPE;
6394 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6395
6396 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6397
6398 dreg = ins->dreg;
6399 NULLIFY_INS (ins);
6400 ins->opcode = OP_XCONV_R8_TO_I4;
6401
6402 ins->klass = mono_defaults.int32_class;
6403 ins->sreg1 = fconv->dreg;
6404 ins->dreg = dreg;
6405 ins->type = STACK_I4;
6406 ins->backend.source_opcode = src_opcode;
6407 }
6408
6409 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6410
6411 void
6412 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6413 {
6414 MonoInst *ins;
6415 int vreg;
6416
6417 if (long_ins->opcode == OP_LNEG) {
6418 ins = long_ins;
6419 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6420 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6421 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6422 NULLIFY_INS (ins);
6423 return;
6424 }
6425
6426 #ifdef MONO_ARCH_SIMD_INTRINSICS
6427
6428 if (!(cfg->opt & MONO_OPT_SIMD))
6429 return;
6430
6431 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6432 switch (long_ins->opcode) {
6433 case OP_EXTRACT_I8:
6434 vreg = long_ins->sreg1;
6435
6436 if (long_ins->inst_c0) {
6437 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6438 ins->klass = long_ins->klass;
6439 ins->sreg1 = long_ins->sreg1;
6440 ins->inst_c0 = 2;
6441 ins->type = STACK_VTYPE;
6442 ins->dreg = vreg = alloc_ireg (cfg);
6443 MONO_ADD_INS (cfg->cbb, ins);
6444 }
6445
6446 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6447 ins->klass = mono_defaults.int32_class;
6448 ins->sreg1 = vreg;
6449 ins->type = STACK_I4;
6450 ins->dreg = long_ins->dreg + 1;
6451 MONO_ADD_INS (cfg->cbb, ins);
6452
6453 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6454 ins->klass = long_ins->klass;
6455 ins->sreg1 = long_ins->sreg1;
6456 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6457 ins->type = STACK_VTYPE;
6458 ins->dreg = vreg = alloc_ireg (cfg);
6459 MONO_ADD_INS (cfg->cbb, ins);
6460
6461 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6462 ins->klass = mono_defaults.int32_class;
6463 ins->sreg1 = vreg;
6464 ins->type = STACK_I4;
6465 ins->dreg = long_ins->dreg + 2;
6466 MONO_ADD_INS (cfg->cbb, ins);
6467
6468 long_ins->opcode = OP_NOP;
6469 break;
6470 case OP_INSERTX_I8_SLOW:
6471 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6472 ins->dreg = long_ins->dreg;
6473 ins->sreg1 = long_ins->dreg;
6474 ins->sreg2 = long_ins->sreg2 + 1;
6475 ins->inst_c0 = long_ins->inst_c0 * 2;
6476 MONO_ADD_INS (cfg->cbb, ins);
6477
6478 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6479 ins->dreg = long_ins->dreg;
6480 ins->sreg1 = long_ins->dreg;
6481 ins->sreg2 = long_ins->sreg2 + 2;
6482 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6483 MONO_ADD_INS (cfg->cbb, ins);
6484
6485 long_ins->opcode = OP_NOP;
6486 break;
6487 case OP_EXPAND_I8:
6488 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6489 ins->dreg = long_ins->dreg;
6490 ins->sreg1 = long_ins->sreg1 + 1;
6491 ins->klass = long_ins->klass;
6492 ins->type = STACK_VTYPE;
6493 MONO_ADD_INS (cfg->cbb, ins);
6494
6495 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6496 ins->dreg = long_ins->dreg;
6497 ins->sreg1 = long_ins->dreg;
6498 ins->sreg2 = long_ins->sreg1 + 2;
6499 ins->inst_c0 = 1;
6500 ins->klass = long_ins->klass;
6501 ins->type = STACK_VTYPE;
6502 MONO_ADD_INS (cfg->cbb, ins);
6503
6504 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6505 ins->dreg = long_ins->dreg;
6506 ins->sreg1 = long_ins->dreg;;
6507 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6508 ins->klass = long_ins->klass;
6509 ins->type = STACK_VTYPE;
6510 MONO_ADD_INS (cfg->cbb, ins);
6511
6512 long_ins->opcode = OP_NOP;
6513 break;
6514 }
6515 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6516 }
6517
6518 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6519 gpointer
6520 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6521 {
6522 int offset;
6523 gpointer *sp, old_value;
6524 char *bp;
6525
6526 offset = clause->exvar_offset;
6527
6528 /*Load the spvar*/
6529 bp = MONO_CONTEXT_GET_BP (ctx);
6530 sp = *(gpointer*)(bp + offset);
6531
6532 old_value = *sp;
6533 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6534 return old_value;
6535
6536 *sp = new_value;
6537
6538 return old_value;
6539 }
6540
6541 /*
6542 * mono_aot_emit_load_got_addr:
6543 *
6544 * Emit code to load the got address.
6545 * On x86, the result is placed into EBX.
6546 */
6547 guint8*
6548 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6549 {
6550 x86_call_imm (code, 0);
6551 /*
6552 * The patch needs to point to the pop, since the GOT offset needs
6553 * to be added to that address.
6554 */
6555 if (cfg)
6556 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6557 else
6558 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6559 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6560 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6561
6562 return code;
6563 }
6564
6565 static guint8*
6566 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6567 {
6568 if (cfg)
6569 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6570 else
6571 g_assert_not_reached ();
6572 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6573 return code;
6574 }
6575
6576 /*
6577 * mono_arch_emit_load_aotconst:
6578 *
6579 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6580 * TARGET from the mscorlib GOT in full-aot code.
6581 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6582 * EAX.
6583 */
6584 guint8*
6585 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6586 {
6587 /* Load the mscorlib got address */
6588 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6589 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6590 /* arch_emit_got_access () patches this */
6591 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6592
6593 return code;
6594 }
6595
6596 /* Can't put this into mini-x86.h */
6597 gpointer
6598 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6599
6600 GSList *
6601 mono_arch_get_trampolines (gboolean aot)
6602 {
6603 MonoTrampInfo *info;
6604 GSList *tramps = NULL;
6605
6606 mono_x86_get_signal_exception_trampoline (&info, aot);
6607
6608 tramps = g_slist_append (tramps, info);
6609
6610 return tramps;
6611 }
6612
6613
6614 #if __APPLE__
6615 #define DBG_SIGNAL SIGBUS
6616 #else
6617 #define DBG_SIGNAL SIGSEGV
6618 #endif
6619
6620 /* Soft Debug support */
6621 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6622
6623 /*
6624 * mono_arch_set_breakpoint:
6625 *
6626 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6627 * The location should contain code emitted by OP_SEQ_POINT.
6628 */
6629 void
6630 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6631 {
6632 guint8 *code = ip;
6633
6634 /*
6635 * In production, we will use int3 (has to fix the size in the md
6636 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6637 * instead.
6638 */
6639 g_assert (code [0] == 0x90);
6640 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6641 }
6642
6643 /*
6644 * mono_arch_clear_breakpoint:
6645 *
6646 * Clear the breakpoint at IP.
6647 */
6648 void
6649 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6650 {
6651 guint8 *code = ip;
6652 int i;
6653
6654 for (i = 0; i < 6; ++i)
6655 x86_nop (code);
6656 }
6657
6658 /*
6659 * mono_arch_start_single_stepping:
6660 *
6661 * Start single stepping.
6662 */
6663 void
6664 mono_arch_start_single_stepping (void)
6665 {
6666 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6667 }
6668
6669 /*
6670 * mono_arch_stop_single_stepping:
6671 *
6672 * Stop single stepping.
6673 */
6674 void
6675 mono_arch_stop_single_stepping (void)
6676 {
6677 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6678 }
6679
6680 /*
6681 * mono_arch_is_single_step_event:
6682 *
6683 * Return whenever the machine state in SIGCTX corresponds to a single
6684 * step event.
6685 */
6686 gboolean
6687 mono_arch_is_single_step_event (void *info, void *sigctx)
6688 {
6689 #ifdef TARGET_WIN32
6690 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6691
6692 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6693 return TRUE;
6694 else
6695 return FALSE;
6696 #else
6697 siginfo_t* sinfo = (siginfo_t*) info;
6698 /* Sometimes the address is off by 4 */
6699 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6700 return TRUE;
6701 else
6702 return FALSE;
6703 #endif
6704 }
6705
6706 gboolean
6707 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6708 {
6709 #ifdef TARGET_WIN32
6710 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6711 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6712 return TRUE;
6713 else
6714 return FALSE;
6715 #else
6716 siginfo_t* sinfo = (siginfo_t*)info;
6717 /* Sometimes the address is off by 4 */
6718 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6719 return TRUE;
6720 else
6721 return FALSE;
6722 #endif
6723 }
6724
6725 #define BREAKPOINT_SIZE 6
6726
6727 /*
6728 * mono_arch_skip_breakpoint:
6729 *
6730 * See mini-amd64.c for docs.
6731 */
6732 void
6733 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6734 {
6735 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6736 }
6737
6738 /*
6739 * mono_arch_skip_single_step:
6740 *
6741 * See mini-amd64.c for docs.
6742 */
6743 void
6744 mono_arch_skip_single_step (MonoContext *ctx)
6745 {
6746 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6747 }
6748
6749 /*
6750 * mono_arch_get_seq_point_info:
6751 *
6752 * See mini-amd64.c for docs.
6753 */
6754 gpointer
6755 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6756 {
6757 NOT_IMPLEMENTED;
6758 return NULL;
6759 }
6760
6761 void
6762 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6763 {
6764 ext->lmf.previous_lmf = (gsize)prev_lmf;
6765 /* Mark that this is a MonoLMFExt */
6766 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6767 ext->lmf.ebp = (gssize)ext;
6768 }
6769
6770 #endif
6771
6772 gboolean
6773 mono_arch_opcode_supported (int opcode)
6774 {
6775 switch (opcode) {
6776 case OP_ATOMIC_ADD_I4:
6777 case OP_ATOMIC_EXCHANGE_I4:
6778 case OP_ATOMIC_CAS_I4:
6779 case OP_ATOMIC_LOAD_I1:
6780 case OP_ATOMIC_LOAD_I2:
6781 case OP_ATOMIC_LOAD_I4:
6782 case OP_ATOMIC_LOAD_U1:
6783 case OP_ATOMIC_LOAD_U2:
6784 case OP_ATOMIC_LOAD_U4:
6785 case OP_ATOMIC_LOAD_R4:
6786 case OP_ATOMIC_LOAD_R8:
6787 case OP_ATOMIC_STORE_I1:
6788 case OP_ATOMIC_STORE_I2:
6789 case OP_ATOMIC_STORE_I4:
6790 case OP_ATOMIC_STORE_U1:
6791 case OP_ATOMIC_STORE_U2:
6792 case OP_ATOMIC_STORE_U4:
6793 case OP_ATOMIC_STORE_R4:
6794 case OP_ATOMIC_STORE_R8:
6795 return TRUE;
6796 default:
6797 return FALSE;
6798 }
6799 }
6800
6801 #if defined(ENABLE_GSHAREDVT)
6802
6803 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6804
6805 #endif /* !MONOTOUCH */
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