mono/utils/mono-memory-model.h

   1 /*
   2  * mono-memory-model.h: Mapping of the arch memory model.
   3  *
   4  * Author:
   5  *      Rodrigo Kumpera (kumpera@gmail.com)
   6  *
   7  * (C) 2011 Xamarin, Inc
   8  */
   9
  10 #ifndef _MONO_UTILS_MONO_MEMMODEL_H_
  11 #define _MONO_UTILS_MONO_MEMMODEL_H_
  12
  13 #include <config.h>
  14 #include <mono/utils/mono-membar.h>
  15
  16 /*
  17 In order to allow for fast concurrent code, we must use fencing to properly order
  18 memory access - specially on arch with weaker memory models such as ARM or PPC.
  19
  20 On the other hand, we can't use arm's weak model on targets such as x86 that have
  21 a stronger model that requires much much less fencing.
  22
  23 The idea of exposing each arch memory model is to avoid fencing whenever possible
  24 but at the same time make all required ordering explicit.
  25
  26 There are four kinds of barriers, LoadLoad, LoadStore, StoreLoad and StoreStore.
  27 Each arch must define which ones needs fencing.
  28
  29 We assume 3 kinds of barriers are available: load, store and memory (load+store).
  30
  31 TODO: Add support for weaker forms of CAS such as present on ARM.
  32 TODO: replace all explicit uses of memory barriers with macros from this section. This will make a nicer read of lazy init code.
  33 TODO: if we find places where a data depencency could replace barriers, add macros here to help with it
  34 TODO: some arch with strong consistency, such as x86, support weaker access. We might need to expose more kinds of barriers once we exploit this.
  35 */
  36
  37 /*
  38  * Keep in sync with the enum in mini/mini-llvm-cpp.h.
  39  */
  40 enum {
  41     MONO_MEMORY_BARRIER_NONE = 0,
  42     MONO_MEMORY_BARRIER_ACQ = 1,
  43     MONO_MEMORY_BARRIER_REL = 2,
  44     MONO_MEMORY_BARRIER_SEQ = 3,
  45 };
  46
  47 #define MEMORY_BARRIER mono_memory_barrier ()
  48 #define LOAD_BARRIER mono_memory_read_barrier ()
  49 #define STORE_BARRIER mono_memory_write_barrier ()
  50
  51 #if defined(__i386__) || defined(__x86_64__)
  52 /*
  53 Both x86 and amd64 follow the SPO memory model:
  54 -Loads are not reordered with other loads
  55 -Stores are not reordered with others stores
  56 -Stores are not reordered with earlier loads
  57 */
  58
  59 /*Neither sfence or mfence provide the required semantics here*/
  60 #define STORE_LOAD_FENCE MEMORY_BARRIER
  61
  62 #define LOAD_RELEASE_FENCE MEMORY_BARRIER
  63 #define STORE_ACQUIRE_FENCE MEMORY_BARRIER
  64
  65 #elif defined(__arm__)
  66 /*
  67 ARM memory model is as weak as it can get. the only guarantee are data dependent
  68 accesses.
  69 LoadStore fences are much better handled using a data depencency such as:
  70 load x;  if (x = x) store y;
  71
  72 This trick can be applied to other fences such as LoadLoad, but require some assembly:
  73
  74 LDR R0, [R1]
  75 AND R0, R0, #0
  76 LDR R3, [R4, R0]
  77 */
  78
  79 #define STORE_STORE_FENCE STORE_BARRIER
  80 #define LOAD_LOAD_FENCE LOAD_BARRIER
  81 #define STORE_LOAD_FENCE MEMORY_BARRIER
  82 #define STORE_ACQUIRE_FENCE MEMORY_BARRIER
  83 #define STORE_RELEASE_FENCE MEMORY_BARRIER
  84 #define LOAD_ACQUIRE_FENCE MEMORY_BARRIER
  85 #define LOAD_RELEASE_FENCE MEMORY_BARRIER
  86
  87 #elif defined(__s390x__)
  88
  89 #define STORE_STORE_FENCE do {} while (0)
  90 #define LOAD_LOAD_FENCE  do {} while (0)
  91 #define STORE_LOAD_FENCE do {} while (0)
  92 #define LOAD_STORE_FENCE do {} while (0)
  93 #define STORE_RELEASE_FENCE do {} while (0)
  94
  95 #else
  96
  97 /*default implementation with the weakest possible memory model */
  98 #define STORE_STORE_FENCE STORE_BARRIER
  99 #define LOAD_LOAD_FENCE LOAD_BARRIER
 100 #define STORE_LOAD_FENCE MEMORY_BARRIER
 101 #define LOAD_STORE_FENCE MEMORY_BARRIER
 102 #define STORE_ACQUIRE_FENCE MEMORY_BARRIER
 103 #define STORE_RELEASE_FENCE MEMORY_BARRIER
 104 #define LOAD_ACQUIRE_FENCE MEMORY_BARRIER
 105 #define LOAD_RELEASE_FENCE MEMORY_BARRIER
 106
 107 #endif
 108
 109 #ifndef STORE_STORE_FENCE
 110 #define STORE_STORE_FENCE
 111 #endif
 112
 113 #ifndef LOAD_LOAD_FENCE
 114 #define LOAD_LOAD_FENCE
 115 #endif
 116
 117 #ifndef STORE_LOAD_FENCE
 118 #define STORE_LOAD_FENCE
 119 #endif
 120
 121 #ifndef LOAD_STORE_FENCE
 122 #define LOAD_STORE_FENCE
 123 #endif
 124
 125 #ifndef STORE_RELEASE_FENCE
 126 #define STORE_RELEASE_FENCE
 127 #endif
 128
 129 #ifndef LOAD_RELEASE_FENCE
 130 #define LOAD_RELEASE_FENCE
 131 #endif
 132
 133 #ifndef STORE_ACQUIRE_FENCE
 134 #define STORE_ACQUIRE_FENCE
 135 #endif
 136
 137 #ifndef LOAD_ACQUIRE_FENCE
 138 #define LOAD_ACQUIRE_FENCE
 139 #endif
 140
 141
 142 /*Makes sure all previous stores as visible before */
 143 #define mono_atomic_store_seq(target,value) do {        \
 144         STORE_STORE_FENCE;      \
 145         *(target) = (value);    \
 146 } while (0)
 147
 148
 149 /*
 150 Acquire/release semantics macros.
 151 */
 152 #define mono_atomic_store_release(target,value) do {    \
 153         STORE_RELEASE_FENCE;    \
 154         *(target) = (value);    \
 155 } while (0)
 156
 157 #define mono_atomic_load_release(_type,target) ({       \
 158         _type __tmp;    \
 159         LOAD_RELEASE_FENCE;     \
 160         __tmp = *(target);      \
 161         __tmp; })
 162
 163 #define mono_atomic_load_acquire(var,_type,target) do { \
 164         _type __tmp = *(target);        \
 165         LOAD_ACQUIRE_FENCE;     \
 166         (var) = __tmp; \
 167 } while (0)
 168
 169 #define mono_atomic_store_acquire(target,value) {       \
 170         *(target) = (value);    \
 171         STORE_ACQUIRE_FENCE;    \
 172         }
 173
 174 #endif /* _MONO_UTILS_MONO_MEMMODEL_H_ */