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update rx (mobile builds).
[mono-project.git] / mono / mini / mini-arm.c
blob5f2c4b446e497627d72f2bb371206389cd8ba498
1 /*
2 * mini-arm.c: ARM backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 *
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 */
12 #include "mini.h"
13 #include <string.h>
14
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
18
19 #include "mini-arm.h"
20 #include "cpu-arm.h"
21 #include "trace.h"
22 #include "ir-emit.h"
23 #include "debugger-agent.h"
24 #include "mini-gc.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
27
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
30 #endif
31
32 #ifdef ARM_FPU_VFP_HARD
33 #define ARM_FPU_VFP 1
34 #endif
35
36 #ifdef ARM_FPU_FPA
37 #define IS_FPA 1
38 #else
39 #define IS_FPA 0
40 #endif
41
42 #ifdef ARM_FPU_VFP
43 #define IS_VFP 1
44 #else
45 #define IS_VFP 0
46 #endif
47
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
50 #else
51 #define IS_SOFT_FLOAT 0
52 #endif
53
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
55
56 #if __APPLE__
57 void sys_icache_invalidate (void *start, size_t len);
58 #endif
59
60 static gint lmf_tls_offset = -1;
61 static gint lmf_addr_tls_offset = -1;
62
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
67
68 static int v5_supported = 0;
69 static int v6_supported = 0;
70 static int v7_supported = 0;
71 static int thumb_supported = 0;
72 /*
73 * Whenever to use the ARM EABI
74 */
75 static int eabi_supported = 0;
76
77 /*
78 * Whenever we are on arm/darwin aka the iphone.
79 */
80 static int darwin = 0;
81 /*
82 * Whenever to use the iphone ABI extensions:
83 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
84 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
85 * This is required for debugging/profiling tools to work, but it has some overhead so it should
86 * only be turned on in debug builds.
87 */
88 static int iphone_abi = 0;
89
90 /*
91 * The FPU we are generating code for. This is NOT runtime configurable right now,
92 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
93 */
94 static MonoArmFPU arm_fpu;
95
96 static int i8_align;
97
98 static volatile int ss_trigger_var = 0;
99
100 static gpointer single_step_func_wrapper;
101 static gpointer breakpoint_func_wrapper;
102
103 /*
104 * The code generated for sequence points reads from this location, which is
105 * made read-only when single stepping is enabled.
106 */
107 static gpointer ss_trigger_page;
108
109 /* Enabled breakpoints read from this trigger page */
110 static gpointer bp_trigger_page;
111
112 /* Structure used by the sequence points in AOTed code */
113 typedef struct {
114 gpointer ss_trigger_page;
115 gpointer bp_trigger_page;
116 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
117 } SeqPointInfo;
118
119 /*
120 * TODO:
121 * floating point support: on ARM it is a mess, there are at least 3
122 * different setups, each of which binary incompat with the other.
123 * 1) FPA: old and ugly, but unfortunately what current distros use
124 * the double binary format has the two words swapped. 8 double registers.
125 * Implemented usually by kernel emulation.
126 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
127 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
128 * 3) VFP: the new and actually sensible and useful FP support. Implemented
129 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
130 *
131 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
132 */
133 int mono_exc_esp_offset = 0;
134
135 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
136 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
137 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
138
139 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
140 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
141 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
142
143 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
144 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
145 #define DEBUG_IMT 0
146
147 /* A variant of ARM_LDR_IMM which can handle large offsets */
148 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
149 if (arm_is_imm12 ((offset))) { \
150 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
151 } else { \
152 g_assert ((scratch_reg) != (basereg)); \
153 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
154 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
155 } \
156 } while (0)
157
158 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
159 if (arm_is_imm12 ((offset))) { \
160 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
161 } else { \
162 g_assert ((scratch_reg) != (basereg)); \
163 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
164 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
165 } \
166 } while (0)
167
168 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
169
170 const char*
171 mono_arch_regname (int reg)
172 {
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 "arm_pc"
178 };
179 if (reg >= 0 && reg < 16)
180 return rnames [reg];
181 return "unknown";
182 }
183
184 const char*
185 mono_arch_fregname (int reg)
186 {
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 "arm_f30", "arm_f31"
195 };
196 if (reg >= 0 && reg < 32)
197 return rnames [reg];
198 return "unknown";
199 }
200
201 #ifndef DISABLE_JIT
202
203 static guint8*
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
205 {
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
209 return code;
210 }
211 g_assert (dreg != sreg);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
214 return code;
215 }
216
217 static guint8*
218 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
219 {
220 /* we can use r0-r3, since this is called only for incoming args on the stack */
221 if (size > sizeof (gpointer) * 4) {
222 guint8 *start_loop;
223 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
224 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
225 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
226 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
227 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
228 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
229 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
230 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
231 ARM_B_COND (code, ARMCOND_NE, 0);
232 arm_patch (code - 4, start_loop);
233 return code;
234 }
235 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
236 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
237 while (size >= 4) {
238 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
239 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
240 doffset += 4;
241 soffset += 4;
242 size -= 4;
243 }
244 } else if (size) {
245 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
246 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
247 doffset = soffset = 0;
248 while (size >= 4) {
249 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
250 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
251 doffset += 4;
252 soffset += 4;
253 size -= 4;
254 }
255 }
256 g_assert (size == 0);
257 return code;
258 }
259
260 static guint8*
261 emit_call_reg (guint8 *code, int reg)
262 {
263 if (v5_supported) {
264 ARM_BLX_REG (code, reg);
265 } else {
266 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
267 if (thumb_supported)
268 ARM_BX (code, reg);
269 else
270 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
271 }
272 return code;
273 }
274
275 static guint8*
276 emit_call_seq (MonoCompile *cfg, guint8 *code)
277 {
278 if (cfg->method->dynamic) {
279 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
280 ARM_B (code, 0);
281 *(gpointer*)code = NULL;
282 code += 4;
283 code = emit_call_reg (code, ARMREG_IP);
284 } else {
285 ARM_BL (code, 0);
286 }
287 return code;
288 }
289
290 static guint8*
291 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
292 {
293 switch (ins->opcode) {
294 case OP_FCALL:
295 case OP_FCALL_REG:
296 case OP_FCALL_MEMBASE:
297 if (IS_FPA) {
298 if (ins->dreg != ARM_FPA_F0)
299 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
300 } else if (IS_VFP) {
301 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
302 ARM_FMSR (code, ins->dreg, ARMREG_R0);
303 ARM_CVTS (code, ins->dreg, ins->dreg);
304 } else {
305 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
306 }
307 }
308 break;
309 }
310
311 return code;
312 }
313
314 /*
315 * emit_save_lmf:
316 *
317 * Emit code to push an LMF structure on the LMF stack.
318 * On arm, this is intermixed with the initialization of other fields of the structure.
319 */
320 static guint8*
321 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
322 {
323 gboolean get_lmf_fast = FALSE;
324 int i;
325
326 #ifdef HAVE_AEABI_READ_TP
327 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
328
329 if (lmf_addr_tls_offset != -1) {
330 get_lmf_fast = TRUE;
331
332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
333 (gpointer)"__aeabi_read_tp");
334 code = emit_call_seq (cfg, code);
335
336 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
337 get_lmf_fast = TRUE;
338 }
339 #endif
340 if (!get_lmf_fast) {
341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
342 (gpointer)"mono_get_lmf_addr");
343 code = emit_call_seq (cfg, code);
344 }
345 /* we build the MonoLMF structure on the stack - see mini-arm.h */
346 /* lmf_offset is the offset from the previous stack pointer,
347 * alloc_size is the total stack space allocated, so the offset
348 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
349 * The pointer to the struct is put in r1 (new_lmf).
350 * ip is used as scratch
351 * The callee-saved registers are already in the MonoLMF structure
352 */
353 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
354 /* r0 is the result from mono_get_lmf_addr () */
355 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
356 /* new_lmf->previous_lmf = *lmf_addr */
357 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
358 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
359 /* *(lmf_addr) = r1 */
360 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
361 /* Skip method (only needed for trampoline LMF frames) */
362 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
363 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
364 /* save the current IP */
365 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
366 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
367
368 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
369 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
370
371 return code;
372 }
373
374 /*
375 * emit_save_lmf:
376 *
377 * Emit code to pop an LMF structure from the LMF stack.
378 */
379 static guint8*
380 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
381 {
382 int basereg, offset;
383
384 if (lmf_offset < 32) {
385 basereg = cfg->frame_reg;
386 offset = lmf_offset;
387 } else {
388 basereg = ARMREG_R2;
389 offset = 0;
390 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
391 }
392
393 /* ip = previous_lmf */
394 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
395 /* lr = lmf_addr */
396 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
397 /* *(lmf_addr) = previous_lmf */
398 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
399
400 return code;
401 }
402
403 #endif /* #ifndef DISABLE_JIT */
404
405 /*
406 * mono_arch_get_argument_info:
407 * @csig: a method signature
408 * @param_count: the number of parameters to consider
409 * @arg_info: an array to store the result infos
410 *
411 * Gathers information on parameters such as size, alignment and
412 * padding. arg_info should be large enought to hold param_count + 1 entries.
413 *
414 * Returns the size of the activation frame.
415 */
416 int
417 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
418 {
419 int k, frame_size = 0;
420 guint32 size, align, pad;
421 int offset = 8;
422 MonoType *t;
423
424 t = mini_type_get_underlying_type (gsctx, csig->ret);
425 if (MONO_TYPE_ISSTRUCT (t)) {
426 frame_size += sizeof (gpointer);
427 offset += 4;
428 }
429
430 arg_info [0].offset = offset;
431
432 if (csig->hasthis) {
433 frame_size += sizeof (gpointer);
434 offset += 4;
435 }
436
437 arg_info [0].size = frame_size;
438
439 for (k = 0; k < param_count; k++) {
440 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
441
442 /* ignore alignment for now */
443 align = 1;
444
445 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
446 arg_info [k].pad = pad;
447 frame_size += size;
448 arg_info [k + 1].pad = 0;
449 arg_info [k + 1].size = size;
450 offset += pad;
451 arg_info [k + 1].offset = offset;
452 offset += size;
453 }
454
455 align = MONO_ARCH_FRAME_ALIGNMENT;
456 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
457 arg_info [k].pad = pad;
458
459 return frame_size;
460 }
461
462 #define MAX_ARCH_DELEGATE_PARAMS 3
463
464 static gpointer
465 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
466 {
467 guint8 *code, *start;
468
469 if (has_target) {
470 start = code = mono_global_codeman_reserve (12);
471
472 /* Replace the this argument with the target */
473 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
474 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
475 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
476
477 g_assert ((code - start) <= 12);
478
479 mono_arch_flush_icache (start, 12);
480 } else {
481 int size, i;
482
483 size = 8 + param_count * 4;
484 start = code = mono_global_codeman_reserve (size);
485
486 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
487 /* slide down the arguments */
488 for (i = 0; i < param_count; ++i) {
489 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
490 }
491 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
492
493 g_assert ((code - start) <= size);
494
495 mono_arch_flush_icache (start, size);
496 }
497
498 if (code_size)
499 *code_size = code - start;
500
501 return start;
502 }
503
504 /*
505 * mono_arch_get_delegate_invoke_impls:
506 *
507 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
508 * trampolines.
509 */
510 GSList*
511 mono_arch_get_delegate_invoke_impls (void)
512 {
513 GSList *res = NULL;
514 guint8 *code;
515 guint32 code_len;
516 int i;
517
518 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
519 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
520
521 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
522 code = get_delegate_invoke_impl (FALSE, i, &code_len);
523 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
524 }
525
526 return res;
527 }
528
529 gpointer
530 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
531 {
532 guint8 *code, *start;
533
534 /* FIXME: Support more cases */
535 if (MONO_TYPE_ISSTRUCT (sig->ret))
536 return NULL;
537
538 if (has_target) {
539 static guint8* cached = NULL;
540 mono_mini_arch_lock ();
541 if (cached) {
542 mono_mini_arch_unlock ();
543 return cached;
544 }
545
546 if (mono_aot_only)
547 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
548 else
549 start = get_delegate_invoke_impl (TRUE, 0, NULL);
550 cached = start;
551 mono_mini_arch_unlock ();
552 return cached;
553 } else {
554 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
555 int i;
556
557 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
558 return NULL;
559 for (i = 0; i < sig->param_count; ++i)
560 if (!mono_is_regsize_var (sig->params [i]))
561 return NULL;
562
563 mono_mini_arch_lock ();
564 code = cache [sig->param_count];
565 if (code) {
566 mono_mini_arch_unlock ();
567 return code;
568 }
569
570 if (mono_aot_only) {
571 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
572 start = mono_aot_get_trampoline (name);
573 g_free (name);
574 } else {
575 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
576 }
577 cache [sig->param_count] = start;
578 mono_mini_arch_unlock ();
579 return start;
580 }
581
582 return NULL;
583 }
584
585 gpointer
586 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
587 {
588 return (gpointer)regs [ARMREG_R0];
589 }
590
591 /*
592 * Initialize the cpu to execute managed code.
593 */
594 void
595 mono_arch_cpu_init (void)
596 {
597 #if defined(__ARM_EABI__)
598 eabi_supported = TRUE;
599 #endif
600 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
601 i8_align = 4;
602 #else
603 i8_align = __alignof__ (gint64);
604 #endif
605 }
606
607 static gpointer
608 create_function_wrapper (gpointer function)
609 {
610 guint8 *start, *code;
611
612 start = code = mono_global_codeman_reserve (96);
613
614 /*
615 * Construct the MonoContext structure on the stack.
616 */
617
618 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
619
620 /* save ip, lr and pc into their correspodings ctx.regs slots. */
621 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
622 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
623 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
624
625 /* save r0..r10 and fp */
626 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
627 ARM_STM (code, ARMREG_IP, 0x0fff);
628
629 /* now we can update fp. */
630 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
631
632 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
633 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
634 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
635 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
636
637 /* make ctx.eip hold the address of the call. */
638 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
639 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
640
641 /* r0 now points to the MonoContext */
642 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
643
644 /* call */
645 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
646 ARM_B (code, 0);
647 *(gpointer*)code = function;
648 code += 4;
649 ARM_BLX_REG (code, ARMREG_IP);
650
651 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
652 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
653 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
654 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
655
656 /* make ip point to the regs array, then restore everything, including pc. */
657 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
658 ARM_LDM (code, ARMREG_IP, 0xffff);
659
660 mono_arch_flush_icache (start, code - start);
661
662 return start;
663 }
664
665 /*
666 * Initialize architecture specific code.
667 */
668 void
669 mono_arch_init (void)
670 {
671 InitializeCriticalSection (&mini_arch_mutex);
672
673 if (mini_get_debug_options ()->soft_breakpoints) {
674 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
675 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
676 } else {
677 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
678 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
679 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
680 }
681
682 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
683 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
684 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
685 #ifdef MONOTOUCH
686 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
687 #endif
688
689 #ifdef ARM_FPU_FPA
690 arm_fpu = MONO_ARM_FPU_FPA;
691 #elif defined(ARM_FPU_VFP_HARD)
692 arm_fpu = MONO_ARM_FPU_VFP_HARD;
693 #elif defined(ARM_FPU_VFP)
694 arm_fpu = MONO_ARM_FPU_VFP;
695 #else
696 arm_fpu = MONO_ARM_FPU_NONE;
697 #endif
698 }
699
700 /*
701 * Cleanup architecture specific code.
702 */
703 void
704 mono_arch_cleanup (void)
705 {
706 }
707
708 /*
709 * This function returns the optimizations supported on this cpu.
710 */
711 guint32
712 mono_arch_cpu_optimizations (guint32 *exclude_mask)
713 {
714 guint32 opts = 0;
715 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
716 if (cpu_arch != NULL) {
717 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
718 if (strncmp (cpu_arch, "armv", 4) == 0) {
719 v5_supported = cpu_arch [4] >= '5';
720 v6_supported = cpu_arch [4] >= '6';
721 v7_supported = cpu_arch [4] >= '7';
722 }
723 } else {
724 #if __APPLE__
725 thumb_supported = TRUE;
726 v5_supported = TRUE;
727 darwin = TRUE;
728 iphone_abi = TRUE;
729 #else
730 char buf [512];
731 char *line;
732 FILE *file = fopen ("/proc/cpuinfo", "r");
733 if (file) {
734 while ((line = fgets (buf, 512, file))) {
735 if (strncmp (line, "Processor", 9) == 0) {
736 char *ver = strstr (line, "(v");
737 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
738 v5_supported = TRUE;
739 if (ver && (ver [2] == '6' || ver [2] == '7'))
740 v6_supported = TRUE;
741 if (ver && (ver [2] == '7'))
742 v7_supported = TRUE;
743 continue;
744 }
745 if (strncmp (line, "Features", 8) == 0) {
746 char *th = strstr (line, "thumb");
747 if (th) {
748 thumb_supported = TRUE;
749 if (v5_supported)
750 break;
751 }
752 continue;
753 }
754 }
755 fclose (file);
756 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
757 }
758 #endif
759 }
760
761 /* no arm-specific optimizations yet */
762 *exclude_mask = 0;
763 return opts;
764 }
765
766 /*
767 * This function test for all SIMD functions supported.
768 *
769 * Returns a bitmask corresponding to all supported versions.
770 *
771 */
772 guint32
773 mono_arch_cpu_enumerate_simd_versions (void)
774 {
775 /* SIMD is currently unimplemented */
776 return 0;
777 }
778
779
780 #ifndef DISABLE_JIT
781
782 static gboolean
783 is_regsize_var (MonoGenericSharingContext *gsctx, MonoType *t) {
784 if (t->byref)
785 return TRUE;
786 t = mini_type_get_underlying_type (gsctx, t);
787 switch (t->type) {
788 case MONO_TYPE_I4:
789 case MONO_TYPE_U4:
790 case MONO_TYPE_I:
791 case MONO_TYPE_U:
792 case MONO_TYPE_PTR:
793 case MONO_TYPE_FNPTR:
794 return TRUE;
795 case MONO_TYPE_OBJECT:
796 case MONO_TYPE_STRING:
797 case MONO_TYPE_CLASS:
798 case MONO_TYPE_SZARRAY:
799 case MONO_TYPE_ARRAY:
800 return TRUE;
801 case MONO_TYPE_GENERICINST:
802 if (!mono_type_generic_inst_is_valuetype (t))
803 return TRUE;
804 return FALSE;
805 case MONO_TYPE_VALUETYPE:
806 return FALSE;
807 }
808 return FALSE;
809 }
810
811 GList *
812 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
813 {
814 GList *vars = NULL;
815 int i;
816
817 for (i = 0; i < cfg->num_varinfo; i++) {
818 MonoInst *ins = cfg->varinfo [i];
819 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
820
821 /* unused vars */
822 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
823 continue;
824
825 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
826 continue;
827
828 /* we can only allocate 32 bit values */
829 if (is_regsize_var (cfg->generic_sharing_context, ins->inst_vtype)) {
830 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
831 g_assert (i == vmv->idx);
832 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
833 }
834 }
835
836 return vars;
837 }
838
839 #define USE_EXTRA_TEMPS 0
840
841 GList *
842 mono_arch_get_global_int_regs (MonoCompile *cfg)
843 {
844 GList *regs = NULL;
845
846 mono_arch_compute_omit_fp (cfg);
847
848 /*
849 * FIXME: Interface calls might go through a static rgctx trampoline which
850 * sets V5, but it doesn't save it, so we need to save it ourselves, and
851 * avoid using it.
852 */
853 if (cfg->flags & MONO_CFG_HAS_CALLS)
854 cfg->uses_rgctx_reg = TRUE;
855
856 if (cfg->arch.omit_fp)
857 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
858 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
860 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
861 if (darwin)
862 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
863 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
864 else
865 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
866 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
867 /* V5 is reserved for passing the vtable/rgctx/IMT method */
868 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
869 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
870 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
871
872 return regs;
873 }
874
875 /*
876 * mono_arch_regalloc_cost:
877 *
878 * Return the cost, in number of memory references, of the action of
879 * allocating the variable VMV into a register during global register
880 * allocation.
881 */
882 guint32
883 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
884 {
885 /* FIXME: */
886 return 2;
887 }
888
889 #endif /* #ifndef DISABLE_JIT */
890
891 #ifndef __GNUC_PREREQ
892 #define __GNUC_PREREQ(maj, min) (0)
893 #endif
894
895 void
896 mono_arch_flush_icache (guint8 *code, gint size)
897 {
898 #ifdef MONO_CROSS_COMPILE
899 #elif __APPLE__
900 sys_icache_invalidate (code, size);
901 #elif __GNUC_PREREQ(4, 1)
902 __clear_cache (code, code + size);
903 #elif defined(PLATFORM_ANDROID)
904 const int syscall = 0xf0002;
905 __asm __volatile (
906 "mov r0, %0\n"
907 "mov r1, %1\n"
908 "mov r7, %2\n"
909 "mov r2, #0x0\n"
910 "svc 0x00000000\n"
911 :
912 : "r" (code), "r" (code + size), "r" (syscall)
913 : "r0", "r1", "r7", "r2"
914 );
915 #else
916 __asm __volatile ("mov r0, %0\n"
917 "mov r1, %1\n"
918 "mov r2, %2\n"
919 "swi 0x9f0002 @ sys_cacheflush"
920 : /* no outputs */
921 : "r" (code), "r" (code + size), "r" (0)
922 : "r0", "r1", "r3" );
923 #endif
924 }
925
926 typedef enum {
927 RegTypeNone,
928 RegTypeGeneral,
929 RegTypeIRegPair,
930 RegTypeBase,
931 RegTypeBaseGen,
932 RegTypeFP,
933 RegTypeStructByVal,
934 RegTypeStructByAddr
935 } ArgStorage;
936
937 typedef struct {
938 gint32 offset;
939 guint16 vtsize; /* in param area */
940 guint8 reg;
941 ArgStorage storage;
942 gint32 struct_size;
943 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
944 } ArgInfo;
945
946 typedef struct {
947 int nargs;
948 guint32 stack_usage;
949 gboolean vtype_retaddr;
950 /* The index of the vret arg in the argument list */
951 int vret_arg_index;
952 ArgInfo ret;
953 ArgInfo sig_cookie;
954 ArgInfo args [1];
955 } CallInfo;
956
957 #define DEBUG(a)
958
959 #ifndef __GNUC__
960 /*#define __alignof__(a) sizeof(a)*/
961 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
962 #endif
963
964 #define PARAM_REGS 4
965
966 static void inline
967 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
968 {
969 if (simple) {
970 if (*gr > ARMREG_R3) {
971 ainfo->offset = *stack_size;
972 ainfo->reg = ARMREG_SP; /* in the caller */
973 ainfo->storage = RegTypeBase;
974 *stack_size += 4;
975 } else {
976 ainfo->storage = RegTypeGeneral;
977 ainfo->reg = *gr;
978 }
979 } else {
980 gboolean split;
981
982 if (eabi_supported)
983 split = i8_align == 4;
984 else
985 split = TRUE;
986
987 if (*gr == ARMREG_R3 && split) {
988 /* first word in r3 and the second on the stack */
989 ainfo->offset = *stack_size;
990 ainfo->reg = ARMREG_SP; /* in the caller */
991 ainfo->storage = RegTypeBaseGen;
992 *stack_size += 4;
993 } else if (*gr >= ARMREG_R3) {
994 if (eabi_supported) {
995 /* darwin aligns longs to 4 byte only */
996 if (i8_align == 8) {
997 *stack_size += 7;
998 *stack_size &= ~7;
999 }
1000 }
1001 ainfo->offset = *stack_size;
1002 ainfo->reg = ARMREG_SP; /* in the caller */
1003 ainfo->storage = RegTypeBase;
1004 *stack_size += 8;
1005 } else {
1006 if (eabi_supported) {
1007 if (i8_align == 8 && ((*gr) & 1))
1008 (*gr) ++;
1009 }
1010 ainfo->storage = RegTypeIRegPair;
1011 ainfo->reg = *gr;
1012 }
1013 (*gr) ++;
1014 }
1015 (*gr) ++;
1016 }
1017
1018 static CallInfo*
1019 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1020 {
1021 guint i, gr, pstart;
1022 int n = sig->hasthis + sig->param_count;
1023 MonoType *simpletype;
1024 guint32 stack_size = 0;
1025 CallInfo *cinfo;
1026 gboolean is_pinvoke = sig->pinvoke;
1027 MonoType *t;
1028
1029 if (mp)
1030 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1031 else
1032 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1033
1034 cinfo->nargs = n;
1035 gr = ARMREG_R0;
1036
1037 /* FIXME: handle returning a struct */
1038 t = mini_type_get_underlying_type (gsctx, sig->ret);
1039 if (MONO_TYPE_ISSTRUCT (t)) {
1040 guint32 align;
1041
1042 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer)) {
1043 cinfo->ret.storage = RegTypeStructByVal;
1044 } else {
1045 cinfo->vtype_retaddr = TRUE;
1046 }
1047 }
1048
1049 pstart = 0;
1050 n = 0;
1051 /*
1052 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1053 * the first argument, allowing 'this' to be always passed in the first arg reg.
1054 * Also do this if the first argument is a reference type, since virtual calls
1055 * are sometimes made using calli without sig->hasthis set, like in the delegate
1056 * invoke wrappers.
1057 */
1058 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1059 if (sig->hasthis) {
1060 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1061 } else {
1062 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1063 pstart = 1;
1064 }
1065 n ++;
1066 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1067 cinfo->vret_arg_index = 1;
1068 } else {
1069 /* this */
1070 if (sig->hasthis) {
1071 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1072 n ++;
1073 }
1074
1075 if (cinfo->vtype_retaddr)
1076 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1077 }
1078
1079 DEBUG(printf("params: %d\n", sig->param_count));
1080 for (i = pstart; i < sig->param_count; ++i) {
1081 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1082 /* Prevent implicit arguments and sig_cookie from
1083 being passed in registers */
1084 gr = ARMREG_R3 + 1;
1085 /* Emit the signature cookie just before the implicit arguments */
1086 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1087 }
1088 DEBUG(printf("param %d: ", i));
1089 if (sig->params [i]->byref) {
1090 DEBUG(printf("byref\n"));
1091 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1092 n++;
1093 continue;
1094 }
1095 simpletype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1096 switch (simpletype->type) {
1097 case MONO_TYPE_BOOLEAN:
1098 case MONO_TYPE_I1:
1099 case MONO_TYPE_U1:
1100 cinfo->args [n].size = 1;
1101 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1102 n++;
1103 break;
1104 case MONO_TYPE_CHAR:
1105 case MONO_TYPE_I2:
1106 case MONO_TYPE_U2:
1107 cinfo->args [n].size = 2;
1108 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1109 n++;
1110 break;
1111 case MONO_TYPE_I4:
1112 case MONO_TYPE_U4:
1113 cinfo->args [n].size = 4;
1114 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1115 n++;
1116 break;
1117 case MONO_TYPE_I:
1118 case MONO_TYPE_U:
1119 case MONO_TYPE_PTR:
1120 case MONO_TYPE_FNPTR:
1121 case MONO_TYPE_CLASS:
1122 case MONO_TYPE_OBJECT:
1123 case MONO_TYPE_STRING:
1124 case MONO_TYPE_SZARRAY:
1125 case MONO_TYPE_ARRAY:
1126 case MONO_TYPE_R4:
1127 cinfo->args [n].size = sizeof (gpointer);
1128 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1129 n++;
1130 break;
1131 case MONO_TYPE_GENERICINST:
1132 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1133 cinfo->args [n].size = sizeof (gpointer);
1134 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1135 n++;
1136 break;
1137 }
1138 /* Fall through */
1139 case MONO_TYPE_TYPEDBYREF:
1140 case MONO_TYPE_VALUETYPE: {
1141 gint size;
1142 int align_size;
1143 int nwords;
1144 guint32 align;
1145
1146 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1147 size = sizeof (MonoTypedRef);
1148 align = sizeof (gpointer);
1149 } else {
1150 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1151 if (is_pinvoke)
1152 size = mono_class_native_size (klass, &align);
1153 else
1154 size = mini_type_stack_size_full (gsctx, simpletype, &align, FALSE);
1155 }
1156 DEBUG(printf ("load %d bytes struct\n", size));
1157 align_size = size;
1158 nwords = 0;
1159 align_size += (sizeof (gpointer) - 1);
1160 align_size &= ~(sizeof (gpointer) - 1);
1161 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1162 cinfo->args [n].storage = RegTypeStructByVal;
1163 cinfo->args [n].struct_size = size;
1164 /* FIXME: align stack_size if needed */
1165 if (eabi_supported) {
1166 if (align >= 8 && (gr & 1))
1167 gr ++;
1168 }
1169 if (gr > ARMREG_R3) {
1170 cinfo->args [n].size = 0;
1171 cinfo->args [n].vtsize = nwords;
1172 } else {
1173 int rest = ARMREG_R3 - gr + 1;
1174 int n_in_regs = rest >= nwords? nwords: rest;
1175
1176 cinfo->args [n].size = n_in_regs;
1177 cinfo->args [n].vtsize = nwords - n_in_regs;
1178 cinfo->args [n].reg = gr;
1179 gr += n_in_regs;
1180 nwords -= n_in_regs;
1181 }
1182 cinfo->args [n].offset = stack_size;
1183 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1184 stack_size += nwords * sizeof (gpointer);
1185 n++;
1186 break;
1187 }
1188 case MONO_TYPE_U8:
1189 case MONO_TYPE_I8:
1190 case MONO_TYPE_R8:
1191 cinfo->args [n].size = 8;
1192 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1193 n++;
1194 break;
1195 default:
1196 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1197 }
1198 }
1199
1200 /* Handle the case where there are no implicit arguments */
1201 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1202 /* Prevent implicit arguments and sig_cookie from
1203 being passed in registers */
1204 gr = ARMREG_R3 + 1;
1205 /* Emit the signature cookie just before the implicit arguments */
1206 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1207 }
1208
1209 {
1210 simpletype = mini_type_get_underlying_type (gsctx, sig->ret);
1211 switch (simpletype->type) {
1212 case MONO_TYPE_BOOLEAN:
1213 case MONO_TYPE_I1:
1214 case MONO_TYPE_U1:
1215 case MONO_TYPE_I2:
1216 case MONO_TYPE_U2:
1217 case MONO_TYPE_CHAR:
1218 case MONO_TYPE_I4:
1219 case MONO_TYPE_U4:
1220 case MONO_TYPE_I:
1221 case MONO_TYPE_U:
1222 case MONO_TYPE_PTR:
1223 case MONO_TYPE_FNPTR:
1224 case MONO_TYPE_CLASS:
1225 case MONO_TYPE_OBJECT:
1226 case MONO_TYPE_SZARRAY:
1227 case MONO_TYPE_ARRAY:
1228 case MONO_TYPE_STRING:
1229 cinfo->ret.storage = RegTypeGeneral;
1230 cinfo->ret.reg = ARMREG_R0;
1231 break;
1232 case MONO_TYPE_U8:
1233 case MONO_TYPE_I8:
1234 cinfo->ret.storage = RegTypeIRegPair;
1235 cinfo->ret.reg = ARMREG_R0;
1236 break;
1237 case MONO_TYPE_R4:
1238 case MONO_TYPE_R8:
1239 cinfo->ret.storage = RegTypeFP;
1240 cinfo->ret.reg = ARMREG_R0;
1241 /* FIXME: cinfo->ret.reg = ???;
1242 cinfo->ret.storage = RegTypeFP;*/
1243 break;
1244 case MONO_TYPE_GENERICINST:
1245 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1246 cinfo->ret.storage = RegTypeGeneral;
1247 cinfo->ret.reg = ARMREG_R0;
1248 break;
1249 }
1250 /* Fall through */
1251 case MONO_TYPE_VALUETYPE:
1252 case MONO_TYPE_TYPEDBYREF:
1253 if (cinfo->ret.storage != RegTypeStructByVal)
1254 cinfo->ret.storage = RegTypeStructByAddr;
1255 break;
1256 case MONO_TYPE_VOID:
1257 break;
1258 default:
1259 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1260 }
1261 }
1262
1263 /* align stack size to 8 */
1264 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1265 stack_size = (stack_size + 7) & ~7;
1266
1267 cinfo->stack_usage = stack_size;
1268 return cinfo;
1269 }
1270
1271 #ifndef DISABLE_JIT
1272
1273 static gboolean
1274 debug_omit_fp (void)
1275 {
1276 #if 0
1277 return mono_debug_count ();
1278 #else
1279 return TRUE;
1280 #endif
1281 }
1282
1283 /**
1284 * mono_arch_compute_omit_fp:
1285 *
1286 * Determine whenever the frame pointer can be eliminated.
1287 */
1288 static void
1289 mono_arch_compute_omit_fp (MonoCompile *cfg)
1290 {
1291 MonoMethodSignature *sig;
1292 MonoMethodHeader *header;
1293 int i, locals_size;
1294 CallInfo *cinfo;
1295
1296 if (cfg->arch.omit_fp_computed)
1297 return;
1298
1299 header = cfg->header;
1300
1301 sig = mono_method_signature (cfg->method);
1302
1303 if (!cfg->arch.cinfo)
1304 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1305 cinfo = cfg->arch.cinfo;
1306
1307 /*
1308 * FIXME: Remove some of the restrictions.
1309 */
1310 cfg->arch.omit_fp = TRUE;
1311 cfg->arch.omit_fp_computed = TRUE;
1312
1313 if (cfg->disable_omit_fp)
1314 cfg->arch.omit_fp = FALSE;
1315 if (!debug_omit_fp ())
1316 cfg->arch.omit_fp = FALSE;
1317 /*
1318 if (cfg->method->save_lmf)
1319 cfg->arch.omit_fp = FALSE;
1320 */
1321 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1322 cfg->arch.omit_fp = FALSE;
1323 if (header->num_clauses)
1324 cfg->arch.omit_fp = FALSE;
1325 if (cfg->param_area)
1326 cfg->arch.omit_fp = FALSE;
1327 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1328 cfg->arch.omit_fp = FALSE;
1329 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1330 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1331 cfg->arch.omit_fp = FALSE;
1332 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1333 ArgInfo *ainfo = &cinfo->args [i];
1334
1335 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1336 /*
1337 * The stack offset can only be determined when the frame
1338 * size is known.
1339 */
1340 cfg->arch.omit_fp = FALSE;
1341 }
1342 }
1343
1344 locals_size = 0;
1345 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1346 MonoInst *ins = cfg->varinfo [i];
1347 int ialign;
1348
1349 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1350 }
1351 }
1352
1353 /*
1354 * Set var information according to the calling convention. arm version.
1355 * The locals var stuff should most likely be split in another method.
1356 */
1357 void
1358 mono_arch_allocate_vars (MonoCompile *cfg)
1359 {
1360 MonoMethodSignature *sig;
1361 MonoMethodHeader *header;
1362 MonoInst *ins;
1363 int i, offset, size, align, curinst;
1364 CallInfo *cinfo;
1365 guint32 ualign;
1366
1367 sig = mono_method_signature (cfg->method);
1368
1369 if (!cfg->arch.cinfo)
1370 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1371 cinfo = cfg->arch.cinfo;
1372
1373 mono_arch_compute_omit_fp (cfg);
1374
1375 if (cfg->arch.omit_fp)
1376 cfg->frame_reg = ARMREG_SP;
1377 else
1378 cfg->frame_reg = ARMREG_FP;
1379
1380 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1381
1382 /* allow room for the vararg method args: void* and long/double */
1383 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1384 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1385
1386 header = cfg->header;
1387
1388 /* See mono_arch_get_global_int_regs () */
1389 if (cfg->flags & MONO_CFG_HAS_CALLS)
1390 cfg->uses_rgctx_reg = TRUE;
1391
1392 if (cfg->frame_reg != ARMREG_SP)
1393 cfg->used_int_regs |= 1 << cfg->frame_reg;
1394
1395 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1396 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1397 cfg->used_int_regs |= (1 << ARMREG_V5);
1398
1399 offset = 0;
1400 curinst = 0;
1401 if (!MONO_TYPE_ISSTRUCT (sig->ret) && !cinfo->vtype_retaddr) {
1402 if (sig->ret->type != MONO_TYPE_VOID) {
1403 cfg->ret->opcode = OP_REGVAR;
1404 cfg->ret->inst_c0 = ARMREG_R0;
1405 }
1406 }
1407 /* local vars are at a positive offset from the stack pointer */
1408 /*
1409 * also note that if the function uses alloca, we use FP
1410 * to point at the local variables.
1411 */
1412 offset = 0; /* linkage area */
1413 /* align the offset to 16 bytes: not sure this is needed here */
1414 //offset += 8 - 1;
1415 //offset &= ~(8 - 1);
1416
1417 /* add parameter area size for called functions */
1418 offset += cfg->param_area;
1419 offset += 8 - 1;
1420 offset &= ~(8 - 1);
1421 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1422 offset += 8;
1423
1424 /* allow room to save the return value */
1425 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1426 offset += 8;
1427
1428 /* the MonoLMF structure is stored just below the stack pointer */
1429 if (cinfo->ret.storage == RegTypeStructByVal) {
1430 cfg->ret->opcode = OP_REGOFFSET;
1431 cfg->ret->inst_basereg = cfg->frame_reg;
1432 offset += sizeof (gpointer) - 1;
1433 offset &= ~(sizeof (gpointer) - 1);
1434 cfg->ret->inst_offset = - offset;
1435 offset += sizeof(gpointer);
1436 } else if (cinfo->vtype_retaddr) {
1437 ins = cfg->vret_addr;
1438 offset += sizeof(gpointer) - 1;
1439 offset &= ~(sizeof(gpointer) - 1);
1440 ins->inst_offset = offset;
1441 ins->opcode = OP_REGOFFSET;
1442 ins->inst_basereg = cfg->frame_reg;
1443 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1444 printf ("vret_addr =");
1445 mono_print_ins (cfg->vret_addr);
1446 }
1447 offset += sizeof(gpointer);
1448 }
1449
1450 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1451 if (cfg->arch.seq_point_info_var) {
1452 MonoInst *ins;
1453
1454 ins = cfg->arch.seq_point_info_var;
1455
1456 size = 4;
1457 align = 4;
1458 offset += align - 1;
1459 offset &= ~(align - 1);
1460 ins->opcode = OP_REGOFFSET;
1461 ins->inst_basereg = cfg->frame_reg;
1462 ins->inst_offset = offset;
1463 offset += size;
1464
1465 ins = cfg->arch.ss_trigger_page_var;
1466 size = 4;
1467 align = 4;
1468 offset += align - 1;
1469 offset &= ~(align - 1);
1470 ins->opcode = OP_REGOFFSET;
1471 ins->inst_basereg = cfg->frame_reg;
1472 ins->inst_offset = offset;
1473 offset += size;
1474 }
1475
1476 if (cfg->arch.seq_point_read_var) {
1477 MonoInst *ins;
1478
1479 ins = cfg->arch.seq_point_read_var;
1480
1481 size = 4;
1482 align = 4;
1483 offset += align - 1;
1484 offset &= ~(align - 1);
1485 ins->opcode = OP_REGOFFSET;
1486 ins->inst_basereg = cfg->frame_reg;
1487 ins->inst_offset = offset;
1488 offset += size;
1489
1490 ins = cfg->arch.seq_point_ss_method_var;
1491 size = 4;
1492 align = 4;
1493 offset += align - 1;
1494 offset &= ~(align - 1);
1495 ins->opcode = OP_REGOFFSET;
1496 ins->inst_basereg = cfg->frame_reg;
1497 ins->inst_offset = offset;
1498 offset += size;
1499
1500 ins = cfg->arch.seq_point_bp_method_var;
1501 size = 4;
1502 align = 4;
1503 offset += align - 1;
1504 offset &= ~(align - 1);
1505 ins->opcode = OP_REGOFFSET;
1506 ins->inst_basereg = cfg->frame_reg;
1507 ins->inst_offset = offset;
1508 offset += size;
1509 }
1510
1511 cfg->locals_min_stack_offset = offset;
1512
1513 curinst = cfg->locals_start;
1514 for (i = curinst; i < cfg->num_varinfo; ++i) {
1515 MonoType *t;
1516
1517 ins = cfg->varinfo [i];
1518 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1519 continue;
1520
1521 t = ins->inst_vtype;
1522 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (cfg, t))
1523 t = mini_get_gsharedvt_alloc_type_for_type (cfg, t);
1524
1525 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1526 * pinvoke wrappers when they call functions returning structure */
1527 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1528 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1529 align = ualign;
1530 }
1531 else
1532 size = mono_type_size (t, &align);
1533
1534 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1535 * since it loads/stores misaligned words, which don't do the right thing.
1536 */
1537 if (align < 4 && size >= 4)
1538 align = 4;
1539 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1540 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1541 offset += align - 1;
1542 offset &= ~(align - 1);
1543 ins->opcode = OP_REGOFFSET;
1544 ins->inst_offset = offset;
1545 ins->inst_basereg = cfg->frame_reg;
1546 offset += size;
1547 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1548 }
1549
1550 cfg->locals_max_stack_offset = offset;
1551
1552 curinst = 0;
1553 if (sig->hasthis) {
1554 ins = cfg->args [curinst];
1555 if (ins->opcode != OP_REGVAR) {
1556 ins->opcode = OP_REGOFFSET;
1557 ins->inst_basereg = cfg->frame_reg;
1558 offset += sizeof (gpointer) - 1;
1559 offset &= ~(sizeof (gpointer) - 1);
1560 ins->inst_offset = offset;
1561 offset += sizeof (gpointer);
1562 }
1563 curinst++;
1564 }
1565
1566 if (sig->call_convention == MONO_CALL_VARARG) {
1567 size = 4;
1568 align = 4;
1569
1570 /* Allocate a local slot to hold the sig cookie address */
1571 offset += align - 1;
1572 offset &= ~(align - 1);
1573 cfg->sig_cookie = offset;
1574 offset += size;
1575 }
1576
1577 for (i = 0; i < sig->param_count; ++i) {
1578 ins = cfg->args [curinst];
1579
1580 if (ins->opcode != OP_REGVAR) {
1581 ins->opcode = OP_REGOFFSET;
1582 ins->inst_basereg = cfg->frame_reg;
1583 size = mini_type_stack_size_full (cfg->generic_sharing_context, sig->params [i], &ualign, sig->pinvoke);
1584 align = ualign;
1585 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1586 * since it loads/stores misaligned words, which don't do the right thing.
1587 */
1588 if (align < 4 && size >= 4)
1589 align = 4;
1590 /* The code in the prolog () stores words when storing vtypes received in a register */
1591 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1592 align = 4;
1593 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1594 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1595 offset += align - 1;
1596 offset &= ~(align - 1);
1597 ins->inst_offset = offset;
1598 offset += size;
1599 }
1600 curinst++;
1601 }
1602
1603 /* align the offset to 8 bytes */
1604 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1605 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1606 offset += 8 - 1;
1607 offset &= ~(8 - 1);
1608
1609 /* change sign? */
1610 cfg->stack_offset = offset;
1611 }
1612
1613 void
1614 mono_arch_create_vars (MonoCompile *cfg)
1615 {
1616 MonoMethodSignature *sig;
1617 CallInfo *cinfo;
1618
1619 sig = mono_method_signature (cfg->method);
1620
1621 if (!cfg->arch.cinfo)
1622 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1623 cinfo = cfg->arch.cinfo;
1624
1625 if (cinfo->ret.storage == RegTypeStructByVal)
1626 cfg->ret_var_is_local = TRUE;
1627
1628 if (cinfo->vtype_retaddr) {
1629 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1630 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1631 printf ("vret_addr = ");
1632 mono_print_ins (cfg->vret_addr);
1633 }
1634 }
1635
1636 if (cfg->gen_seq_points) {
1637 if (cfg->soft_breakpoints) {
1638 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1639 ins->flags |= MONO_INST_VOLATILE;
1640 cfg->arch.seq_point_read_var = ins;
1641
1642 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1643 ins->flags |= MONO_INST_VOLATILE;
1644 cfg->arch.seq_point_ss_method_var = ins;
1645
1646 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1647 ins->flags |= MONO_INST_VOLATILE;
1648 cfg->arch.seq_point_bp_method_var = ins;
1649
1650 g_assert (!cfg->compile_aot);
1651 } else if (cfg->compile_aot) {
1652 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1653 ins->flags |= MONO_INST_VOLATILE;
1654 cfg->arch.seq_point_info_var = ins;
1655
1656 /* Allocate a separate variable for this to save 1 load per seq point */
1657 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1658 ins->flags |= MONO_INST_VOLATILE;
1659 cfg->arch.ss_trigger_page_var = ins;
1660 }
1661 }
1662 }
1663
1664 static void
1665 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1666 {
1667 MonoMethodSignature *tmp_sig;
1668 int sig_reg;
1669
1670 if (call->tail_call)
1671 NOT_IMPLEMENTED;
1672
1673 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1674
1675 /*
1676 * mono_ArgIterator_Setup assumes the signature cookie is
1677 * passed first and all the arguments which were before it are
1678 * passed on the stack after the signature. So compensate by
1679 * passing a different signature.
1680 */
1681 tmp_sig = mono_metadata_signature_dup (call->signature);
1682 tmp_sig->param_count -= call->signature->sentinelpos;
1683 tmp_sig->sentinelpos = 0;
1684 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1685
1686 sig_reg = mono_alloc_ireg (cfg);
1687 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1688
1689 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1690 }
1691
1692 #ifdef ENABLE_LLVM
1693 LLVMCallInfo*
1694 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1695 {
1696 int i, n;
1697 CallInfo *cinfo;
1698 ArgInfo *ainfo;
1699 LLVMCallInfo *linfo;
1700
1701 n = sig->param_count + sig->hasthis;
1702
1703 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1704
1705 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1706
1707 /*
1708 * LLVM always uses the native ABI while we use our own ABI, the
1709 * only difference is the handling of vtypes:
1710 * - we only pass/receive them in registers in some cases, and only
1711 * in 1 or 2 integer registers.
1712 */
1713 if (cinfo->vtype_retaddr) {
1714 /* Vtype returned using a hidden argument */
1715 linfo->ret.storage = LLVMArgVtypeRetAddr;
1716 linfo->vret_arg_index = cinfo->vret_arg_index;
1717 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1718 cfg->exception_message = g_strdup ("unknown ret conv");
1719 cfg->disable_llvm = TRUE;
1720 return linfo;
1721 }
1722
1723 for (i = 0; i < n; ++i) {
1724 ainfo = cinfo->args + i;
1725
1726 linfo->args [i].storage = LLVMArgNone;
1727
1728 switch (ainfo->storage) {
1729 case RegTypeGeneral:
1730 case RegTypeIRegPair:
1731 case RegTypeBase:
1732 linfo->args [i].storage = LLVMArgInIReg;
1733 break;
1734 case RegTypeStructByVal:
1735 // FIXME: Passing entirely on the stack or split reg/stack
1736 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1737 linfo->args [i].storage = LLVMArgVtypeInReg;
1738 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1739 if (ainfo->size == 2)
1740 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1741 else
1742 linfo->args [i].pair_storage [1] = LLVMArgNone;
1743 } else {
1744 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1745 cfg->disable_llvm = TRUE;
1746 }
1747 break;
1748 default:
1749 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1750 cfg->disable_llvm = TRUE;
1751 break;
1752 }
1753 }
1754
1755 return linfo;
1756 }
1757 #endif
1758
1759 void
1760 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1761 {
1762 MonoInst *in, *ins;
1763 MonoMethodSignature *sig;
1764 int i, n;
1765 CallInfo *cinfo;
1766
1767 sig = call->signature;
1768 n = sig->param_count + sig->hasthis;
1769
1770 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1771
1772 for (i = 0; i < n; ++i) {
1773 ArgInfo *ainfo = cinfo->args + i;
1774 MonoType *t;
1775
1776 if (i >= sig->hasthis)
1777 t = sig->params [i - sig->hasthis];
1778 else
1779 t = &mono_defaults.int_class->byval_arg;
1780 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1781
1782 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1783 /* Emit the signature cookie just before the implicit arguments */
1784 emit_sig_cookie (cfg, call, cinfo);
1785 }
1786
1787 in = call->args [i];
1788
1789 switch (ainfo->storage) {
1790 case RegTypeGeneral:
1791 case RegTypeIRegPair:
1792 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1793 MONO_INST_NEW (cfg, ins, OP_MOVE);
1794 ins->dreg = mono_alloc_ireg (cfg);
1795 ins->sreg1 = in->dreg + 1;
1796 MONO_ADD_INS (cfg->cbb, ins);
1797 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1798
1799 MONO_INST_NEW (cfg, ins, OP_MOVE);
1800 ins->dreg = mono_alloc_ireg (cfg);
1801 ins->sreg1 = in->dreg + 2;
1802 MONO_ADD_INS (cfg->cbb, ins);
1803 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1804 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1805 if (ainfo->size == 4) {
1806 if (IS_SOFT_FLOAT) {
1807 /* mono_emit_call_args () have already done the r8->r4 conversion */
1808 /* The converted value is in an int vreg */
1809 MONO_INST_NEW (cfg, ins, OP_MOVE);
1810 ins->dreg = mono_alloc_ireg (cfg);
1811 ins->sreg1 = in->dreg;
1812 MONO_ADD_INS (cfg->cbb, ins);
1813 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1814 } else {
1815 int creg;
1816
1817 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1818 creg = mono_alloc_ireg (cfg);
1819 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1820 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1821 }
1822 } else {
1823 if (IS_SOFT_FLOAT) {
1824 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1825 ins->dreg = mono_alloc_ireg (cfg);
1826 ins->sreg1 = in->dreg;
1827 MONO_ADD_INS (cfg->cbb, ins);
1828 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1829
1830 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1831 ins->dreg = mono_alloc_ireg (cfg);
1832 ins->sreg1 = in->dreg;
1833 MONO_ADD_INS (cfg->cbb, ins);
1834 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1835 } else {
1836 int creg;
1837
1838 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1839 creg = mono_alloc_ireg (cfg);
1840 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1841 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1842 creg = mono_alloc_ireg (cfg);
1843 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1844 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1845 }
1846 }
1847 cfg->flags |= MONO_CFG_HAS_FPOUT;
1848 } else {
1849 MONO_INST_NEW (cfg, ins, OP_MOVE);
1850 ins->dreg = mono_alloc_ireg (cfg);
1851 ins->sreg1 = in->dreg;
1852 MONO_ADD_INS (cfg->cbb, ins);
1853
1854 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1855 }
1856 break;
1857 case RegTypeStructByAddr:
1858 NOT_IMPLEMENTED;
1859 #if 0
1860 /* FIXME: where si the data allocated? */
1861 arg->backend.reg3 = ainfo->reg;
1862 call->used_iregs |= 1 << ainfo->reg;
1863 g_assert_not_reached ();
1864 #endif
1865 break;
1866 case RegTypeStructByVal:
1867 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1868 ins->opcode = OP_OUTARG_VT;
1869 ins->sreg1 = in->dreg;
1870 ins->klass = in->klass;
1871 ins->inst_p0 = call;
1872 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1873 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1874 mono_call_inst_add_outarg_vt (cfg, call, ins);
1875 MONO_ADD_INS (cfg->cbb, ins);
1876 break;
1877 case RegTypeBase:
1878 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1879 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1880 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1881 if (t->type == MONO_TYPE_R8) {
1882 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1883 } else {
1884 if (IS_SOFT_FLOAT)
1885 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1886 else
1887 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1888 }
1889 } else {
1890 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1891 }
1892 break;
1893 case RegTypeBaseGen:
1894 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1896 MONO_INST_NEW (cfg, ins, OP_MOVE);
1897 ins->dreg = mono_alloc_ireg (cfg);
1898 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1899 MONO_ADD_INS (cfg->cbb, ins);
1900 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1901 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1902 int creg;
1903
1904 /* This should work for soft-float as well */
1905
1906 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1907 creg = mono_alloc_ireg (cfg);
1908 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1909 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1910 creg = mono_alloc_ireg (cfg);
1911 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1912 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1913 cfg->flags |= MONO_CFG_HAS_FPOUT;
1914 } else {
1915 g_assert_not_reached ();
1916 }
1917 break;
1918 case RegTypeFP: {
1919 /* FIXME: */
1920 NOT_IMPLEMENTED;
1921 #if 0
1922 arg->backend.reg3 = ainfo->reg;
1923 /* FP args are passed in int regs */
1924 call->used_iregs |= 1 << ainfo->reg;
1925 if (ainfo->size == 8) {
1926 arg->opcode = OP_OUTARG_R8;
1927 call->used_iregs |= 1 << (ainfo->reg + 1);
1928 } else {
1929 arg->opcode = OP_OUTARG_R4;
1930 }
1931 #endif
1932 cfg->flags |= MONO_CFG_HAS_FPOUT;
1933 break;
1934 }
1935 default:
1936 g_assert_not_reached ();
1937 }
1938 }
1939
1940 /* Handle the case where there are no implicit arguments */
1941 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1942 emit_sig_cookie (cfg, call, cinfo);
1943
1944 if (cinfo->ret.storage == RegTypeStructByVal) {
1945 /* The JIT will transform this into a normal call */
1946 call->vret_in_reg = TRUE;
1947 } else if (cinfo->vtype_retaddr) {
1948 MonoInst *vtarg;
1949 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1950 vtarg->sreg1 = call->vret_var->dreg;
1951 vtarg->dreg = mono_alloc_preg (cfg);
1952 MONO_ADD_INS (cfg->cbb, vtarg);
1953
1954 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1955 }
1956
1957 call->stack_usage = cinfo->stack_usage;
1958
1959 g_free (cinfo);
1960 }
1961
1962 void
1963 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1964 {
1965 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1966 ArgInfo *ainfo = ins->inst_p1;
1967 int ovf_size = ainfo->vtsize;
1968 int doffset = ainfo->offset;
1969 int struct_size = ainfo->struct_size;
1970 int i, soffset, dreg, tmpreg;
1971
1972 soffset = 0;
1973 for (i = 0; i < ainfo->size; ++i) {
1974 dreg = mono_alloc_ireg (cfg);
1975 switch (struct_size) {
1976 case 1:
1977 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1978 break;
1979 case 2:
1980 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1981 break;
1982 case 3:
1983 tmpreg = mono_alloc_ireg (cfg);
1984 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1985 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1986 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1987 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1988 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1989 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1990 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1991 break;
1992 default:
1993 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1994 break;
1995 }
1996 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1997 soffset += sizeof (gpointer);
1998 struct_size -= sizeof (gpointer);
1999 }
2000 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2001 if (ovf_size != 0)
2002 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2003 }
2004
2005 void
2006 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2007 {
2008 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2009
2010 if (!ret->byref) {
2011 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2012 MonoInst *ins;
2013
2014 if (COMPILE_LLVM (cfg)) {
2015 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2016 } else {
2017 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2018 ins->sreg1 = val->dreg + 1;
2019 ins->sreg2 = val->dreg + 2;
2020 MONO_ADD_INS (cfg->cbb, ins);
2021 }
2022 return;
2023 }
2024 switch (arm_fpu) {
2025 case MONO_ARM_FPU_NONE:
2026 if (ret->type == MONO_TYPE_R8) {
2027 MonoInst *ins;
2028
2029 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2030 ins->dreg = cfg->ret->dreg;
2031 ins->sreg1 = val->dreg;
2032 MONO_ADD_INS (cfg->cbb, ins);
2033 return;
2034 }
2035 if (ret->type == MONO_TYPE_R4) {
2036 /* Already converted to an int in method_to_ir () */
2037 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2038 return;
2039 }
2040 break;
2041 case MONO_ARM_FPU_VFP:
2042 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2043 MonoInst *ins;
2044
2045 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2046 ins->dreg = cfg->ret->dreg;
2047 ins->sreg1 = val->dreg;
2048 MONO_ADD_INS (cfg->cbb, ins);
2049 return;
2050 }
2051 break;
2052 case MONO_ARM_FPU_FPA:
2053 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2054 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2055 return;
2056 }
2057 break;
2058 default:
2059 g_assert_not_reached ();
2060 }
2061 }
2062
2063 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2064 }
2065
2066 #endif /* #ifndef DISABLE_JIT */
2067
2068 gboolean
2069 mono_arch_is_inst_imm (gint64 imm)
2070 {
2071 return TRUE;
2072 }
2073
2074 #define DYN_CALL_STACK_ARGS 6
2075
2076 typedef struct {
2077 MonoMethodSignature *sig;
2078 CallInfo *cinfo;
2079 } ArchDynCallInfo;
2080
2081 typedef struct {
2082 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2083 mgreg_t res, res2;
2084 guint8 *ret;
2085 } DynCallArgs;
2086
2087 static gboolean
2088 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2089 {
2090 int i;
2091
2092 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2093 return FALSE;
2094
2095 switch (cinfo->ret.storage) {
2096 case RegTypeNone:
2097 case RegTypeGeneral:
2098 case RegTypeIRegPair:
2099 case RegTypeStructByAddr:
2100 break;
2101 case RegTypeFP:
2102 if (IS_FPA)
2103 return FALSE;
2104 else if (IS_VFP)
2105 break;
2106 else
2107 return FALSE;
2108 default:
2109 return FALSE;
2110 }
2111
2112 for (i = 0; i < cinfo->nargs; ++i) {
2113 switch (cinfo->args [i].storage) {
2114 case RegTypeGeneral:
2115 break;
2116 case RegTypeIRegPair:
2117 break;
2118 case RegTypeBase:
2119 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2120 return FALSE;
2121 break;
2122 case RegTypeStructByVal:
2123 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2124 return FALSE;
2125 break;
2126 default:
2127 return FALSE;
2128 }
2129 }
2130
2131 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2132 for (i = 0; i < sig->param_count; ++i) {
2133 MonoType *t = sig->params [i];
2134
2135 if (t->byref)
2136 continue;
2137
2138 switch (t->type) {
2139 case MONO_TYPE_R4:
2140 case MONO_TYPE_R8:
2141 if (IS_SOFT_FLOAT)
2142 return FALSE;
2143 else
2144 break;
2145 /*
2146 case MONO_TYPE_I8:
2147 case MONO_TYPE_U8:
2148 return FALSE;
2149 */
2150 default:
2151 break;
2152 }
2153 }
2154
2155 return TRUE;
2156 }
2157
2158 MonoDynCallInfo*
2159 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2160 {
2161 ArchDynCallInfo *info;
2162 CallInfo *cinfo;
2163
2164 cinfo = get_call_info (NULL, NULL, sig);
2165
2166 if (!dyn_call_supported (cinfo, sig)) {
2167 g_free (cinfo);
2168 return NULL;
2169 }
2170
2171 info = g_new0 (ArchDynCallInfo, 1);
2172 // FIXME: Preprocess the info to speed up start_dyn_call ()
2173 info->sig = sig;
2174 info->cinfo = cinfo;
2175
2176 return (MonoDynCallInfo*)info;
2177 }
2178
2179 void
2180 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2181 {
2182 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2183
2184 g_free (ainfo->cinfo);
2185 g_free (ainfo);
2186 }
2187
2188 void
2189 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2190 {
2191 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2192 DynCallArgs *p = (DynCallArgs*)buf;
2193 int arg_index, greg, i, j, pindex;
2194 MonoMethodSignature *sig = dinfo->sig;
2195
2196 g_assert (buf_len >= sizeof (DynCallArgs));
2197
2198 p->res = 0;
2199 p->ret = ret;
2200
2201 arg_index = 0;
2202 greg = 0;
2203 pindex = 0;
2204
2205 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2206 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2207 if (!sig->hasthis)
2208 pindex = 1;
2209 }
2210
2211 if (dinfo->cinfo->vtype_retaddr)
2212 p->regs [greg ++] = (mgreg_t)ret;
2213
2214 for (i = pindex; i < sig->param_count; i++) {
2215 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2216 gpointer *arg = args [arg_index ++];
2217 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2218 int slot = -1;
2219
2220 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2221 slot = ainfo->reg;
2222 else if (ainfo->storage == RegTypeBase)
2223 slot = PARAM_REGS + (ainfo->offset / 4);
2224 else
2225 g_assert_not_reached ();
2226
2227 if (t->byref) {
2228 p->regs [slot] = (mgreg_t)*arg;
2229 continue;
2230 }
2231
2232 switch (t->type) {
2233 case MONO_TYPE_STRING:
2234 case MONO_TYPE_CLASS:
2235 case MONO_TYPE_ARRAY:
2236 case MONO_TYPE_SZARRAY:
2237 case MONO_TYPE_OBJECT:
2238 case MONO_TYPE_PTR:
2239 case MONO_TYPE_I:
2240 case MONO_TYPE_U:
2241 p->regs [slot] = (mgreg_t)*arg;
2242 break;
2243 case MONO_TYPE_BOOLEAN:
2244 case MONO_TYPE_U1:
2245 p->regs [slot] = *(guint8*)arg;
2246 break;
2247 case MONO_TYPE_I1:
2248 p->regs [slot] = *(gint8*)arg;
2249 break;
2250 case MONO_TYPE_I2:
2251 p->regs [slot] = *(gint16*)arg;
2252 break;
2253 case MONO_TYPE_U2:
2254 case MONO_TYPE_CHAR:
2255 p->regs [slot] = *(guint16*)arg;
2256 break;
2257 case MONO_TYPE_I4:
2258 p->regs [slot] = *(gint32*)arg;
2259 break;
2260 case MONO_TYPE_U4:
2261 p->regs [slot] = *(guint32*)arg;
2262 break;
2263 case MONO_TYPE_I8:
2264 case MONO_TYPE_U8:
2265 p->regs [slot ++] = (mgreg_t)arg [0];
2266 p->regs [slot] = (mgreg_t)arg [1];
2267 break;
2268 case MONO_TYPE_R4:
2269 p->regs [slot] = *(mgreg_t*)arg;
2270 break;
2271 case MONO_TYPE_R8:
2272 p->regs [slot ++] = (mgreg_t)arg [0];
2273 p->regs [slot] = (mgreg_t)arg [1];
2274 break;
2275 case MONO_TYPE_GENERICINST:
2276 if (MONO_TYPE_IS_REFERENCE (t)) {
2277 p->regs [slot] = (mgreg_t)*arg;
2278 break;
2279 } else {
2280 /* Fall though */
2281 }
2282 case MONO_TYPE_VALUETYPE:
2283 g_assert (ainfo->storage == RegTypeStructByVal);
2284
2285 if (ainfo->size == 0)
2286 slot = PARAM_REGS + (ainfo->offset / 4);
2287 else
2288 slot = ainfo->reg;
2289
2290 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2291 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2292 break;
2293 default:
2294 g_assert_not_reached ();
2295 }
2296 }
2297 }
2298
2299 void
2300 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2301 {
2302 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2303 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2304 guint8 *ret = ((DynCallArgs*)buf)->ret;
2305 mgreg_t res = ((DynCallArgs*)buf)->res;
2306 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2307
2308 switch (mono_type_get_underlying_type (sig->ret)->type) {
2309 case MONO_TYPE_VOID:
2310 *(gpointer*)ret = NULL;
2311 break;
2312 case MONO_TYPE_STRING:
2313 case MONO_TYPE_CLASS:
2314 case MONO_TYPE_ARRAY:
2315 case MONO_TYPE_SZARRAY:
2316 case MONO_TYPE_OBJECT:
2317 case MONO_TYPE_I:
2318 case MONO_TYPE_U:
2319 case MONO_TYPE_PTR:
2320 *(gpointer*)ret = (gpointer)res;
2321 break;
2322 case MONO_TYPE_I1:
2323 *(gint8*)ret = res;
2324 break;
2325 case MONO_TYPE_U1:
2326 case MONO_TYPE_BOOLEAN:
2327 *(guint8*)ret = res;
2328 break;
2329 case MONO_TYPE_I2:
2330 *(gint16*)ret = res;
2331 break;
2332 case MONO_TYPE_U2:
2333 case MONO_TYPE_CHAR:
2334 *(guint16*)ret = res;
2335 break;
2336 case MONO_TYPE_I4:
2337 *(gint32*)ret = res;
2338 break;
2339 case MONO_TYPE_U4:
2340 *(guint32*)ret = res;
2341 break;
2342 case MONO_TYPE_I8:
2343 case MONO_TYPE_U8:
2344 /* This handles endianness as well */
2345 ((gint32*)ret) [0] = res;
2346 ((gint32*)ret) [1] = res2;
2347 break;
2348 case MONO_TYPE_GENERICINST:
2349 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2350 *(gpointer*)ret = (gpointer)res;
2351 break;
2352 } else {
2353 /* Fall though */
2354 }
2355 case MONO_TYPE_VALUETYPE:
2356 g_assert (ainfo->cinfo->vtype_retaddr);
2357 /* Nothing to do */
2358 break;
2359 case MONO_TYPE_R4:
2360 g_assert (IS_VFP);
2361 *(float*)ret = *(float*)&res;
2362 break;
2363 case MONO_TYPE_R8: {
2364 mgreg_t regs [2];
2365
2366 g_assert (IS_VFP);
2367 regs [0] = res;
2368 regs [1] = res2;
2369
2370 *(double*)ret = *(double*)&regs;
2371 break;
2372 }
2373 default:
2374 g_assert_not_reached ();
2375 }
2376 }
2377
2378 #ifndef DISABLE_JIT
2379
2380 /*
2381 * Allow tracing to work with this interface (with an optional argument)
2382 */
2383
2384 void*
2385 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2386 {
2387 guchar *code = p;
2388
2389 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2390 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2391 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2392 code = emit_call_reg (code, ARMREG_R2);
2393 return code;
2394 }
2395
2396 enum {
2397 SAVE_NONE,
2398 SAVE_STRUCT,
2399 SAVE_ONE,
2400 SAVE_TWO,
2401 SAVE_FP
2402 };
2403
2404 void*
2405 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2406 {
2407 guchar *code = p;
2408 int save_mode = SAVE_NONE;
2409 int offset;
2410 MonoMethod *method = cfg->method;
2411 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2412 int save_offset = cfg->param_area;
2413 save_offset += 7;
2414 save_offset &= ~7;
2415
2416 offset = code - cfg->native_code;
2417 /* we need about 16 instructions */
2418 if (offset > (cfg->code_size - 16 * 4)) {
2419 cfg->code_size *= 2;
2420 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2421 code = cfg->native_code + offset;
2422 }
2423 switch (rtype) {
2424 case MONO_TYPE_VOID:
2425 /* special case string .ctor icall */
2426 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2427 save_mode = SAVE_ONE;
2428 else
2429 save_mode = SAVE_NONE;
2430 break;
2431 case MONO_TYPE_I8:
2432 case MONO_TYPE_U8:
2433 save_mode = SAVE_TWO;
2434 break;
2435 case MONO_TYPE_R4:
2436 case MONO_TYPE_R8:
2437 save_mode = SAVE_FP;
2438 break;
2439 case MONO_TYPE_VALUETYPE:
2440 save_mode = SAVE_STRUCT;
2441 break;
2442 default:
2443 save_mode = SAVE_ONE;
2444 break;
2445 }
2446
2447 switch (save_mode) {
2448 case SAVE_TWO:
2449 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2450 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2451 if (enable_arguments) {
2452 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2453 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2454 }
2455 break;
2456 case SAVE_ONE:
2457 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2458 if (enable_arguments) {
2459 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2460 }
2461 break;
2462 case SAVE_FP:
2463 /* FIXME: what reg? */
2464 if (enable_arguments) {
2465 /* FIXME: what reg? */
2466 }
2467 break;
2468 case SAVE_STRUCT:
2469 if (enable_arguments) {
2470 /* FIXME: get the actual address */
2471 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2472 }
2473 break;
2474 case SAVE_NONE:
2475 default:
2476 break;
2477 }
2478
2479 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2480 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2481 code = emit_call_reg (code, ARMREG_IP);
2482
2483 switch (save_mode) {
2484 case SAVE_TWO:
2485 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2486 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2487 break;
2488 case SAVE_ONE:
2489 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2490 break;
2491 case SAVE_FP:
2492 /* FIXME */
2493 break;
2494 case SAVE_NONE:
2495 default:
2496 break;
2497 }
2498
2499 return code;
2500 }
2501
2502 /*
2503 * The immediate field for cond branches is big enough for all reasonable methods
2504 */
2505 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2506 if (0 && ins->inst_true_bb->native_offset) { \
2507 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2508 } else { \
2509 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2510 ARM_B_COND (code, (condcode), 0); \
2511 }
2512
2513 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2514
2515 /* emit an exception if condition is fail
2516 *
2517 * We assign the extra code used to throw the implicit exceptions
2518 * to cfg->bb_exit as far as the big branch handling is concerned
2519 */
2520 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2521 do { \
2522 mono_add_patch_info (cfg, code - cfg->native_code, \
2523 MONO_PATCH_INFO_EXC, exc_name); \
2524 ARM_BL_COND (code, (condcode), 0); \
2525 } while (0);
2526
2527 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2528
2529 void
2530 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2531 {
2532 }
2533
2534 void
2535 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2536 {
2537 MonoInst *ins, *n, *last_ins = NULL;
2538
2539 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2540 switch (ins->opcode) {
2541 case OP_MUL_IMM:
2542 case OP_IMUL_IMM:
2543 /* Already done by an arch-independent pass */
2544 break;
2545 case OP_LOAD_MEMBASE:
2546 case OP_LOADI4_MEMBASE:
2547 /*
2548 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2549 * OP_LOAD_MEMBASE offset(basereg), reg
2550 */
2551 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2552 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2553 ins->inst_basereg == last_ins->inst_destbasereg &&
2554 ins->inst_offset == last_ins->inst_offset) {
2555 if (ins->dreg == last_ins->sreg1) {
2556 MONO_DELETE_INS (bb, ins);
2557 continue;
2558 } else {
2559 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2560 ins->opcode = OP_MOVE;
2561 ins->sreg1 = last_ins->sreg1;
2562 }
2563
2564 /*
2565 * Note: reg1 must be different from the basereg in the second load
2566 * OP_LOAD_MEMBASE offset(basereg), reg1
2567 * OP_LOAD_MEMBASE offset(basereg), reg2
2568 * -->
2569 * OP_LOAD_MEMBASE offset(basereg), reg1
2570 * OP_MOVE reg1, reg2
2571 */
2572 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2573 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2574 ins->inst_basereg != last_ins->dreg &&
2575 ins->inst_basereg == last_ins->inst_basereg &&
2576 ins->inst_offset == last_ins->inst_offset) {
2577
2578 if (ins->dreg == last_ins->dreg) {
2579 MONO_DELETE_INS (bb, ins);
2580 continue;
2581 } else {
2582 ins->opcode = OP_MOVE;
2583 ins->sreg1 = last_ins->dreg;
2584 }
2585
2586 //g_assert_not_reached ();
2587
2588 #if 0
2589 /*
2590 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2591 * OP_LOAD_MEMBASE offset(basereg), reg
2592 * -->
2593 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2594 * OP_ICONST reg, imm
2595 */
2596 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2597 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2598 ins->inst_basereg == last_ins->inst_destbasereg &&
2599 ins->inst_offset == last_ins->inst_offset) {
2600 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2601 ins->opcode = OP_ICONST;
2602 ins->inst_c0 = last_ins->inst_imm;
2603 g_assert_not_reached (); // check this rule
2604 #endif
2605 }
2606 break;
2607 case OP_LOADU1_MEMBASE:
2608 case OP_LOADI1_MEMBASE:
2609 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2610 ins->inst_basereg == last_ins->inst_destbasereg &&
2611 ins->inst_offset == last_ins->inst_offset) {
2612 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2613 ins->sreg1 = last_ins->sreg1;
2614 }
2615 break;
2616 case OP_LOADU2_MEMBASE:
2617 case OP_LOADI2_MEMBASE:
2618 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2619 ins->inst_basereg == last_ins->inst_destbasereg &&
2620 ins->inst_offset == last_ins->inst_offset) {
2621 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2622 ins->sreg1 = last_ins->sreg1;
2623 }
2624 break;
2625 case OP_MOVE:
2626 ins->opcode = OP_MOVE;
2627 /*
2628 * OP_MOVE reg, reg
2629 */
2630 if (ins->dreg == ins->sreg1) {
2631 MONO_DELETE_INS (bb, ins);
2632 continue;
2633 }
2634 /*
2635 * OP_MOVE sreg, dreg
2636 * OP_MOVE dreg, sreg
2637 */
2638 if (last_ins && last_ins->opcode == OP_MOVE &&
2639 ins->sreg1 == last_ins->dreg &&
2640 ins->dreg == last_ins->sreg1) {
2641 MONO_DELETE_INS (bb, ins);
2642 continue;
2643 }
2644 break;
2645 }
2646 last_ins = ins;
2647 ins = ins->next;
2648 }
2649 bb->last_ins = last_ins;
2650 }
2651
2652 /*
2653 * the branch_cc_table should maintain the order of these
2654 * opcodes.
2655 case CEE_BEQ:
2656 case CEE_BGE:
2657 case CEE_BGT:
2658 case CEE_BLE:
2659 case CEE_BLT:
2660 case CEE_BNE_UN:
2661 case CEE_BGE_UN:
2662 case CEE_BGT_UN:
2663 case CEE_BLE_UN:
2664 case CEE_BLT_UN:
2665 */
2666 static const guchar
2667 branch_cc_table [] = {
2668 ARMCOND_EQ,
2669 ARMCOND_GE,
2670 ARMCOND_GT,
2671 ARMCOND_LE,
2672 ARMCOND_LT,
2673
2674 ARMCOND_NE,
2675 ARMCOND_HS,
2676 ARMCOND_HI,
2677 ARMCOND_LS,
2678 ARMCOND_LO
2679 };
2680
2681 #define ADD_NEW_INS(cfg,dest,op) do { \
2682 MONO_INST_NEW ((cfg), (dest), (op)); \
2683 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2684 } while (0)
2685
2686 static int
2687 map_to_reg_reg_op (int op)
2688 {
2689 switch (op) {
2690 case OP_ADD_IMM:
2691 return OP_IADD;
2692 case OP_SUB_IMM:
2693 return OP_ISUB;
2694 case OP_AND_IMM:
2695 return OP_IAND;
2696 case OP_COMPARE_IMM:
2697 return OP_COMPARE;
2698 case OP_ICOMPARE_IMM:
2699 return OP_ICOMPARE;
2700 case OP_ADDCC_IMM:
2701 return OP_ADDCC;
2702 case OP_ADC_IMM:
2703 return OP_ADC;
2704 case OP_SUBCC_IMM:
2705 return OP_SUBCC;
2706 case OP_SBB_IMM:
2707 return OP_SBB;
2708 case OP_OR_IMM:
2709 return OP_IOR;
2710 case OP_XOR_IMM:
2711 return OP_IXOR;
2712 case OP_LOAD_MEMBASE:
2713 return OP_LOAD_MEMINDEX;
2714 case OP_LOADI4_MEMBASE:
2715 return OP_LOADI4_MEMINDEX;
2716 case OP_LOADU4_MEMBASE:
2717 return OP_LOADU4_MEMINDEX;
2718 case OP_LOADU1_MEMBASE:
2719 return OP_LOADU1_MEMINDEX;
2720 case OP_LOADI2_MEMBASE:
2721 return OP_LOADI2_MEMINDEX;
2722 case OP_LOADU2_MEMBASE:
2723 return OP_LOADU2_MEMINDEX;
2724 case OP_LOADI1_MEMBASE:
2725 return OP_LOADI1_MEMINDEX;
2726 case OP_STOREI1_MEMBASE_REG:
2727 return OP_STOREI1_MEMINDEX;
2728 case OP_STOREI2_MEMBASE_REG:
2729 return OP_STOREI2_MEMINDEX;
2730 case OP_STOREI4_MEMBASE_REG:
2731 return OP_STOREI4_MEMINDEX;
2732 case OP_STORE_MEMBASE_REG:
2733 return OP_STORE_MEMINDEX;
2734 case OP_STORER4_MEMBASE_REG:
2735 return OP_STORER4_MEMINDEX;
2736 case OP_STORER8_MEMBASE_REG:
2737 return OP_STORER8_MEMINDEX;
2738 case OP_STORE_MEMBASE_IMM:
2739 return OP_STORE_MEMBASE_REG;
2740 case OP_STOREI1_MEMBASE_IMM:
2741 return OP_STOREI1_MEMBASE_REG;
2742 case OP_STOREI2_MEMBASE_IMM:
2743 return OP_STOREI2_MEMBASE_REG;
2744 case OP_STOREI4_MEMBASE_IMM:
2745 return OP_STOREI4_MEMBASE_REG;
2746 }
2747 g_assert_not_reached ();
2748 }
2749
2750 /*
2751 * Remove from the instruction list the instructions that can't be
2752 * represented with very simple instructions with no register
2753 * requirements.
2754 */
2755 void
2756 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2757 {
2758 MonoInst *ins, *temp, *last_ins = NULL;
2759 int rot_amount, imm8, low_imm;
2760
2761 MONO_BB_FOR_EACH_INS (bb, ins) {
2762 loop_start:
2763 switch (ins->opcode) {
2764 case OP_ADD_IMM:
2765 case OP_SUB_IMM:
2766 case OP_AND_IMM:
2767 case OP_COMPARE_IMM:
2768 case OP_ICOMPARE_IMM:
2769 case OP_ADDCC_IMM:
2770 case OP_ADC_IMM:
2771 case OP_SUBCC_IMM:
2772 case OP_SBB_IMM:
2773 case OP_OR_IMM:
2774 case OP_XOR_IMM:
2775 case OP_IADD_IMM:
2776 case OP_ISUB_IMM:
2777 case OP_IAND_IMM:
2778 case OP_IADC_IMM:
2779 case OP_ISBB_IMM:
2780 case OP_IOR_IMM:
2781 case OP_IXOR_IMM:
2782 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2783 ADD_NEW_INS (cfg, temp, OP_ICONST);
2784 temp->inst_c0 = ins->inst_imm;
2785 temp->dreg = mono_alloc_ireg (cfg);
2786 ins->sreg2 = temp->dreg;
2787 ins->opcode = mono_op_imm_to_op (ins->opcode);
2788 }
2789 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2790 goto loop_start;
2791 else
2792 break;
2793 case OP_MUL_IMM:
2794 case OP_IMUL_IMM:
2795 if (ins->inst_imm == 1) {
2796 ins->opcode = OP_MOVE;
2797 break;
2798 }
2799 if (ins->inst_imm == 0) {
2800 ins->opcode = OP_ICONST;
2801 ins->inst_c0 = 0;
2802 break;
2803 }
2804 imm8 = mono_is_power_of_two (ins->inst_imm);
2805 if (imm8 > 0) {
2806 ins->opcode = OP_SHL_IMM;
2807 ins->inst_imm = imm8;
2808 break;
2809 }
2810 ADD_NEW_INS (cfg, temp, OP_ICONST);
2811 temp->inst_c0 = ins->inst_imm;
2812 temp->dreg = mono_alloc_ireg (cfg);
2813 ins->sreg2 = temp->dreg;
2814 ins->opcode = OP_IMUL;
2815 break;
2816 case OP_SBB:
2817 case OP_ISBB:
2818 case OP_SUBCC:
2819 case OP_ISUBCC:
2820 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2821 /* ARM sets the C flag to 1 if there was _no_ overflow */
2822 ins->next->opcode = OP_COND_EXC_NC;
2823 break;
2824 case OP_LOCALLOC_IMM:
2825 ADD_NEW_INS (cfg, temp, OP_ICONST);
2826 temp->inst_c0 = ins->inst_imm;
2827 temp->dreg = mono_alloc_ireg (cfg);
2828 ins->sreg1 = temp->dreg;
2829 ins->opcode = OP_LOCALLOC;
2830 break;
2831 case OP_LOAD_MEMBASE:
2832 case OP_LOADI4_MEMBASE:
2833 case OP_LOADU4_MEMBASE:
2834 case OP_LOADU1_MEMBASE:
2835 /* we can do two things: load the immed in a register
2836 * and use an indexed load, or see if the immed can be
2837 * represented as an ad_imm + a load with a smaller offset
2838 * that fits. We just do the first for now, optimize later.
2839 */
2840 if (arm_is_imm12 (ins->inst_offset))
2841 break;
2842 ADD_NEW_INS (cfg, temp, OP_ICONST);
2843 temp->inst_c0 = ins->inst_offset;
2844 temp->dreg = mono_alloc_ireg (cfg);
2845 ins->sreg2 = temp->dreg;
2846 ins->opcode = map_to_reg_reg_op (ins->opcode);
2847 break;
2848 case OP_LOADI2_MEMBASE:
2849 case OP_LOADU2_MEMBASE:
2850 case OP_LOADI1_MEMBASE:
2851 if (arm_is_imm8 (ins->inst_offset))
2852 break;
2853 ADD_NEW_INS (cfg, temp, OP_ICONST);
2854 temp->inst_c0 = ins->inst_offset;
2855 temp->dreg = mono_alloc_ireg (cfg);
2856 ins->sreg2 = temp->dreg;
2857 ins->opcode = map_to_reg_reg_op (ins->opcode);
2858 break;
2859 case OP_LOADR4_MEMBASE:
2860 case OP_LOADR8_MEMBASE:
2861 if (arm_is_fpimm8 (ins->inst_offset))
2862 break;
2863 low_imm = ins->inst_offset & 0x1ff;
2864 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2865 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2866 temp->inst_imm = ins->inst_offset & ~0x1ff;
2867 temp->sreg1 = ins->inst_basereg;
2868 temp->dreg = mono_alloc_ireg (cfg);
2869 ins->inst_basereg = temp->dreg;
2870 ins->inst_offset = low_imm;
2871 } else {
2872 MonoInst *add_ins;
2873
2874 ADD_NEW_INS (cfg, temp, OP_ICONST);
2875 temp->inst_c0 = ins->inst_offset;
2876 temp->dreg = mono_alloc_ireg (cfg);
2877
2878 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2879 add_ins->sreg1 = ins->inst_basereg;
2880 add_ins->sreg2 = temp->dreg;
2881 add_ins->dreg = mono_alloc_ireg (cfg);
2882
2883 ins->inst_basereg = add_ins->dreg;
2884 ins->inst_offset = 0;
2885 }
2886 break;
2887 case OP_STORE_MEMBASE_REG:
2888 case OP_STOREI4_MEMBASE_REG:
2889 case OP_STOREI1_MEMBASE_REG:
2890 if (arm_is_imm12 (ins->inst_offset))
2891 break;
2892 ADD_NEW_INS (cfg, temp, OP_ICONST);
2893 temp->inst_c0 = ins->inst_offset;
2894 temp->dreg = mono_alloc_ireg (cfg);
2895 ins->sreg2 = temp->dreg;
2896 ins->opcode = map_to_reg_reg_op (ins->opcode);
2897 break;
2898 case OP_STOREI2_MEMBASE_REG:
2899 if (arm_is_imm8 (ins->inst_offset))
2900 break;
2901 ADD_NEW_INS (cfg, temp, OP_ICONST);
2902 temp->inst_c0 = ins->inst_offset;
2903 temp->dreg = mono_alloc_ireg (cfg);
2904 ins->sreg2 = temp->dreg;
2905 ins->opcode = map_to_reg_reg_op (ins->opcode);
2906 break;
2907 case OP_STORER4_MEMBASE_REG:
2908 case OP_STORER8_MEMBASE_REG:
2909 if (arm_is_fpimm8 (ins->inst_offset))
2910 break;
2911 low_imm = ins->inst_offset & 0x1ff;
2912 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2913 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2914 temp->inst_imm = ins->inst_offset & ~0x1ff;
2915 temp->sreg1 = ins->inst_destbasereg;
2916 temp->dreg = mono_alloc_ireg (cfg);
2917 ins->inst_destbasereg = temp->dreg;
2918 ins->inst_offset = low_imm;
2919 } else {
2920 MonoInst *add_ins;
2921
2922 ADD_NEW_INS (cfg, temp, OP_ICONST);
2923 temp->inst_c0 = ins->inst_offset;
2924 temp->dreg = mono_alloc_ireg (cfg);
2925
2926 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2927 add_ins->sreg1 = ins->inst_destbasereg;
2928 add_ins->sreg2 = temp->dreg;
2929 add_ins->dreg = mono_alloc_ireg (cfg);
2930
2931 ins->inst_destbasereg = add_ins->dreg;
2932 ins->inst_offset = 0;
2933 }
2934 break;
2935 case OP_STORE_MEMBASE_IMM:
2936 case OP_STOREI1_MEMBASE_IMM:
2937 case OP_STOREI2_MEMBASE_IMM:
2938 case OP_STOREI4_MEMBASE_IMM:
2939 ADD_NEW_INS (cfg, temp, OP_ICONST);
2940 temp->inst_c0 = ins->inst_imm;
2941 temp->dreg = mono_alloc_ireg (cfg);
2942 ins->sreg1 = temp->dreg;
2943 ins->opcode = map_to_reg_reg_op (ins->opcode);
2944 last_ins = temp;
2945 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2946 case OP_FCOMPARE: {
2947 gboolean swap = FALSE;
2948 int reg;
2949
2950 if (!ins->next) {
2951 /* Optimized away */
2952 NULLIFY_INS (ins);
2953 break;
2954 }
2955
2956 /* Some fp compares require swapped operands */
2957 switch (ins->next->opcode) {
2958 case OP_FBGT:
2959 ins->next->opcode = OP_FBLT;
2960 swap = TRUE;
2961 break;
2962 case OP_FBGT_UN:
2963 ins->next->opcode = OP_FBLT_UN;
2964 swap = TRUE;
2965 break;
2966 case OP_FBLE:
2967 ins->next->opcode = OP_FBGE;
2968 swap = TRUE;
2969 break;
2970 case OP_FBLE_UN:
2971 ins->next->opcode = OP_FBGE_UN;
2972 swap = TRUE;
2973 break;
2974 default:
2975 break;
2976 }
2977 if (swap) {
2978 reg = ins->sreg1;
2979 ins->sreg1 = ins->sreg2;
2980 ins->sreg2 = reg;
2981 }
2982 break;
2983 }
2984 }
2985
2986 last_ins = ins;
2987 }
2988 bb->last_ins = last_ins;
2989 bb->max_vreg = cfg->next_vreg;
2990 }
2991
2992 void
2993 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2994 {
2995 MonoInst *ins;
2996
2997 if (long_ins->opcode == OP_LNEG) {
2998 ins = long_ins;
2999 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3000 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3001 NULLIFY_INS (ins);
3002 }
3003 }
3004
3005 static guchar*
3006 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3007 {
3008 /* sreg is a float, dreg is an integer reg */
3009 if (IS_FPA)
3010 ARM_FPA_FIXZ (code, dreg, sreg);
3011 else if (IS_VFP) {
3012 if (is_signed)
3013 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3014 else
3015 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3016 ARM_FMRS (code, dreg, ARM_VFP_F0);
3017 }
3018 if (!is_signed) {
3019 if (size == 1)
3020 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3021 else if (size == 2) {
3022 ARM_SHL_IMM (code, dreg, dreg, 16);
3023 ARM_SHR_IMM (code, dreg, dreg, 16);
3024 }
3025 } else {
3026 if (size == 1) {
3027 ARM_SHL_IMM (code, dreg, dreg, 24);
3028 ARM_SAR_IMM (code, dreg, dreg, 24);
3029 } else if (size == 2) {
3030 ARM_SHL_IMM (code, dreg, dreg, 16);
3031 ARM_SAR_IMM (code, dreg, dreg, 16);
3032 }
3033 }
3034 return code;
3035 }
3036
3037 #endif /* #ifndef DISABLE_JIT */
3038
3039 typedef struct {
3040 guchar *code;
3041 const guchar *target;
3042 int absolute;
3043 int found;
3044 } PatchData;
3045
3046 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3047
3048 static int
3049 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3050 PatchData *pdata = (PatchData*)user_data;
3051 guchar *code = data;
3052 guint32 *thunks = data;
3053 guint32 *endthunks = (guint32*)(code + bsize);
3054 int count = 0;
3055 int difflow, diffhigh;
3056
3057 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3058 difflow = (char*)pdata->code - (char*)thunks;
3059 diffhigh = (char*)pdata->code - (char*)endthunks;
3060 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3061 return 0;
3062
3063 /*
3064 * The thunk is composed of 3 words:
3065 * load constant from thunks [2] into ARM_IP
3066 * bx to ARM_IP
3067 * address constant
3068 * Note that the LR register is already setup
3069 */
3070 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3071 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3072 while (thunks < endthunks) {
3073 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3074 if (thunks [2] == (guint32)pdata->target) {
3075 arm_patch (pdata->code, (guchar*)thunks);
3076 mono_arch_flush_icache (pdata->code, 4);
3077 pdata->found = 1;
3078 return 1;
3079 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3080 /* found a free slot instead: emit thunk */
3081 /* ARMREG_IP is fine to use since this can't be an IMT call
3082 * which is indirect
3083 */
3084 code = (guchar*)thunks;
3085 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3086 if (thumb_supported)
3087 ARM_BX (code, ARMREG_IP);
3088 else
3089 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3090 thunks [2] = (guint32)pdata->target;
3091 mono_arch_flush_icache ((guchar*)thunks, 12);
3092
3093 arm_patch (pdata->code, (guchar*)thunks);
3094 mono_arch_flush_icache (pdata->code, 4);
3095 pdata->found = 1;
3096 return 1;
3097 }
3098 /* skip 12 bytes, the size of the thunk */
3099 thunks += 3;
3100 count++;
3101 }
3102 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3103 }
3104 return 0;
3105 }
3106
3107 static void
3108 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3109 {
3110 PatchData pdata;
3111
3112 if (!domain)
3113 domain = mono_domain_get ();
3114
3115 pdata.code = code;
3116 pdata.target = target;
3117 pdata.absolute = absolute;
3118 pdata.found = 0;
3119
3120 if (dyn_code_mp) {
3121 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3122 }
3123
3124 if (pdata.found != 1) {
3125 mono_domain_lock (domain);
3126 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3127
3128 if (!pdata.found) {
3129 /* this uses the first available slot */
3130 pdata.found = 2;
3131 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3132 }
3133 mono_domain_unlock (domain);
3134 }
3135
3136 if (pdata.found != 1) {
3137 GHashTable *hash;
3138 GHashTableIter iter;
3139 MonoJitDynamicMethodInfo *ji;
3140
3141 /*
3142 * This might be a dynamic method, search its code manager. We can only
3143 * use the dynamic method containing CODE, since the others might be freed later.
3144 */
3145 pdata.found = 0;
3146
3147 mono_domain_lock (domain);
3148 hash = domain_jit_info (domain)->dynamic_code_hash;
3149 if (hash) {
3150 /* FIXME: Speed this up */
3151 g_hash_table_iter_init (&iter, hash);
3152 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3153 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3154 if (pdata.found == 1)
3155 break;
3156 }
3157 }
3158 mono_domain_unlock (domain);
3159 }
3160 if (pdata.found != 1)
3161 g_print ("thunk failed for %p from %p\n", target, code);
3162 g_assert (pdata.found == 1);
3163 }
3164
3165 static void
3166 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3167 {
3168 guint32 *code32 = (void*)code;
3169 guint32 ins = *code32;
3170 guint32 prim = (ins >> 25) & 7;
3171 guint32 tval = GPOINTER_TO_UINT (target);
3172
3173 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3174 if (prim == 5) { /* 101b */
3175 /* the diff starts 8 bytes from the branch opcode */
3176 gint diff = target - code - 8;
3177 gint tbits;
3178 gint tmask = 0xffffffff;
3179 if (tval & 1) { /* entering thumb mode */
3180 diff = target - 1 - code - 8;
3181 g_assert (thumb_supported);
3182 tbits = 0xf << 28; /* bl->blx bit pattern */
3183 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3184 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3185 if (diff & 2) {
3186 tbits |= 1 << 24;
3187 }
3188 tmask = ~(1 << 24); /* clear the link bit */
3189 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3190 } else {
3191 tbits = 0;
3192 }
3193 if (diff >= 0) {
3194 if (diff <= 33554431) {
3195 diff >>= 2;
3196 ins = (ins & 0xff000000) | diff;
3197 ins &= tmask;
3198 *code32 = ins | tbits;
3199 return;
3200 }
3201 } else {
3202 /* diff between 0 and -33554432 */
3203 if (diff >= -33554432) {
3204 diff >>= 2;
3205 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3206 ins &= tmask;
3207 *code32 = ins | tbits;
3208 return;
3209 }
3210 }
3211
3212 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3213 return;
3214 }
3215
3216 /*
3217 * The alternative call sequences looks like this:
3218 *
3219 * ldr ip, [pc] // loads the address constant
3220 * b 1f // jumps around the constant
3221 * address constant embedded in the code
3222 * 1f:
3223 * mov lr, pc
3224 * mov pc, ip
3225 *
3226 * There are two cases for patching:
3227 * a) at the end of method emission: in this case code points to the start
3228 * of the call sequence
3229 * b) during runtime patching of the call site: in this case code points
3230 * to the mov pc, ip instruction
3231 *
3232 * We have to handle also the thunk jump code sequence:
3233 *
3234 * ldr ip, [pc]
3235 * mov pc, ip
3236 * address constant // execution never reaches here
3237 */
3238 if ((ins & 0x0ffffff0) == 0x12fff10) {
3239 /* Branch and exchange: the address is constructed in a reg
3240 * We can patch BX when the code sequence is the following:
3241 * ldr ip, [pc, #0] ; 0x8
3242 * b 0xc
3243 * .word code_ptr
3244 * mov lr, pc
3245 * bx ips
3246 * */
3247 guint32 ccode [4];
3248 guint8 *emit = (guint8*)ccode;
3249 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3250 ARM_B (emit, 0);
3251 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3252 ARM_BX (emit, ARMREG_IP);
3253
3254 /*patching from magic trampoline*/
3255 if (ins == ccode [3]) {
3256 g_assert (code32 [-4] == ccode [0]);
3257 g_assert (code32 [-3] == ccode [1]);
3258 g_assert (code32 [-1] == ccode [2]);
3259 code32 [-2] = (guint32)target;
3260 return;
3261 }
3262 /*patching from JIT*/
3263 if (ins == ccode [0]) {
3264 g_assert (code32 [1] == ccode [1]);
3265 g_assert (code32 [3] == ccode [2]);
3266 g_assert (code32 [4] == ccode [3]);
3267 code32 [2] = (guint32)target;
3268 return;
3269 }
3270 g_assert_not_reached ();
3271 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3272 /*
3273 * ldr ip, [pc, #0]
3274 * b 0xc
3275 * .word code_ptr
3276 * blx ip
3277 */
3278 guint32 ccode [4];
3279 guint8 *emit = (guint8*)ccode;
3280 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3281 ARM_B (emit, 0);
3282 ARM_BLX_REG (emit, ARMREG_IP);
3283
3284 g_assert (code32 [-3] == ccode [0]);
3285 g_assert (code32 [-2] == ccode [1]);
3286 g_assert (code32 [0] == ccode [2]);
3287
3288 code32 [-1] = (guint32)target;
3289 } else {
3290 guint32 ccode [4];
3291 guint32 *tmp = ccode;
3292 guint8 *emit = (guint8*)tmp;
3293 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3294 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3295 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3296 ARM_BX (emit, ARMREG_IP);
3297 if (ins == ccode [2]) {
3298 g_assert_not_reached (); // should be -2 ...
3299 code32 [-1] = (guint32)target;
3300 return;
3301 }
3302 if (ins == ccode [0]) {
3303 /* handles both thunk jump code and the far call sequence */
3304 code32 [2] = (guint32)target;
3305 return;
3306 }
3307 g_assert_not_reached ();
3308 }
3309 // g_print ("patched with 0x%08x\n", ins);
3310 }
3311
3312 void
3313 arm_patch (guchar *code, const guchar *target)
3314 {
3315 arm_patch_general (NULL, code, target, NULL);
3316 }
3317
3318 /*
3319 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3320 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3321 * to be used with the emit macros.
3322 * Return -1 otherwise.
3323 */
3324 int
3325 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3326 {
3327 guint32 res, i;
3328 for (i = 0; i < 31; i+= 2) {
3329 res = (val << (32 - i)) | (val >> i);
3330 if (res & ~0xff)
3331 continue;
3332 *rot_amount = i? 32 - i: 0;
3333 return res;
3334 }
3335 return -1;
3336 }
3337
3338 /*
3339 * Emits in code a sequence of instructions that load the value 'val'
3340 * into the dreg register. Uses at most 4 instructions.
3341 */
3342 guint8*
3343 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3344 {
3345 int imm8, rot_amount;
3346 #if 0
3347 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3348 /* skip the constant pool */
3349 ARM_B (code, 0);
3350 *(int*)code = val;
3351 code += 4;
3352 return code;
3353 #endif
3354 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3355 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3356 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3357 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3358 } else {
3359 if (v7_supported) {
3360 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3361 if (val >> 16)
3362 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3363 return code;
3364 }
3365 if (val & 0xFF) {
3366 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3367 if (val & 0xFF00) {
3368 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3369 }
3370 if (val & 0xFF0000) {
3371 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3372 }
3373 if (val & 0xFF000000) {
3374 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3375 }
3376 } else if (val & 0xFF00) {
3377 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3378 if (val & 0xFF0000) {
3379 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3380 }
3381 if (val & 0xFF000000) {
3382 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3383 }
3384 } else if (val & 0xFF0000) {
3385 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3386 if (val & 0xFF000000) {
3387 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3388 }
3389 }
3390 //g_assert_not_reached ();
3391 }
3392 return code;
3393 }
3394
3395 gboolean
3396 mono_arm_thumb_supported (void)
3397 {
3398 return thumb_supported;
3399 }
3400
3401 #ifndef DISABLE_JIT
3402
3403 /*
3404 * emit_load_volatile_arguments:
3405 *
3406 * Load volatile arguments from the stack to the original input registers.
3407 * Required before a tail call.
3408 */
3409 static guint8*
3410 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3411 {
3412 MonoMethod *method = cfg->method;
3413 MonoMethodSignature *sig;
3414 MonoInst *inst;
3415 CallInfo *cinfo;
3416 guint32 i, pos;
3417
3418 /* FIXME: Generate intermediate code instead */
3419
3420 sig = mono_method_signature (method);
3421
3422 /* This is the opposite of the code in emit_prolog */
3423
3424 pos = 0;
3425
3426 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3427
3428 if (cinfo->vtype_retaddr) {
3429 ArgInfo *ainfo = &cinfo->ret;
3430 inst = cfg->vret_addr;
3431 g_assert (arm_is_imm12 (inst->inst_offset));
3432 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3433 }
3434 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3435 ArgInfo *ainfo = cinfo->args + i;
3436 inst = cfg->args [pos];
3437
3438 if (cfg->verbose_level > 2)
3439 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3440 if (inst->opcode == OP_REGVAR) {
3441 if (ainfo->storage == RegTypeGeneral)
3442 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3443 else if (ainfo->storage == RegTypeFP) {
3444 g_assert_not_reached ();
3445 } else if (ainfo->storage == RegTypeBase) {
3446 // FIXME:
3447 NOT_IMPLEMENTED;
3448 /*
3449 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3450 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3451 } else {
3452 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3453 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3454 }
3455 */
3456 } else
3457 g_assert_not_reached ();
3458 } else {
3459 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3460 switch (ainfo->size) {
3461 case 1:
3462 case 2:
3463 // FIXME:
3464 NOT_IMPLEMENTED;
3465 break;
3466 case 8:
3467 g_assert (arm_is_imm12 (inst->inst_offset));
3468 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3469 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3470 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3471 break;
3472 default:
3473 if (arm_is_imm12 (inst->inst_offset)) {
3474 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3475 } else {
3476 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3477 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3478 }
3479 break;
3480 }
3481 } else if (ainfo->storage == RegTypeBaseGen) {
3482 // FIXME:
3483 NOT_IMPLEMENTED;
3484 } else if (ainfo->storage == RegTypeBase) {
3485 /* Nothing to do */
3486 } else if (ainfo->storage == RegTypeFP) {
3487 g_assert_not_reached ();
3488 } else if (ainfo->storage == RegTypeStructByVal) {
3489 int doffset = inst->inst_offset;
3490 int soffset = 0;
3491 int cur_reg;
3492 int size = 0;
3493 if (mono_class_from_mono_type (inst->inst_vtype))
3494 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3495 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3496 if (arm_is_imm12 (doffset)) {
3497 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3498 } else {
3499 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3500 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3501 }
3502 soffset += sizeof (gpointer);
3503 doffset += sizeof (gpointer);
3504 }
3505 if (ainfo->vtsize)
3506 // FIXME:
3507 NOT_IMPLEMENTED;
3508 } else if (ainfo->storage == RegTypeStructByAddr) {
3509 } else {
3510 // FIXME:
3511 NOT_IMPLEMENTED;
3512 }
3513 }
3514 pos ++;
3515 }
3516
3517 g_free (cinfo);
3518
3519 return code;
3520 }
3521
3522 void
3523 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3524 {
3525 MonoInst *ins;
3526 MonoCallInst *call;
3527 guint offset;
3528 guint8 *code = cfg->native_code + cfg->code_len;
3529 MonoInst *last_ins = NULL;
3530 guint last_offset = 0;
3531 int max_len, cpos;
3532 int imm8, rot_amount;
3533
3534 /* we don't align basic blocks of loops on arm */
3535
3536 if (cfg->verbose_level > 2)
3537 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3538
3539 cpos = bb->max_offset;
3540
3541 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3542 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3543 //g_assert (!mono_compile_aot);
3544 //cpos += 6;
3545 //if (bb->cil_code)
3546 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3547 /* this is not thread save, but good enough */
3548 /* fixme: howto handle overflows? */
3549 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3550 }
3551
3552 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3553 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3554 (gpointer)"mono_break");
3555 code = emit_call_seq (cfg, code);
3556 }
3557
3558 MONO_BB_FOR_EACH_INS (bb, ins) {
3559 offset = code - cfg->native_code;
3560
3561 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3562
3563 if (offset > (cfg->code_size - max_len - 16)) {
3564 cfg->code_size *= 2;
3565 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3566 code = cfg->native_code + offset;
3567 }
3568 // if (ins->cil_code)
3569 // g_print ("cil code\n");
3570 mono_debug_record_line_number (cfg, ins, offset);
3571
3572 switch (ins->opcode) {
3573 case OP_MEMORY_BARRIER:
3574 if (v6_supported) {
3575 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3576 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3577 }
3578 break;
3579 case OP_TLS_GET:
3580 #ifdef HAVE_AEABI_READ_TP
3581 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3582 (gpointer)"__aeabi_read_tp");
3583 code = emit_call_seq (cfg, code);
3584
3585 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3586 #else
3587 g_assert_not_reached ();
3588 #endif
3589 break;
3590 /*case OP_BIGMUL:
3591 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3592 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3593 break;
3594 case OP_BIGMUL_UN:
3595 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3596 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3597 break;*/
3598 case OP_STOREI1_MEMBASE_IMM:
3599 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3600 g_assert (arm_is_imm12 (ins->inst_offset));
3601 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3602 break;
3603 case OP_STOREI2_MEMBASE_IMM:
3604 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3605 g_assert (arm_is_imm8 (ins->inst_offset));
3606 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3607 break;
3608 case OP_STORE_MEMBASE_IMM:
3609 case OP_STOREI4_MEMBASE_IMM:
3610 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3611 g_assert (arm_is_imm12 (ins->inst_offset));
3612 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3613 break;
3614 case OP_STOREI1_MEMBASE_REG:
3615 g_assert (arm_is_imm12 (ins->inst_offset));
3616 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3617 break;
3618 case OP_STOREI2_MEMBASE_REG:
3619 g_assert (arm_is_imm8 (ins->inst_offset));
3620 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3621 break;
3622 case OP_STORE_MEMBASE_REG:
3623 case OP_STOREI4_MEMBASE_REG:
3624 /* this case is special, since it happens for spill code after lowering has been called */
3625 if (arm_is_imm12 (ins->inst_offset)) {
3626 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3627 } else {
3628 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3629 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3630 }
3631 break;
3632 case OP_STOREI1_MEMINDEX:
3633 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3634 break;
3635 case OP_STOREI2_MEMINDEX:
3636 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3637 break;
3638 case OP_STORE_MEMINDEX:
3639 case OP_STOREI4_MEMINDEX:
3640 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3641 break;
3642 case OP_LOADU4_MEM:
3643 g_assert_not_reached ();
3644 break;
3645 case OP_LOAD_MEMINDEX:
3646 case OP_LOADI4_MEMINDEX:
3647 case OP_LOADU4_MEMINDEX:
3648 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3649 break;
3650 case OP_LOADI1_MEMINDEX:
3651 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3652 break;
3653 case OP_LOADU1_MEMINDEX:
3654 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3655 break;
3656 case OP_LOADI2_MEMINDEX:
3657 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3658 break;
3659 case OP_LOADU2_MEMINDEX:
3660 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3661 break;
3662 case OP_LOAD_MEMBASE:
3663 case OP_LOADI4_MEMBASE:
3664 case OP_LOADU4_MEMBASE:
3665 /* this case is special, since it happens for spill code after lowering has been called */
3666 if (arm_is_imm12 (ins->inst_offset)) {
3667 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3668 } else {
3669 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3670 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3671 }
3672 break;
3673 case OP_LOADI1_MEMBASE:
3674 g_assert (arm_is_imm8 (ins->inst_offset));
3675 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3676 break;
3677 case OP_LOADU1_MEMBASE:
3678 g_assert (arm_is_imm12 (ins->inst_offset));
3679 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3680 break;
3681 case OP_LOADU2_MEMBASE:
3682 g_assert (arm_is_imm8 (ins->inst_offset));
3683 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3684 break;
3685 case OP_LOADI2_MEMBASE:
3686 g_assert (arm_is_imm8 (ins->inst_offset));
3687 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3688 break;
3689 case OP_ICONV_TO_I1:
3690 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3691 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3692 break;
3693 case OP_ICONV_TO_I2:
3694 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3695 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3696 break;
3697 case OP_ICONV_TO_U1:
3698 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3699 break;
3700 case OP_ICONV_TO_U2:
3701 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3702 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3703 break;
3704 case OP_COMPARE:
3705 case OP_ICOMPARE:
3706 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3707 break;
3708 case OP_COMPARE_IMM:
3709 case OP_ICOMPARE_IMM:
3710 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3711 g_assert (imm8 >= 0);
3712 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3713 break;
3714 case OP_BREAK:
3715 /*
3716 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3717 * So instead of emitting a trap, we emit a call a C function and place a
3718 * breakpoint there.
3719 */
3720 //*(int*)code = 0xef9f0001;
3721 //code += 4;
3722 //ARM_DBRK (code);
3723 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3724 (gpointer)"mono_break");
3725 code = emit_call_seq (cfg, code);
3726 break;
3727 case OP_RELAXED_NOP:
3728 ARM_NOP (code);
3729 break;
3730 case OP_NOP:
3731 case OP_DUMMY_USE:
3732 case OP_DUMMY_STORE:
3733 case OP_NOT_REACHED:
3734 case OP_NOT_NULL:
3735 break;
3736 case OP_SEQ_POINT: {
3737 int i;
3738 MonoInst *info_var = cfg->arch.seq_point_info_var;
3739 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3740 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3741 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3742 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3743 MonoInst *var;
3744 int dreg = ARMREG_LR;
3745
3746 if (cfg->soft_breakpoints) {
3747 g_assert (!cfg->compile_aot);
3748 }
3749
3750 /*
3751 * For AOT, we use one got slot per method, which will point to a
3752 * SeqPointInfo structure, containing all the information required
3753 * by the code below.
3754 */
3755 if (cfg->compile_aot) {
3756 g_assert (info_var);
3757 g_assert (info_var->opcode == OP_REGOFFSET);
3758 g_assert (arm_is_imm12 (info_var->inst_offset));
3759 }
3760
3761 if (!cfg->soft_breakpoints) {
3762 /*
3763 * Read from the single stepping trigger page. This will cause a
3764 * SIGSEGV when single stepping is enabled.
3765 * We do this _before_ the breakpoint, so single stepping after
3766 * a breakpoint is hit will step to the next IL offset.
3767 */
3768 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3769 }
3770
3771 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3772 if (cfg->soft_breakpoints) {
3773 /* Load the address of the sequence point trigger variable. */
3774 var = ss_read_var;
3775 g_assert (var);
3776 g_assert (var->opcode == OP_REGOFFSET);
3777 g_assert (arm_is_imm12 (var->inst_offset));
3778 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3779
3780 /* Read the value and check whether it is non-zero. */
3781 ARM_LDR_IMM (code, dreg, dreg, 0);
3782 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3783
3784 /* Load the address of the sequence point method. */
3785 var = ss_method_var;
3786 g_assert (var);
3787 g_assert (var->opcode == OP_REGOFFSET);
3788 g_assert (arm_is_imm12 (var->inst_offset));
3789 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3790
3791 /* Call it conditionally. */
3792 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3793 } else {
3794 if (cfg->compile_aot) {
3795 /* Load the trigger page addr from the variable initialized in the prolog */
3796 var = ss_trigger_page_var;
3797 g_assert (var);
3798 g_assert (var->opcode == OP_REGOFFSET);
3799 g_assert (arm_is_imm12 (var->inst_offset));
3800 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3801 } else {
3802 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3803 ARM_B (code, 0);
3804 *(int*)code = (int)ss_trigger_page;
3805 code += 4;
3806 }
3807 ARM_LDR_IMM (code, dreg, dreg, 0);
3808 }
3809 }
3810
3811 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3812
3813 if (cfg->soft_breakpoints) {
3814 /* Load the address of the breakpoint method into ip. */
3815 var = bp_method_var;
3816 g_assert (var);
3817 g_assert (var->opcode == OP_REGOFFSET);
3818 g_assert (arm_is_imm12 (var->inst_offset));
3819 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3820
3821 /*
3822 * A placeholder for a possible breakpoint inserted by
3823 * mono_arch_set_breakpoint ().
3824 */
3825 ARM_NOP (code);
3826 } else if (cfg->compile_aot) {
3827 guint32 offset = code - cfg->native_code;
3828 guint32 val;
3829
3830 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3831 /* Add the offset */
3832 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3833 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3834 if (val & 0xFF00)
3835 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3836 if (val & 0xFF0000)
3837 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3838 g_assert (!(val & 0xFF000000));
3839 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3840 ARM_LDR_IMM (code, dreg, dreg, 0);
3841
3842 /* What is faster, a branch or a load ? */
3843 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3844 /* The breakpoint instruction */
3845 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3846 } else {
3847 /*
3848 * A placeholder for a possible breakpoint inserted by
3849 * mono_arch_set_breakpoint ().
3850 */
3851 for (i = 0; i < 4; ++i)
3852 ARM_NOP (code);
3853 }
3854 break;
3855 }
3856 case OP_ADDCC:
3857 case OP_IADDCC:
3858 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3859 break;
3860 case OP_IADD:
3861 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3862 break;
3863 case OP_ADC:
3864 case OP_IADC:
3865 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3866 break;
3867 case OP_ADDCC_IMM:
3868 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3869 g_assert (imm8 >= 0);
3870 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3871 break;
3872 case OP_ADD_IMM:
3873 case OP_IADD_IMM:
3874 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3875 g_assert (imm8 >= 0);
3876 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3877 break;
3878 case OP_ADC_IMM:
3879 case OP_IADC_IMM:
3880 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3881 g_assert (imm8 >= 0);
3882 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3883 break;
3884 case OP_IADD_OVF:
3885 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3886 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3887 break;
3888 case OP_IADD_OVF_UN:
3889 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3890 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3891 break;
3892 case OP_ISUB_OVF:
3893 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3894 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3895 break;
3896 case OP_ISUB_OVF_UN:
3897 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3898 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3899 break;
3900 case OP_ADD_OVF_CARRY:
3901 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3902 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3903 break;
3904 case OP_ADD_OVF_UN_CARRY:
3905 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3906 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3907 break;
3908 case OP_SUB_OVF_CARRY:
3909 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3910 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3911 break;
3912 case OP_SUB_OVF_UN_CARRY:
3913 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3914 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3915 break;
3916 case OP_SUBCC:
3917 case OP_ISUBCC:
3918 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3919 break;
3920 case OP_SUBCC_IMM:
3921 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3922 g_assert (imm8 >= 0);
3923 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3924 break;
3925 case OP_ISUB:
3926 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3927 break;
3928 case OP_SBB:
3929 case OP_ISBB:
3930 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3931 break;
3932 case OP_SUB_IMM:
3933 case OP_ISUB_IMM:
3934 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3935 g_assert (imm8 >= 0);
3936 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3937 break;
3938 case OP_SBB_IMM:
3939 case OP_ISBB_IMM:
3940 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3941 g_assert (imm8 >= 0);
3942 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3943 break;
3944 case OP_ARM_RSBS_IMM:
3945 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3946 g_assert (imm8 >= 0);
3947 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3948 break;
3949 case OP_ARM_RSC_IMM:
3950 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3951 g_assert (imm8 >= 0);
3952 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3953 break;
3954 case OP_IAND:
3955 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3956 break;
3957 case OP_AND_IMM:
3958 case OP_IAND_IMM:
3959 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3960 g_assert (imm8 >= 0);
3961 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3962 break;
3963 case OP_IDIV:
3964 case OP_IDIV_UN:
3965 case OP_DIV_IMM:
3966 case OP_IREM:
3967 case OP_IREM_UN:
3968 case OP_REM_IMM:
3969 /* crappy ARM arch doesn't have a DIV instruction */
3970 g_assert_not_reached ();
3971 case OP_IOR:
3972 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3973 break;
3974 case OP_OR_IMM:
3975 case OP_IOR_IMM:
3976 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3977 g_assert (imm8 >= 0);
3978 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3979 break;
3980 case OP_IXOR:
3981 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3982 break;
3983 case OP_XOR_IMM:
3984 case OP_IXOR_IMM:
3985 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3986 g_assert (imm8 >= 0);
3987 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3988 break;
3989 case OP_ISHL:
3990 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3991 break;
3992 case OP_SHL_IMM:
3993 case OP_ISHL_IMM:
3994 if (ins->inst_imm)
3995 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3996 else if (ins->dreg != ins->sreg1)
3997 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3998 break;
3999 case OP_ISHR:
4000 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4001 break;
4002 case OP_SHR_IMM:
4003 case OP_ISHR_IMM:
4004 if (ins->inst_imm)
4005 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4006 else if (ins->dreg != ins->sreg1)
4007 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4008 break;
4009 case OP_SHR_UN_IMM:
4010 case OP_ISHR_UN_IMM:
4011 if (ins->inst_imm)
4012 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4013 else if (ins->dreg != ins->sreg1)
4014 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4015 break;
4016 case OP_ISHR_UN:
4017 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4018 break;
4019 case OP_INOT:
4020 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4021 break;
4022 case OP_INEG:
4023 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4024 break;
4025 case OP_IMUL:
4026 if (ins->dreg == ins->sreg2)
4027 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4028 else
4029 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4030 break;
4031 case OP_MUL_IMM:
4032 g_assert_not_reached ();
4033 break;
4034 case OP_IMUL_OVF:
4035 /* FIXME: handle ovf/ sreg2 != dreg */
4036 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4037 /* FIXME: MUL doesn't set the C/O flags on ARM */
4038 break;
4039 case OP_IMUL_OVF_UN:
4040 /* FIXME: handle ovf/ sreg2 != dreg */
4041 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4042 /* FIXME: MUL doesn't set the C/O flags on ARM */
4043 break;
4044 case OP_ICONST:
4045 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4046 break;
4047 case OP_AOTCONST:
4048 /* Load the GOT offset */
4049 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4050 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4051 ARM_B (code, 0);
4052 *(gpointer*)code = NULL;
4053 code += 4;
4054 /* Load the value from the GOT */
4055 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4056 break;
4057 case OP_ICONV_TO_I4:
4058 case OP_ICONV_TO_U4:
4059 case OP_MOVE:
4060 if (ins->dreg != ins->sreg1)
4061 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4062 break;
4063 case OP_SETLRET: {
4064 int saved = ins->sreg2;
4065 if (ins->sreg2 == ARM_LSW_REG) {
4066 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4067 saved = ARMREG_LR;
4068 }
4069 if (ins->sreg1 != ARM_LSW_REG)
4070 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4071 if (saved != ARM_MSW_REG)
4072 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4073 break;
4074 }
4075 case OP_FMOVE:
4076 if (IS_FPA)
4077 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4078 else if (IS_VFP)
4079 ARM_CPYD (code, ins->dreg, ins->sreg1);
4080 break;
4081 case OP_FCONV_TO_R4:
4082 if (IS_FPA)
4083 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4084 else if (IS_VFP) {
4085 ARM_CVTD (code, ins->dreg, ins->sreg1);
4086 ARM_CVTS (code, ins->dreg, ins->dreg);
4087 }
4088 break;
4089 case OP_JMP:
4090 /*
4091 * Keep in sync with mono_arch_emit_epilog
4092 */
4093 g_assert (!cfg->method->save_lmf);
4094
4095 code = emit_load_volatile_arguments (cfg, code);
4096
4097 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4098 if (iphone_abi) {
4099 if (cfg->used_int_regs)
4100 ARM_POP (code, cfg->used_int_regs);
4101 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4102 } else {
4103 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4104 }
4105 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4106 if (cfg->compile_aot) {
4107 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4108 ARM_B (code, 0);
4109 *(gpointer*)code = NULL;
4110 code += 4;
4111 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4112 } else {
4113 ARM_B (code, 0);
4114 }
4115 break;
4116 case OP_CHECK_THIS:
4117 /* ensure ins->sreg1 is not NULL */
4118 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4119 break;
4120 case OP_ARGLIST: {
4121 g_assert (cfg->sig_cookie < 128);
4122 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4123 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4124 break;
4125 }
4126 case OP_FCALL:
4127 case OP_LCALL:
4128 case OP_VCALL:
4129 case OP_VCALL2:
4130 case OP_VOIDCALL:
4131 case OP_CALL:
4132 call = (MonoCallInst*)ins;
4133 if (ins->flags & MONO_INST_HAS_METHOD)
4134 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4135 else
4136 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4137 code = emit_call_seq (cfg, code);
4138 ins->flags |= MONO_INST_GC_CALLSITE;
4139 ins->backend.pc_offset = code - cfg->native_code;
4140 code = emit_move_return_value (cfg, ins, code);
4141 break;
4142 case OP_FCALL_REG:
4143 case OP_LCALL_REG:
4144 case OP_VCALL_REG:
4145 case OP_VCALL2_REG:
4146 case OP_VOIDCALL_REG:
4147 case OP_CALL_REG:
4148 code = emit_call_reg (code, ins->sreg1);
4149 ins->flags |= MONO_INST_GC_CALLSITE;
4150 ins->backend.pc_offset = code - cfg->native_code;
4151 code = emit_move_return_value (cfg, ins, code);
4152 break;
4153 case OP_FCALL_MEMBASE:
4154 case OP_LCALL_MEMBASE:
4155 case OP_VCALL_MEMBASE:
4156 case OP_VCALL2_MEMBASE:
4157 case OP_VOIDCALL_MEMBASE:
4158 case OP_CALL_MEMBASE: {
4159 gboolean imt_arg = FALSE;
4160
4161 g_assert (ins->sreg1 != ARMREG_LR);
4162 call = (MonoCallInst*)ins;
4163 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE)
4164 imt_arg = TRUE;
4165 if (!arm_is_imm12 (ins->inst_offset))
4166 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
4167 if (imt_arg)
4168 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4169 else
4170 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4171 if (!arm_is_imm12 (ins->inst_offset))
4172 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
4173 else
4174 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4175 if (imt_arg) {
4176 /*
4177 * We can't embed the method in the code stream in PIC code, or
4178 * in gshared code.
4179 * Instead, we put it in V5 in code emitted by
4180 * mono_arch_emit_imt_argument (), and embed NULL here to
4181 * signal the IMT thunk that the value is in V5.
4182 */
4183 if (call->dynamic_imt_arg)
4184 *((gpointer*)code) = NULL;
4185 else
4186 *((gpointer*)code) = (gpointer)call->method;
4187 code += 4;
4188 }
4189 ins->flags |= MONO_INST_GC_CALLSITE;
4190 ins->backend.pc_offset = code - cfg->native_code;
4191 code = emit_move_return_value (cfg, ins, code);
4192 break;
4193 }
4194 case OP_LOCALLOC: {
4195 /* keep alignment */
4196 int alloca_waste = cfg->param_area;
4197 alloca_waste += 7;
4198 alloca_waste &= ~7;
4199 /* round the size to 8 bytes */
4200 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4201 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4202 if (alloca_waste)
4203 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4204 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4205 /* memzero the area: dreg holds the size, sp is the pointer */
4206 if (ins->flags & MONO_INST_INIT) {
4207 guint8 *start_loop, *branch_to_cond;
4208 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4209 branch_to_cond = code;
4210 ARM_B (code, 0);
4211 start_loop = code;
4212 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4213 arm_patch (branch_to_cond, code);
4214 /* decrement by 4 and set flags */
4215 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4216 ARM_B_COND (code, ARMCOND_GE, 0);
4217 arm_patch (code - 4, start_loop);
4218 }
4219 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4220 break;
4221 }
4222 case OP_DYN_CALL: {
4223 int i;
4224 MonoInst *var = cfg->dyn_call_var;
4225
4226 g_assert (var->opcode == OP_REGOFFSET);
4227 g_assert (arm_is_imm12 (var->inst_offset));
4228
4229 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4230 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4231 /* ip = ftn */
4232 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4233
4234 /* Save args buffer */
4235 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4236
4237 /* Set stack slots using R0 as scratch reg */
4238 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4239 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4240 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4241 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4242 }
4243
4244 /* Set argument registers */
4245 for (i = 0; i < PARAM_REGS; ++i)
4246 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4247
4248 /* Make the call */
4249 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4250 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4251
4252 /* Save result */
4253 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4254 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4255 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4256 break;
4257 }
4258 case OP_THROW: {
4259 if (ins->sreg1 != ARMREG_R0)
4260 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4261 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4262 (gpointer)"mono_arch_throw_exception");
4263 code = emit_call_seq (cfg, code);
4264 break;
4265 }
4266 case OP_RETHROW: {
4267 if (ins->sreg1 != ARMREG_R0)
4268 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4269 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4270 (gpointer)"mono_arch_rethrow_exception");
4271 code = emit_call_seq (cfg, code);
4272 break;
4273 }
4274 case OP_START_HANDLER: {
4275 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4276 int i, rot_amount;
4277
4278 /* Reserve a param area, see filter-stack.exe */
4279 if (cfg->param_area) {
4280 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4281 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4282 } else {
4283 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4284 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4285 }
4286 }
4287
4288 if (arm_is_imm12 (spvar->inst_offset)) {
4289 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4290 } else {
4291 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4292 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4293 }
4294 break;
4295 }
4296 case OP_ENDFILTER: {
4297 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4298 int i, rot_amount;
4299
4300 /* Free the param area */
4301 if (cfg->param_area) {
4302 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4303 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4304 } else {
4305 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4306 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4307 }
4308 }
4309
4310 if (ins->sreg1 != ARMREG_R0)
4311 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4312 if (arm_is_imm12 (spvar->inst_offset)) {
4313 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4314 } else {
4315 g_assert (ARMREG_IP != spvar->inst_basereg);
4316 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4317 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4318 }
4319 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4320 break;
4321 }
4322 case OP_ENDFINALLY: {
4323 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4324 int i, rot_amount;
4325
4326 /* Free the param area */
4327 if (cfg->param_area) {
4328 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4329 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4330 } else {
4331 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4332 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4333 }
4334 }
4335
4336 if (arm_is_imm12 (spvar->inst_offset)) {
4337 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4338 } else {
4339 g_assert (ARMREG_IP != spvar->inst_basereg);
4340 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4341 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4342 }
4343 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4344 break;
4345 }
4346 case OP_CALL_HANDLER:
4347 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4348 ARM_BL (code, 0);
4349 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4350 break;
4351 case OP_LABEL:
4352 ins->inst_c0 = code - cfg->native_code;
4353 break;
4354 case OP_BR:
4355 /*if (ins->inst_target_bb->native_offset) {
4356 ARM_B (code, 0);
4357 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4358 } else*/ {
4359 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4360 ARM_B (code, 0);
4361 }
4362 break;
4363 case OP_BR_REG:
4364 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4365 break;
4366 case OP_SWITCH:
4367 /*
4368 * In the normal case we have:
4369 * ldr pc, [pc, ins->sreg1 << 2]
4370 * nop
4371 * If aot, we have:
4372 * ldr lr, [pc, ins->sreg1 << 2]
4373 * add pc, pc, lr
4374 * After follows the data.
4375 * FIXME: add aot support.
4376 */
4377 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4378 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4379 if (offset + max_len > (cfg->code_size - 16)) {
4380 cfg->code_size += max_len;
4381 cfg->code_size *= 2;
4382 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4383 code = cfg->native_code + offset;
4384 }
4385 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4386 ARM_NOP (code);
4387 code += 4 * GPOINTER_TO_INT (ins->klass);
4388 break;
4389 case OP_CEQ:
4390 case OP_ICEQ:
4391 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4392 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4393 break;
4394 case OP_CLT:
4395 case OP_ICLT:
4396 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4397 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4398 break;
4399 case OP_CLT_UN:
4400 case OP_ICLT_UN:
4401 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4402 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4403 break;
4404 case OP_CGT:
4405 case OP_ICGT:
4406 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4407 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4408 break;
4409 case OP_CGT_UN:
4410 case OP_ICGT_UN:
4411 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4412 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4413 break;
4414 case OP_COND_EXC_EQ:
4415 case OP_COND_EXC_NE_UN:
4416 case OP_COND_EXC_LT:
4417 case OP_COND_EXC_LT_UN:
4418 case OP_COND_EXC_GT:
4419 case OP_COND_EXC_GT_UN:
4420 case OP_COND_EXC_GE:
4421 case OP_COND_EXC_GE_UN:
4422 case OP_COND_EXC_LE:
4423 case OP_COND_EXC_LE_UN:
4424 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4425 break;
4426 case OP_COND_EXC_IEQ:
4427 case OP_COND_EXC_INE_UN:
4428 case OP_COND_EXC_ILT:
4429 case OP_COND_EXC_ILT_UN:
4430 case OP_COND_EXC_IGT:
4431 case OP_COND_EXC_IGT_UN:
4432 case OP_COND_EXC_IGE:
4433 case OP_COND_EXC_IGE_UN:
4434 case OP_COND_EXC_ILE:
4435 case OP_COND_EXC_ILE_UN:
4436 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4437 break;
4438 case OP_COND_EXC_C:
4439 case OP_COND_EXC_IC:
4440 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4441 break;
4442 case OP_COND_EXC_OV:
4443 case OP_COND_EXC_IOV:
4444 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4445 break;
4446 case OP_COND_EXC_NC:
4447 case OP_COND_EXC_INC:
4448 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4449 break;
4450 case OP_COND_EXC_NO:
4451 case OP_COND_EXC_INO:
4452 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4453 break;
4454 case OP_IBEQ:
4455 case OP_IBNE_UN:
4456 case OP_IBLT:
4457 case OP_IBLT_UN:
4458 case OP_IBGT:
4459 case OP_IBGT_UN:
4460 case OP_IBGE:
4461 case OP_IBGE_UN:
4462 case OP_IBLE:
4463 case OP_IBLE_UN:
4464 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4465 break;
4466
4467 /* floating point opcodes */
4468 #ifdef ARM_FPU_FPA
4469 case OP_R8CONST:
4470 if (cfg->compile_aot) {
4471 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4472 ARM_B (code, 1);
4473 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4474 code += 4;
4475 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4476 code += 4;
4477 } else {
4478 /* FIXME: we can optimize the imm load by dealing with part of
4479 * the displacement in LDFD (aligning to 512).
4480 */
4481 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4482 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4483 }
4484 break;
4485 case OP_R4CONST:
4486 if (cfg->compile_aot) {
4487 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4488 ARM_B (code, 0);
4489 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4490 code += 4;
4491 } else {
4492 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4493 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4494 }
4495 break;
4496 case OP_STORER8_MEMBASE_REG:
4497 /* This is generated by the local regalloc pass which runs after the lowering pass */
4498 if (!arm_is_fpimm8 (ins->inst_offset)) {
4499 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4500 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4501 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4502 } else {
4503 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4504 }
4505 break;
4506 case OP_LOADR8_MEMBASE:
4507 /* This is generated by the local regalloc pass which runs after the lowering pass */
4508 if (!arm_is_fpimm8 (ins->inst_offset)) {
4509 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4510 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4511 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4512 } else {
4513 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4514 }
4515 break;
4516 case OP_STORER4_MEMBASE_REG:
4517 g_assert (arm_is_fpimm8 (ins->inst_offset));
4518 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4519 break;
4520 case OP_LOADR4_MEMBASE:
4521 g_assert (arm_is_fpimm8 (ins->inst_offset));
4522 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4523 break;
4524 case OP_ICONV_TO_R_UN: {
4525 int tmpreg;
4526 tmpreg = ins->dreg == 0? 1: 0;
4527 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4528 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4529 ARM_B_COND (code, ARMCOND_GE, 8);
4530 /* save the temp register */
4531 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4532 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4533 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4534 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4535 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4536 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4537 /* skip the constant pool */
4538 ARM_B (code, 8);
4539 code += 4;
4540 *(int*)code = 0x41f00000;
4541 code += 4;
4542 *(int*)code = 0;
4543 code += 4;
4544 /* FIXME: adjust:
4545 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4546 * adfltd fdest, fdest, ftemp
4547 */
4548 break;
4549 }
4550 case OP_ICONV_TO_R4:
4551 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4552 break;
4553 case OP_ICONV_TO_R8:
4554 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4555 break;
4556
4557 #elif defined(ARM_FPU_VFP)
4558
4559 case OP_R8CONST:
4560 if (cfg->compile_aot) {
4561 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4562 ARM_B (code, 1);
4563 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4564 code += 4;
4565 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4566 code += 4;
4567 } else {
4568 /* FIXME: we can optimize the imm load by dealing with part of
4569 * the displacement in LDFD (aligning to 512).
4570 */
4571 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4572 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4573 }
4574 break;
4575 case OP_R4CONST:
4576 if (cfg->compile_aot) {
4577 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4578 ARM_B (code, 0);
4579 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4580 code += 4;
4581 ARM_CVTS (code, ins->dreg, ins->dreg);
4582 } else {
4583 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4584 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4585 ARM_CVTS (code, ins->dreg, ins->dreg);
4586 }
4587 break;
4588 case OP_STORER8_MEMBASE_REG:
4589 /* This is generated by the local regalloc pass which runs after the lowering pass */
4590 if (!arm_is_fpimm8 (ins->inst_offset)) {
4591 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4592 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4593 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4594 } else {
4595 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4596 }
4597 break;
4598 case OP_LOADR8_MEMBASE:
4599 /* This is generated by the local regalloc pass which runs after the lowering pass */
4600 if (!arm_is_fpimm8 (ins->inst_offset)) {
4601 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4602 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4603 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4604 } else {
4605 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4606 }
4607 break;
4608 case OP_STORER4_MEMBASE_REG:
4609 g_assert (arm_is_fpimm8 (ins->inst_offset));
4610 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4611 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4612 break;
4613 case OP_LOADR4_MEMBASE:
4614 g_assert (arm_is_fpimm8 (ins->inst_offset));
4615 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4616 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4617 break;
4618 case OP_ICONV_TO_R_UN: {
4619 g_assert_not_reached ();
4620 break;
4621 }
4622 case OP_ICONV_TO_R4:
4623 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4624 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4625 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4626 break;
4627 case OP_ICONV_TO_R8:
4628 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4629 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4630 break;
4631
4632 case OP_SETFRET:
4633 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4634 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4635 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4636 } else {
4637 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4638 }
4639 break;
4640
4641 #endif
4642
4643 case OP_FCONV_TO_I1:
4644 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4645 break;
4646 case OP_FCONV_TO_U1:
4647 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4648 break;
4649 case OP_FCONV_TO_I2:
4650 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4651 break;
4652 case OP_FCONV_TO_U2:
4653 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4654 break;
4655 case OP_FCONV_TO_I4:
4656 case OP_FCONV_TO_I:
4657 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4658 break;
4659 case OP_FCONV_TO_U4:
4660 case OP_FCONV_TO_U:
4661 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4662 break;
4663 case OP_FCONV_TO_I8:
4664 case OP_FCONV_TO_U8:
4665 g_assert_not_reached ();
4666 /* Implemented as helper calls */
4667 break;
4668 case OP_LCONV_TO_R_UN:
4669 g_assert_not_reached ();
4670 /* Implemented as helper calls */
4671 break;
4672 case OP_LCONV_TO_OVF_I4_2: {
4673 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4674 /*
4675 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4676 */
4677
4678 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4679 high_bit_not_set = code;
4680 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4681
4682 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4683 valid_negative = code;
4684 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4685 invalid_negative = code;
4686 ARM_B_COND (code, ARMCOND_AL, 0);
4687
4688 arm_patch (high_bit_not_set, code);
4689
4690 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4691 valid_positive = code;
4692 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4693
4694 arm_patch (invalid_negative, code);
4695 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4696
4697 arm_patch (valid_negative, code);
4698 arm_patch (valid_positive, code);
4699
4700 if (ins->dreg != ins->sreg1)
4701 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4702 break;
4703 }
4704 #ifdef ARM_FPU_FPA
4705 case OP_FADD:
4706 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 break;
4708 case OP_FSUB:
4709 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 break;
4711 case OP_FMUL:
4712 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 break;
4714 case OP_FDIV:
4715 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4716 break;
4717 case OP_FNEG:
4718 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4719 break;
4720 #elif defined(ARM_FPU_VFP)
4721 case OP_FADD:
4722 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 break;
4724 case OP_FSUB:
4725 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 break;
4727 case OP_FMUL:
4728 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 break;
4730 case OP_FDIV:
4731 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4732 break;
4733 case OP_FNEG:
4734 ARM_NEGD (code, ins->dreg, ins->sreg1);
4735 break;
4736 #endif
4737 case OP_FREM:
4738 /* emulated */
4739 g_assert_not_reached ();
4740 break;
4741 case OP_FCOMPARE:
4742 if (IS_FPA) {
4743 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4744 } else if (IS_VFP) {
4745 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4746 ARM_FMSTAT (code);
4747 }
4748 break;
4749 case OP_FCEQ:
4750 if (IS_FPA) {
4751 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4752 } else if (IS_VFP) {
4753 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4754 ARM_FMSTAT (code);
4755 }
4756 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4757 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4758 break;
4759 case OP_FCLT:
4760 if (IS_FPA) {
4761 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4762 } else {
4763 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4764 ARM_FMSTAT (code);
4765 }
4766 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4767 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4768 break;
4769 case OP_FCLT_UN:
4770 if (IS_FPA) {
4771 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4772 } else if (IS_VFP) {
4773 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4774 ARM_FMSTAT (code);
4775 }
4776 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4777 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4778 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4779 break;
4780 case OP_FCGT:
4781 /* swapped */
4782 if (IS_FPA) {
4783 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4784 } else if (IS_VFP) {
4785 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4786 ARM_FMSTAT (code);
4787 }
4788 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4789 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4790 break;
4791 case OP_FCGT_UN:
4792 /* swapped */
4793 if (IS_FPA) {
4794 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4795 } else if (IS_VFP) {
4796 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4797 ARM_FMSTAT (code);
4798 }
4799 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4800 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4801 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4802 break;
4803 /* ARM FPA flags table:
4804 * N Less than ARMCOND_MI
4805 * Z Equal ARMCOND_EQ
4806 * C Greater Than or Equal ARMCOND_CS
4807 * V Unordered ARMCOND_VS
4808 */
4809 case OP_FBEQ:
4810 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4811 break;
4812 case OP_FBNE_UN:
4813 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4814 break;
4815 case OP_FBLT:
4816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4817 break;
4818 case OP_FBLT_UN:
4819 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4820 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4821 break;
4822 case OP_FBGT:
4823 case OP_FBGT_UN:
4824 case OP_FBLE:
4825 case OP_FBLE_UN:
4826 g_assert_not_reached ();
4827 break;
4828 case OP_FBGE:
4829 if (IS_VFP) {
4830 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4831 } else {
4832 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4833 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4834 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4835 }
4836 break;
4837 case OP_FBGE_UN:
4838 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4839 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4840 break;
4841
4842 case OP_CKFINITE: {
4843 if (IS_FPA) {
4844 if (ins->dreg != ins->sreg1)
4845 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4846 } else if (IS_VFP) {
4847 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4848 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4849 ARM_B (code, 1);
4850 *(guint32*)code = 0xffffffff;
4851 code += 4;
4852 *(guint32*)code = 0x7fefffff;
4853 code += 4;
4854 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4855 ARM_FMSTAT (code);
4856 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4857 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4858 ARM_FMSTAT (code);
4859 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4860 ARM_CPYD (code, ins->dreg, ins->sreg1);
4861 }
4862 break;
4863 }
4864
4865 case OP_GC_LIVENESS_DEF:
4866 case OP_GC_LIVENESS_USE:
4867 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4868 ins->backend.pc_offset = code - cfg->native_code;
4869 break;
4870 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4871 ins->backend.pc_offset = code - cfg->native_code;
4872 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4873 break;
4874
4875 default:
4876 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4877 g_assert_not_reached ();
4878 }
4879
4880 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4881 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4882 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4883 g_assert_not_reached ();
4884 }
4885
4886 cpos += max_len;
4887
4888 last_ins = ins;
4889 last_offset = offset;
4890 }
4891
4892 cfg->code_len = code - cfg->native_code;
4893 }
4894
4895 #endif /* DISABLE_JIT */
4896
4897 #ifdef HAVE_AEABI_READ_TP
4898 void __aeabi_read_tp (void);
4899 #endif
4900
4901 void
4902 mono_arch_register_lowlevel_calls (void)
4903 {
4904 /* The signature doesn't matter */
4905 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4906 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4907
4908 #ifndef MONO_CROSS_COMPILE
4909 #ifdef HAVE_AEABI_READ_TP
4910 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4911 #endif
4912 #endif
4913 }
4914
4915 #define patch_lis_ori(ip,val) do {\
4916 guint16 *__lis_ori = (guint16*)(ip); \
4917 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4918 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4919 } while (0)
4920
4921 void
4922 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4923 {
4924 MonoJumpInfo *patch_info;
4925 gboolean compile_aot = !run_cctors;
4926
4927 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4928 unsigned char *ip = patch_info->ip.i + code;
4929 const unsigned char *target;
4930
4931 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4932 gpointer *jt = (gpointer*)(ip + 8);
4933 int i;
4934 /* jt is the inlined jump table, 2 instructions after ip
4935 * In the normal case we store the absolute addresses,
4936 * otherwise the displacements.
4937 */
4938 for (i = 0; i < patch_info->data.table->table_size; i++)
4939 jt [i] = code + (int)patch_info->data.table->table [i];
4940 continue;
4941 }
4942 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4943
4944 if (compile_aot) {
4945 switch (patch_info->type) {
4946 case MONO_PATCH_INFO_BB:
4947 case MONO_PATCH_INFO_LABEL:
4948 break;
4949 default:
4950 /* No need to patch these */
4951 continue;
4952 }
4953 }
4954
4955 switch (patch_info->type) {
4956 case MONO_PATCH_INFO_IP:
4957 g_assert_not_reached ();
4958 patch_lis_ori (ip, ip);
4959 continue;
4960 case MONO_PATCH_INFO_METHOD_REL:
4961 g_assert_not_reached ();
4962 *((gpointer *)(ip)) = code + patch_info->data.offset;
4963 continue;
4964 case MONO_PATCH_INFO_METHODCONST:
4965 case MONO_PATCH_INFO_CLASS:
4966 case MONO_PATCH_INFO_IMAGE:
4967 case MONO_PATCH_INFO_FIELD:
4968 case MONO_PATCH_INFO_VTABLE:
4969 case MONO_PATCH_INFO_IID:
4970 case MONO_PATCH_INFO_SFLDA:
4971 case MONO_PATCH_INFO_LDSTR:
4972 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4973 case MONO_PATCH_INFO_LDTOKEN:
4974 g_assert_not_reached ();
4975 /* from OP_AOTCONST : lis + ori */
4976 patch_lis_ori (ip, target);
4977 continue;
4978 case MONO_PATCH_INFO_R4:
4979 case MONO_PATCH_INFO_R8:
4980 g_assert_not_reached ();
4981 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4982 continue;
4983 case MONO_PATCH_INFO_EXC_NAME:
4984 g_assert_not_reached ();
4985 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4986 continue;
4987 case MONO_PATCH_INFO_NONE:
4988 case MONO_PATCH_INFO_BB_OVF:
4989 case MONO_PATCH_INFO_EXC_OVF:
4990 /* everything is dealt with at epilog output time */
4991 continue;
4992 default:
4993 break;
4994 }
4995 arm_patch_general (domain, ip, target, dyn_code_mp);
4996 }
4997 }
4998
4999 #ifndef DISABLE_JIT
5000
5001 /*
5002 * Stack frame layout:
5003 *
5004 * ------------------- fp
5005 * MonoLMF structure or saved registers
5006 * -------------------
5007 * locals
5008 * -------------------
5009 * spilled regs
5010 * -------------------
5011 * optional 8 bytes for tracing
5012 * -------------------
5013 * param area size is cfg->param_area
5014 * ------------------- sp
5015 */
5016 guint8 *
5017 mono_arch_emit_prolog (MonoCompile *cfg)
5018 {
5019 MonoMethod *method = cfg->method;
5020 MonoBasicBlock *bb;
5021 MonoMethodSignature *sig;
5022 MonoInst *inst;
5023 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5024 guint8 *code;
5025 CallInfo *cinfo;
5026 int tracing = 0;
5027 int lmf_offset = 0;
5028 int prev_sp_offset, reg_offset;
5029
5030 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5031 tracing = 1;
5032
5033 sig = mono_method_signature (method);
5034 cfg->code_size = 256 + sig->param_count * 64;
5035 code = cfg->native_code = g_malloc (cfg->code_size);
5036
5037 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5038
5039 alloc_size = cfg->stack_offset;
5040 pos = 0;
5041 prev_sp_offset = 0;
5042
5043 if (!method->save_lmf) {
5044 if (iphone_abi) {
5045 /*
5046 * The iphone uses R7 as the frame pointer, and it points at the saved
5047 * r7+lr:
5048 * <lr>
5049 * r7 -> <r7>
5050 * <rest of frame>
5051 * We can't use r7 as a frame pointer since it points into the middle of
5052 * the frame, so we keep using our own frame pointer.
5053 * FIXME: Optimize this.
5054 */
5055 g_assert (darwin);
5056 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5057 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5058 prev_sp_offset += 8; /* r7 and lr */
5059 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5060 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5061
5062 /* No need to push LR again */
5063 if (cfg->used_int_regs)
5064 ARM_PUSH (code, cfg->used_int_regs);
5065 } else {
5066 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5067 prev_sp_offset += 4;
5068 }
5069 for (i = 0; i < 16; ++i) {
5070 if (cfg->used_int_regs & (1 << i))
5071 prev_sp_offset += 4;
5072 }
5073 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5074 reg_offset = 0;
5075 for (i = 0; i < 16; ++i) {
5076 if ((cfg->used_int_regs & (1 << i))) {
5077 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5078 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5079 reg_offset += 4;
5080 }
5081 }
5082 if (iphone_abi) {
5083 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5084 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5085 } else {
5086 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5087 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5088 }
5089 } else {
5090 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5091 ARM_PUSH (code, 0x5ff0);
5092 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5093 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5094 reg_offset = 0;
5095 for (i = 0; i < 16; ++i) {
5096 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5097 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5098 reg_offset += 4;
5099 }
5100 }
5101 pos += sizeof (MonoLMF) - prev_sp_offset;
5102 lmf_offset = pos;
5103 }
5104 alloc_size += pos;
5105 orig_alloc_size = alloc_size;
5106 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5107 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5108 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5109 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5110 }
5111
5112 /* the stack used in the pushed regs */
5113 if (prev_sp_offset & 4)
5114 alloc_size += 4;
5115 cfg->stack_usage = alloc_size;
5116 if (alloc_size) {
5117 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5118 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5119 } else {
5120 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5121 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5122 }
5123 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5124 }
5125 if (cfg->frame_reg != ARMREG_SP) {
5126 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5127 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5128 }
5129 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5130 prev_sp_offset += alloc_size;
5131
5132 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5133 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5134
5135 /* compute max_offset in order to use short forward jumps
5136 * we could skip do it on arm because the immediate displacement
5137 * for jumps is large enough, it may be useful later for constant pools
5138 */
5139 max_offset = 0;
5140 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5141 MonoInst *ins = bb->code;
5142 bb->max_offset = max_offset;
5143
5144 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5145 max_offset += 6;
5146
5147 MONO_BB_FOR_EACH_INS (bb, ins)
5148 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5149 }
5150
5151 /* store runtime generic context */
5152 if (cfg->rgctx_var) {
5153 MonoInst *ins = cfg->rgctx_var;
5154
5155 g_assert (ins->opcode == OP_REGOFFSET);
5156
5157 if (arm_is_imm12 (ins->inst_offset)) {
5158 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5159 } else {
5160 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5161 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5162 }
5163 }
5164
5165 /* load arguments allocated to register from the stack */
5166 pos = 0;
5167
5168 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5169
5170 if (cinfo->vtype_retaddr) {
5171 ArgInfo *ainfo = &cinfo->ret;
5172 inst = cfg->vret_addr;
5173 g_assert (arm_is_imm12 (inst->inst_offset));
5174 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5175 }
5176
5177 if (sig->call_convention == MONO_CALL_VARARG) {
5178 ArgInfo *cookie = &cinfo->sig_cookie;
5179
5180 /* Save the sig cookie address */
5181 g_assert (cookie->storage == RegTypeBase);
5182
5183 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5184 g_assert (arm_is_imm12 (cfg->sig_cookie));
5185 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5186 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5187 }
5188
5189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5190 ArgInfo *ainfo = cinfo->args + i;
5191 inst = cfg->args [pos];
5192
5193 if (cfg->verbose_level > 2)
5194 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5195 if (inst->opcode == OP_REGVAR) {
5196 if (ainfo->storage == RegTypeGeneral)
5197 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5198 else if (ainfo->storage == RegTypeFP) {
5199 g_assert_not_reached ();
5200 } else if (ainfo->storage == RegTypeBase) {
5201 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5202 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5203 } else {
5204 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5205 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5206 }
5207 } else
5208 g_assert_not_reached ();
5209
5210 if (cfg->verbose_level > 2)
5211 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5212 } else {
5213 /* the argument should be put on the stack: FIXME handle size != word */
5214 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5215 switch (ainfo->size) {
5216 case 1:
5217 if (arm_is_imm12 (inst->inst_offset))
5218 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5219 else {
5220 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5221 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5222 }
5223 break;
5224 case 2:
5225 if (arm_is_imm8 (inst->inst_offset)) {
5226 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5227 } else {
5228 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5229 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5230 }
5231 break;
5232 case 8:
5233 if (arm_is_imm12 (inst->inst_offset)) {
5234 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5235 } else {
5236 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5237 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5238 }
5239 if (arm_is_imm12 (inst->inst_offset + 4)) {
5240 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5241 } else {
5242 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5243 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5244 }
5245 break;
5246 default:
5247 if (arm_is_imm12 (inst->inst_offset)) {
5248 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5249 } else {
5250 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5251 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5252 }
5253 break;
5254 }
5255 } else if (ainfo->storage == RegTypeBaseGen) {
5256 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5257 g_assert (arm_is_imm12 (inst->inst_offset));
5258 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5259 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5260 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5261 } else if (ainfo->storage == RegTypeBase) {
5262 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5263 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5264 } else {
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5266 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5267 }
5268
5269 switch (ainfo->size) {
5270 case 1:
5271 if (arm_is_imm8 (inst->inst_offset)) {
5272 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5273 } else {
5274 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5275 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5276 }
5277 break;
5278 case 2:
5279 if (arm_is_imm8 (inst->inst_offset)) {
5280 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5281 } else {
5282 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5283 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5284 }
5285 break;
5286 case 8:
5287 if (arm_is_imm12 (inst->inst_offset)) {
5288 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5289 } else {
5290 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5291 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5292 }
5293 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5295 } else {
5296 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5297 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5298 }
5299 if (arm_is_imm12 (inst->inst_offset + 4)) {
5300 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5301 } else {
5302 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5303 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5304 }
5305 break;
5306 default:
5307 if (arm_is_imm12 (inst->inst_offset)) {
5308 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5309 } else {
5310 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5311 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5312 }
5313 break;
5314 }
5315 } else if (ainfo->storage == RegTypeFP) {
5316 g_assert_not_reached ();
5317 } else if (ainfo->storage == RegTypeStructByVal) {
5318 int doffset = inst->inst_offset;
5319 int soffset = 0;
5320 int cur_reg;
5321 int size = 0;
5322 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5323 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5324 if (arm_is_imm12 (doffset)) {
5325 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5326 } else {
5327 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5328 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5329 }
5330 soffset += sizeof (gpointer);
5331 doffset += sizeof (gpointer);
5332 }
5333 if (ainfo->vtsize) {
5334 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5335 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5336 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5337 }
5338 } else if (ainfo->storage == RegTypeStructByAddr) {
5339 g_assert_not_reached ();
5340 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5341 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5342 } else
5343 g_assert_not_reached ();
5344 }
5345 pos++;
5346 }
5347
5348 if (method->save_lmf)
5349 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5350
5351 if (tracing)
5352 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5353
5354 if (cfg->arch.seq_point_info_var) {
5355 MonoInst *ins = cfg->arch.seq_point_info_var;
5356
5357 /* Initialize the variable from a GOT slot */
5358 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5359 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5360 ARM_B (code, 0);
5361 *(gpointer*)code = NULL;
5362 code += 4;
5363 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5364
5365 g_assert (ins->opcode == OP_REGOFFSET);
5366
5367 if (arm_is_imm12 (ins->inst_offset)) {
5368 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5369 } else {
5370 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5371 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5372 }
5373 }
5374
5375 /* Initialize ss_trigger_page_var */
5376 if (!cfg->soft_breakpoints) {
5377 MonoInst *info_var = cfg->arch.seq_point_info_var;
5378 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5379 int dreg = ARMREG_LR;
5380
5381 if (info_var) {
5382 g_assert (info_var->opcode == OP_REGOFFSET);
5383 g_assert (arm_is_imm12 (info_var->inst_offset));
5384
5385 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5386 /* Load the trigger page addr */
5387 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5388 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5389 }
5390 }
5391
5392 if (cfg->arch.seq_point_read_var) {
5393 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5394 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5395 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5396
5397 g_assert (read_ins->opcode == OP_REGOFFSET);
5398 g_assert (arm_is_imm12 (read_ins->inst_offset));
5399 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5400 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5401 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5402 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5403
5404 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5405 ARM_B (code, 2);
5406 *(volatile int **)code = &ss_trigger_var;
5407 code += 4;
5408 *(gpointer*)code = single_step_func_wrapper;
5409 code += 4;
5410 *(gpointer*)code = breakpoint_func_wrapper;
5411 code += 4;
5412
5413 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5414 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5415 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5416 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5417 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5418 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5419 }
5420
5421 cfg->code_len = code - cfg->native_code;
5422 g_assert (cfg->code_len < cfg->code_size);
5423 g_free (cinfo);
5424
5425 return code;
5426 }
5427
5428 void
5429 mono_arch_emit_epilog (MonoCompile *cfg)
5430 {
5431 MonoMethod *method = cfg->method;
5432 int pos, i, rot_amount;
5433 int max_epilog_size = 16 + 20*4;
5434 guint8 *code;
5435 CallInfo *cinfo;
5436
5437 if (cfg->method->save_lmf)
5438 max_epilog_size += 128;
5439
5440 if (mono_jit_trace_calls != NULL)
5441 max_epilog_size += 50;
5442
5443 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5444 max_epilog_size += 50;
5445
5446 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5447 cfg->code_size *= 2;
5448 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5449 cfg->stat_code_reallocs++;
5450 }
5451
5452 /*
5453 * Keep in sync with OP_JMP
5454 */
5455 code = cfg->native_code + cfg->code_len;
5456
5457 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5458 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5459 }
5460 pos = 0;
5461
5462 /* Load returned vtypes into registers if needed */
5463 cinfo = cfg->arch.cinfo;
5464 if (cinfo->ret.storage == RegTypeStructByVal) {
5465 MonoInst *ins = cfg->ret;
5466
5467 if (arm_is_imm12 (ins->inst_offset)) {
5468 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5469 } else {
5470 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5471 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5472 }
5473 }
5474
5475 if (method->save_lmf) {
5476 int lmf_offset, reg, sp_adj, regmask;
5477 /* all but r0-r3, sp and pc */
5478 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5479 lmf_offset = pos;
5480
5481 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5482
5483 /* This points to r4 inside MonoLMF->iregs */
5484 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5485 reg = ARMREG_R4;
5486 regmask = 0x9ff0; /* restore lr to pc */
5487 /* Skip caller saved registers not used by the method */
5488 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5489 regmask &= ~(1 << reg);
5490 sp_adj += 4;
5491 reg ++;
5492 }
5493 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5494 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5495 /* restore iregs */
5496 ARM_POP (code, regmask);
5497 } else {
5498 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5499 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5500 } else {
5501 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5502 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5503 }
5504
5505 if (iphone_abi) {
5506 /* Restore saved gregs */
5507 if (cfg->used_int_regs)
5508 ARM_POP (code, cfg->used_int_regs);
5509 /* Restore saved r7, restore LR to PC */
5510 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5511 } else {
5512 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5513 }
5514 }
5515
5516 cfg->code_len = code - cfg->native_code;
5517
5518 g_assert (cfg->code_len < cfg->code_size);
5519
5520 }
5521
5522 /* remove once throw_exception_by_name is eliminated */
5523 static int
5524 exception_id_by_name (const char *name)
5525 {
5526 if (strcmp (name, "IndexOutOfRangeException") == 0)
5527 return MONO_EXC_INDEX_OUT_OF_RANGE;
5528 if (strcmp (name, "OverflowException") == 0)
5529 return MONO_EXC_OVERFLOW;
5530 if (strcmp (name, "ArithmeticException") == 0)
5531 return MONO_EXC_ARITHMETIC;
5532 if (strcmp (name, "DivideByZeroException") == 0)
5533 return MONO_EXC_DIVIDE_BY_ZERO;
5534 if (strcmp (name, "InvalidCastException") == 0)
5535 return MONO_EXC_INVALID_CAST;
5536 if (strcmp (name, "NullReferenceException") == 0)
5537 return MONO_EXC_NULL_REF;
5538 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5539 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5540 if (strcmp (name, "ArgumentException") == 0)
5541 return MONO_EXC_ARGUMENT;
5542 g_error ("Unknown intrinsic exception %s\n", name);
5543 return -1;
5544 }
5545
5546 void
5547 mono_arch_emit_exceptions (MonoCompile *cfg)
5548 {
5549 MonoJumpInfo *patch_info;
5550 int i;
5551 guint8 *code;
5552 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5553 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5554 int max_epilog_size = 50;
5555
5556 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5557 exc_throw_pos [i] = NULL;
5558 exc_throw_found [i] = 0;
5559 }
5560
5561 /* count the number of exception infos */
5562
5563 /*
5564 * make sure we have enough space for exceptions
5565 */
5566 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5567 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5568 i = exception_id_by_name (patch_info->data.target);
5569 if (!exc_throw_found [i]) {
5570 max_epilog_size += 32;
5571 exc_throw_found [i] = TRUE;
5572 }
5573 }
5574 }
5575
5576 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5577 cfg->code_size *= 2;
5578 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5579 cfg->stat_code_reallocs++;
5580 }
5581
5582 code = cfg->native_code + cfg->code_len;
5583
5584 /* add code to raise exceptions */
5585 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5586 switch (patch_info->type) {
5587 case MONO_PATCH_INFO_EXC: {
5588 MonoClass *exc_class;
5589 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5590
5591 i = exception_id_by_name (patch_info->data.target);
5592 if (exc_throw_pos [i]) {
5593 arm_patch (ip, exc_throw_pos [i]);
5594 patch_info->type = MONO_PATCH_INFO_NONE;
5595 break;
5596 } else {
5597 exc_throw_pos [i] = code;
5598 }
5599 arm_patch (ip, code);
5600
5601 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5602 g_assert (exc_class);
5603
5604 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5605 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5606 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5607 patch_info->data.name = "mono_arch_throw_corlib_exception";
5608 patch_info->ip.i = code - cfg->native_code;
5609 ARM_BL (code, 0);
5610 *(guint32*)(gpointer)code = exc_class->type_token;
5611 code += 4;
5612 break;
5613 }
5614 default:
5615 /* do nothing */
5616 break;
5617 }
5618 }
5619
5620 cfg->code_len = code - cfg->native_code;
5621
5622 g_assert (cfg->code_len < cfg->code_size);
5623
5624 }
5625
5626 #endif /* #ifndef DISABLE_JIT */
5627
5628 void
5629 mono_arch_finish_init (void)
5630 {
5631 lmf_tls_offset = mono_get_lmf_tls_offset ();
5632 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5633 }
5634
5635 void
5636 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5637 {
5638 }
5639
5640 MonoInst*
5641 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5642 {
5643 /* FIXME: */
5644 return NULL;
5645 }
5646
5647 gboolean
5648 mono_arch_print_tree (MonoInst *tree, int arity)
5649 {
5650 return 0;
5651 }
5652
5653 MonoInst*
5654 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5655 {
5656 return mono_get_domain_intrinsic (cfg);
5657 }
5658
5659 guint32
5660 mono_arch_get_patch_offset (guint8 *code)
5661 {
5662 /* OP_AOTCONST */
5663 return 8;
5664 }
5665
5666 void
5667 mono_arch_flush_register_windows (void)
5668 {
5669 }
5670
5671 #ifdef MONO_ARCH_HAVE_IMT
5672
5673 #ifndef DISABLE_JIT
5674
5675 void
5676 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5677 {
5678 if (cfg->compile_aot) {
5679 int method_reg = mono_alloc_ireg (cfg);
5680 MonoInst *ins;
5681
5682 call->dynamic_imt_arg = TRUE;
5683
5684 if (imt_arg) {
5685 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5686 } else {
5687 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5688 ins->dreg = method_reg;
5689 ins->inst_p0 = call->method;
5690 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5691 MONO_ADD_INS (cfg->cbb, ins);
5692
5693 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5694 }
5695 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5696
5697 /* Always pass in a register for simplicity */
5698 call->dynamic_imt_arg = TRUE;
5699
5700 cfg->uses_rgctx_reg = TRUE;
5701
5702 if (imt_arg) {
5703 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5704 } else {
5705 MonoInst *ins;
5706 int method_reg = mono_alloc_preg (cfg);
5707
5708 MONO_INST_NEW (cfg, ins, OP_PCONST);
5709 ins->inst_p0 = call->method;
5710 ins->dreg = method_reg;
5711 MONO_ADD_INS (cfg->cbb, ins);
5712
5713 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5714 }
5715 }
5716 }
5717
5718 #endif /* DISABLE_JIT */
5719
5720 MonoMethod*
5721 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5722 {
5723 guint32 *code_ptr = (guint32*)code;
5724 code_ptr -= 2;
5725
5726 if (mono_use_llvm)
5727 /* Passed in V5 */
5728 return (MonoMethod*)regs [ARMREG_V5];
5729
5730 /* The IMT value is stored in the code stream right after the LDC instruction. */
5731 if (!IS_LDR_PC (code_ptr [0])) {
5732 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5733 g_assert (IS_LDR_PC (code_ptr [0]));
5734 }
5735 if (code_ptr [1] == 0)
5736 /* This is AOTed code, the IMT method is in V5 */
5737 return (MonoMethod*)regs [ARMREG_V5];
5738 else
5739 return (MonoMethod*) code_ptr [1];
5740 }
5741
5742 MonoVTable*
5743 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5744 {
5745 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5746 }
5747
5748 #define ENABLE_WRONG_METHOD_CHECK 0
5749 #define BASE_SIZE (6 * 4)
5750 #define BSEARCH_ENTRY_SIZE (4 * 4)
5751 #define CMP_SIZE (3 * 4)
5752 #define BRANCH_SIZE (1 * 4)
5753 #define CALL_SIZE (2 * 4)
5754 #define WMC_SIZE (5 * 4)
5755 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5756
5757 static arminstr_t *
5758 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5759 {
5760 guint32 delta = DISTANCE (target, code);
5761 delta -= 8;
5762 g_assert (delta >= 0 && delta <= 0xFFF);
5763 *target = *target | delta;
5764 *code = value;
5765 return code + 1;
5766 }
5767
5768 gpointer
5769 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5770 gpointer fail_tramp)
5771 {
5772 int size, i, extra_space = 0;
5773 arminstr_t *code, *start, *vtable_target = NULL;
5774 gboolean large_offsets = FALSE;
5775 guint32 **constant_pool_starts;
5776
5777 size = BASE_SIZE;
5778 constant_pool_starts = g_new0 (guint32*, count);
5779
5780 for (i = 0; i < count; ++i) {
5781 MonoIMTCheckItem *item = imt_entries [i];
5782 if (item->is_equals) {
5783 gboolean fail_case = !item->check_target_idx && fail_tramp;
5784
5785 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5786 item->chunk_size += 32;
5787 large_offsets = TRUE;
5788 }
5789
5790 if (item->check_target_idx || fail_case) {
5791 if (!item->compare_done || fail_case)
5792 item->chunk_size += CMP_SIZE;
5793 item->chunk_size += BRANCH_SIZE;
5794 } else {
5795 #if ENABLE_WRONG_METHOD_CHECK
5796 item->chunk_size += WMC_SIZE;
5797 #endif
5798 }
5799 if (fail_case) {
5800 item->chunk_size += 16;
5801 large_offsets = TRUE;
5802 }
5803 item->chunk_size += CALL_SIZE;
5804 } else {
5805 item->chunk_size += BSEARCH_ENTRY_SIZE;
5806 imt_entries [item->check_target_idx]->compare_done = TRUE;
5807 }
5808 size += item->chunk_size;
5809 }
5810
5811 if (large_offsets)
5812 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5813
5814 if (fail_tramp)
5815 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5816 else
5817 code = mono_domain_code_reserve (domain, size);
5818 start = code;
5819
5820 #if DEBUG_IMT
5821 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5822 for (i = 0; i < count; ++i) {
5823 MonoIMTCheckItem *item = imt_entries [i];
5824 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5825 }
5826 #endif
5827
5828 if (large_offsets)
5829 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5830 else
5831 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5832 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5833 vtable_target = code;
5834 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5835
5836 if (mono_use_llvm) {
5837 /* LLVM always passes the IMT method in R5 */
5838 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5839 } else {
5840 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5841 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5842 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5843 }
5844
5845 for (i = 0; i < count; ++i) {
5846 MonoIMTCheckItem *item = imt_entries [i];
5847 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5848 gint32 vtable_offset;
5849
5850 item->code_target = (guint8*)code;
5851
5852 if (item->is_equals) {
5853 gboolean fail_case = !item->check_target_idx && fail_tramp;
5854
5855 if (item->check_target_idx || fail_case) {
5856 if (!item->compare_done || fail_case) {
5857 imt_method = code;
5858 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5859 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5860 }
5861 item->jmp_code = (guint8*)code;
5862 ARM_B_COND (code, ARMCOND_NE, 0);
5863 } else {
5864 /*Enable the commented code to assert on wrong method*/
5865 #if ENABLE_WRONG_METHOD_CHECK
5866 imt_method = code;
5867 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5868 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5869 ARM_B_COND (code, ARMCOND_NE, 1);
5870
5871 ARM_DBRK (code);
5872 #endif
5873 }
5874
5875 if (item->has_target_code) {
5876 target_code_ins = code;
5877 /* Load target address */
5878 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5879 /* Save it to the fourth slot */
5880 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5881 /* Restore registers and branch */
5882 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5883
5884 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5885 } else {
5886 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5887 if (!arm_is_imm12 (vtable_offset)) {
5888 /*
5889 * We need to branch to a computed address but we don't have
5890 * a free register to store it, since IP must contain the
5891 * vtable address. So we push the two values to the stack, and
5892 * load them both using LDM.
5893 */
5894 /* Compute target address */
5895 vtable_offset_ins = code;
5896 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5897 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5898 /* Save it to the fourth slot */
5899 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5900 /* Restore registers and branch */
5901 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5902
5903 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5904 } else {
5905 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5906 if (large_offsets)
5907 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5908 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5909 }
5910 }
5911
5912 if (fail_case) {
5913 arm_patch (item->jmp_code, (guchar*)code);
5914
5915 target_code_ins = code;
5916 /* Load target address */
5917 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5918 /* Save it to the fourth slot */
5919 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5920 /* Restore registers and branch */
5921 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5922
5923 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5924 item->jmp_code = NULL;
5925 }
5926
5927 if (imt_method)
5928 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5929
5930 /*must emit after unconditional branch*/
5931 if (vtable_target) {
5932 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5933 item->chunk_size += 4;
5934 vtable_target = NULL;
5935 }
5936
5937 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5938 constant_pool_starts [i] = code;
5939 if (extra_space) {
5940 code += extra_space;
5941 extra_space = 0;
5942 }
5943 } else {
5944 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5945 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5946
5947 item->jmp_code = (guint8*)code;
5948 ARM_B_COND (code, ARMCOND_GE, 0);
5949 ++extra_space;
5950 }
5951 }
5952
5953 for (i = 0; i < count; ++i) {
5954 MonoIMTCheckItem *item = imt_entries [i];
5955 if (item->jmp_code) {
5956 if (item->check_target_idx)
5957 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5958 }
5959 if (i > 0 && item->is_equals) {
5960 int j;
5961 arminstr_t *space_start = constant_pool_starts [i];
5962 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5963 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5964 }
5965 }
5966 }
5967
5968 #if DEBUG_IMT
5969 {
5970 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5971 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5972 g_free (buff);
5973 }
5974 #endif
5975
5976 g_free (constant_pool_starts);
5977
5978 mono_arch_flush_icache ((guint8*)start, size);
5979 mono_stats.imt_thunks_size += code - start;
5980
5981 g_assert (DISTANCE (start, code) <= size);
5982 return start;
5983 }
5984
5985 #endif
5986
5987 mgreg_t
5988 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5989 {
5990 return ctx->regs [reg];
5991 }
5992
5993 void
5994 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5995 {
5996 ctx->regs [reg] = val;
5997 }
5998
5999 /*
6000 * mono_arch_get_trampolines:
6001 *
6002 * Return a list of MonoTrampInfo structures describing arch specific trampolines
6003 * for AOT.
6004 */
6005 GSList *
6006 mono_arch_get_trampolines (gboolean aot)
6007 {
6008 return mono_arm_get_exception_trampolines (aot);
6009 }
6010
6011 /*
6012 * mono_arch_set_breakpoint:
6013 *
6014 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6015 * The location should contain code emitted by OP_SEQ_POINT.
6016 */
6017 void
6018 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6019 {
6020 guint8 *code = ip;
6021 guint32 native_offset = ip - (guint8*)ji->code_start;
6022 MonoDebugOptions *opt = mini_get_debug_options ();
6023
6024 if (opt->soft_breakpoints) {
6025 g_assert (!ji->from_aot);
6026 code += 4;
6027 ARM_BLX_REG (code, ARMREG_LR);
6028 mono_arch_flush_icache (code - 4, 4);
6029 } else if (ji->from_aot) {
6030 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6031
6032 g_assert (native_offset % 4 == 0);
6033 g_assert (info->bp_addrs [native_offset / 4] == 0);
6034 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6035 } else {
6036 int dreg = ARMREG_LR;
6037
6038 /* Read from another trigger page */
6039 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6040 ARM_B (code, 0);
6041 *(int*)code = (int)bp_trigger_page;
6042 code += 4;
6043 ARM_LDR_IMM (code, dreg, dreg, 0);
6044
6045 mono_arch_flush_icache (code - 16, 16);
6046
6047 #if 0
6048 /* This is currently implemented by emitting an SWI instruction, which
6049 * qemu/linux seems to convert to a SIGILL.
6050 */
6051 *(int*)code = (0xef << 24) | 8;
6052 code += 4;
6053 mono_arch_flush_icache (code - 4, 4);
6054 #endif
6055 }
6056 }
6057
6058 /*
6059 * mono_arch_clear_breakpoint:
6060 *
6061 * Clear the breakpoint at IP.
6062 */
6063 void
6064 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6065 {
6066 MonoDebugOptions *opt = mini_get_debug_options ();
6067 guint8 *code = ip;
6068 int i;
6069
6070 if (opt->soft_breakpoints) {
6071 g_assert (!ji->from_aot);
6072 code += 4;
6073 ARM_NOP (code);
6074 mono_arch_flush_icache (code - 4, 4);
6075 } else if (ji->from_aot) {
6076 guint32 native_offset = ip - (guint8*)ji->code_start;
6077 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6078
6079 g_assert (native_offset % 4 == 0);
6080 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6081 info->bp_addrs [native_offset / 4] = 0;
6082 } else {
6083 for (i = 0; i < 4; ++i)
6084 ARM_NOP (code);
6085
6086 mono_arch_flush_icache (ip, code - ip);
6087 }
6088 }
6089
6090 /*
6091 * mono_arch_start_single_stepping:
6092 *
6093 * Start single stepping.
6094 */
6095 void
6096 mono_arch_start_single_stepping (void)
6097 {
6098 if (ss_trigger_page)
6099 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6100 else
6101 ss_trigger_var = 1;
6102 }
6103
6104 /*
6105 * mono_arch_stop_single_stepping:
6106 *
6107 * Stop single stepping.
6108 */
6109 void
6110 mono_arch_stop_single_stepping (void)
6111 {
6112 if (ss_trigger_page)
6113 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6114 else
6115 ss_trigger_var = 0;
6116 }
6117
6118 #if __APPLE__
6119 #define DBG_SIGNAL SIGBUS
6120 #else
6121 #define DBG_SIGNAL SIGSEGV
6122 #endif
6123
6124 /*
6125 * mono_arch_is_single_step_event:
6126 *
6127 * Return whenever the machine state in SIGCTX corresponds to a single
6128 * step event.
6129 */
6130 gboolean
6131 mono_arch_is_single_step_event (void *info, void *sigctx)
6132 {
6133 siginfo_t *sinfo = info;
6134
6135 if (!ss_trigger_page)
6136 return FALSE;
6137
6138 /* Sometimes the address is off by 4 */
6139 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6140 return TRUE;
6141 else
6142 return FALSE;
6143 }
6144
6145 /*
6146 * mono_arch_is_breakpoint_event:
6147 *
6148 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6149 */
6150 gboolean
6151 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6152 {
6153 siginfo_t *sinfo = info;
6154
6155 if (!ss_trigger_page)
6156 return FALSE;
6157
6158 if (sinfo->si_signo == DBG_SIGNAL) {
6159 /* Sometimes the address is off by 4 */
6160 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6161 return TRUE;
6162 else
6163 return FALSE;
6164 } else {
6165 return FALSE;
6166 }
6167 }
6168
6169 /*
6170 * mono_arch_skip_breakpoint:
6171 *
6172 * See mini-amd64.c for docs.
6173 */
6174 void
6175 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6176 {
6177 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6178 }
6179
6180 /*
6181 * mono_arch_skip_single_step:
6182 *
6183 * See mini-amd64.c for docs.
6184 */
6185 void
6186 mono_arch_skip_single_step (MonoContext *ctx)
6187 {
6188 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6189 }
6190
6191 /*
6192 * mono_arch_get_seq_point_info:
6193 *
6194 * See mini-amd64.c for docs.
6195 */
6196 gpointer
6197 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6198 {
6199 SeqPointInfo *info;
6200 MonoJitInfo *ji;
6201
6202 // FIXME: Add a free function
6203
6204 mono_domain_lock (domain);
6205 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6206 code);
6207 mono_domain_unlock (domain);
6208
6209 if (!info) {
6210 ji = mono_jit_info_table_find (domain, (char*)code);
6211 g_assert (ji);
6212
6213 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6214
6215 info->ss_trigger_page = ss_trigger_page;
6216 info->bp_trigger_page = bp_trigger_page;
6217
6218 mono_domain_lock (domain);
6219 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6220 code, info);
6221 mono_domain_unlock (domain);
6222 }
6223
6224 return info;
6225 }
6226
6227 /*
6228 * mono_arch_set_target:
6229 *
6230 * Set the target architecture the JIT backend should generate code for, in the form
6231 * of a GNU target triplet. Only used in AOT mode.
6232 */
6233 void
6234 mono_arch_set_target (char *mtriple)
6235 {
6236 /* The GNU target triple format is not very well documented */
6237 if (strstr (mtriple, "armv7")) {
6238 v6_supported = TRUE;
6239 v7_supported = TRUE;
6240 }
6241 if (strstr (mtriple, "armv6")) {
6242 v6_supported = TRUE;
6243 }
6244 if (strstr (mtriple, "darwin")) {
6245 v5_supported = TRUE;
6246 thumb_supported = TRUE;
6247 darwin = TRUE;
6248 iphone_abi = TRUE;
6249 }
6250 if (strstr (mtriple, "gnueabi"))
6251 eabi_supported = TRUE;
6252 }
6253
6254 #ifdef MONOTOUCH
6255
6256 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
6257
6258 #else
6259
6260 gboolean
6261 mono_arch_gsharedvt_sig_supported (MonoMethodSignature *sig)
6262 {
6263 return FALSE;
6264 }
6265
6266 gpointer
6267 mono_arch_get_gsharedvt_call_info (gpointer addr, MonoMethod *normal_method, MonoMethod *gsharedvt_method, MonoGenericSharingContext *gsctx, gboolean gsharedvt_in, gint32 vcall_offset)
6268 {
6269 NOT_IMPLEMENTED;
6270 return NULL;
6271 }
6272
6273 #endif /* !MONOTOUCH */
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