| blob | 21f842f016f1f3478c803047d73e4fdfe9b5a263 |
1 /*
2 * mini-amd64.c: AMD64 backend for the Mono code generator
3 *
4 * Based on mini-x86.c.
5 *
6 * Authors:
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
9 * Patrik Torstensson
10 * Zoltan Varga (vargaz@gmail.com)
11 *
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 */
17 #include <string.h>
18 #include <math.h>
19 #ifdef HAVE_UNISTD_H
20 #include <unistd.h>
21 #endif
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
45 #ifdef MONO_XEN_OPT
47 #else
48 #define optimize_for_xen 0
49 #endif
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 #ifdef HOST_WIN32
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #else
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
62 #endif
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
69 MonoBreakpointInfo
72 /* Structure used by the sequence points in AOTed code */
74 gpointer ss_trigger_page;
75 gpointer bp_trigger_page;
79 /*
80 * The code generated for sequence points reads from this location, which is
81 * made read-only when single stepping is enabled.
82 */
85 /* Enabled breakpoints read from this trigger page */
88 /* The size of the breakpoint sequence */
91 /* The size of the breakpoint instruction causing the actual fault */
94 /* The size of the single step instruction causing the actual fault */
97 #ifdef HOST_WIN32
98 /* On Win64 always reserve first 32 bytes for first four arguments */
99 #define ARGS_OFFSET 48
100 #else
101 #define ARGS_OFFSET 16
102 #endif
103 #define GP_SCRATCH_REG AMD64_R11
105 /*
106 * AMD64 register usage:
107 * - callee saved registers are used for global register allocation
108 * - %r11 is used for materializing 64 bit constants in opcodes
109 * - the rest is used for local allocation
110 */
112 /*
113 * Floating point comparison results:
114 * ZF PF CF
115 * A > B 0 0 0
116 * A < B 0 0 1
117 * A = B 1 0 0
118 * A > B 0 0 0
119 * UNORDERED 1 1 1
120 */
124 {
142 }
144 }
149 };
154 };
158 {
161 else
163 }
167 {
170 else
172 }
174 static gboolean
176 {
177 #if 0
179 #else
181 #endif
182 }
186 {
187 /* Skip REX */
192 }
194 #ifdef __native_client_codegen__
196 /* Keep track of instruction "depth", that is, the level of sub-instruction */
197 /* for any given instruction. For instance, amd64_call_reg resolves to */
198 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
199 /* We only want to force bundle alignment for the top level instruction, */
200 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
206 void
208 {
210 }
212 void
214 {
217 }
219 void
221 {
223 }
225 guint8*
227 {
229 }
231 guint8*
233 {
235 }
237 /* Increment the instruction "depth" described above */
238 void
240 {
242 depth++;
244 }
246 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
247 /* alignment if depth == 0 (top level instruction) */
248 /* IN: start, end pointers to instruction beginning and end */
249 /* OUT: start, end pointers to beginning and end after possible alignment */
250 /* GLOBALS: nacl_instruction_depth defined above */
251 void
253 {
255 depth--;
263 /* if legacy prefix is present, and if it was emitted before */
264 /* the start of the instruction sequence, adjust the start */
268 }
271 /* Only check for instructions which are less than */
272 /* kNaClAlignment. The only instructions that should ever */
273 /* be that long are call sequences, which are already */
274 /* padded out to align the return to the next bundle. */
285 }
288 }
289 }
291 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
292 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
293 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
294 /* make sure the upper 32-bits are cleared, and use that register in the */
295 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
296 /* IN: code */
297 /* pointer to current instruction stream (in the */
298 /* middle of an instruction, after opcode is emitted) */
299 /* basereg/offset/dreg */
300 /* operands of normal membase address */
301 /* OUT: code */
302 /* pointer to the end of the membase/memindex emit */
303 /* GLOBALS: nacl_rex_tag */
304 /* position in instruction stream that rex prefix was emitted */
305 /* nacl_legacy_prefix_tag */
306 /* (possibly NULL) position in instruction of legacy x86 prefix */
307 void
309 {
312 /* Cache these values, they might change */
313 /* as new instructions are emitted below. */
317 /* 'basereg' is given masked to 0x7 at this point, so check */
318 /* the rex prefix to see if this is an extended register. */
321 }
323 #define X86_LEA_OPCODE (0x8D)
328 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
329 /* 32-bits of the old base register (new index register) */
337 /* The old rex.B should be the new rex.X */
340 }
341 /* Since our new base is %r15 set rex.B */
344 /* Shift the instruction by one byte */
345 /* so we can insert a rex prefix */
348 /* New rex prefix only needs rex.B for %r15 base */
350 }
356 }
358 /* Clears the upper 32-bits of the previous base register */
362 /* Move the old instruction forward to make */
363 /* room for 'mov' stored in 'buf_ptr' */
364 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
368 /* Sandboxed replacement for the normal membase_emit */
372 /* Normal default behavior, emit membase memory location */
374 }
375 }
380 {
381 guint8 in_nop;
387 }
391 }
396 }
401 }
407 }
413 }
420 }
427 }
430 }
432 guint8*
434 {
436 }
442 {
445 #ifdef __native_client_codegen__
447 #endif
448 #if defined(__native_client_codegen__) && defined(__native_client__)
450 /* For tail calls, code is patched after being installed */
451 /* but not through the normal "patch callsite" method. */
456 /* Patch a temp buffer of bundle size, */
457 /* then install to actual location. */
462 }
464 #endif
466 /* Skip REX */
470 }
473 /* amd64_set_reg_template */
475 }
476 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
477 /* mov 0(%rip), %dreg */
479 }
481 /* call *<OFFSET>(%rip) */
483 }
485 /* call <DISP> */
489 }
490 else
492 }
494 void
496 {
498 }
501 ArgInIReg,
502 ArgInFloatSSEReg,
503 ArgInDoubleSSEReg,
504 ArgOnStack,
505 ArgValuetypeInReg,
506 ArgValuetypeAddrInIReg,
507 ArgNone /* only in pair_storage */
511 gint16 offset;
512 gint8 reg;
513 ArgStorage storage;
515 /* Only if storage == ArgValuetypeInReg */
523 guint32 stack_usage;
524 guint32 reg_usage;
525 guint32 freg_usage;
526 gboolean need_stack_align;
527 gboolean vtype_retaddr;
528 /* The index of the vret arg in the argument list */
530 ArgInfo ret;
531 ArgInfo sig_cookie;
535 #define DEBUG(a) if (cfg->verbose_level > 1) a
537 #ifdef HOST_WIN32
538 #define PARAM_REGS 4
543 #else
544 #define PARAM_REGS 6
546 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
549 #endif
553 {
558 /* Since the same stack slot size is used for all arg */
559 /* types, it needs to be big enough to hold them all */
561 }
566 }
567 }
569 #ifdef HOST_WIN32
570 #define FLOAT_PARAM_REGS 4
571 #else
572 #define FLOAT_PARAM_REGS 8
573 #endif
577 {
582 /* Since the same stack slot size is used for both float */
583 /* types, it needs to be big enough to hold them both */
585 }
587 /* A double register */
590 else
594 }
595 }
598 ARG_CLASS_NO_CLASS,
599 ARG_CLASS_MEMORY,
600 ARG_CLASS_INTEGER,
601 ARG_CLASS_SSE
604 static ArgumentClass
606 {
635 #ifdef HOST_WIN32
637 #else
639 #endif
649 }
650 /* fall through */
658 }
660 }
663 }
665 /* Merge */
667 ;
674 else
678 }
679 #ifdef __native_client_codegen__
683 /* Default alignment for Native Client is 32-byte. */
686 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
687 /* Check that alignment doesn't cross an alignment boundary. */
688 guint8*
690 {
694 /* assertion: alignment cannot cross a block boundary */
700 }
703 }
704 #endif
706 static void
707 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
708 gboolean is_return,
710 {
712 /* Keep track of the size used in each quad so we can */
713 /* use the right size when copying args/return vars. */
718 MonoGenericSharingContext tmp_gsctx;
721 /*
722 * The gsctx currently contains no data, it is only used for checking whenever
723 * open types are allowed, some callers like mono_arch_get_argument_info ()
724 * don't pass it to us, so work around that.
725 */
731 #ifndef HOST_WIN32
732 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
733 /* We pass and return vtypes of size 8 in a register */
736 }
737 #else
740 }
741 #endif
743 /* If this struct can't be split up naturally into 8-byte */
744 /* chunks (registers), pass it on the stack. */
746 guint32 align;
747 guint32 field_size;
758 }
759 }
760 }
763 /* Allways pass in memory */
769 }
771 /* FIXME: Handle structs smaller than 8 bytes */
772 //if ((size % 8) != 0)
773 // NOT_IMPLEMENTED;
777 else
781 /* Always pass in 1 or 2 integer registers */
784 /* Only the simplest cases are supported */
788 }
790 /*
791 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
792 * The X87 and SSEUP stuff is left out since there are no such types in
793 * the CLR.
794 */
798 #ifndef HOST_WIN32
805 }
806 #else
815 }
823 }
828 }
829 }
832 }
833 #endif
839 guint32 align;
840 ArgumentClass class1;
844 else
851 /* Unaligned field */
852 NOT_IMPLEMENTED;
853 }
855 /* Skip fields in other quad */
861 /* How far into this quad this data extends.*/
862 /* (8 is size of quad) */
866 }
869 }
870 }
872 /* Post merger cleanup */
876 /* Allocate registers */
877 {
893 else
896 }
907 }
913 }
914 }
917 /* Revert possible register assignments */
924 else
927 }
928 }
929 }
931 /*
932 * get_call_info:
933 *
934 * Obtain information about a call according to the calling convention.
935 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
936 * Draft Version 0.23" document for more information.
937 */
940 {
950 else
958 /* return value */
959 {
1000 }
1001 /* fall through */
1008 /* The caller passes the address where the value is stored */
1009 }
1011 }
1013 /* Same as a valuetype with size 24 */
1020 }
1021 }
1024 /*
1025 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1026 * the first argument, allowing 'this' to be always passed in the first arg reg.
1027 * Also do this if the first argument is a reference type, since virtual calls
1028 * are sometimes made using calli without sig->hasthis set, like in the delegate
1029 * invoke wrappers.
1030 */
1031 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1037 }
1041 /* this */
1047 }
1053 /* Emit the signature cookie just before the implicit arguments */
1055 }
1061 #ifdef HOST_WIN32
1062 /* The float param registers and other param registers must be the same index on Windows x64.*/
1067 #endif
1070 /* We allways pass the sig cookie on the stack for simplicity */
1071 /*
1072 * Prevent implicit arguments + the sig cookie from being passed
1073 * in registers.
1074 */
1078 /* Emit the signature cookie just before the implicit arguments */
1080 }
1113 }
1114 /* fall through */
1119 #ifdef HOST_WIN32
1121 #else
1124 #endif
1138 }
1139 }
1141 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1145 /* Emit the signature cookie just before the implicit arguments */
1147 }
1149 #ifdef HOST_WIN32
1150 // There always is 32 bytes reserved on the stack when calling on Winx64
1152 #endif
1154 #ifndef MONO_AMD64_NO_PUSHES
1156 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1159 }
1160 #endif
1166 }
1168 /*
1169 * mono_arch_get_argument_info:
1170 * @csig: a method signature
1171 * @param_count: the number of parameters to consider
1172 * @arg_info: an array to store the result infos
1173 *
1174 * Gathers information on parameters such as size, alignment and
1175 * padding. arg_info should be large enought to hold param_count + 1 entries.
1176 *
1177 * Returns the size of the argument area on the stack.
1178 */
1179 int
1180 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1181 {
1186 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1189 }
1193 /* FIXME: */
1195 }
1200 }
1202 gboolean
1203 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1204 {
1206 gboolean res;
1211 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1212 /* An address on the callee's stack is passed as the first argument */
1219 }
1221 static int
1223 {
1224 #if defined(MONO_CROSS_COMPILE)
1226 #else
1227 #ifndef _MSC_VER
1231 #else
1238 #endif
1240 #endif
1241 }
1243 /*
1244 * Initialize the cpu to execute managed code.
1245 */
1246 void
1248 {
1249 #ifndef _MSC_VER
1250 guint16 fpcw;
1252 /* spec compliance requires running with double precision */
1258 #else
1259 /* TODO: This is crashing on Win64 right now.
1260 * _control87 (_PC_53, MCW_PC);
1261 */
1262 #endif
1263 }
1265 /*
1266 * Initialize architecture specific code.
1267 */
1268 void
1270 {
1274 #if defined(__native_client_codegen__)
1279 #endif
1281 #ifdef MONO_ARCH_NOMAP32BIT
1283 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1286 #else
1288 /* amd64_mov_reg_mem () */
1291 #endif
1293 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1301 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1303 }
1305 /*
1306 * Cleanup architecture specific code.
1307 */
1308 void
1310 {
1312 #if defined(__native_client_codegen__)
1316 #endif
1317 }
1319 /*
1320 * This function returns the optimizations supported on this cpu.
1321 */
1322 guint32
1324 {
1329 /* Feature Flags function, flags returned in EDX. */
1335 else
1339 }
1342 }
1344 /*
1345 * This function test for all SSE functions supported.
1346 *
1347 * Returns a bitmask corresponding to all supported versions.
1348 *
1349 */
1350 guint32
1352 {
1369 }
1371 /* Yes, all this needs to be done to check for sse4a.
1372 See: "Amd: CPUID Specification"
1373 */
1375 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1376 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1380 }
1381 }
1384 }
1386 #ifndef DISABLE_JIT
1388 GList *
1390 {
1398 /* unused vars */
1410 }
1411 }
1416 }
1418 /**
1419 * mono_arch_compute_omit_fp:
1420 *
1421 * Determine whenever the frame pointer can be eliminated.
1422 */
1423 static void
1425 {
1442 /*
1443 * FIXME: Remove some of the restrictions.
1444 */
1448 #ifdef __native_client_codegen__
1449 /* NaCl modules may not change the value of RBP, so it cannot be */
1450 /* used as a normal register, but it can be used as a frame pointer*/
1453 #endif
1460 /*
1461 if (cfg->method->save_lmf)
1462 cfg->arch.omit_fp = FALSE;
1463 */
1479 /*
1480 * The stack offset can only be determined when the frame
1481 * size is known.
1482 */
1484 }
1485 }
1493 }
1494 }
1496 GList *
1498 {
1511 #ifndef __native_client_codegen__
1513 #endif
1527 /* We use the callee saved registers for global allocation */
1532 #ifndef __native_client_codegen__
1534 #endif
1535 #ifdef HOST_WIN32
1538 #endif
1539 }
1542 }
1544 GList*
1546 {
1550 /* All XMM registers */
1555 }
1557 GList*
1559 {
1570 #ifndef __native_client_codegen__
1572 #endif
1584 }
1587 }
1589 GList*
1591 {
1602 }
1605 }
1607 /*
1608 * mono_arch_regalloc_cost:
1609 *
1610 * Return the cost, in number of memory references, of the action of
1611 * allocating the variable VMV into a register during global register
1612 * allocation.
1613 */
1614 guint32
1616 {
1620 /* The register is already saved */
1621 /* substract 1 for the invisible store in the prolog */
1623 else
1624 /* push+pop */
1626 }
1628 /*
1629 * mono_arch_fill_argument_info:
1630 *
1631 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1632 * of the method.
1633 */
1634 void
1636 {
1649 /*
1650 * Contrary to mono_arch_allocate_vars (), the information should describe
1651 * where the arguments are at the beginning of the method, not where they can be
1652 * accessed during the execution of the method. The later makes no sense for the
1653 * global register allocator, since a variable can be in more than one location.
1654 */
1660 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1663 }
1667 }
1676 }
1677 }
1687 else
1703 /* Dummy */
1708 }
1709 }
1710 }
1712 void
1714 {
1731 /*
1732 * We use the ABI calling conventions for managed code as well.
1733 * Exception: valuetypes are only sometimes passed or returned in registers.
1734 */
1736 /*
1737 * The stack looks like this:
1738 * <incoming arguments passed on the stack>
1739 * <return value>
1740 * <lmf/caller saved registers>
1741 * <locals>
1742 * <spill area>
1743 * <localloc area> -> grows dynamically
1744 * <params area>
1745 */
1752 /* Locals are allocated backwards from %fp */
1755 }
1758 /* The LMF var is allocated normally */
1762 /* Reserve space for callee saved registers */
1766 }
1767 }
1774 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1779 /* The register is volatile */
1788 }
1792 }
1793 }
1794 }
1798 }
1801 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1810 }
1814 }
1817 }
1819 /* Allocate locals */
1821 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1828 }
1833 }
1840 }
1849 else
1851 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1852 }
1853 }
1855 }
1861 }
1872 else
1876 /* The new allocator needs info about the original locations of the arguments */
1893 /* These arguments are saved to the stack in the prolog */
1897 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1899 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1901 }
1905 }
1908 }
1910 /* FIXME: Allocate volatile arguments to registers */
1914 /*
1915 * Under AMD64, all registers used to pass arguments to functions
1916 * are volatile across calls.
1917 * FIXME: Optimize this.
1918 */
1919 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1931 }
1952 }
1956 }
1962 }
1964 NOT_IMPLEMENTED;
1965 }
1970 /* These arguments are saved to the stack in the prolog */
1974 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1975 // Arguments are yet supported by the stack map creation code
1976 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1978 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1980 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1981 }
1982 }
1983 }
1984 }
1987 }
1989 void
1991 {
2009 }
2010 }
2019 }
2024 }
2026 #ifdef MONO_AMD64_NO_PUSHES
2027 /*
2028 * When this is set, we pass arguments on the stack by moves, and by allocating
2029 * a bigger stack frame, instead of pushes.
2030 * Pushes complicate exception handling because the arguments on the stack have
2031 * to be popped each time a frame is unwound. They also make fp elimination
2032 * impossible.
2033 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2034 * on a new frame which doesn't include a param area.
2035 */
2037 #endif
2040 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2044 }
2046 #ifndef MONO_AMD64_NO_PUSHES
2048 #endif
2049 }
2051 static void
2052 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2053 {
2083 }
2084 }
2086 static int
2088 {
2091 #if defined(__mono_ilp32__)
2093 #else
2095 #endif
2102 }
2105 }
2107 static void
2109 {
2115 NOT_IMPLEMENTED;
2119 /*
2120 * mono_ArgIterator_Setup assumes the signature cookie is
2121 * passed first and all the arguments which were before it are
2122 * passed on the stack after the signature. So compensate by
2123 * passing a different signature.
2124 */
2128 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2134 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2139 }
2140 }
2144 {
2153 }
2154 }
2156 #ifdef ENABLE_LLVM
2157 LLVMCallInfo*
2159 {
2171 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2173 /*
2174 * LLVM always uses the native ABI while we use our own ABI, the
2175 * only difference is the handling of vtypes:
2176 * - we only pass/receive them in registers in some cases, and only
2177 * in 1 or 2 integer registers.
2178 */
2184 }
2188 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2189 }
2192 /* Vtype returned using a hidden argument */
2195 }
2202 else
2225 }
2226 }
2233 }
2237 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2243 }
2244 }
2247 }
2248 #endif
2250 void
2252 {
2267 /* We shouldn't be called in the llvm case */
2270 }
2275 }
2277 /*
2278 * Emit all arguments which are passed on the stack to prevent register
2279 * allocation problems.
2280 */
2290 else
2299 else
2303 }
2308 }
2309 }
2310 }
2311 }
2313 /*
2314 * Emit all parameters passed in registers in non-reverse order for better readability
2315 * and to help the optimization in emit_prolog ().
2316 */
2324 }
2333 /* Already done */
2347 guint32 align;
2348 guint32 size;
2353 }
2358 /*
2359 * Other backends use mono_type_stack_size (), but that
2360 * aligns the size to 8, which is larger than the size of
2361 * the source, leading to reads of invalid memory if the
2362 * source is at the end of address space.
2363 */
2365 }
2366 }
2370 /* Avoid asserts in emit_memcpy () */
2373 /* Continue normally */
2374 }
2386 }
2389 /* Already done */
2404 }
2405 }
2407 }
2408 }
2412 }
2415 /* Emit the signature cookie just before the implicit arguments */
2417 }
2419 /* Handle the case where there are no implicit arguments */
2428 /*
2429 * Tell the JIT to use a more efficient calling convention: call using
2430 * OP_CALL, compute the result location after the call, and save the
2431 * result there.
2432 */
2434 /*
2435 * Nullify the instruction computing the vret addr to enable
2436 * future optimizations.
2437 */
2442 NOT_IMPLEMENTED;
2443 /*
2444 * The valuetype is in RAX:RDX after the call, need to be copied to
2445 * the stack. Push the address here, so the call instruction can
2446 * access it.
2447 */
2449 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2450 /* Prevent it from being register allocated or optimized away */
2452 }
2454 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2455 }
2456 }
2464 }
2465 }
2467 #ifdef HOST_WIN32
2470 }
2471 #endif
2476 }
2479 }
2481 void
2483 {
2511 }
2515 }
2542 }
2551 /* Can't use this for < 8 since it does an 8 byte memory load */
2556 }
2563 }
2566 // FIXME: Code growth
2574 }
2575 }
2580 }
2581 }
2582 }
2584 void
2586 {
2592 else
2598 }
2601 }
2605 #define EMIT_COND_BRANCH(ins,cond,sign) \
2606 if (ins->inst_true_bb->native_offset) { \
2607 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2608 } else { \
2609 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2610 if ((cfg->opt & MONO_OPT_BRANCH) && \
2611 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2612 x86_branch8 (code, cond, 0, sign); \
2613 else \
2614 x86_branch32 (code, cond, 0, sign); \
2615 }
2624 mgreg_t res;
2628 static gboolean
2630 {
2633 #ifdef HOST_WIN32
2635 #endif
2649 }
2652 }
2667 }
2668 }
2671 }
2673 /*
2674 * mono_arch_dyn_call_prepare:
2675 *
2676 * Return a pointer to an arch-specific structure which contains information
2677 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2678 * supported for SIG.
2679 * This function is equivalent to ffi_prep_cif in libffi.
2680 */
2681 MonoDynCallInfo*
2683 {
2692 }
2695 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2700 }
2702 /*
2703 * mono_arch_dyn_call_free:
2704 *
2705 * Free a MonoDynCallInfo structure.
2706 */
2707 void
2709 {
2714 }
2716 #if !defined(__native_client__)
2717 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2718 #define GREG_TO_PTR(greg) (gpointer)(greg)
2719 #else
2720 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2721 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2722 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2723 #endif
2725 /*
2726 * mono_arch_get_start_dyn_call:
2727 *
2728 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2729 * store the result into BUF.
2730 * ARGS should be an array of pointers pointing to the arguments.
2731 * RET should point to a memory buffer large enought to hold the result of the
2732 * call.
2733 * This function should be as fast as possible, any work which does not depend
2734 * on the actual values of the arguments should be done in
2735 * mono_arch_dyn_call_prepare ().
2736 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2737 * libffi.
2738 */
2739 void
2740 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2741 {
2760 }
2772 }
2783 #if !defined(__mono_ilp32__)
2786 #endif
2790 #if defined(__mono_ilp32__)
2796 #endif
2822 /* Fall through */
2823 }
2831 }
2835 }
2837 }
2840 }
2841 }
2844 }
2846 /*
2847 * mono_arch_finish_dyn_call:
2848 *
2849 * Store the result of a dyn call into the return value buffer passed to
2850 * start_dyn_call ().
2851 * This function should be as fast as possible, any work which does not depend
2852 * on the actual values of the arguments should be done in
2853 * mono_arch_dyn_call_prepare ().
2854 */
2855 void
2857 {
2908 /* Fall through */
2909 }
2912 /* Nothing to do */
2921 }
2924 }
2928 }
2929 }
2931 /* emit an exception if condition is fail */
2932 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2933 do { \
2934 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2935 if (tins == NULL) { \
2936 mono_add_patch_info (cfg, code - cfg->native_code, \
2937 MONO_PATCH_INFO_EXC, exc_name); \
2938 x86_branch32 (code, cond, 0, signed); \
2939 } else { \
2940 EMIT_COND_BRANCH (tins, cond, signed); \
2941 } \
2942 } while (0);
2944 #define EMIT_FPCOMPARE(code) do { \
2945 amd64_fcompp (code); \
2946 amd64_fnstsw (code); \
2947 } while (0);
2949 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2950 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2951 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2952 amd64_ ##op (code); \
2953 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2954 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2955 } while (0);
2959 {
2962 /*
2963 * FIXME: Add support for thunks
2964 */
2965 {
2968 /*
2969 * Indirect calls are expensive so try to make a near call if possible.
2970 * The caller memory is allocated by the code manager so it is
2971 * guaranteed to be at a 32 bit offset.
2972 */
2975 /* The target is in memory allocated using the code manager */
2980 /* The callee might be an AOT method */
2983 /* The target is in malloc-ed memory */
2985 }
2988 /*
2989 * The call might go directly to a native function without
2990 * the wrapper.
2991 */
2997 }
2998 }
2999 }
3002 /*
3003 * This is not really an optimization, but required because the
3004 * generic class init trampolines use R11 to pass the vtable.
3005 */
3012 /* A call to the wrapped function */
3016 }
3018 /* No wrapper */
3021 }
3023 /* See the comment in mono_codegen () */
3024 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3026 }
3027 }
3031 }
3032 }
3033 }
3036 /* These methods are allocated using malloc */
3039 #ifdef MONO_ARCH_NOMAP32BIT
3041 #endif
3043 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3050 }
3053 /*
3054 * Align the call displacement to an address divisible by 4 so it does
3055 * not span cache lines. This is required for code patching to work on SMP
3056 * systems.
3057 */
3061 }
3064 }
3069 }
3070 }
3073 }
3076 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3077 {
3078 #ifdef HOST_WIN32
3081 #endif
3083 #ifdef HOST_WIN32
3086 #endif
3089 }
3093 {
3101 }
3104 }
3106 #ifndef DISABLE_JIT
3108 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3110 /*
3111 * mono_arch_peephole_pass_1:
3112 *
3113 * Perform peephole opts which should/can be performed before local regalloc
3114 */
3115 void
3117 {
3128 /*
3129 * X86_LEA is like ADD, but doesn't have the
3130 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3131 * its operand to 64 bit.
3132 */
3135 }
3142 /*
3143 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3144 * the latter has length 2-3 instead of 6 (reverse constant
3145 * propagation). These instruction sequences are very common
3146 * in the initlocals bblock.
3147 */
3149 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3152 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3153 /* Continue */
3154 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3156 /* Continue */
3159 }
3160 }
3161 }
3165 /* OP_COMPARE_IMM (reg, 0)
3166 * -->
3167 * OP_AMD64_TEST_NULL (reg)
3168 */
3177 /*
3178 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3179 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3180 * -->
3181 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3182 * OP_COMPARE_IMM reg, imm
3183 *
3184 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3185 */
3192 /* check if we can remove cmp reg,0 with test null */
3195 }
3198 }
3201 }
3202 }
3204 void
3206 {
3213 /* reg = 0 -> XOR (reg, reg) */
3214 /* XOR sets cflags on x86, so we cant do it always */
3215 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3219 /* Fall through */
3222 }
3223 }
3225 /*
3226 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3227 * 0 result into 64 bits.
3228 */
3231 }
3232 /* Fall through */
3237 /*
3238 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3239 * the latter has length 2-3 instead of 6 (reverse constant
3240 * propagation). These instruction sequences are very common
3241 * in the initlocals bblock.
3242 */
3244 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3247 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3248 /* Continue */
3249 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3251 /* Continue */
3254 }
3255 }
3256 }
3266 }
3269 }
3270 }
3272 #define NEW_INS(cfg,ins,dest,op) do { \
3273 MONO_INST_NEW ((cfg), (dest), (op)); \
3274 (dest)->cil_code = (ins)->cil_code; \
3275 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3276 } while (0)
3278 /*
3279 * mono_arch_lowering_pass:
3280 *
3281 * Converts complex opcodes into simpler ones so that each IR instruction
3282 * corresponds to one machine instruction.
3283 */
3284 void
3286 {
3289 /*
3290 * FIXME: Need to add more instructions, but the current machine
3291 * description can't model some parts of the composite instructions like
3292 * cdq.
3293 */
3304 /* Keep the opcode if we can implement it efficiently */
3316 }
3318 #ifndef __mono_ilp32__
3320 #endif
3322 #ifndef __native_client_codegen__
3323 /* Don't generate memindex opcodes (to simplify */
3324 /* read sandboxing) */
3331 }
3332 #endif
3334 #ifndef __mono_ilp32__
3336 #endif
3344 }
3346 #ifdef MONO_ARCH_SIMD_INTRINSICS
3367 }
3369 #endif
3372 }
3373 }
3376 }
3378 static const int
3379 branch_cc_table [] = {
3383 };
3385 /* Maps CMP_... constants to X86_CC_... constants */
3386 static const int
3387 cc_table [] = {
3390 };
3392 static const int
3393 cc_signed_table [] = {
3396 };
3398 /*#include "cprop.c"*/
3401 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3402 {
3410 }
3414 {
3418 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3421 #endif
3426 /*
3427 * Under Windows:
3428 * If requested stack size is larger than one page,
3429 * perform stack-touch operation
3430 */
3431 /*
3432 * Generate stack probe code.
3433 * Under Windows, it is necessary to allocate one page at a time,
3434 * "touching" stack after each successful sub-allocation. This is
3435 * because of the way stack growth is implemented - there is a
3436 * guard page before the lowest stack page that is currently commited.
3437 * Stack normally grows sequentially so OS traps access to the
3438 * guard page and commits more pages when needed.
3439 */
3460 }
3461 else
3469 }
3473 }
3477 }
3488 #if defined(__default_codegen__)
3491 #elif defined(__native_client_codegen__)
3492 /* NaCl stos pseudo-instruction */
3494 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3496 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3509 }
3511 }
3515 {
3517 guint32 quad;
3519 /* Move return value to the target register */
3520 /* FIXME: do this in the local reg allocator */
3535 }
3539 }
3547 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3551 /* Load the destination address */
3553 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3558 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3569 NOT_IMPLEMENTED;
3570 }
3571 }
3572 }
3574 }
3577 }
3581 #ifdef __APPLE__
3583 #endif
3585 gboolean
3587 {
3588 #ifdef __APPLE__
3598 /*
3599 * We're looking for these two instructions:
3600 *
3601 * mov %gs:[offset](,%rdi,8),%rax
3602 * retq
3603 */
3619 #else
3621 #endif
3622 }
3624 /*
3625 * mono_amd64_emit_tls_get:
3626 * @code: buffer to store code to
3627 * @dreg: hard register where to place the result
3628 * @tls_offset: offset info
3629 *
3630 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3631 * the dreg register the item in the thread local storage identified
3632 * by tls_offset.
3633 *
3634 * Returns: a pointer to the end of the stored code
3635 */
3636 guint8*
3638 {
3639 #ifdef HOST_WIN32
3643 #elif defined(__APPLE__)
3646 #else
3654 }
3655 #endif
3657 }
3659 /*
3660 * emit_setup_lmf:
3661 *
3662 * Emit code to initialize an LMF structure at LMF_OFFSET.
3663 */
3666 {
3669 /*
3670 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3671 */
3672 /*
3673 * sp is saved right before calls but we need to save it here too so
3674 * async stack walks would work.
3675 */
3676 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3677 /* Skip method (only needed for trampoline LMF frames) */
3678 /* Save callee saved regs */
3688 #ifndef __native_client_codegen__
3690 #endif
3691 #ifdef HOST_WIN32
3694 #endif
3698 }
3704 }
3705 }
3707 /* These can't contain refs */
3708 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3709 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3710 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
3714 /* These are handled automatically by the stack marking code */
3721 #ifdef HOST_WIN32
3724 #endif
3727 }
3729 /*
3730 * emit_save_lmf:
3731 *
3732 * Emit code to push an LMF structure on the LMF stack.
3733 */
3736 {
3738 /*
3739 * Optimized version which uses the mono_lmf TLS variable instead of
3740 * indirection through the mono_lmf_addr TLS variable.
3741 */
3742 /* %rax = previous_lmf */
3746 /* Save previous_lmf */
3747 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3748 /* Set new lmf */
3756 }
3759 /* Load lmf quicky using the FS register */
3761 #ifdef HOST_WIN32
3762 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3763 /* FIXME: Add a separate key for LMF to avoid this */
3765 #endif
3766 }
3768 /*
3769 * The call might clobber argument registers, but they are already
3770 * saved to the stack/global regs.
3771 */
3776 }
3778 /* Save lmf_addr */
3779 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3780 /* Save previous_lmf */
3782 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3783 /* Set new lmf */
3786 }
3789 }
3791 /*
3792 * emit_save_lmf:
3793 *
3794 * Emit code to pop an LMF structure from the LMF stack.
3795 */
3798 {
3800 /*
3801 * Optimized version which uses the mono_lmf TLS variable instead of indirection
3802 * through the mono_lmf_addr TLS variable.
3803 */
3804 /* reg = previous_lmf */
3805 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3809 /* Restore previous lmf */
3810 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3811 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3813 }
3816 }
3818 #define REAL_PRINT_REG(text,reg) \
3819 mono_assert (reg >= 0); \
3820 amd64_push_reg (code, AMD64_RAX); \
3821 amd64_push_reg (code, AMD64_RDX); \
3822 amd64_push_reg (code, AMD64_RCX); \
3823 amd64_push_reg (code, reg); \
3824 amd64_push_imm (code, reg); \
3826 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3827 amd64_call_reg (code, AMD64_RAX); \
3828 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3829 amd64_pop_reg (code, AMD64_RCX); \
3830 amd64_pop_reg (code, AMD64_RDX); \
3831 amd64_pop_reg (code, AMD64_RAX);
3833 /* benchmark and set based on cpu */
3834 #define LOOP_ALIGNMENT 8
3835 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3837 #ifndef DISABLE_JIT
3839 #if defined(__native_client__) || defined(__native_client_codegen__)
3841 {
3842 #ifdef __native_client_gc__
3844 #endif
3845 }
3846 #endif
3848 void
3850 {
3853 guint offset;
3859 /* Fix max_offset estimate for each successor bb */
3866 }
3867 }
3871 /* set alignment depending on cpu */
3874 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3878 }
3879 }
3881 #if defined(__native_client_codegen__)
3882 /* For Native Client, all indirect call/jump targets must be */
3883 /* 32-byte aligned. Exception handler blocks are jumped to */
3884 /* indirectly as well. */
3893 }
3905 /* this is not thread save, but good enough */
3907 }
3913 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3921 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3928 }
3958 /* In AMD64 NaCl, pointers are 4 bytes, */
3959 /* so STORE_* != STOREI8_*. Likewise below. */
3961 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3970 #ifndef __native_client_codegen__
3971 /* In NaCl, this could be a PCONST type, which could */
3972 /* mean a pointer type was copied directly into the */
3973 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3974 /* the value would be 0x00000000FFFFFFFF which is */
3975 /* not proper for an imm32 unless you cast it. */
3977 #endif
3978 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3985 #ifdef __mono_ilp32__
3986 /* In ILP32, pointers are 4 bytes, so separate these */
3987 /* cases, use literal 8 below where we really want 8 */
3991 #endif
3993 // FIXME: Decompose this earlier
3999 }
4006 // FIXME: Decompose this earlier
4012 }
4019 /* For NaCl, pointers are 4 bytes, so separate these */
4020 /* cases, use literal 8 below where we really want 8 */
4026 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4029 /* Use literal 8 instead of sizeof pointer or */
4030 /* register, we really want 8 for this opcode */
4041 /* The cpu zero extends the result into 64 bits */
4042 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4048 /* The cpu zero extends the result into 64 bits */
4049 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4076 /* Clean out the upper word */
4118 /* FIXME: Make a 64 version too */
4119 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4123 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4127 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4131 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4135 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4138 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4141 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4144 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4150 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4169 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4172 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4175 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4179 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4182 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4208 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4211 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4214 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4220 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4225 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4229 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4233 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4237 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4241 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4263 /*
4264 * Read from the single stepping trigger page. This will cause a
4265 * SIGSEGV when single stepping is enabled.
4266 * We do this _before_ the breakpoint, so single stepping after
4267 * a breakpoint is hit will step to the next IL offset.
4268 */
4274 }
4276 /*
4277 * This is the address which is saved in seq points,
4278 */
4283 guint32 val;
4286 /* Load info var */
4289 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4293 /*
4294 * A placeholder for a possible breakpoint inserted by
4295 * mono_arch_set_breakpoint ().
4296 */
4299 }
4300 /*
4301 * Add an additional nop so skipping the bp doesn't cause the ip to point
4302 * to another IL offset.
4303 */
4306 }
4357 /* MOV r1, r2 */
4358 /* ADD r1, r1 */
4364 /* LEA r1, [r2 + r2*2] */
4368 /* LEA r1, [r2 + r2*4] */
4372 /* LEA r1, [r2 + r2*2] */
4373 /* ADD r1, r1 */
4378 /* LEA r1, [r2 + r2*8] */
4382 /* LEA r1, [r2 + r2*4] */
4383 /* ADD r1, r1 */
4388 /* LEA r1, [r2 + r2*2] */
4389 /* SHL r1, 2 */
4394 /* LEA r1, [r2 + r2*4] */
4395 /* LEA r1, [r1 + r1*4] */
4400 /* LEA r1, [r2 + r2*4] */
4401 /* SHL r1, 2 */
4402 /* LEA r1, [r1 + r1*4] */
4410 }
4412 }
4415 /* Regalloc magic makes the div/rem cases the same */
4423 }
4434 }
4445 }
4456 }
4468 }
4470 /* Based on gcc code */
4472 /* Add compensation for negative dividents */
4478 /* Compute remainder */
4480 /* Remove compensation */
4483 }
4621 /* the mul operation and the exception check should most likely be split */
4624 /*g_assert (ins->sreg2 == X86_EAX);
4625 g_assert (ins->dreg == X86_EAX);*/
4631 /* no need to save since we're going to store to it anyway */
4635 }
4638 }
4643 }
4647 }
4649 /* save before the check since pop and mov don't change the flags */
4658 }
4685 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4709 /* This needs to operate on 64 bit values */
4710 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4724 else
4741 }
4746 }
4751 /* FIXME: no tracing support... */
4759 /* Pop callee-saved registers */
4764 }
4767 // FIXME:
4769 NOT_IMPLEMENTED;
4770 }
4776 /* Restore callee-saved registers */
4781 }
4782 }
4784 /* Copy arguments on the stack to our argument area */
4788 }
4794 }
4800 else
4806 }
4808 /* ensure ins->sreg1 is not NULL */
4815 }
4823 /*
4824 * The AMD64 ABI forces callers to know about varargs.
4825 */
4828 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4829 /*
4830 * Since the unmanaged calling convention doesn't contain a
4831 * 'vararg' entry, we have to treat every pinvoke call as a
4832 * potential vararg call.
4833 */
4838 nregs ++;
4841 else
4843 }
4847 else
4851 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4866 }
4868 /*
4869 * The AMD64 ABI forces callers to know about varargs.
4870 */
4875 }
4877 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4878 /*
4879 * Since the unmanaged calling convention doesn't contain a
4880 * 'vararg' entry, we have to treat every pinvoke call as a
4881 * potential vararg call.
4882 */
4887 nregs ++;
4891 }
4894 else
4896 }
4901 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4916 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4926 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4928 /* r10 = ftn */
4931 /* Save args buffer */
4934 /* Set argument registers */
4938 /* Make the call */
4944 /* Save result */
4948 }
4951 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4953 }
4978 else
4989 }
4991 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5000 /* keep alignment */
5028 }
5032 }
5036 }
5044 }
5052 }
5054 /* Align stack */
5059 /* Restore stack alignment */
5063 /* Even though we're saving RSP, use sizeof */
5064 /* gpointer because spvar is of type IntPtr */
5065 /* see: mono_create_spvar_for_region */
5067 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5072 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5073 }
5075 }
5078 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5081 }
5084 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5085 /* The local allocator will put the result into RAX */
5088 }
5094 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5095 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5096 //break;
5104 else
5106 }
5126 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5149 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5166 /* floating point opcodes */
5172 }
5176 }
5178 }
5184 }
5189 }
5191 }
5199 /* This requires a double->single conversion */
5216 /* FIXME: nothing to do ?? */
5243 /* Based on gcc code */
5247 /* Positive case */
5252 /* Negative case */
5253 /* Save to the red zone */
5263 /* Restore */
5268 }
5303 }
5318 }
5373 /*
5374 * The two arguments are swapped because the fbranch instructions
5375 * depend on this for the non-sse case to work.
5376 */
5380 /* zeroing the register at the start results in
5381 * shorter and faster code (we can also remove the widening op)
5382 */
5391 }
5394 /* zeroing the register at the start results in
5395 * shorter and faster code (we can also remove the widening op)
5396 */
5411 }
5415 /* zeroing the register at the start results in
5416 * shorter and faster code (we can also remove the widening op)
5417 */
5428 }
5430 }
5456 }
5478 }
5480 }
5487 }
5489 /* Branch if C013 != 100 */
5490 /* branch if !ZF or (PF|CF) */
5507 /* skip branch if C1=1 */
5510 /* branch if (C0 | C3) = 1 */
5516 }
5519 /* Branch if C013 == 100 or 001 */
5522 /* skip branch if C1=1 */
5525 /* branch if (C0 | C3) = 1 */
5529 }
5531 /* Branch if C013 == 000 */
5535 /* Branch if C013=000 or 100 */
5538 /* skip branch if C1=1 */
5541 /* branch if C0=0 */
5545 }
5547 /* Branch if C013 != 001 */
5552 /* Transfer value to the fp stack */
5570 }
5575 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5579 }
5581 }
5600 }
5612 /* dreg contains the old value, add with sreg2 value */
5619 }
5625 guint32 size;
5630 else
5633 /*
5634 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5635 * an explanation of how this works.
5636 */
5638 /* cmpxchg uses eax as comperand, need to make sure we can use it
5639 * hack to overcome limits in x86 reg allocator
5640 * (req: dreg == eax and sreg2 != eax and breg != eax)
5641 */
5645 /* Highly unlikely, but possible */
5648 /* The pushes invalidate rsp */
5652 }
5654 /* We need the EAX reg for the comparand */
5665 }
5666 }
5679 }
5682 guint32 size;
5686 else
5689 /*
5690 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5691 * an explanation of how this works.
5692 */
5703 }
5709 gpointer card_table_mask;
5716 /*If either point to the stack we can simply avoid the WB. This happens due to
5717 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5718 */
5722 /*
5723 * We need one register we can clobber, we choose EDX and make sreg1
5724 * fixed EAX to work around limitations in the local register allocator.
5725 * sreg2 might get allocated to EDX, but that is not a problem since
5726 * we use it before clobbering EDX.
5727 */
5730 /*
5731 * This is the code we produce:
5732 *
5733 * edx = value
5734 * edx >>= nursery_shift
5735 * cmp edx, (nursery_start >> nursery_shift)
5736 * jne done
5737 * edx = ptr
5738 * edx >>= card_table_shift
5739 * edx += cardtable
5740 * [edx] = 1
5741 * done:
5742 */
5749 /*
5750 * The value we need to compare against is 64 bits, so we need
5751 * another spare register. We use RBX, which we save and
5752 * restore.
5753 */
5760 }
5762 }
5768 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5775 }
5776 #ifdef MONO_ARCH_SIMD_INTRINSICS
5777 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6167 /*TODO: This is appart of the sse spec but not added
6168 case OP_PSARQ:
6169 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6170 break;
6171 case OP_PSARQ_REG:
6172 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6173 break;
6174 */
6219 }
6230 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6231 if (ins->inst_c0)
6232 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6239 else
6249 /*sreg1 is the extracted ireg (scratch)
6250 /sreg2 is the to be inserted ireg (scratch)
6251 /dreg is the xreg to receive the value*/
6253 /*clear the bits from the extracted word*/
6255 /*shift the value to insert if needed*/
6258 /*join them together*/
6271 else
6295 }
6300 else
6324 /*FIXME the peephole pass should have killed this*/
6355 }
6380 #endif
6383 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6386 }
6389 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6392 }
6394 #if defined(__native_client_codegen__)
6396 #endif
6398 }
6411 }
6414 #if !defined(__native_client_codegen__)
6418 #endif
6419 }
6423 }
6426 }
6430 void
6432 {
6433 /* The signature doesn't matter */
6434 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6435 }
6437 void
6438 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6439 {
6455 /* No need to patch these */
6457 }
6458 }
6472 }
6474 /*
6475 * Debug code to help track down problems where the target of a near call is
6476 * is not valid.
6477 */
6493 }
6494 }
6495 }
6498 }
6499 }
6501 #ifndef DISABLE_JIT
6503 static int
6505 {
6520 }
6522 /*
6523 * This macro is used for testing whenever the unwinder works correctly at every point
6524 * where an async exception can happen.
6525 */
6526 /* This will generate a SIGSEGV at the given point in the code */
6527 #define async_exc_point(code) do { \
6528 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6529 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6530 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6531 cfg->arch.async_point_count ++; \
6532 } \
6533 } while (0)
6535 guint8 *
6537 {
6548 #ifdef __native_client_codegen__
6549 guint alignment_check;
6550 #endif
6554 #if defined(__default_codegen__)
6556 #elif defined(__native_client_codegen__)
6557 /* native_code_alloc is not 32-byte aligned, native_code is. */
6560 /* Align native_code to next nearest kNaclAlignment byte. */
6568 #endif
6573 /* Amount of stack space allocated by register saving code */
6576 /* Offset between RSP and the CFA */
6579 /*
6580 * The prolog consists of the following parts:
6581 * FP present:
6582 * - push rbp, mov rbp, rsp
6583 * - save callee saved regs using pushes
6584 * - allocate frame
6585 * - save rgctx if needed
6586 * - save lmf if needed
6587 * FP not present:
6588 * - allocate frame
6589 * - save rgctx if needed
6590 * - save lmf if needed
6591 * - save callee saved regs using moves
6592 */
6594 // CFA = sp + 8
6597 // IP saved at CFA - 8
6608 #ifdef HOST_WIN32
6609 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6610 #endif
6611 /* These are handled automatically by the stack marking code */
6617 #ifdef HOST_WIN32
6619 #endif
6620 }
6622 /* Save callee saved registers */
6634 /* These are handled automatically by the stack marking code */
6636 }
6637 }
6639 /* The param area is always at offset 0 from sp */
6640 /* This needs to be allocated here, since it has to come after the spill area */
6643 // FIXME:
6646 }
6649 /*
6650 * On enter, the stack is misaligned by the pushing of the return
6651 * address. It is either made aligned by the pushing of %rbp, or by
6652 * this.
6653 */
6657 /* Mark the padding slot as NOREF */
6659 }
6663 /* Mark the padding slot as NOREF */
6665 }
6668 }
6672 /* Allocate stack frame */
6674 /* See mono_emit_stack_alloc */
6675 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6677 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6678 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6686 }
6693 }
6695 #ifdef HOST_WIN32
6698 #endif
6702 }
6709 }
6710 #ifdef HOST_WIN32
6712 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6713 #endif
6714 }
6715 #else
6721 }
6722 #endif
6723 }
6725 /* Stack alignment check */
6726 #if 0
6727 {
6733 }
6734 #endif
6736 #ifndef TARGET_WIN32
6738 /* Fill the stack frame with a dummy value to force deterministic behavior */
6740 /* Save registers to the red zone */
6749 #if defined(__default_codegen__)
6752 #elif defined(__native_client_codegen__)
6753 /* NaCl stos pseudo-instruction */
6755 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6757 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6766 }
6767 #endif
6769 /* Save LMF */
6772 }
6774 /* Save callee saved registers */
6778 /* Save caller saved registers after sp is adjusted */
6779 /* The registers are saved at the bottom of the frame */
6780 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6786 /* These are handled automatically by the stack marking code */
6791 }
6792 }
6794 /* store runtime generic context */
6799 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6801 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6802 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6803 }
6805 /* compute max_length in order to use short forward jumps */
6814 /* max alignment for loops */
6817 #ifdef __native_client_codegen__
6818 /* max alignment for native client */
6820 #endif
6823 #ifdef __native_client_codegen__
6824 {
6830 }
6831 }
6834 }
6836 /* Take prolog and epilog instrumentation into account */
6841 }
6842 }
6850 /* Save volatile arguments to the stack */
6852 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6853 }
6855 /* Keep this in sync with emit_load_volatile_arguments */
6858 gint32 stack_offset;
6864 /* Unused arguments */
6869 else
6875 /* All the other moves are done by the register allocator */
6884 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6887 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6890 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6896 }
6897 }
6901 }
6904 }
6906 /* Save volatile arguments to the stack */
6912 /* FIXME: I1 etc */
6913 /*
6914 if (stack_offset & 0x1)
6915 size = 1;
6916 else if (stack_offset & 0x2)
6917 size = 2;
6918 else if (stack_offset & 0x4)
6919 size = 4;
6920 else
6921 size = 8;
6922 */
6925 /*
6926 * Save the original location of 'this',
6927 * get_generic_info_from_stack_frame () needs this to properly look up
6928 * the argument value during the handling of async exceptions.
6929 */
6932 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6933 }
6935 }
6946 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6949 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6952 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6958 }
6959 }
6963 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6967 }
6969 /* Argument allocated to (non-volatile) register */
6979 }
6984 }
6985 }
6986 }
6990 }
6995 }
7000 /*
7001 * Optimize the common case of the first bblock making a call with the same
7002 * arguments as the method. This works because the arguments are still in their
7003 * original argument registers.
7004 * FIXME: Generalize this
7005 */
7014 }
7027 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7034 /* Only continue if the instruction doesn't change argument regs */
7037 }
7038 }
7040 }
7043 }
7045 /* Argument allocated to (non-volatile) register */
7051 }
7055 }
7056 }
7060 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7063 }
7064 }
7065 }
7070 /* Initialize seq_point_info_var */
7072 /* Initialize the variable from a GOT slot */
7073 /* Same as OP_AOTCONST */
7074 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7078 }
7080 /* Initialize ss_trigger_page_var */
7087 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7090 }
7092 }
7099 }
7101 void
7103 {
7117 }
7124 /* the code restoring the registers must be kept in sync with OP_JMP */
7128 /* check if we need to restore protection of the stack after a stack overflow */
7132 /* we load the value in a separate instruction: this mechanism may be
7133 * used later as a safer way to do thread interruption
7134 */
7135 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7139 /* note that the call trampoline will preserve eax/edx */
7143 /* FIXME: maybe save the jit tls in the prolog */
7144 }
7148 /* Restore caller saved regs */
7150 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7151 }
7153 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7154 }
7156 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7157 }
7159 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7160 }
7162 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7163 }
7165 #if defined(__default_codegen__)
7166 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7167 #elif defined(__native_client_codegen__)
7169 #endif
7170 }
7171 #ifdef HOST_WIN32
7173 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7174 }
7176 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7177 }
7178 #endif
7188 }
7189 }
7197 /* Only one register, so avoid lea */
7201 }
7202 }
7206 /* Pop registers in reverse order */
7210 }
7211 }
7212 }
7213 }
7214 }
7216 /* Load returned vtypes into registers if needed */
7225 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7228 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7231 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7237 }
7238 }
7239 }
7246 }
7253 }
7255 void
7257 {
7265 /* Compute needed space */
7275 }
7277 #ifdef __native_client_codegen__
7278 /* Give us extra room on Native Client. This could be */
7279 /* more carefully calculated, but bundle alignment makes */
7280 /* it much trickier, so *2 like other places is good. */
7282 #endif
7288 }
7292 /* add code to raise exceptions */
7299 guint32 throw_ip;
7307 //x86_breakpoint (code);
7308 /* Find a throw sequence for the same exception class */
7316 }
7325 }
7330 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7338 nthrows ++;
7339 }
7340 }
7342 }
7344 /* do nothing */
7346 }
7348 }
7350 /* Handle relocations with RIP relative addressing */
7359 guint32 target_pos;
7361 /* The SSE opcodes require a 16 byte alignment */
7362 #if defined(__default_codegen__)
7364 #elif defined(__native_client_codegen__)
7365 {
7366 /* Pad this out with HLT instructions */
7367 /* or we can get garbage bytes emitted */
7368 /* which will fail validation */
7370 /* extra align to make room for */
7371 /* mov/push below */
7374 /* The technique of hiding data in an */
7375 /* instruction has a problem here: we */
7376 /* need the data aligned to a 16-byte */
7377 /* boundary but the instruction cannot */
7378 /* cross the bundle boundary. so only */
7379 /* odd multiples of 16 can be used */
7382 }
7385 }
7386 }
7387 #endif
7393 }
7397 }
7400 #ifdef __native_client_codegen__
7401 /* Hide 64-bit data in a */
7402 /* "mov imm64, r11" instruction. */
7403 /* write it before the start of */
7404 /* the data*/
7407 #endif
7411 #ifdef __native_client_codegen__
7412 /* Hide 32-bit data in a */
7413 /* "push imm32" instruction. */
7415 #endif
7418 }
7424 }
7431 /*loading is faster against aligned addresses.*/
7437 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7440 else
7448 }
7451 }
7460 ;
7462 }
7463 }
7465 }
7471 }
7477 {
7484 /* Keep this in sync with mono_arch_get_argument_info */
7487 /* Allocate a new area on the stack and save arguments there */
7506 }
7507 }
7508 }
7519 }
7522 SAVE_NONE,
7523 SAVE_STRUCT,
7524 SAVE_EAX,
7525 SAVE_EAX_EDX,
7526 SAVE_XMM
7527 };
7530 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7531 {
7535 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7540 /* special case string .ctor icall */
7543 else
7558 }
7559 /* Fall through */
7566 }
7568 /* Save the result and copy it into the proper argument register */
7572 /* Align stack */
7578 /* FIXME: */
7585 /* Align stack */
7587 /*
7588 * The result is already in the proper argument register so no copying
7589 * needed.
7590 */
7596 }
7598 /* Set %al since this is a varargs call */
7601 else
7607 }
7616 }
7618 /* Restore result */
7625 /* FIXME: */
7636 }
7639 }
7641 void
7643 {
7644 /* Not needed */
7645 }
7647 void
7649 {
7650 }
7652 gboolean
7654 {
7656 }
7658 /*
7659 * Determine whenever the trap whose info is in SIGINFO is caused by
7660 * integer overflow.
7661 */
7662 gboolean
7664 {
7665 MonoContext ctx;
7668 gint64 value;
7676 rip ++;
7677 }
7678 else
7681 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7682 /* idiv REG */
7725 }
7729 }
7732 }
7734 guint32
7736 {
7738 }
7740 /**
7741 * mono_breakpoint_clean_code:
7742 *
7743 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7744 * breakpoints in the original code, they are removed in the copy.
7745 *
7746 * Returns TRUE if no sw breakpoint was present.
7747 */
7748 gboolean
7749 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7750 {
7753 /*
7754 * If method_start is non-NULL we need to perform bound checks, since we access memory
7755 * at code - offset we could go before the start of the method and end up in a different
7756 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7757 * instead.
7758 */
7765 }
7776 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7778 }
7779 }
7781 }
7783 #if defined(__native_client_codegen__)
7784 /* For membase calls, we want the base register. for Native Client, */
7785 /* all indirect calls have the following sequence with the given sizes: */
7786 /* mov %eXX,%eXX [2-3] */
7787 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7788 /* and $0xffffffffffffffe0,%r11d [4] */
7789 /* add %r15,%r11 [3] */
7790 /* callq *%r11 [3] */
7793 /* Determine if code points to a NaCl call-through-register sequence, */
7794 /* (i.e., the last 3 instructions listed above) */
7795 int
7797 {
7802 }
7804 /* Determine if code points to the first opcode of the mov membase component */
7805 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7806 /* (there could be a REX prefix before the opcode but it is ignored) */
7807 static int
7809 {
7810 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7812 /* and that src reg = dest reg */
7814 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7817 /* and has dst of r11 and base of r15 */
7820 }
7823 int
7825 {
7827 }
7829 gpointer
7831 {
7833 }
7835 #define MAX_ARCH_DELEGATE_PARAMS 10
7837 static gpointer
7839 {
7846 /* Replace the this argument with the target */
7848 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7858 /* We have to shift the arguments left */
7861 #ifdef HOST_WIN32
7864 else
7866 #else
7868 #endif
7869 }
7872 }
7874 }
7888 else
7893 }
7896 }
7898 /*
7899 * mono_arch_get_delegate_invoke_impls:
7900 *
7901 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7902 * trampolines.
7903 */
7904 GSList*
7906 {
7909 guint32 code_len;
7913 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7917 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7918 }
7921 }
7923 gpointer
7925 {
7932 /* FIXME: Support more cases */
7944 else
7968 }
7973 }
7976 }
7977 void
7979 {
7980 #ifdef HOST_WIN32
7981 /*
7982 * We need to init this multiple times, since when we are first called, the key might not
7983 * be initialized yet.
7984 */
7989 /* Only 64 tls entries can be accessed using inline code */
7996 #else
7997 #ifdef MONO_XEN_OPT
7999 #endif
8003 #endif
8004 }
8006 void
8008 {
8009 }
8011 #ifdef MONO_ARCH_HAVE_IMT
8013 #if defined(__default_codegen__)
8014 #define CMP_SIZE (6 + 1)
8015 #define CMP_REG_REG_SIZE (4 + 1)
8016 #define BR_SMALL_SIZE 2
8017 #define BR_LARGE_SIZE 6
8018 #define MOV_REG_IMM_SIZE 10
8019 #define MOV_REG_IMM_32BIT_SIZE 6
8020 #define JUMP_REG_SIZE (2 + 1)
8021 #elif defined(__native_client_codegen__)
8022 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8023 #define CMP_SIZE ((6 + 1) * 2 - 1)
8024 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8025 #define BR_SMALL_SIZE (2 * 2 - 1)
8026 #define BR_LARGE_SIZE (6 * 2 - 1)
8027 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8028 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8029 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8030 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8031 /* Jump membase's size is large and unpredictable */
8032 /* in native client, just pad it out a whole bundle. */
8033 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8034 #endif
8036 static int
8038 {
8043 }
8045 /*
8046 * LOCKING: called with the domain lock held
8047 */
8048 gpointer
8049 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8050 gpointer fail_tramp)
8051 {
8064 else
8066 }
8072 else
8074 #ifdef __native_client_codegen__
8076 #endif
8077 }
8086 else
8089 /* with assert below:
8090 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8091 */
8092 #ifdef __native_client_codegen__
8094 #endif
8095 }
8096 }
8100 else
8104 }
8106 }
8107 #if defined(__native_client__) && defined(__native_client_codegen__)
8108 /* In Native Client, we don't re-use thunks, allocate from the */
8109 /* normal code manager paths. */
8111 #else
8114 else
8116 #endif
8131 }
8132 }
8139 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8141 }
8148 }
8150 /* enable the commented code to assert on wrong method */
8151 #if 0
8157 }
8160 /* See the comment below about R10 */
8161 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8166 #else
8167 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8168 needs to be preserved. R10 needs
8169 to be preserved for calls which
8170 require a runtime generic context,
8171 but interface calls don't. */
8172 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8174 #endif
8175 }
8182 }
8186 else
8188 }
8190 }
8191 /* patch the branches to get to the target items */
8197 }
8198 }
8199 }
8208 }
8210 MonoMethod*
8212 {
8214 }
8215 #endif
8217 MonoVTable*
8219 {
8221 }
8223 GSList*
8225 {
8232 }
8234 MonoInst*
8235 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8236 {
8249 }
8257 }
8279 }
8280 }
8289 }
8291 #if 0
8292 /* OP_FREM is not IEEE compatible */
8297 }
8298 #endif
8299 }
8301 /*
8302 * Can't implement CompareExchange methods this way since they have
8303 * three arguments.
8304 */
8307 }
8309 gboolean
8311 {
8313 }
8316 {
8325 }
8327 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8329 mgreg_t
8331 {
8343 else
8345 }
8346 }
8348 void
8350 {
8372 else
8374 }
8375 }
8377 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8378 gpointer
8379 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8380 {
8386 /*Decode the first instruction to figure out where did we store the spvar*/
8387 /*Our jit MUST generate the following:
8388 mov %rsp, ?(%rbp)
8390 Which is encoded as: REX.W 0x89 mod_rm
8391 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8392 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8393 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8395 FIXME can we generate frameless methods on this case?
8397 */
8400 /*REX.W*/
8405 /*mov r, r/m */
8414 else
8417 /*Load the spvar*/
8428 }
8430 /*
8431 * mono_arch_emit_load_aotconst:
8432 *
8433 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8434 * TARGET from the mscorlib GOT in full-aot code.
8435 * On AMD64, the result is placed into R11.
8436 */
8437 guint8*
8438 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8439 {
8444 }
8446 /*
8447 * mono_arch_get_trampolines:
8448 *
8449 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8450 * for AOT.
8451 */
8452 GSList *
8454 {
8456 }
8458 /* Soft Debug support */
8459 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8461 /*
8462 * mono_arch_set_breakpoint:
8463 *
8464 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8465 * The location should contain code emitted by OP_SEQ_POINT.
8466 */
8467 void
8469 {
8480 /*
8481 * In production, we will use int3 (has to fix the size in the md
8482 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8483 * instead.
8484 */
8491 }
8494 }
8495 }
8497 /*
8498 * mono_arch_clear_breakpoint:
8499 *
8500 * Clear the breakpoint at IP.
8501 */
8502 void
8504 {
8517 }
8518 }
8520 gboolean
8522 {
8523 #ifdef HOST_WIN32
8526 #else
8528 /* Sometimes the address is off by 4 */
8529 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8531 else
8533 #endif
8534 }
8536 /*
8537 * mono_arch_skip_breakpoint:
8538 *
8539 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8540 * we resume, the instruction is not executed again.
8541 */
8542 void
8544 {
8546 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8550 }
8551 }
8553 /*
8554 * mono_arch_start_single_stepping:
8555 *
8556 * Start single stepping.
8557 */
8558 void
8560 {
8562 }
8564 /*
8565 * mono_arch_stop_single_stepping:
8566 *
8567 * Stop single stepping.
8568 */
8569 void
8571 {
8573 }
8575 /*
8576 * mono_arch_is_single_step_event:
8577 *
8578 * Return whenever the machine state in SIGCTX corresponds to a single
8579 * step event.
8580 */
8581 gboolean
8583 {
8584 #ifdef HOST_WIN32
8587 #else
8589 /* Sometimes the address is off by 4 */
8590 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8592 else
8594 #endif
8595 }
8597 /*
8598 * mono_arch_skip_single_step:
8599 *
8600 * Modify CTX so the ip is placed after the single step trigger instruction,
8601 * we resume, the instruction is not executed again.
8602 */
8603 void
8605 {
8607 }
8609 /*
8610 * mono_arch_create_seq_point_info:
8611 *
8612 * Return a pointer to a data structure which is used by the sequence
8613 * point implementation in AOTed code.
8614 */
8615 gpointer
8617 {
8622 // FIXME: Add a free function
8626 code);
8633 // FIXME: Optimize the size
8638 /* Initialize to a valid address */
8646 }
8649 }
8651 #endif