mono/mini/mini-mips.h

   1 #ifndef __MONO_MINI_MIPS_H__
   2 #define __MONO_MINI_MIPS_H__
   3
   4 #include <glib.h>
   5 #include <mono/arch/mips/mips-codegen.h>
   6 #include <mono/utils/mono-context.h>
   7
   8 #if _MIPS_SIM == _ABIO32
   9 /* o32 fully supported */
  10 #elif _MIPS_SIM == _ABIN32
  11 /* n32 under development */
  12 #warning "MIPS using n32 - under development"
  13 #else
  14 /* o64 not supported */
  15 /* n64 not supported */
  16 #error "MIPS unsupported ABI"
  17 #endif
  18
  19
  20 #define MONO_ARCH_CPU_SPEC mono_mips_desc
  21
  22 #define MONO_MAX_IREGS 32
  23 #define MONO_MAX_FREGS 32
  24
  25 #define MONO_SAVED_GREGS 32
  26 #define MONO_SAVED_FREGS 32
  27
  28
  29 #if SIZEOF_REGISTER == 4
  30 #define IREG_SIZE       4
  31 #define FREG_SIZE       4
  32 typedef gfloat          mips_freg;
  33
  34 #elif SIZEOF_REGISTER == 8
  35
  36 #define IREG_SIZE       8
  37 #define FREG_SIZE       8
  38 typedef gdouble         mips_freg;
  39
  40 #else
  41 #error Unknown REGISTER_SIZE
  42 #endif
  43
  44 /*
  45  * at and t0 used internally
  46  * v0, v1 aren't here for clarity reasons
  47  * a0, a1, a2, a3 are for arguments
  48  * Use t9 for indirect calls to match the ABI
  49  */
  50
  51 #define MIPS_V_REGS     ((1 << mips_v0) | \
  52                          (1 << mips_v1))
  53 #if _MIPS_SIM == _ABIO32
  54 #define MIPS_T_REGS     ((1 << mips_t0) | \
  55                          (1 << mips_t1) | \
  56                          (1 << mips_t2) | \
  57                          (1 << mips_t3) | \
  58                          (1 << mips_t4) | \
  59                          (1 << mips_t5) | \
  60                          (1 << mips_t6) | \
  61                          (1 << mips_t7))
  62 #elif _MIPS_SIM == _ABIN32
  63 #define MIPS_T_REGS     ((1 << mips_t0) | \
  64                          (1 << mips_t1) | \
  65                          (1 << mips_t2) | \
  66                          (1 << mips_t3))
  67 #endif
  68
  69
  70 #define MIPS_S_REGS     ((1 << mips_s0) | \
  71                          (1 << mips_s1) | \
  72                          (1 << mips_s2) | \
  73                          (1 << mips_s3) | \
  74                          (1 << mips_s4) | \
  75                          (1 << mips_s5) | \
  76                          (1 << mips_s6) | \
  77                          (1 << mips_s7) | \
  78                          (1 << mips_fp))
  79 #if _MIPS_SIM == _ABIO32
  80 #define MIPS_A_REGS     ((1 << mips_a0) | \
  81                          (1 << mips_a1) | \
  82                          (1 << mips_a2) | \
  83                          (1 << mips_a3))
  84 #elif _MIPS_SIM == _ABIN32
  85 #define MIPS_A_REGS     ((1 << mips_a0) | \
  86                          (1 << mips_a1) | \
  87                          (1 << mips_a2) | \
  88                          (1 << mips_a3) | \
  89                          (1 << mips_a4) | \
  90                          (1 << mips_a5) | \
  91                          (1 << mips_a6) | \
  92                          (1 << mips_a7))
  93 #endif
  94
  95 #define mips_temp mips_t8
  96
  97 #define MONO_ARCH_CALLEE_REGS           (MIPS_T_REGS | MIPS_V_REGS | MIPS_A_REGS)
  98 #define MONO_ARCH_CALLEE_SAVED_REGS     MIPS_S_REGS
  99 #define MIPS_ARG_REGS                   MIPS_A_REGS
 100
 101 #if 0
 102 #define MIPS_FP_PAIR(reg)       ((1 << (reg)) | (1 << ((reg)+1)))
 103 #else
 104 /* Only put the even regs in */
 105 #define MIPS_FP_PAIR(reg)       (1 << (reg))
 106 #endif
 107
 108 #if _MIPS_SIM == _ABIO32
 109 #define MONO_ARCH_CALLEE_FREGS          (MIPS_FP_PAIR(mips_f0) |        \
 110                                          MIPS_FP_PAIR(mips_f2) |        \
 111                                          MIPS_FP_PAIR(mips_f4) |        \
 112                                          MIPS_FP_PAIR(mips_f6) |        \
 113                                          MIPS_FP_PAIR(mips_f8) |        \
 114                                          MIPS_FP_PAIR(mips_f10) |       \
 115                                          MIPS_FP_PAIR(mips_f12) |       \
 116                                          MIPS_FP_PAIR(mips_f14) |       \
 117                                          MIPS_FP_PAIR(mips_f16) |       \
 118                                          MIPS_FP_PAIR(mips_f18))
 119
 120 #define MONO_ARCH_CALLEE_SAVED_FREGS    (MIPS_FP_PAIR(mips_f20) |       \
 121                                          MIPS_FP_PAIR(mips_f22) |       \
 122                                          MIPS_FP_PAIR(mips_f24) |       \
 123                                          MIPS_FP_PAIR(mips_f26) |       \
 124                                          MIPS_FP_PAIR(mips_f28) |       \
 125                                          MIPS_FP_PAIR(mips_f30))
 126 #elif _MIPS_SIM == _ABIN32
 127 #define MONO_ARCH_CALLEE_FREGS          (MIPS_FP_PAIR(mips_f0) |        \
 128                                          MIPS_FP_PAIR(mips_f1) |        \
 129                                          MIPS_FP_PAIR(mips_f2) |        \
 130                                          MIPS_FP_PAIR(mips_f3) |        \
 131                                          MIPS_FP_PAIR(mips_f4) |        \
 132                                          MIPS_FP_PAIR(mips_f5) |        \
 133                                          MIPS_FP_PAIR(mips_f6) |        \
 134                                          MIPS_FP_PAIR(mips_f7) |        \
 135                                          MIPS_FP_PAIR(mips_f8) |        \
 136                                          MIPS_FP_PAIR(mips_f9) |        \
 137                                          MIPS_FP_PAIR(mips_f10) |       \
 138                                          MIPS_FP_PAIR(mips_f11) |       \
 139                                          MIPS_FP_PAIR(mips_f12) |       \
 140                                          MIPS_FP_PAIR(mips_f13) |       \
 141                                          MIPS_FP_PAIR(mips_f14) |       \
 142                                          MIPS_FP_PAIR(mips_f15) |       \
 143                                          MIPS_FP_PAIR(mips_f16) |       \
 144                                          MIPS_FP_PAIR(mips_f17) |       \
 145                                          MIPS_FP_PAIR(mips_f18) |       \
 146                                          MIPS_FP_PAIR(mips_f19))
 147
 148 #define MONO_ARCH_CALLEE_SAVED_FREGS    (MIPS_FP_PAIR(mips_f20) |       \
 149                                          MIPS_FP_PAIR(mips_f21) |       \
 150                                          MIPS_FP_PAIR(mips_f22) |       \
 151                                          MIPS_FP_PAIR(mips_f23) |       \
 152                                          MIPS_FP_PAIR(mips_f24) |       \
 153                                          MIPS_FP_PAIR(mips_f25) |       \
 154                                          MIPS_FP_PAIR(mips_f26) |       \
 155                                          MIPS_FP_PAIR(mips_f27) |       \
 156                                          MIPS_FP_PAIR(mips_f28) |       \
 157                                          MIPS_FP_PAIR(mips_f29) |       \
 158                                          MIPS_FP_PAIR(mips_f30) |       \
 159                                          MIPS_FP_PAIR(mips_f31))
 160 #endif
 161
 162 #define mips_ftemp mips_f18
 163
 164 #define MONO_ARCH_USE_FPSTACK FALSE
 165 #define MONO_ARCH_FPSTACK_SIZE 0
 166
 167 /* Parameters used by the register allocator */
 168
 169 /* On Mips, for regpairs, the lower-numbered reg is most significant
 170  * This is true in both big and little endian
 171  */
 172
 173 #if G_BYTE_ORDER == G_LITTLE_ENDIAN
 174 #define RET_REG1 mips_v0
 175 #define RET_REG2 mips_v1
 176 #else
 177 #define RET_REG1 mips_v1
 178 #define RET_REG2 mips_v0
 179 #endif
 180
 181 #define MONO_ARCH_INST_SREG2_MASK(ins)          (0)
 182 #define MONO_ARCH_INST_IS_REGPAIR(desc)         ((desc) == 'V' || (desc) == 'l')
 183 #define MONO_ARCH_INST_REGPAIR_REG2(desc,hreg1) (((desc) == 'l') ? ((hreg1) + 1) : (((desc) == 'V') ? RET_REG2 : -1))
 184 #define MONO_ARCH_INST_IS_FLOAT(desc)           ((desc == 'f') || (desc == 'g'))
 185
 186 // This define is called to get specific dest register as defined
 187 // by md file (letter after "dest"). Overwise return -1
 188
 189 #define MONO_ARCH_INST_FIXED_REG(desc)          (((desc) == '0') ? mips_zero : (((desc) == 'a') ? mips_at : ((((desc) == 'v')) ? mips_v0 : (((desc) == 'V') ? RET_REG1 : (((desc) == 'g') ? mips_f0 : -1)))))
 190
 191 #define MONO_ARCH_FRAME_ALIGNMENT 8
 192
 193 /* fixme: align to 16byte instead of 32byte (we align to 32byte to get
 194  * reproduceable results for benchmarks */
 195 #define MONO_ARCH_CODE_ALIGNMENT 32
 196
 197 void mips_patch (guint32 *code, guint32 target);
 198
 199 #define MIPS_LMF_MAGIC1 0xa5a5a5a5
 200 #define MIPS_LMF_MAGIC2 0xc3c3c3c3
 201
 202 /* Registers saved in lmf->iregs */
 203 #define MIPS_LMF_IREGMASK (0xffffffff & ~((1 << mips_zero) | (1 << mips_at) | MONO_ARCH_CALLEE_REGS))
 204
 205 struct MonoLMF {
 206         gpointer        previous_lmf;
 207         gpointer        lmf_addr;
 208         MonoMethod      *method;
 209         gpointer        eip;
 210         mgreg_t     iregs [MONO_SAVED_GREGS];
 211         mips_freg       fregs [MONO_SAVED_FREGS];
 212         gulong          magic;
 213 };
 214
 215 typedef struct MonoCompileArch {
 216         gpointer    cinfo;
 217         guint           iregs_offset;
 218         guint           lmf_offset;
 219         guint           local_alloc_offset;
 220         guint           spillvar_offset;
 221         guint           spillvar_offset_float;
 222         guint           tracing_offset;
 223         guint           long_branch;
 224         gboolean    omit_fp;
 225         gboolean    omit_fp_computed;
 226 } MonoCompileArch;
 227
 228 #if SIZEOF_REGISTER == 4
 229 #define MONO_ARCH_EMULATE_FCONV_TO_I8 1
 230 #define MONO_ARCH_EMULATE_LCONV_TO_R8 1
 231 #define MONO_ARCH_EMULATE_LCONV_TO_R4 1
 232 #define MONO_ARCH_EMULATE_LCONV_TO_R8_UN 1
 233 #define MONO_ARCH_EMULATE_FREM 1
 234 #endif
 235
 236 /*
 237  * mips backend misses some instructions that enable emitting of optimal
 238  * code on other targets and, additionally, the register allocator gets
 239  * confused by this optimization, failing to allocate all hw regs.
 240  */
 241 #if SIZEOF_REGISTER == 4
 242 #define MONO_ARCH_NO_DIV_WITH_MUL
 243 #endif
 244
 245 #if SIZEOF_REGISTER == 8
 246 #define MONO_ARCH_NO_EMULATE_LONG_MUL_OPTS
 247 #endif
 248
 249 #define MIPS_RET_ADDR_OFFSET    (-sizeof(gpointer))
 250 #define MIPS_FP_ADDR_OFFSET     (-8)
 251 #define MIPS_STACK_ALIGNMENT    16
 252 #define MIPS_STACK_PARAM_OFFSET 16              /* from sp to first parameter */
 253 #define MIPS_MINIMAL_STACK_SIZE (4*sizeof(mgreg_t) + 4*sizeof(mgreg_t))
 254 #define MIPS_EXTRA_STACK_SIZE   16              /* from last parameter to top of frame */
 255
 256 #if _MIPS_SIM == _ABIO32
 257 #define MIPS_FIRST_ARG_REG      mips_a0
 258 #define MIPS_LAST_ARG_REG       mips_a3
 259 #define MIPS_FIRST_FPARG_REG    mips_f12
 260 #define MIPS_LAST_FPARG_REG     mips_f14
 261 #elif _MIPS_SIM == _ABIN32
 262 #define MIPS_FIRST_ARG_REG      mips_a0
 263 #define MIPS_LAST_ARG_REG       mips_t3
 264 #define MIPS_FIRST_FPARG_REG    mips_f12
 265 #define MIPS_LAST_FPARG_REG     mips_f19
 266 #endif
 267
 268 #define MONO_ARCH_IMT_REG       mips_t0
 269
 270 #define MONO_ARCH_VTABLE_REG    mips_a0
 271 #define MONO_ARCH_RGCTX_REG     MONO_ARCH_IMT_REG
 272
 273 #define MONO_ARCH_HAVE_DECOMPOSE_OPTS 1
 274 #define MONO_ARCH_HAVE_DECOMPOSE_LONG_OPTS 1
 275
 276 #define MONO_ARCH_HAVE_GENERALIZED_IMT_TRAMPOLINE 1
 277 #define MONO_ARCH_SOFT_DEBUG_SUPPORTED 1
 278 #define MONO_ARCH_HAVE_SIGCTX_TO_MONOCTX 1
 279 #define MONO_ARCH_HAVE_SETUP_RESUME_FROM_SIGNAL_HANDLER_CTX 1
 280 #define MONO_ARCH_GSHARED_SUPPORTED 1
 281
 282 /* set the next to 0 once inssel-mips.brg is updated */
 283 #define MIPS_PASS_STRUCTS_BY_VALUE 1
 284
 285 #define MONO_ARCH_USE_SIGACTION
 286 #define MONO_ARCH_NEED_DIV_CHECK 1
 287 #define MONO_ARCH_NO_IOV_CHECK 1
 288
 289 #define MIPS_NUM_REG_ARGS (MIPS_LAST_ARG_REG-MIPS_FIRST_ARG_REG+1)
 290 #define MIPS_NUM_REG_FPARGS (MIPS_LAST_FPARG_REG-MIPS_FIRST_FPARG_REG+1)
 291
 292 typedef struct {
 293         unsigned long zero;
 294         unsigned long at; /* assembler temp */
 295         unsigned long v0; /* return values */
 296         unsigned long v1;
 297         unsigned long a0; /* 4 - func arguments */
 298         unsigned long a1;
 299         unsigned long a2;
 300         unsigned long a3;
 301         unsigned long t0; /* 8 temporaries */
 302         unsigned long t1;
 303         unsigned long t2;
 304         unsigned long t3;
 305         unsigned long t4;
 306         unsigned long t5;
 307         unsigned long t6;
 308         unsigned long t7;
 309         unsigned long s0; /* 16 calle saved */
 310         unsigned long s1;
 311         unsigned long s2;
 312         unsigned long s3;
 313         unsigned long s4;
 314         unsigned long s5;
 315         unsigned long s6;
 316         unsigned long s7;
 317         unsigned long t8; /* 24 temps */
 318         unsigned long t9; /* 25 temp / pic call-through register */
 319         unsigned long k0; /* 26 kernel-reserved */
 320         unsigned long k1;
 321         unsigned long gp; /* 28 */
 322         unsigned long sp; /* stack pointer */
 323         unsigned long fp; /* frame pointer */
 324         unsigned long ra; /* return address */
 325 } MonoMipsStackFrame;
 326
 327 #define MONO_INIT_CONTEXT_FROM_FUNC(ctx,func) do {      \
 328         MONO_CONTEXT_SET_BP ((ctx), __builtin_frame_address (0));                       \
 329         MONO_CONTEXT_SET_SP ((ctx), __builtin_frame_address (0));                       \
 330         MONO_CONTEXT_SET_IP ((ctx), (func));                                                            \
 331         } while (0)
 332
 333 #define MONO_ARCH_INIT_TOP_LMF_ENTRY(lmf)
 334
 335 /* re-attaches with gdb - sometimes causes executable to hang */
 336 #undef HAVE_BACKTRACE_SYMBOLS
 337
 338 #undef DEBUG_EXCEPTIONS
 339
 340 #define MONO_EMIT_NEW_MIPS_COND_EXC(cfg,cond,sr1,sr2,name) do { \
 341                 MonoInst *inst; \
 342                 MONO_INST_NEW ((cfg), (inst), cond); \
 343                 inst->inst_p1 = (char*)name; \
 344                 inst->sreg1 = sr1; \
 345                 inst->sreg2 = sr2; \
 346                 MONO_ADD_INS ((cfg)->cbb, inst); \
 347         } while (0)
 348
 349 #ifndef MONO_EMIT_NEW_COMPARE_EXC
 350 #define MONO_EMIT_NEW_COMPARE_EXC(cfg, cmp_op, sreg1, sreg2, exc) do { \
 351                 switch (OP_MIPS_COND_EXC_##cmp_op) { \
 352                 case OP_MIPS_COND_EXC_EQ: \
 353                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, sreg1, sreg2, exc); \
 354                         break; \
 355                 case OP_MIPS_COND_EXC_NE_UN: \
 356                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, sreg1, sreg2, exc); \
 357                         break; \
 358                 case OP_MIPS_COND_EXC_GT: \
 359                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
 360                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
 361                         break; \
 362                 case OP_MIPS_COND_EXC_GT_UN: \
 363                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
 364                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
 365                         break; \
 366                 case OP_MIPS_COND_EXC_LE: \
 367                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
 368                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
 369                         break; \
 370                 case OP_MIPS_COND_EXC_LE_UN: \
 371                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
 372                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
 373                         break; \
 374                 case OP_MIPS_COND_EXC_LT: \
 375                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg1, sreg2); \
 376                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
 377                         break; \
 378                 case OP_MIPS_COND_EXC_LT_UN: \
 379                         MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
 380                         MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
 381                         break; \
 382                 default: \
 383                         g_warning ("unknown comparison %s\n", #cmp_op); \
 384                         g_assert_not_reached (); \
 385                 } \
 386         } while (0)
 387 #endif
 388
 389 #ifndef MONO_EMIT_NEW_COMPARE_IMM_EXC
 390 #define MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
 391                 guint32 cmp_reg; \
 392                 if (!(imm)) { \
 393                         cmp_reg = mips_zero; \
 394                 } \
 395                 else { \
 396                         cmp_reg = mips_at; \
 397                         MONO_EMIT_NEW_ICONST (cfg, cmp_reg, (imm)); \
 398                 } \
 399                 MONO_EMIT_NEW_COMPARE_EXC (cfg, cmp_op, sreg1, cmp_reg, exc); \
 400         } while (0)
 401 #endif
 402
 403 #ifndef MONO_EMIT_NEW_ICOMPARE_IMM_EXC
 404 #define MONO_EMIT_NEW_ICOMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
 405                 MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc); \
 406         } while (0)
 407 #endif
 408
 409 typedef struct {
 410         gint8 reg;
 411         gint8 size;
 412         int vtsize;
 413         int offset;
 414 } MonoMIPSArgInfo;
 415
 416 extern guint8 *mips_emit_load_const(guint8 *code, int dreg, mgreg_t v);
 417
 418 #endif /* __MONO_MINI_MIPS_H__ */