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[Facades] Use the Open.snk key for the System.ValueTuple facade (#4173)
[mono-project.git] / mono / mini / mini-arm.c
blobcfbbd02cec19520d411d9e7a7a31face0b72f112
1 /*
2 * mini-arm.c: ARM backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 *
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
12 */
13 #include "mini.h"
14 #include <string.h>
15
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
24
25 #include "mini-arm.h"
26 #include "cpu-arm.h"
27 #include "trace.h"
28 #include "ir-emit.h"
29 #include "debugger-agent.h"
30 #include "mini-gc.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
32
33 /* Sanity check: This makes no sense */
34 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
35 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
36 #endif
37
38 /*
39 * IS_SOFT_FLOAT: Is full software floating point used?
40 * IS_HARD_FLOAT: Is full hardware floating point used?
41 * IS_VFP: Is hardware floating point with software ABI used?
42 *
43 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
44 * IS_VFP may delegate to mono_arch_is_soft_float ().
45 */
46
47 #if defined(ARM_FPU_VFP_HARD)
48 #define IS_SOFT_FLOAT (FALSE)
49 #define IS_HARD_FLOAT (TRUE)
50 #define IS_VFP (TRUE)
51 #elif defined(ARM_FPU_NONE)
52 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
53 #define IS_HARD_FLOAT (FALSE)
54 #define IS_VFP (!mono_arch_is_soft_float ())
55 #else
56 #define IS_SOFT_FLOAT (FALSE)
57 #define IS_HARD_FLOAT (FALSE)
58 #define IS_VFP (TRUE)
59 #endif
60
61 #define THUNK_SIZE (3 * 4)
62
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64
65 #if __APPLE__
66 void sys_icache_invalidate (void *start, size_t len);
67 #endif
68
69 /* This mutex protects architecture specific caches */
70 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
71 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
72 static mono_mutex_t mini_arch_mutex;
73
74 static gboolean v5_supported = FALSE;
75 static gboolean v6_supported = FALSE;
76 static gboolean v7_supported = FALSE;
77 static gboolean v7s_supported = FALSE;
78 static gboolean v7k_supported = FALSE;
79 static gboolean thumb_supported = FALSE;
80 static gboolean thumb2_supported = FALSE;
81 /*
82 * Whenever to use the ARM EABI
83 */
84 static gboolean eabi_supported = FALSE;
85
86 /*
87 * Whenever to use the iphone ABI extensions:
88 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
89 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
90 * This is required for debugging/profiling tools to work, but it has some overhead so it should
91 * only be turned on in debug builds.
92 */
93 static gboolean iphone_abi = FALSE;
94
95 /*
96 * The FPU we are generating code for. This is NOT runtime configurable right now,
97 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
98 */
99 static MonoArmFPU arm_fpu;
100
101 #if defined(ARM_FPU_VFP_HARD)
102 /*
103 * On armhf, d0-d7 are used for argument passing and d8-d15
104 * must be preserved across calls, which leaves us no room
105 * for scratch registers. So we use d14-d15 but back up their
106 * previous contents to a stack slot before using them - see
107 * mono_arm_emit_vfp_scratch_save/_restore ().
108 */
109 static int vfp_scratch1 = ARM_VFP_D14;
110 static int vfp_scratch2 = ARM_VFP_D15;
111 #else
112 /*
113 * On armel, d0-d7 do not need to be preserved, so we can
114 * freely make use of them as scratch registers.
115 */
116 static int vfp_scratch1 = ARM_VFP_D0;
117 static int vfp_scratch2 = ARM_VFP_D1;
118 #endif
119
120 static int i8_align;
121
122 static gpointer single_step_tramp, breakpoint_tramp;
123 static gpointer get_tls_tramp;
124
125 /*
126 * The code generated for sequence points reads from this location, which is
127 * made read-only when single stepping is enabled.
128 */
129 static gpointer ss_trigger_page;
130
131 /* Enabled breakpoints read from this trigger page */
132 static gpointer bp_trigger_page;
133
134 /*
135 * TODO:
136 * floating point support: on ARM it is a mess, there are at least 3
137 * different setups, each of which binary incompat with the other.
138 * 1) FPA: old and ugly, but unfortunately what current distros use
139 * the double binary format has the two words swapped. 8 double registers.
140 * Implemented usually by kernel emulation.
141 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
142 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
143 * 3) VFP: the new and actually sensible and useful FP support. Implemented
144 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
145 *
146 * We do not care about FPA. We will support soft float and VFP.
147 */
148 int mono_exc_esp_offset = 0;
149
150 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
151 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
152 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
153
154 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
155 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
156 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
157
158 //#define DEBUG_IMT 0
159
160 #ifndef DISABLE_JIT
161 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
162 #endif
163
164 static guint8*
165 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
166
167 const char*
168 mono_arch_regname (int reg)
169 {
170 static const char * rnames[] = {
171 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
172 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
173 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
174 "arm_pc"
175 };
176 if (reg >= 0 && reg < 16)
177 return rnames [reg];
178 return "unknown";
179 }
180
181 const char*
182 mono_arch_fregname (int reg)
183 {
184 static const char * rnames[] = {
185 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
186 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
187 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
188 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
189 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
190 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
191 "arm_f30", "arm_f31"
192 };
193 if (reg >= 0 && reg < 32)
194 return rnames [reg];
195 return "unknown";
196 }
197
198
199 #ifndef DISABLE_JIT
200 static guint8*
201 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
202 {
203 int imm8, rot_amount;
204 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
205 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
206 return code;
207 }
208 if (dreg == sreg) {
209 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
210 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
211 } else {
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
214 }
215 return code;
216 }
217
218 /* If dreg == sreg, this clobbers IP */
219 static guint8*
220 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
221 {
222 int imm8, rot_amount;
223 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
224 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
225 return code;
226 }
227 if (dreg == sreg) {
228 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
229 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
230 } else {
231 code = mono_arm_emit_load_imm (code, dreg, imm);
232 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
233 }
234 return code;
235 }
236
237 static guint8*
238 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
239 {
240 /* we can use r0-r3, since this is called only for incoming args on the stack */
241 if (size > sizeof (gpointer) * 4) {
242 guint8 *start_loop;
243 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
244 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
245 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
246 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
247 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
248 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
250 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
251 ARM_B_COND (code, ARMCOND_NE, 0);
252 arm_patch (code - 4, start_loop);
253 return code;
254 }
255 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
256 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
257 while (size >= 4) {
258 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
259 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
260 doffset += 4;
261 soffset += 4;
262 size -= 4;
263 }
264 } else if (size) {
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 doffset = soffset = 0;
268 while (size >= 4) {
269 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
270 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
271 doffset += 4;
272 soffset += 4;
273 size -= 4;
274 }
275 }
276 g_assert (size == 0);
277 return code;
278 }
279
280 static guint8*
281 emit_call_reg (guint8 *code, int reg)
282 {
283 if (v5_supported) {
284 ARM_BLX_REG (code, reg);
285 } else {
286 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
287 if (thumb_supported)
288 ARM_BX (code, reg);
289 else
290 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
291 }
292 return code;
293 }
294
295 static guint8*
296 emit_call_seq (MonoCompile *cfg, guint8 *code)
297 {
298 if (cfg->method->dynamic) {
299 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
300 ARM_B (code, 0);
301 *(gpointer*)code = NULL;
302 code += 4;
303 code = emit_call_reg (code, ARMREG_IP);
304 } else {
305 ARM_BL (code, 0);
306 }
307 cfg->thunk_area += THUNK_SIZE;
308 return code;
309 }
310
311 guint8*
312 mono_arm_patchable_b (guint8 *code, int cond)
313 {
314 ARM_B_COND (code, cond, 0);
315 return code;
316 }
317
318 guint8*
319 mono_arm_patchable_bl (guint8 *code, int cond)
320 {
321 ARM_BL_COND (code, cond, 0);
322 return code;
323 }
324
325 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
326 #define HAVE_AEABI_READ_TP 1
327 #endif
328
329 #ifdef HAVE_AEABI_READ_TP
330 gpointer __aeabi_read_tp (void);
331 #endif
332
333 gboolean
334 mono_arch_have_fast_tls (void)
335 {
336 #ifdef HAVE_AEABI_READ_TP
337 static gboolean have_fast_tls = FALSE;
338 static gboolean inited = FALSE;
339 gpointer tp1, tp2;
340
341 if (mini_get_debug_options ()->use_fallback_tls)
342 return FALSE;
343
344 if (inited)
345 return have_fast_tls;
346
347 tp1 = __aeabi_read_tp ();
348 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
349
350 have_fast_tls = tp1 && tp1 == tp2;
351 inited = TRUE;
352 return have_fast_tls;
353 #else
354 return FALSE;
355 #endif
356 }
357
358 static guint8*
359 emit_tls_get (guint8 *code, int dreg, int tls_offset)
360 {
361 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
362 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
363 return code;
364 }
365
366 static guint8*
367 emit_tls_set (guint8 *code, int sreg, int tls_offset)
368 {
369 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
370 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
371 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
372 return code;
373 }
374
375 /*
376 * emit_save_lmf:
377 *
378 * Emit code to push an LMF structure on the LMF stack.
379 * On arm, this is intermixed with the initialization of other fields of the structure.
380 */
381 static guint8*
382 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
383 {
384 int i;
385
386 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
387 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
388 } else {
389 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
390 (gpointer)"mono_tls_get_lmf_addr");
391 code = emit_call_seq (cfg, code);
392 }
393 /* we build the MonoLMF structure on the stack - see mini-arm.h */
394 /* lmf_offset is the offset from the previous stack pointer,
395 * alloc_size is the total stack space allocated, so the offset
396 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
397 * The pointer to the struct is put in r1 (new_lmf).
398 * ip is used as scratch
399 * The callee-saved registers are already in the MonoLMF structure
400 */
401 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
402 /* r0 is the result from mono_get_lmf_addr () */
403 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
404 /* new_lmf->previous_lmf = *lmf_addr */
405 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
406 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 /* *(lmf_addr) = r1 */
408 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
409 /* Skip method (only needed for trampoline LMF frames) */
410 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
411 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
412 /* save the current IP */
413 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
414 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
415
416 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
417 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
418
419 return code;
420 }
421
422 typedef struct {
423 gint32 vreg;
424 gint32 hreg;
425 } FloatArgData;
426
427 static guint8 *
428 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
429 {
430 GSList *list;
431
432 for (list = inst->float_args; list; list = list->next) {
433 FloatArgData *fad = list->data;
434 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
435 gboolean imm = arm_is_fpimm8 (var->inst_offset);
436
437 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
438 if (!imm)
439 *max_len += 20 + 4;
440
441 *max_len += 4;
442
443 if (*offset + *max_len > cfg->code_size) {
444 cfg->code_size += *max_len;
445 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
446
447 code = cfg->native_code + *offset;
448 }
449
450 if (!imm) {
451 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
452 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
453 } else
454 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
455
456 *offset = code - cfg->native_code;
457 }
458
459 return code;
460 }
461
462 static guint8 *
463 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
464 {
465 MonoInst *inst;
466
467 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
468
469 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
470
471 if (IS_HARD_FLOAT) {
472 if (!arm_is_fpimm8 (inst->inst_offset)) {
473 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
474 ARM_FSTD (code, reg, ARMREG_LR, 0);
475 } else
476 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
477 }
478
479 return code;
480 }
481
482 static guint8 *
483 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
484 {
485 MonoInst *inst;
486
487 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
488
489 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
490
491 if (IS_HARD_FLOAT) {
492 if (!arm_is_fpimm8 (inst->inst_offset)) {
493 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
494 ARM_FLDD (code, reg, ARMREG_LR, 0);
495 } else
496 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
497 }
498
499 return code;
500 }
501
502 /*
503 * emit_restore_lmf:
504 *
505 * Emit code to pop an LMF structure from the LMF stack.
506 */
507 static guint8*
508 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
509 {
510 int basereg, offset;
511
512 if (lmf_offset < 32) {
513 basereg = cfg->frame_reg;
514 offset = lmf_offset;
515 } else {
516 basereg = ARMREG_R2;
517 offset = 0;
518 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
519 }
520
521 /* ip = previous_lmf */
522 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
523 /* lr = lmf_addr */
524 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
525 /* *(lmf_addr) = previous_lmf */
526 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
527
528 return code;
529 }
530
531 #endif /* #ifndef DISABLE_JIT */
532
533 /*
534 * mono_arch_get_argument_info:
535 * @csig: a method signature
536 * @param_count: the number of parameters to consider
537 * @arg_info: an array to store the result infos
538 *
539 * Gathers information on parameters such as size, alignment and
540 * padding. arg_info should be large enought to hold param_count + 1 entries.
541 *
542 * Returns the size of the activation frame.
543 */
544 int
545 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
546 {
547 int k, frame_size = 0;
548 guint32 size, align, pad;
549 int offset = 8;
550 MonoType *t;
551
552 t = mini_get_underlying_type (csig->ret);
553 if (MONO_TYPE_ISSTRUCT (t)) {
554 frame_size += sizeof (gpointer);
555 offset += 4;
556 }
557
558 arg_info [0].offset = offset;
559
560 if (csig->hasthis) {
561 frame_size += sizeof (gpointer);
562 offset += 4;
563 }
564
565 arg_info [0].size = frame_size;
566
567 for (k = 0; k < param_count; k++) {
568 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
569
570 /* ignore alignment for now */
571 align = 1;
572
573 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
574 arg_info [k].pad = pad;
575 frame_size += size;
576 arg_info [k + 1].pad = 0;
577 arg_info [k + 1].size = size;
578 offset += pad;
579 arg_info [k + 1].offset = offset;
580 offset += size;
581 }
582
583 align = MONO_ARCH_FRAME_ALIGNMENT;
584 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
585 arg_info [k].pad = pad;
586
587 return frame_size;
588 }
589
590 #define MAX_ARCH_DELEGATE_PARAMS 3
591
592 static gpointer
593 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
594 {
595 guint8 *code, *start;
596 GSList *unwind_ops = mono_arch_get_cie_program ();
597
598 if (has_target) {
599 start = code = mono_global_codeman_reserve (12);
600
601 /* Replace the this argument with the target */
602 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
603 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
604 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
605
606 g_assert ((code - start) <= 12);
607
608 mono_arch_flush_icache (start, 12);
609 } else {
610 int size, i;
611
612 size = 8 + param_count * 4;
613 start = code = mono_global_codeman_reserve (size);
614
615 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
616 /* slide down the arguments */
617 for (i = 0; i < param_count; ++i) {
618 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
619 }
620 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
621
622 g_assert ((code - start) <= size);
623
624 mono_arch_flush_icache (start, size);
625 }
626
627 if (has_target) {
628 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
629 } else {
630 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
631 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
632 g_free (name);
633 }
634
635 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
636
637 return start;
638 }
639
640 /*
641 * mono_arch_get_delegate_invoke_impls:
642 *
643 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
644 * trampolines.
645 */
646 GSList*
647 mono_arch_get_delegate_invoke_impls (void)
648 {
649 GSList *res = NULL;
650 MonoTrampInfo *info;
651 int i;
652
653 get_delegate_invoke_impl (&info, TRUE, 0);
654 res = g_slist_prepend (res, info);
655
656 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
657 get_delegate_invoke_impl (&info, FALSE, i);
658 res = g_slist_prepend (res, info);
659 }
660
661 return res;
662 }
663
664 gpointer
665 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
666 {
667 guint8 *code, *start;
668 MonoType *sig_ret;
669
670 /* FIXME: Support more cases */
671 sig_ret = mini_get_underlying_type (sig->ret);
672 if (MONO_TYPE_ISSTRUCT (sig_ret))
673 return NULL;
674
675 if (has_target) {
676 static guint8* cached = NULL;
677 mono_mini_arch_lock ();
678 if (cached) {
679 mono_mini_arch_unlock ();
680 return cached;
681 }
682
683 if (mono_aot_only) {
684 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
685 } else {
686 MonoTrampInfo *info;
687 start = get_delegate_invoke_impl (&info, TRUE, 0);
688 mono_tramp_info_register (info, NULL);
689 }
690 cached = start;
691 mono_mini_arch_unlock ();
692 return cached;
693 } else {
694 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
695 int i;
696
697 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
698 return NULL;
699 for (i = 0; i < sig->param_count; ++i)
700 if (!mono_is_regsize_var (sig->params [i]))
701 return NULL;
702
703 mono_mini_arch_lock ();
704 code = cache [sig->param_count];
705 if (code) {
706 mono_mini_arch_unlock ();
707 return code;
708 }
709
710 if (mono_aot_only) {
711 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
712 start = mono_aot_get_trampoline (name);
713 g_free (name);
714 } else {
715 MonoTrampInfo *info;
716 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
717 mono_tramp_info_register (info, NULL);
718 }
719 cache [sig->param_count] = start;
720 mono_mini_arch_unlock ();
721 return start;
722 }
723
724 return NULL;
725 }
726
727 gpointer
728 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
729 {
730 return NULL;
731 }
732
733 gpointer
734 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
735 {
736 return (gpointer)regs [ARMREG_R0];
737 }
738
739 /*
740 * Initialize the cpu to execute managed code.
741 */
742 void
743 mono_arch_cpu_init (void)
744 {
745 i8_align = MONO_ABI_ALIGNOF (gint64);
746 #ifdef MONO_CROSS_COMPILE
747 /* Need to set the alignment of i8 since it can different on the target */
748 #ifdef TARGET_ANDROID
749 /* linux gnueabi */
750 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
751 #endif
752 #endif
753 }
754
755 /*
756 * Initialize architecture specific code.
757 */
758 void
759 mono_arch_init (void)
760 {
761 const char *cpu_arch;
762
763 #ifdef TARGET_WATCHOS
764 mini_get_debug_options ()->soft_breakpoints = TRUE;
765 #endif
766
767 mono_os_mutex_init_recursive (&mini_arch_mutex);
768 if (mini_get_debug_options ()->soft_breakpoints) {
769 if (!mono_aot_only)
770 breakpoint_tramp = mini_get_breakpoint_trampoline ();
771 } else {
772 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
773 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
775 }
776
777 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
779 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
780 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
781 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
782 #endif
783 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
784
785 #if defined(__ARM_EABI__)
786 eabi_supported = TRUE;
787 #endif
788
789 #if defined(ARM_FPU_VFP_HARD)
790 arm_fpu = MONO_ARM_FPU_VFP_HARD;
791 #else
792 arm_fpu = MONO_ARM_FPU_VFP;
793
794 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
795 /*
796 * If we're compiling with a soft float fallback and it
797 * turns out that no VFP unit is available, we need to
798 * switch to soft float. We don't do this for iOS, since
799 * iOS devices always have a VFP unit.
800 */
801 if (!mono_hwcap_arm_has_vfp)
802 arm_fpu = MONO_ARM_FPU_NONE;
803
804 /*
805 * This environment variable can be useful in testing
806 * environments to make sure the soft float fallback
807 * works. Most ARM devices have VFP units these days, so
808 * normally soft float code would not be exercised much.
809 */
810 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
811
812 if (soft && !strncmp (soft, "1", 1))
813 arm_fpu = MONO_ARM_FPU_NONE;
814 #endif
815 #endif
816
817 v5_supported = mono_hwcap_arm_is_v5;
818 v6_supported = mono_hwcap_arm_is_v6;
819 v7_supported = mono_hwcap_arm_is_v7;
820
821 /*
822 * On weird devices, the hwcap code may fail to detect
823 * the ARM version. In that case, we can at least safely
824 * assume the version the runtime was compiled for.
825 */
826 #ifdef HAVE_ARMV5
827 v5_supported = TRUE;
828 #endif
829 #ifdef HAVE_ARMV6
830 v6_supported = TRUE;
831 #endif
832 #ifdef HAVE_ARMV7
833 v7_supported = TRUE;
834 #endif
835
836 #if defined(__APPLE__)
837 /* iOS is special-cased here because we don't yet
838 have a way to properly detect CPU features on it. */
839 thumb_supported = TRUE;
840 iphone_abi = TRUE;
841 #else
842 thumb_supported = mono_hwcap_arm_has_thumb;
843 thumb2_supported = mono_hwcap_arm_has_thumb2;
844 #endif
845
846 /* Format: armv(5|6|7[s])[-thumb[2]] */
847 cpu_arch = g_getenv ("MONO_CPU_ARCH");
848
849 /* Do this here so it overrides any detection. */
850 if (cpu_arch) {
851 if (strncmp (cpu_arch, "armv", 4) == 0) {
852 v5_supported = cpu_arch [4] >= '5';
853 v6_supported = cpu_arch [4] >= '6';
854 v7_supported = cpu_arch [4] >= '7';
855 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
856 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
857 }
858
859 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
860 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
861 }
862 }
863
864 /*
865 * Cleanup architecture specific code.
866 */
867 void
868 mono_arch_cleanup (void)
869 {
870 }
871
872 /*
873 * This function returns the optimizations supported on this cpu.
874 */
875 guint32
876 mono_arch_cpu_optimizations (guint32 *exclude_mask)
877 {
878 /* no arm-specific optimizations yet */
879 *exclude_mask = 0;
880 return 0;
881 }
882
883 /*
884 * This function test for all SIMD functions supported.
885 *
886 * Returns a bitmask corresponding to all supported versions.
887 *
888 */
889 guint32
890 mono_arch_cpu_enumerate_simd_versions (void)
891 {
892 /* SIMD is currently unimplemented */
893 return 0;
894 }
895
896 gboolean
897 mono_arm_is_hard_float (void)
898 {
899 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
900 }
901
902 #ifndef DISABLE_JIT
903
904 gboolean
905 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
906 {
907 if (v7s_supported || v7k_supported) {
908 switch (opcode) {
909 case OP_IDIV:
910 case OP_IREM:
911 case OP_IDIV_UN:
912 case OP_IREM_UN:
913 return FALSE;
914 default:
915 break;
916 }
917 }
918 return TRUE;
919 }
920
921 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
922 gboolean
923 mono_arch_is_soft_float (void)
924 {
925 return arm_fpu == MONO_ARM_FPU_NONE;
926 }
927 #endif
928
929 static gboolean
930 is_regsize_var (MonoType *t)
931 {
932 if (t->byref)
933 return TRUE;
934 t = mini_get_underlying_type (t);
935 switch (t->type) {
936 case MONO_TYPE_I4:
937 case MONO_TYPE_U4:
938 case MONO_TYPE_I:
939 case MONO_TYPE_U:
940 case MONO_TYPE_PTR:
941 case MONO_TYPE_FNPTR:
942 return TRUE;
943 case MONO_TYPE_OBJECT:
944 case MONO_TYPE_STRING:
945 case MONO_TYPE_CLASS:
946 case MONO_TYPE_SZARRAY:
947 case MONO_TYPE_ARRAY:
948 return TRUE;
949 case MONO_TYPE_GENERICINST:
950 if (!mono_type_generic_inst_is_valuetype (t))
951 return TRUE;
952 return FALSE;
953 case MONO_TYPE_VALUETYPE:
954 return FALSE;
955 }
956 return FALSE;
957 }
958
959 GList *
960 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
961 {
962 GList *vars = NULL;
963 int i;
964
965 for (i = 0; i < cfg->num_varinfo; i++) {
966 MonoInst *ins = cfg->varinfo [i];
967 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
968
969 /* unused vars */
970 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
971 continue;
972
973 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
974 continue;
975
976 /* we can only allocate 32 bit values */
977 if (is_regsize_var (ins->inst_vtype)) {
978 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
979 g_assert (i == vmv->idx);
980 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
981 }
982 }
983
984 return vars;
985 }
986
987 GList *
988 mono_arch_get_global_int_regs (MonoCompile *cfg)
989 {
990 GList *regs = NULL;
991
992 mono_arch_compute_omit_fp (cfg);
993
994 /*
995 * FIXME: Interface calls might go through a static rgctx trampoline which
996 * sets V5, but it doesn't save it, so we need to save it ourselves, and
997 * avoid using it.
998 */
999 if (cfg->flags & MONO_CFG_HAS_CALLS)
1000 cfg->uses_rgctx_reg = TRUE;
1001
1002 if (cfg->arch.omit_fp)
1003 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1006 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1007 if (iphone_abi)
1008 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1009 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1010 else
1011 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1012 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1013 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1014 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1015 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1016 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1017
1018 return regs;
1019 }
1020
1021 /*
1022 * mono_arch_regalloc_cost:
1023 *
1024 * Return the cost, in number of memory references, of the action of
1025 * allocating the variable VMV into a register during global register
1026 * allocation.
1027 */
1028 guint32
1029 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1030 {
1031 /* FIXME: */
1032 return 2;
1033 }
1034
1035 #endif /* #ifndef DISABLE_JIT */
1036
1037 void
1038 mono_arch_flush_icache (guint8 *code, gint size)
1039 {
1040 #if defined(MONO_CROSS_COMPILE)
1041 #elif __APPLE__
1042 sys_icache_invalidate (code, size);
1043 #else
1044 __builtin___clear_cache (code, code + size);
1045 #endif
1046 }
1047
1048 #define DEBUG(a)
1049
1050 static void inline
1051 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1052 {
1053 if (simple) {
1054 if (*gr > ARMREG_R3) {
1055 ainfo->size = 4;
1056 ainfo->offset = *stack_size;
1057 ainfo->reg = ARMREG_SP; /* in the caller */
1058 ainfo->storage = RegTypeBase;
1059 *stack_size += 4;
1060 } else {
1061 ainfo->storage = RegTypeGeneral;
1062 ainfo->reg = *gr;
1063 }
1064 } else {
1065 gboolean split;
1066
1067 if (eabi_supported)
1068 split = i8_align == 4;
1069 else
1070 split = TRUE;
1071
1072 ainfo->size = 8;
1073 if (*gr == ARMREG_R3 && split) {
1074 /* first word in r3 and the second on the stack */
1075 ainfo->offset = *stack_size;
1076 ainfo->reg = ARMREG_SP; /* in the caller */
1077 ainfo->storage = RegTypeBaseGen;
1078 *stack_size += 4;
1079 } else if (*gr >= ARMREG_R3) {
1080 if (eabi_supported) {
1081 /* darwin aligns longs to 4 byte only */
1082 if (i8_align == 8) {
1083 *stack_size += 7;
1084 *stack_size &= ~7;
1085 }
1086 }
1087 ainfo->offset = *stack_size;
1088 ainfo->reg = ARMREG_SP; /* in the caller */
1089 ainfo->storage = RegTypeBase;
1090 *stack_size += 8;
1091 } else {
1092 if (eabi_supported) {
1093 if (i8_align == 8 && ((*gr) & 1))
1094 (*gr) ++;
1095 }
1096 ainfo->storage = RegTypeIRegPair;
1097 ainfo->reg = *gr;
1098 }
1099 (*gr) ++;
1100 }
1101 (*gr) ++;
1102 }
1103
1104 static void inline
1105 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1106 {
1107 /*
1108 * If we're calling a function like this:
1109 *
1110 * void foo(float a, double b, float c)
1111 *
1112 * We pass a in s0 and b in d1. That leaves us
1113 * with s1 being unused. The armhf ABI recognizes
1114 * this and requires register assignment to then
1115 * use that for the next single-precision arg,
1116 * i.e. c in this example. So float_spare either
1117 * tells us which reg to use for the next single-
1118 * precision arg, or it's -1, meaning use *fpr.
1119 *
1120 * Note that even though most of the JIT speaks
1121 * double-precision, fpr represents single-
1122 * precision registers.
1123 *
1124 * See parts 5.5 and 6.1.2 of the AAPCS for how
1125 * this all works.
1126 */
1127
1128 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1129 ainfo->storage = RegTypeFP;
1130
1131 if (is_double) {
1132 /*
1133 * If we're passing a double-precision value
1134 * and *fpr is odd (e.g. it's s1, s3, ...)
1135 * we need to use the next even register. So
1136 * we mark the current *fpr as a spare that
1137 * can be used for the next single-precision
1138 * value.
1139 */
1140 if (*fpr % 2) {
1141 *float_spare = *fpr;
1142 (*fpr)++;
1143 }
1144
1145 /*
1146 * At this point, we have an even register
1147 * so we assign that and move along.
1148 */
1149 ainfo->reg = *fpr;
1150 *fpr += 2;
1151 } else if (*float_spare >= 0) {
1152 /*
1153 * We're passing a single-precision value
1154 * and it looks like a spare single-
1155 * precision register is available. Let's
1156 * use it.
1157 */
1158
1159 ainfo->reg = *float_spare;
1160 *float_spare = -1;
1161 } else {
1162 /*
1163 * If we hit this branch, we're passing a
1164 * single-precision value and we can simply
1165 * use the next available register.
1166 */
1167
1168 ainfo->reg = *fpr;
1169 (*fpr)++;
1170 }
1171 } else {
1172 /*
1173 * We've exhausted available floating point
1174 * regs, so pass the rest on the stack.
1175 */
1176
1177 if (is_double) {
1178 *stack_size += 7;
1179 *stack_size &= ~7;
1180 }
1181
1182 ainfo->offset = *stack_size;
1183 ainfo->reg = ARMREG_SP;
1184 ainfo->storage = RegTypeBase;
1185
1186 *stack_size += 8;
1187 }
1188 }
1189
1190 static gboolean
1191 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1192 {
1193 MonoClass *klass;
1194 gpointer iter;
1195 MonoClassField *field;
1196 MonoType *ftype, *prev_ftype = NULL;
1197 int nfields = 0;
1198
1199 klass = mono_class_from_mono_type (t);
1200 iter = NULL;
1201 while ((field = mono_class_get_fields (klass, &iter))) {
1202 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1203 continue;
1204 ftype = mono_field_get_type (field);
1205 ftype = mini_get_underlying_type (ftype);
1206
1207 if (MONO_TYPE_ISSTRUCT (ftype)) {
1208 int nested_nfields, nested_esize;
1209
1210 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1211 return FALSE;
1212 if (nested_esize == 4)
1213 ftype = &mono_defaults.single_class->byval_arg;
1214 else
1215 ftype = &mono_defaults.double_class->byval_arg;
1216 if (prev_ftype && prev_ftype->type != ftype->type)
1217 return FALSE;
1218 prev_ftype = ftype;
1219 nfields += nested_nfields;
1220 } else {
1221 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1222 return FALSE;
1223 if (prev_ftype && prev_ftype->type != ftype->type)
1224 return FALSE;
1225 prev_ftype = ftype;
1226 nfields ++;
1227 }
1228 }
1229 if (nfields == 0 || nfields > 4)
1230 return FALSE;
1231 *out_nfields = nfields;
1232 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1233 return TRUE;
1234 }
1235
1236 static CallInfo*
1237 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1238 {
1239 guint i, gr, fpr, pstart;
1240 gint float_spare;
1241 int n = sig->hasthis + sig->param_count;
1242 int nfields, esize;
1243 guint32 align;
1244 MonoType *t;
1245 guint32 stack_size = 0;
1246 CallInfo *cinfo;
1247 gboolean is_pinvoke = sig->pinvoke;
1248 gboolean vtype_retaddr = FALSE;
1249
1250 if (mp)
1251 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1252 else
1253 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1254
1255 cinfo->nargs = n;
1256 gr = ARMREG_R0;
1257 fpr = ARM_VFP_F0;
1258 float_spare = -1;
1259
1260 t = mini_get_underlying_type (sig->ret);
1261 switch (t->type) {
1262 case MONO_TYPE_I1:
1263 case MONO_TYPE_U1:
1264 case MONO_TYPE_I2:
1265 case MONO_TYPE_U2:
1266 case MONO_TYPE_I4:
1267 case MONO_TYPE_U4:
1268 case MONO_TYPE_I:
1269 case MONO_TYPE_U:
1270 case MONO_TYPE_PTR:
1271 case MONO_TYPE_FNPTR:
1272 case MONO_TYPE_CLASS:
1273 case MONO_TYPE_OBJECT:
1274 case MONO_TYPE_SZARRAY:
1275 case MONO_TYPE_ARRAY:
1276 case MONO_TYPE_STRING:
1277 cinfo->ret.storage = RegTypeGeneral;
1278 cinfo->ret.reg = ARMREG_R0;
1279 break;
1280 case MONO_TYPE_U8:
1281 case MONO_TYPE_I8:
1282 cinfo->ret.storage = RegTypeIRegPair;
1283 cinfo->ret.reg = ARMREG_R0;
1284 break;
1285 case MONO_TYPE_R4:
1286 case MONO_TYPE_R8:
1287 cinfo->ret.storage = RegTypeFP;
1288
1289 if (t->type == MONO_TYPE_R4)
1290 cinfo->ret.size = 4;
1291 else
1292 cinfo->ret.size = 8;
1293
1294 if (IS_HARD_FLOAT) {
1295 cinfo->ret.reg = ARM_VFP_F0;
1296 } else {
1297 cinfo->ret.reg = ARMREG_R0;
1298 }
1299 break;
1300 case MONO_TYPE_GENERICINST:
1301 if (!mono_type_generic_inst_is_valuetype (t)) {
1302 cinfo->ret.storage = RegTypeGeneral;
1303 cinfo->ret.reg = ARMREG_R0;
1304 break;
1305 }
1306 if (mini_is_gsharedvt_variable_type (t)) {
1307 cinfo->ret.storage = RegTypeStructByAddr;
1308 break;
1309 }
1310 /* Fall through */
1311 case MONO_TYPE_VALUETYPE:
1312 case MONO_TYPE_TYPEDBYREF:
1313 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1314 cinfo->ret.storage = RegTypeHFA;
1315 cinfo->ret.reg = 0;
1316 cinfo->ret.nregs = nfields;
1317 cinfo->ret.esize = esize;
1318 } else {
1319 if (is_pinvoke) {
1320 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1321 int max_size;
1322
1323 #ifdef TARGET_WATCHOS
1324 max_size = 16;
1325 #else
1326 max_size = 4;
1327 #endif
1328 if (native_size <= max_size) {
1329 cinfo->ret.storage = RegTypeStructByVal;
1330 cinfo->ret.struct_size = native_size;
1331 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1332 } else {
1333 cinfo->ret.storage = RegTypeStructByAddr;
1334 }
1335 } else {
1336 cinfo->ret.storage = RegTypeStructByAddr;
1337 }
1338 }
1339 break;
1340 case MONO_TYPE_VAR:
1341 case MONO_TYPE_MVAR:
1342 g_assert (mini_is_gsharedvt_type (t));
1343 cinfo->ret.storage = RegTypeStructByAddr;
1344 break;
1345 case MONO_TYPE_VOID:
1346 break;
1347 default:
1348 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1349 }
1350
1351 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1352
1353 pstart = 0;
1354 n = 0;
1355 /*
1356 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1357 * the first argument, allowing 'this' to be always passed in the first arg reg.
1358 * Also do this if the first argument is a reference type, since virtual calls
1359 * are sometimes made using calli without sig->hasthis set, like in the delegate
1360 * invoke wrappers.
1361 */
1362 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1363 if (sig->hasthis) {
1364 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1365 } else {
1366 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1367 pstart = 1;
1368 }
1369 n ++;
1370 cinfo->ret.reg = gr;
1371 gr ++;
1372 cinfo->vret_arg_index = 1;
1373 } else {
1374 /* this */
1375 if (sig->hasthis) {
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1377 n ++;
1378 }
1379 if (vtype_retaddr) {
1380 cinfo->ret.reg = gr;
1381 gr ++;
1382 }
1383 }
1384
1385 DEBUG(g_print("params: %d\n", sig->param_count));
1386 for (i = pstart; i < sig->param_count; ++i) {
1387 ArgInfo *ainfo = &cinfo->args [n];
1388
1389 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1390 /* Prevent implicit arguments and sig_cookie from
1391 being passed in registers */
1392 gr = ARMREG_R3 + 1;
1393 fpr = ARM_VFP_F16;
1394 /* Emit the signature cookie just before the implicit arguments */
1395 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1396 }
1397 DEBUG(g_print("param %d: ", i));
1398 if (sig->params [i]->byref) {
1399 DEBUG(g_print("byref\n"));
1400 add_general (&gr, &stack_size, ainfo, TRUE);
1401 n++;
1402 continue;
1403 }
1404 t = mini_get_underlying_type (sig->params [i]);
1405 switch (t->type) {
1406 case MONO_TYPE_I1:
1407 case MONO_TYPE_U1:
1408 cinfo->args [n].size = 1;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1410 break;
1411 case MONO_TYPE_I2:
1412 case MONO_TYPE_U2:
1413 cinfo->args [n].size = 2;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1415 break;
1416 case MONO_TYPE_I4:
1417 case MONO_TYPE_U4:
1418 cinfo->args [n].size = 4;
1419 add_general (&gr, &stack_size, ainfo, TRUE);
1420 break;
1421 case MONO_TYPE_I:
1422 case MONO_TYPE_U:
1423 case MONO_TYPE_PTR:
1424 case MONO_TYPE_FNPTR:
1425 case MONO_TYPE_CLASS:
1426 case MONO_TYPE_OBJECT:
1427 case MONO_TYPE_STRING:
1428 case MONO_TYPE_SZARRAY:
1429 case MONO_TYPE_ARRAY:
1430 cinfo->args [n].size = sizeof (gpointer);
1431 add_general (&gr, &stack_size, ainfo, TRUE);
1432 break;
1433 case MONO_TYPE_GENERICINST:
1434 if (!mono_type_generic_inst_is_valuetype (t)) {
1435 cinfo->args [n].size = sizeof (gpointer);
1436 add_general (&gr, &stack_size, ainfo, TRUE);
1437 break;
1438 }
1439 if (mini_is_gsharedvt_variable_type (t)) {
1440 /* gsharedvt arguments are passed by ref */
1441 g_assert (mini_is_gsharedvt_type (t));
1442 add_general (&gr, &stack_size, ainfo, TRUE);
1443 switch (ainfo->storage) {
1444 case RegTypeGeneral:
1445 ainfo->storage = RegTypeGSharedVtInReg;
1446 break;
1447 case RegTypeBase:
1448 ainfo->storage = RegTypeGSharedVtOnStack;
1449 break;
1450 default:
1451 g_assert_not_reached ();
1452 }
1453 break;
1454 }
1455 /* Fall through */
1456 case MONO_TYPE_TYPEDBYREF:
1457 case MONO_TYPE_VALUETYPE: {
1458 gint size;
1459 int align_size;
1460 int nwords, nfields, esize;
1461 guint32 align;
1462
1463 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1464 if (fpr + nfields < ARM_VFP_F16) {
1465 ainfo->storage = RegTypeHFA;
1466 ainfo->reg = fpr;
1467 ainfo->nregs = nfields;
1468 ainfo->esize = esize;
1469 if (esize == 4)
1470 fpr += nfields;
1471 else
1472 fpr += nfields * 2;
1473 break;
1474 } else {
1475 fpr = ARM_VFP_F16;
1476 }
1477 }
1478
1479 if (t->type == MONO_TYPE_TYPEDBYREF) {
1480 size = sizeof (MonoTypedRef);
1481 align = sizeof (gpointer);
1482 } else {
1483 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1484 if (is_pinvoke)
1485 size = mono_class_native_size (klass, &align);
1486 else
1487 size = mini_type_stack_size_full (t, &align, FALSE);
1488 }
1489 DEBUG(g_print ("load %d bytes struct\n", size));
1490
1491 #ifdef TARGET_WATCHOS
1492 /* Watchos pass large structures by ref */
1493 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1494 if (sig->pinvoke && size > 16) {
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1496 switch (ainfo->storage) {
1497 case RegTypeGeneral:
1498 ainfo->storage = RegTypeStructByAddr;
1499 break;
1500 case RegTypeBase:
1501 ainfo->storage = RegTypeStructByAddrOnStack;
1502 break;
1503 default:
1504 g_assert_not_reached ();
1505 break;
1506 }
1507 break;
1508 }
1509 #endif
1510
1511 align_size = size;
1512 nwords = 0;
1513 align_size += (sizeof (gpointer) - 1);
1514 align_size &= ~(sizeof (gpointer) - 1);
1515 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1516 ainfo->storage = RegTypeStructByVal;
1517 ainfo->struct_size = size;
1518 /* FIXME: align stack_size if needed */
1519 if (eabi_supported) {
1520 if (align >= 8 && (gr & 1))
1521 gr ++;
1522 }
1523 if (gr > ARMREG_R3) {
1524 ainfo->size = 0;
1525 ainfo->vtsize = nwords;
1526 } else {
1527 int rest = ARMREG_R3 - gr + 1;
1528 int n_in_regs = rest >= nwords? nwords: rest;
1529
1530 ainfo->size = n_in_regs;
1531 ainfo->vtsize = nwords - n_in_regs;
1532 ainfo->reg = gr;
1533 gr += n_in_regs;
1534 nwords -= n_in_regs;
1535 }
1536 if (sig->call_convention == MONO_CALL_VARARG)
1537 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1538 stack_size = ALIGN_TO (stack_size, align);
1539 ainfo->offset = stack_size;
1540 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1541 stack_size += nwords * sizeof (gpointer);
1542 break;
1543 }
1544 case MONO_TYPE_U8:
1545 case MONO_TYPE_I8:
1546 ainfo->size = 8;
1547 add_general (&gr, &stack_size, ainfo, FALSE);
1548 break;
1549 case MONO_TYPE_R4:
1550 ainfo->size = 4;
1551
1552 if (IS_HARD_FLOAT)
1553 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1554 else
1555 add_general (&gr, &stack_size, ainfo, TRUE);
1556 break;
1557 case MONO_TYPE_R8:
1558 ainfo->size = 8;
1559
1560 if (IS_HARD_FLOAT)
1561 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1562 else
1563 add_general (&gr, &stack_size, ainfo, FALSE);
1564 break;
1565 case MONO_TYPE_VAR:
1566 case MONO_TYPE_MVAR:
1567 /* gsharedvt arguments are passed by ref */
1568 g_assert (mini_is_gsharedvt_type (t));
1569 add_general (&gr, &stack_size, ainfo, TRUE);
1570 switch (ainfo->storage) {
1571 case RegTypeGeneral:
1572 ainfo->storage = RegTypeGSharedVtInReg;
1573 break;
1574 case RegTypeBase:
1575 ainfo->storage = RegTypeGSharedVtOnStack;
1576 break;
1577 default:
1578 g_assert_not_reached ();
1579 }
1580 break;
1581 default:
1582 g_error ("Can't handle 0x%x", sig->params [i]->type);
1583 }
1584 n ++;
1585 }
1586
1587 /* Handle the case where there are no implicit arguments */
1588 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1589 /* Prevent implicit arguments and sig_cookie from
1590 being passed in registers */
1591 gr = ARMREG_R3 + 1;
1592 fpr = ARM_VFP_F16;
1593 /* Emit the signature cookie just before the implicit arguments */
1594 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1595 }
1596
1597 /* align stack size to 8 */
1598 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1599 stack_size = (stack_size + 7) & ~7;
1600
1601 cinfo->stack_usage = stack_size;
1602 return cinfo;
1603 }
1604
1605
1606 gboolean
1607 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1608 {
1609 MonoType *callee_ret;
1610 CallInfo *c1, *c2;
1611 gboolean res;
1612
1613 c1 = get_call_info (NULL, caller_sig);
1614 c2 = get_call_info (NULL, callee_sig);
1615
1616 /*
1617 * Tail calls with more callee stack usage than the caller cannot be supported, since
1618 * the extra stack space would be left on the stack after the tail call.
1619 */
1620 res = c1->stack_usage >= c2->stack_usage;
1621 callee_ret = mini_get_underlying_type (callee_sig->ret);
1622 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1623 /* An address on the callee's stack is passed as the first argument */
1624 res = FALSE;
1625
1626 if (c2->stack_usage > 16 * 4)
1627 res = FALSE;
1628
1629 g_free (c1);
1630 g_free (c2);
1631
1632 return res;
1633 }
1634
1635 #ifndef DISABLE_JIT
1636
1637 static gboolean
1638 debug_omit_fp (void)
1639 {
1640 #if 0
1641 return mono_debug_count ();
1642 #else
1643 return TRUE;
1644 #endif
1645 }
1646
1647 /**
1648 * mono_arch_compute_omit_fp:
1649 *
1650 * Determine whenever the frame pointer can be eliminated.
1651 */
1652 static void
1653 mono_arch_compute_omit_fp (MonoCompile *cfg)
1654 {
1655 MonoMethodSignature *sig;
1656 MonoMethodHeader *header;
1657 int i, locals_size;
1658 CallInfo *cinfo;
1659
1660 if (cfg->arch.omit_fp_computed)
1661 return;
1662
1663 header = cfg->header;
1664
1665 sig = mono_method_signature (cfg->method);
1666
1667 if (!cfg->arch.cinfo)
1668 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1669 cinfo = cfg->arch.cinfo;
1670
1671 /*
1672 * FIXME: Remove some of the restrictions.
1673 */
1674 cfg->arch.omit_fp = TRUE;
1675 cfg->arch.omit_fp_computed = TRUE;
1676
1677 if (cfg->disable_omit_fp)
1678 cfg->arch.omit_fp = FALSE;
1679 if (!debug_omit_fp ())
1680 cfg->arch.omit_fp = FALSE;
1681 /*
1682 if (cfg->method->save_lmf)
1683 cfg->arch.omit_fp = FALSE;
1684 */
1685 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1686 cfg->arch.omit_fp = FALSE;
1687 if (header->num_clauses)
1688 cfg->arch.omit_fp = FALSE;
1689 if (cfg->param_area)
1690 cfg->arch.omit_fp = FALSE;
1691 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1692 cfg->arch.omit_fp = FALSE;
1693 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1694 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1695 cfg->arch.omit_fp = FALSE;
1696 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1697 ArgInfo *ainfo = &cinfo->args [i];
1698
1699 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1700 /*
1701 * The stack offset can only be determined when the frame
1702 * size is known.
1703 */
1704 cfg->arch.omit_fp = FALSE;
1705 }
1706 }
1707
1708 locals_size = 0;
1709 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1710 MonoInst *ins = cfg->varinfo [i];
1711 int ialign;
1712
1713 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1714 }
1715 }
1716
1717 /*
1718 * Set var information according to the calling convention. arm version.
1719 * The locals var stuff should most likely be split in another method.
1720 */
1721 void
1722 mono_arch_allocate_vars (MonoCompile *cfg)
1723 {
1724 MonoMethodSignature *sig;
1725 MonoMethodHeader *header;
1726 MonoInst *ins;
1727 MonoType *sig_ret;
1728 int i, offset, size, align, curinst;
1729 CallInfo *cinfo;
1730 ArgInfo *ainfo;
1731 guint32 ualign;
1732
1733 sig = mono_method_signature (cfg->method);
1734
1735 if (!cfg->arch.cinfo)
1736 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1737 cinfo = cfg->arch.cinfo;
1738 sig_ret = mini_get_underlying_type (sig->ret);
1739
1740 mono_arch_compute_omit_fp (cfg);
1741
1742 if (cfg->arch.omit_fp)
1743 cfg->frame_reg = ARMREG_SP;
1744 else
1745 cfg->frame_reg = ARMREG_FP;
1746
1747 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1748
1749 /* allow room for the vararg method args: void* and long/double */
1750 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1751 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1752
1753 header = cfg->header;
1754
1755 /* See mono_arch_get_global_int_regs () */
1756 if (cfg->flags & MONO_CFG_HAS_CALLS)
1757 cfg->uses_rgctx_reg = TRUE;
1758
1759 if (cfg->frame_reg != ARMREG_SP)
1760 cfg->used_int_regs |= 1 << cfg->frame_reg;
1761
1762 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1763 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1764 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1765
1766 offset = 0;
1767 curinst = 0;
1768 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1769 if (sig_ret->type != MONO_TYPE_VOID) {
1770 cfg->ret->opcode = OP_REGVAR;
1771 cfg->ret->inst_c0 = ARMREG_R0;
1772 }
1773 }
1774 /* local vars are at a positive offset from the stack pointer */
1775 /*
1776 * also note that if the function uses alloca, we use FP
1777 * to point at the local variables.
1778 */
1779 offset = 0; /* linkage area */
1780 /* align the offset to 16 bytes: not sure this is needed here */
1781 //offset += 8 - 1;
1782 //offset &= ~(8 - 1);
1783
1784 /* add parameter area size for called functions */
1785 offset += cfg->param_area;
1786 offset += 8 - 1;
1787 offset &= ~(8 - 1);
1788 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1789 offset += 8;
1790
1791 /* allow room to save the return value */
1792 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1793 offset += 8;
1794
1795 switch (cinfo->ret.storage) {
1796 case RegTypeStructByVal:
1797 case RegTypeHFA:
1798 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1799 offset = ALIGN_TO (offset, 8);
1800 cfg->ret->opcode = OP_REGOFFSET;
1801 cfg->ret->inst_basereg = cfg->frame_reg;
1802 cfg->ret->inst_offset = offset;
1803 if (cinfo->ret.storage == RegTypeStructByVal)
1804 offset += cinfo->ret.nregs * sizeof (gpointer);
1805 else
1806 offset += 32;
1807 break;
1808 case RegTypeStructByAddr:
1809 ins = cfg->vret_addr;
1810 offset += sizeof(gpointer) - 1;
1811 offset &= ~(sizeof(gpointer) - 1);
1812 ins->inst_offset = offset;
1813 ins->opcode = OP_REGOFFSET;
1814 ins->inst_basereg = cfg->frame_reg;
1815 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1816 g_print ("vret_addr =");
1817 mono_print_ins (cfg->vret_addr);
1818 }
1819 offset += sizeof(gpointer);
1820 break;
1821 default:
1822 break;
1823 }
1824
1825 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1826 if (cfg->arch.seq_point_info_var) {
1827 MonoInst *ins;
1828
1829 ins = cfg->arch.seq_point_info_var;
1830
1831 size = 4;
1832 align = 4;
1833 offset += align - 1;
1834 offset &= ~(align - 1);
1835 ins->opcode = OP_REGOFFSET;
1836 ins->inst_basereg = cfg->frame_reg;
1837 ins->inst_offset = offset;
1838 offset += size;
1839 }
1840 if (cfg->arch.ss_trigger_page_var) {
1841 MonoInst *ins;
1842
1843 ins = cfg->arch.ss_trigger_page_var;
1844 size = 4;
1845 align = 4;
1846 offset += align - 1;
1847 offset &= ~(align - 1);
1848 ins->opcode = OP_REGOFFSET;
1849 ins->inst_basereg = cfg->frame_reg;
1850 ins->inst_offset = offset;
1851 offset += size;
1852 }
1853
1854 if (cfg->arch.seq_point_ss_method_var) {
1855 MonoInst *ins;
1856
1857 ins = cfg->arch.seq_point_ss_method_var;
1858 size = 4;
1859 align = 4;
1860 offset += align - 1;
1861 offset &= ~(align - 1);
1862 ins->opcode = OP_REGOFFSET;
1863 ins->inst_basereg = cfg->frame_reg;
1864 ins->inst_offset = offset;
1865 offset += size;
1866 }
1867 if (cfg->arch.seq_point_bp_method_var) {
1868 MonoInst *ins;
1869
1870 ins = cfg->arch.seq_point_bp_method_var;
1871 size = 4;
1872 align = 4;
1873 offset += align - 1;
1874 offset &= ~(align - 1);
1875 ins->opcode = OP_REGOFFSET;
1876 ins->inst_basereg = cfg->frame_reg;
1877 ins->inst_offset = offset;
1878 offset += size;
1879 }
1880
1881 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1882 /* Allocate a temporary used by the atomic ops */
1883 size = 4;
1884 align = 4;
1885
1886 /* Allocate a local slot to hold the sig cookie address */
1887 offset += align - 1;
1888 offset &= ~(align - 1);
1889 cfg->arch.atomic_tmp_offset = offset;
1890 offset += size;
1891 } else {
1892 cfg->arch.atomic_tmp_offset = -1;
1893 }
1894
1895 cfg->locals_min_stack_offset = offset;
1896
1897 curinst = cfg->locals_start;
1898 for (i = curinst; i < cfg->num_varinfo; ++i) {
1899 MonoType *t;
1900
1901 ins = cfg->varinfo [i];
1902 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1903 continue;
1904
1905 t = ins->inst_vtype;
1906 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1907 continue;
1908
1909 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1910 * pinvoke wrappers when they call functions returning structure */
1911 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1912 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1913 align = ualign;
1914 }
1915 else
1916 size = mono_type_size (t, &align);
1917
1918 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1919 * since it loads/stores misaligned words, which don't do the right thing.
1920 */
1921 if (align < 4 && size >= 4)
1922 align = 4;
1923 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1924 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1925 offset += align - 1;
1926 offset &= ~(align - 1);
1927 ins->opcode = OP_REGOFFSET;
1928 ins->inst_offset = offset;
1929 ins->inst_basereg = cfg->frame_reg;
1930 offset += size;
1931 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1932 }
1933
1934 cfg->locals_max_stack_offset = offset;
1935
1936 curinst = 0;
1937 if (sig->hasthis) {
1938 ins = cfg->args [curinst];
1939 if (ins->opcode != OP_REGVAR) {
1940 ins->opcode = OP_REGOFFSET;
1941 ins->inst_basereg = cfg->frame_reg;
1942 offset += sizeof (gpointer) - 1;
1943 offset &= ~(sizeof (gpointer) - 1);
1944 ins->inst_offset = offset;
1945 offset += sizeof (gpointer);
1946 }
1947 curinst++;
1948 }
1949
1950 if (sig->call_convention == MONO_CALL_VARARG) {
1951 size = 4;
1952 align = 4;
1953
1954 /* Allocate a local slot to hold the sig cookie address */
1955 offset += align - 1;
1956 offset &= ~(align - 1);
1957 cfg->sig_cookie = offset;
1958 offset += size;
1959 }
1960
1961 for (i = 0; i < sig->param_count; ++i) {
1962 ainfo = cinfo->args + i;
1963
1964 ins = cfg->args [curinst];
1965
1966 switch (ainfo->storage) {
1967 case RegTypeHFA:
1968 offset = ALIGN_TO (offset, 8);
1969 ins->opcode = OP_REGOFFSET;
1970 ins->inst_basereg = cfg->frame_reg;
1971 /* These arguments are saved to the stack in the prolog */
1972 ins->inst_offset = offset;
1973 if (cfg->verbose_level >= 2)
1974 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1975 // FIXME:
1976 offset += 32;
1977 break;
1978 default:
1979 break;
1980 }
1981
1982 if (ins->opcode != OP_REGVAR) {
1983 ins->opcode = OP_REGOFFSET;
1984 ins->inst_basereg = cfg->frame_reg;
1985 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1986 align = ualign;
1987 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1988 * since it loads/stores misaligned words, which don't do the right thing.
1989 */
1990 if (align < 4 && size >= 4)
1991 align = 4;
1992 /* The code in the prolog () stores words when storing vtypes received in a register */
1993 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1994 align = 4;
1995 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1996 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1997 offset += align - 1;
1998 offset &= ~(align - 1);
1999 ins->inst_offset = offset;
2000 offset += size;
2001 }
2002 curinst++;
2003 }
2004
2005 /* align the offset to 8 bytes */
2006 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2007 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2008 offset += 8 - 1;
2009 offset &= ~(8 - 1);
2010
2011 /* change sign? */
2012 cfg->stack_offset = offset;
2013 }
2014
2015 void
2016 mono_arch_create_vars (MonoCompile *cfg)
2017 {
2018 MonoMethodSignature *sig;
2019 CallInfo *cinfo;
2020 int i;
2021
2022 sig = mono_method_signature (cfg->method);
2023
2024 if (!cfg->arch.cinfo)
2025 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2026 cinfo = cfg->arch.cinfo;
2027
2028 if (IS_HARD_FLOAT) {
2029 for (i = 0; i < 2; i++) {
2030 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2031 inst->flags |= MONO_INST_VOLATILE;
2032
2033 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2034 }
2035 }
2036
2037 if (cinfo->ret.storage == RegTypeStructByVal)
2038 cfg->ret_var_is_local = TRUE;
2039
2040 if (cinfo->ret.storage == RegTypeStructByAddr) {
2041 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2042 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2043 g_print ("vret_addr = ");
2044 mono_print_ins (cfg->vret_addr);
2045 }
2046 }
2047
2048 if (cfg->gen_sdb_seq_points) {
2049 if (cfg->compile_aot) {
2050 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2051 ins->flags |= MONO_INST_VOLATILE;
2052 cfg->arch.seq_point_info_var = ins;
2053
2054 if (!cfg->soft_breakpoints) {
2055 /* Allocate a separate variable for this to save 1 load per seq point */
2056 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2057 ins->flags |= MONO_INST_VOLATILE;
2058 cfg->arch.ss_trigger_page_var = ins;
2059 }
2060 }
2061 if (cfg->soft_breakpoints) {
2062 MonoInst *ins;
2063
2064 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2065 ins->flags |= MONO_INST_VOLATILE;
2066 cfg->arch.seq_point_ss_method_var = ins;
2067
2068 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2069 ins->flags |= MONO_INST_VOLATILE;
2070 cfg->arch.seq_point_bp_method_var = ins;
2071 }
2072 }
2073 }
2074
2075 static void
2076 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2077 {
2078 MonoMethodSignature *tmp_sig;
2079 int sig_reg;
2080
2081 if (call->tail_call)
2082 NOT_IMPLEMENTED;
2083
2084 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2085
2086 /*
2087 * mono_ArgIterator_Setup assumes the signature cookie is
2088 * passed first and all the arguments which were before it are
2089 * passed on the stack after the signature. So compensate by
2090 * passing a different signature.
2091 */
2092 tmp_sig = mono_metadata_signature_dup (call->signature);
2093 tmp_sig->param_count -= call->signature->sentinelpos;
2094 tmp_sig->sentinelpos = 0;
2095 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2096
2097 sig_reg = mono_alloc_ireg (cfg);
2098 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2099
2100 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2101 }
2102
2103 #ifdef ENABLE_LLVM
2104 LLVMCallInfo*
2105 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2106 {
2107 int i, n;
2108 CallInfo *cinfo;
2109 ArgInfo *ainfo;
2110 LLVMCallInfo *linfo;
2111
2112 n = sig->param_count + sig->hasthis;
2113
2114 cinfo = get_call_info (cfg->mempool, sig);
2115
2116 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2117
2118 /*
2119 * LLVM always uses the native ABI while we use our own ABI, the
2120 * only difference is the handling of vtypes:
2121 * - we only pass/receive them in registers in some cases, and only
2122 * in 1 or 2 integer registers.
2123 */
2124 switch (cinfo->ret.storage) {
2125 case RegTypeGeneral:
2126 case RegTypeNone:
2127 case RegTypeFP:
2128 case RegTypeIRegPair:
2129 break;
2130 case RegTypeStructByAddr:
2131 /* Vtype returned using a hidden argument */
2132 linfo->ret.storage = LLVMArgVtypeRetAddr;
2133 linfo->vret_arg_index = cinfo->vret_arg_index;
2134 break;
2135 #if TARGET_WATCHOS
2136 case RegTypeStructByVal:
2137 /* LLVM models this by returning an int array */
2138 linfo->ret.storage = LLVMArgAsIArgs;
2139 linfo->ret.nslots = cinfo->ret.nregs;
2140 break;
2141 #endif
2142 default:
2143 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2144 cfg->disable_llvm = TRUE;
2145 return linfo;
2146 }
2147
2148 for (i = 0; i < n; ++i) {
2149 LLVMArgInfo *lainfo = &linfo->args [i];
2150 ainfo = cinfo->args + i;
2151
2152 lainfo->storage = LLVMArgNone;
2153
2154 switch (ainfo->storage) {
2155 case RegTypeGeneral:
2156 case RegTypeIRegPair:
2157 case RegTypeBase:
2158 case RegTypeBaseGen:
2159 case RegTypeFP:
2160 lainfo->storage = LLVMArgNormal;
2161 break;
2162 case RegTypeStructByVal:
2163 lainfo->storage = LLVMArgAsIArgs;
2164 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2165 break;
2166 case RegTypeStructByAddr:
2167 case RegTypeStructByAddrOnStack:
2168 lainfo->storage = LLVMArgVtypeByRef;
2169 break;
2170 default:
2171 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2172 cfg->disable_llvm = TRUE;
2173 break;
2174 }
2175 }
2176
2177 return linfo;
2178 }
2179 #endif
2180
2181 void
2182 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2183 {
2184 MonoInst *in, *ins;
2185 MonoMethodSignature *sig;
2186 int i, n;
2187 CallInfo *cinfo;
2188
2189 sig = call->signature;
2190 n = sig->param_count + sig->hasthis;
2191
2192 cinfo = get_call_info (cfg->mempool, sig);
2193
2194 switch (cinfo->ret.storage) {
2195 case RegTypeStructByVal:
2196 case RegTypeHFA:
2197 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2198 /* The JIT will transform this into a normal call */
2199 call->vret_in_reg = TRUE;
2200 break;
2201 }
2202 if (call->inst.opcode == OP_TAILCALL)
2203 break;
2204 /*
2205 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2206 * the location pointed to by it after call in emit_move_return_value ().
2207 */
2208 if (!cfg->arch.vret_addr_loc) {
2209 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2210 /* Prevent it from being register allocated or optimized away */
2211 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2212 }
2213
2214 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2215 break;
2216 case RegTypeStructByAddr: {
2217 MonoInst *vtarg;
2218 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2219 vtarg->sreg1 = call->vret_var->dreg;
2220 vtarg->dreg = mono_alloc_preg (cfg);
2221 MONO_ADD_INS (cfg->cbb, vtarg);
2222
2223 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2224 break;
2225 }
2226 default:
2227 break;
2228 }
2229
2230 for (i = 0; i < n; ++i) {
2231 ArgInfo *ainfo = cinfo->args + i;
2232 MonoType *t;
2233
2234 if (i >= sig->hasthis)
2235 t = sig->params [i - sig->hasthis];
2236 else
2237 t = &mono_defaults.int_class->byval_arg;
2238 t = mini_get_underlying_type (t);
2239
2240 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2241 /* Emit the signature cookie just before the implicit arguments */
2242 emit_sig_cookie (cfg, call, cinfo);
2243 }
2244
2245 in = call->args [i];
2246
2247 switch (ainfo->storage) {
2248 case RegTypeGeneral:
2249 case RegTypeIRegPair:
2250 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2251 MONO_INST_NEW (cfg, ins, OP_MOVE);
2252 ins->dreg = mono_alloc_ireg (cfg);
2253 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2254 MONO_ADD_INS (cfg->cbb, ins);
2255 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2256
2257 MONO_INST_NEW (cfg, ins, OP_MOVE);
2258 ins->dreg = mono_alloc_ireg (cfg);
2259 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2260 MONO_ADD_INS (cfg->cbb, ins);
2261 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2262 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2263 if (ainfo->size == 4) {
2264 if (IS_SOFT_FLOAT) {
2265 /* mono_emit_call_args () have already done the r8->r4 conversion */
2266 /* The converted value is in an int vreg */
2267 MONO_INST_NEW (cfg, ins, OP_MOVE);
2268 ins->dreg = mono_alloc_ireg (cfg);
2269 ins->sreg1 = in->dreg;
2270 MONO_ADD_INS (cfg->cbb, ins);
2271 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2272 } else {
2273 int creg;
2274
2275 cfg->param_area = MAX (cfg->param_area, 8);
2276 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2277 creg = mono_alloc_ireg (cfg);
2278 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2279 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2280 }
2281 } else {
2282 if (IS_SOFT_FLOAT) {
2283 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2284 ins->dreg = mono_alloc_ireg (cfg);
2285 ins->sreg1 = in->dreg;
2286 MONO_ADD_INS (cfg->cbb, ins);
2287 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2288
2289 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2290 ins->dreg = mono_alloc_ireg (cfg);
2291 ins->sreg1 = in->dreg;
2292 MONO_ADD_INS (cfg->cbb, ins);
2293 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2294 } else {
2295 int creg;
2296
2297 cfg->param_area = MAX (cfg->param_area, 8);
2298 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2299 creg = mono_alloc_ireg (cfg);
2300 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2301 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2302 creg = mono_alloc_ireg (cfg);
2303 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2304 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2305 }
2306 }
2307 cfg->flags |= MONO_CFG_HAS_FPOUT;
2308 } else {
2309 MONO_INST_NEW (cfg, ins, OP_MOVE);
2310 ins->dreg = mono_alloc_ireg (cfg);
2311 ins->sreg1 = in->dreg;
2312 MONO_ADD_INS (cfg->cbb, ins);
2313
2314 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2315 }
2316 break;
2317 case RegTypeStructByVal:
2318 case RegTypeGSharedVtInReg:
2319 case RegTypeGSharedVtOnStack:
2320 case RegTypeHFA:
2321 case RegTypeStructByAddr:
2322 case RegTypeStructByAddrOnStack:
2323 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2324 ins->opcode = OP_OUTARG_VT;
2325 ins->sreg1 = in->dreg;
2326 ins->klass = in->klass;
2327 ins->inst_p0 = call;
2328 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2329 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2330 mono_call_inst_add_outarg_vt (cfg, call, ins);
2331 MONO_ADD_INS (cfg->cbb, ins);
2332 break;
2333 case RegTypeBase:
2334 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2335 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2336 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2337 if (t->type == MONO_TYPE_R8) {
2338 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2339 } else {
2340 if (IS_SOFT_FLOAT)
2341 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2342 else
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2344 }
2345 } else {
2346 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2347 }
2348 break;
2349 case RegTypeBaseGen:
2350 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2351 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2352 MONO_INST_NEW (cfg, ins, OP_MOVE);
2353 ins->dreg = mono_alloc_ireg (cfg);
2354 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2355 MONO_ADD_INS (cfg->cbb, ins);
2356 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2357 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2358 int creg;
2359
2360 /* This should work for soft-float as well */
2361
2362 cfg->param_area = MAX (cfg->param_area, 8);
2363 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2364 creg = mono_alloc_ireg (cfg);
2365 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2366 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2367 creg = mono_alloc_ireg (cfg);
2368 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2369 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2370 cfg->flags |= MONO_CFG_HAS_FPOUT;
2371 } else {
2372 g_assert_not_reached ();
2373 }
2374 break;
2375 case RegTypeFP: {
2376 int fdreg = mono_alloc_freg (cfg);
2377
2378 if (ainfo->size == 8) {
2379 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2380 ins->sreg1 = in->dreg;
2381 ins->dreg = fdreg;
2382 MONO_ADD_INS (cfg->cbb, ins);
2383
2384 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2385 } else {
2386 FloatArgData *fad;
2387
2388 /*
2389 * Mono's register allocator doesn't speak single-precision registers that
2390 * overlap double-precision registers (i.e. armhf). So we have to work around
2391 * the register allocator and load the value from memory manually.
2392 *
2393 * So we create a variable for the float argument and an instruction to store
2394 * the argument into the variable. We then store the list of these arguments
2395 * in call->float_args. This list is then used by emit_float_args later to
2396 * pass the arguments in the various call opcodes.
2397 *
2398 * This is not very nice, and we should really try to fix the allocator.
2399 */
2400
2401 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2402
2403 /* Make sure the instruction isn't seen as pointless and removed.
2404 */
2405 float_arg->flags |= MONO_INST_VOLATILE;
2406
2407 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2408
2409 /* We use the dreg to look up the instruction later. The hreg is used to
2410 * emit the instruction that loads the value into the FP reg.
2411 */
2412 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2413 fad->vreg = float_arg->dreg;
2414 fad->hreg = ainfo->reg;
2415
2416 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2417 }
2418
2419 call->used_iregs |= 1 << ainfo->reg;
2420 cfg->flags |= MONO_CFG_HAS_FPOUT;
2421 break;
2422 }
2423 default:
2424 g_assert_not_reached ();
2425 }
2426 }
2427
2428 /* Handle the case where there are no implicit arguments */
2429 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2430 emit_sig_cookie (cfg, call, cinfo);
2431
2432 call->call_info = cinfo;
2433 call->stack_usage = cinfo->stack_usage;
2434 }
2435
2436 static void
2437 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2438 {
2439 MonoInst *ins;
2440
2441 switch (storage) {
2442 case RegTypeFP:
2443 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2444 ins->dreg = mono_alloc_freg (cfg);
2445 ins->sreg1 = arg->dreg;
2446 MONO_ADD_INS (cfg->cbb, ins);
2447 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2448 break;
2449 default:
2450 g_assert_not_reached ();
2451 break;
2452 }
2453 }
2454
2455 void
2456 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2457 {
2458 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459 MonoInst *load;
2460 ArgInfo *ainfo = ins->inst_p1;
2461 int ovf_size = ainfo->vtsize;
2462 int doffset = ainfo->offset;
2463 int struct_size = ainfo->struct_size;
2464 int i, soffset, dreg, tmpreg;
2465
2466 switch (ainfo->storage) {
2467 case RegTypeGSharedVtInReg:
2468 case RegTypeStructByAddr:
2469 /* Pass by addr */
2470 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2471 break;
2472 case RegTypeGSharedVtOnStack:
2473 case RegTypeStructByAddrOnStack:
2474 /* Pass by addr on stack */
2475 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2476 break;
2477 case RegTypeHFA:
2478 for (i = 0; i < ainfo->nregs; ++i) {
2479 if (ainfo->esize == 4)
2480 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2481 else
2482 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2483 load->dreg = mono_alloc_freg (cfg);
2484 load->inst_basereg = src->dreg;
2485 load->inst_offset = i * ainfo->esize;
2486 MONO_ADD_INS (cfg->cbb, load);
2487
2488 if (ainfo->esize == 4) {
2489 FloatArgData *fad;
2490
2491 /* See RegTypeFP in mono_arch_emit_call () */
2492 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2493 float_arg->flags |= MONO_INST_VOLATILE;
2494 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2495
2496 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2497 fad->vreg = float_arg->dreg;
2498 fad->hreg = ainfo->reg + i;
2499
2500 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2501 } else {
2502 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2503 }
2504 }
2505 break;
2506 default:
2507 soffset = 0;
2508 for (i = 0; i < ainfo->size; ++i) {
2509 dreg = mono_alloc_ireg (cfg);
2510 switch (struct_size) {
2511 case 1:
2512 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2513 break;
2514 case 2:
2515 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2516 break;
2517 case 3:
2518 tmpreg = mono_alloc_ireg (cfg);
2519 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2520 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2521 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2522 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2523 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2524 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2525 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2526 break;
2527 default:
2528 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2529 break;
2530 }
2531 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2532 soffset += sizeof (gpointer);
2533 struct_size -= sizeof (gpointer);
2534 }
2535 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2536 if (ovf_size != 0)
2537 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2538 break;
2539 }
2540 }
2541
2542 void
2543 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2544 {
2545 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2546
2547 if (!ret->byref) {
2548 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2549 MonoInst *ins;
2550
2551 if (COMPILE_LLVM (cfg)) {
2552 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2553 } else {
2554 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2555 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2556 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2557 MONO_ADD_INS (cfg->cbb, ins);
2558 }
2559 return;
2560 }
2561 switch (arm_fpu) {
2562 case MONO_ARM_FPU_NONE:
2563 if (ret->type == MONO_TYPE_R8) {
2564 MonoInst *ins;
2565
2566 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2567 ins->dreg = cfg->ret->dreg;
2568 ins->sreg1 = val->dreg;
2569 MONO_ADD_INS (cfg->cbb, ins);
2570 return;
2571 }
2572 if (ret->type == MONO_TYPE_R4) {
2573 /* Already converted to an int in method_to_ir () */
2574 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2575 return;
2576 }
2577 break;
2578 case MONO_ARM_FPU_VFP:
2579 case MONO_ARM_FPU_VFP_HARD:
2580 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2581 MonoInst *ins;
2582
2583 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2584 ins->dreg = cfg->ret->dreg;
2585 ins->sreg1 = val->dreg;
2586 MONO_ADD_INS (cfg->cbb, ins);
2587 return;
2588 }
2589 break;
2590 default:
2591 g_assert_not_reached ();
2592 }
2593 }
2594
2595 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2596 }
2597
2598 #endif /* #ifndef DISABLE_JIT */
2599
2600 gboolean
2601 mono_arch_is_inst_imm (gint64 imm)
2602 {
2603 return TRUE;
2604 }
2605
2606 typedef struct {
2607 MonoMethodSignature *sig;
2608 CallInfo *cinfo;
2609 MonoType *rtype;
2610 MonoType **param_types;
2611 } ArchDynCallInfo;
2612
2613 static gboolean
2614 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2615 {
2616 int i;
2617
2618 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2619 return FALSE;
2620
2621 switch (cinfo->ret.storage) {
2622 case RegTypeNone:
2623 case RegTypeGeneral:
2624 case RegTypeIRegPair:
2625 case RegTypeStructByAddr:
2626 break;
2627 case RegTypeFP:
2628 if (IS_VFP)
2629 break;
2630 else
2631 return FALSE;
2632 default:
2633 return FALSE;
2634 }
2635
2636 for (i = 0; i < cinfo->nargs; ++i) {
2637 ArgInfo *ainfo = &cinfo->args [i];
2638 int last_slot;
2639
2640 switch (ainfo->storage) {
2641 case RegTypeGeneral:
2642 case RegTypeIRegPair:
2643 case RegTypeBaseGen:
2644 case RegTypeFP:
2645 break;
2646 case RegTypeBase:
2647 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2648 return FALSE;
2649 break;
2650 case RegTypeStructByVal:
2651 if (ainfo->size == 0)
2652 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2653 else
2654 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2655 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2656 return FALSE;
2657 break;
2658 default:
2659 return FALSE;
2660 }
2661 }
2662
2663 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2664 for (i = 0; i < sig->param_count; ++i) {
2665 MonoType *t = sig->params [i];
2666
2667 if (t->byref)
2668 continue;
2669
2670 t = mini_get_underlying_type (t);
2671
2672 switch (t->type) {
2673 case MONO_TYPE_R4:
2674 case MONO_TYPE_R8:
2675 if (IS_SOFT_FLOAT)
2676 return FALSE;
2677 else
2678 break;
2679 /*
2680 case MONO_TYPE_I8:
2681 case MONO_TYPE_U8:
2682 return FALSE;
2683 */
2684 default:
2685 break;
2686 }
2687 }
2688
2689 return TRUE;
2690 }
2691
2692 MonoDynCallInfo*
2693 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2694 {
2695 ArchDynCallInfo *info;
2696 CallInfo *cinfo;
2697 int i;
2698
2699 cinfo = get_call_info (NULL, sig);
2700
2701 if (!dyn_call_supported (cinfo, sig)) {
2702 g_free (cinfo);
2703 return NULL;
2704 }
2705
2706 info = g_new0 (ArchDynCallInfo, 1);
2707 // FIXME: Preprocess the info to speed up start_dyn_call ()
2708 info->sig = sig;
2709 info->cinfo = cinfo;
2710 info->rtype = mini_get_underlying_type (sig->ret);
2711 info->param_types = g_new0 (MonoType*, sig->param_count);
2712 for (i = 0; i < sig->param_count; ++i)
2713 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2714
2715 return (MonoDynCallInfo*)info;
2716 }
2717
2718 void
2719 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2720 {
2721 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2722
2723 g_free (ainfo->cinfo);
2724 g_free (ainfo);
2725 }
2726
2727 void
2728 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2729 {
2730 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2731 DynCallArgs *p = (DynCallArgs*)buf;
2732 int arg_index, greg, i, j, pindex;
2733 MonoMethodSignature *sig = dinfo->sig;
2734
2735 g_assert (buf_len >= sizeof (DynCallArgs));
2736
2737 p->res = 0;
2738 p->ret = ret;
2739 p->has_fpregs = 0;
2740
2741 arg_index = 0;
2742 greg = 0;
2743 pindex = 0;
2744
2745 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2746 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2747 if (!sig->hasthis)
2748 pindex = 1;
2749 }
2750
2751 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2752 p->regs [greg ++] = (mgreg_t)ret;
2753
2754 for (i = pindex; i < sig->param_count; i++) {
2755 MonoType *t = dinfo->param_types [i];
2756 gpointer *arg = args [arg_index ++];
2757 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2758 int slot = -1;
2759
2760 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2761 slot = ainfo->reg;
2762 } else if (ainfo->storage == RegTypeFP) {
2763 } else if (ainfo->storage == RegTypeBase) {
2764 slot = PARAM_REGS + (ainfo->offset / 4);
2765 } else if (ainfo->storage == RegTypeBaseGen) {
2766 /* slot + 1 is the first stack slot, so the code below will work */
2767 slot = 3;
2768 } else {
2769 g_assert_not_reached ();
2770 }
2771
2772 if (t->byref) {
2773 p->regs [slot] = (mgreg_t)*arg;
2774 continue;
2775 }
2776
2777 switch (t->type) {
2778 case MONO_TYPE_STRING:
2779 case MONO_TYPE_CLASS:
2780 case MONO_TYPE_ARRAY:
2781 case MONO_TYPE_SZARRAY:
2782 case MONO_TYPE_OBJECT:
2783 case MONO_TYPE_PTR:
2784 case MONO_TYPE_I:
2785 case MONO_TYPE_U:
2786 p->regs [slot] = (mgreg_t)*arg;
2787 break;
2788 case MONO_TYPE_U1:
2789 p->regs [slot] = *(guint8*)arg;
2790 break;
2791 case MONO_TYPE_I1:
2792 p->regs [slot] = *(gint8*)arg;
2793 break;
2794 case MONO_TYPE_I2:
2795 p->regs [slot] = *(gint16*)arg;
2796 break;
2797 case MONO_TYPE_U2:
2798 p->regs [slot] = *(guint16*)arg;
2799 break;
2800 case MONO_TYPE_I4:
2801 p->regs [slot] = *(gint32*)arg;
2802 break;
2803 case MONO_TYPE_U4:
2804 p->regs [slot] = *(guint32*)arg;
2805 break;
2806 case MONO_TYPE_I8:
2807 case MONO_TYPE_U8:
2808 p->regs [slot ++] = (mgreg_t)arg [0];
2809 p->regs [slot] = (mgreg_t)arg [1];
2810 break;
2811 case MONO_TYPE_R4:
2812 if (ainfo->storage == RegTypeFP) {
2813 float f = *(float*)arg;
2814 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2815 p->has_fpregs = 1;
2816 } else {
2817 p->regs [slot] = *(mgreg_t*)arg;
2818 }
2819 break;
2820 case MONO_TYPE_R8:
2821 if (ainfo->storage == RegTypeFP) {
2822 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2823 p->has_fpregs = 1;
2824 } else {
2825 p->regs [slot ++] = (mgreg_t)arg [0];
2826 p->regs [slot] = (mgreg_t)arg [1];
2827 }
2828 break;
2829 case MONO_TYPE_GENERICINST:
2830 if (MONO_TYPE_IS_REFERENCE (t)) {
2831 p->regs [slot] = (mgreg_t)*arg;
2832 break;
2833 } else {
2834 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2835 MonoClass *klass = mono_class_from_mono_type (t);
2836 guint8 *nullable_buf;
2837 int size;
2838
2839 size = mono_class_value_size (klass, NULL);
2840 nullable_buf = g_alloca (size);
2841 g_assert (nullable_buf);
2842
2843 /* The argument pointed to by arg is either a boxed vtype or null */
2844 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2845
2846 arg = (gpointer*)nullable_buf;
2847 /* Fall though */
2848 } else {
2849 /* Fall though */
2850 }
2851 }
2852 case MONO_TYPE_VALUETYPE:
2853 g_assert (ainfo->storage == RegTypeStructByVal);
2854
2855 if (ainfo->size == 0)
2856 slot = PARAM_REGS + (ainfo->offset / 4);
2857 else
2858 slot = ainfo->reg;
2859
2860 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2861 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2862 break;
2863 default:
2864 g_assert_not_reached ();
2865 }
2866 }
2867 }
2868
2869 void
2870 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2871 {
2872 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2873 DynCallArgs *p = (DynCallArgs*)buf;
2874 MonoType *ptype = ainfo->rtype;
2875 guint8 *ret = p->ret;
2876 mgreg_t res = p->res;
2877 mgreg_t res2 = p->res2;
2878
2879 switch (ptype->type) {
2880 case MONO_TYPE_VOID:
2881 *(gpointer*)ret = NULL;
2882 break;
2883 case MONO_TYPE_STRING:
2884 case MONO_TYPE_CLASS:
2885 case MONO_TYPE_ARRAY:
2886 case MONO_TYPE_SZARRAY:
2887 case MONO_TYPE_OBJECT:
2888 case MONO_TYPE_I:
2889 case MONO_TYPE_U:
2890 case MONO_TYPE_PTR:
2891 *(gpointer*)ret = (gpointer)res;
2892 break;
2893 case MONO_TYPE_I1:
2894 *(gint8*)ret = res;
2895 break;
2896 case MONO_TYPE_U1:
2897 *(guint8*)ret = res;
2898 break;
2899 case MONO_TYPE_I2:
2900 *(gint16*)ret = res;
2901 break;
2902 case MONO_TYPE_U2:
2903 *(guint16*)ret = res;
2904 break;
2905 case MONO_TYPE_I4:
2906 *(gint32*)ret = res;
2907 break;
2908 case MONO_TYPE_U4:
2909 *(guint32*)ret = res;
2910 break;
2911 case MONO_TYPE_I8:
2912 case MONO_TYPE_U8:
2913 /* This handles endianness as well */
2914 ((gint32*)ret) [0] = res;
2915 ((gint32*)ret) [1] = res2;
2916 break;
2917 case MONO_TYPE_GENERICINST:
2918 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2919 *(gpointer*)ret = (gpointer)res;
2920 break;
2921 } else {
2922 /* Fall though */
2923 }
2924 case MONO_TYPE_VALUETYPE:
2925 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2926 /* Nothing to do */
2927 break;
2928 case MONO_TYPE_R4:
2929 g_assert (IS_VFP);
2930 if (IS_HARD_FLOAT)
2931 *(float*)ret = *(float*)&p->fpregs [0];
2932 else
2933 *(float*)ret = *(float*)&res;
2934 break;
2935 case MONO_TYPE_R8: {
2936 mgreg_t regs [2];
2937
2938 g_assert (IS_VFP);
2939 if (IS_HARD_FLOAT) {
2940 *(double*)ret = p->fpregs [0];
2941 } else {
2942 regs [0] = res;
2943 regs [1] = res2;
2944
2945 *(double*)ret = *(double*)&regs;
2946 }
2947 break;
2948 }
2949 default:
2950 g_assert_not_reached ();
2951 }
2952 }
2953
2954 #ifndef DISABLE_JIT
2955
2956 /*
2957 * Allow tracing to work with this interface (with an optional argument)
2958 */
2959
2960 void*
2961 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2962 {
2963 guchar *code = p;
2964
2965 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2966 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2967 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2968 code = emit_call_reg (code, ARMREG_R2);
2969 return code;
2970 }
2971
2972 enum {
2973 SAVE_NONE,
2974 SAVE_STRUCT,
2975 SAVE_ONE,
2976 SAVE_TWO,
2977 SAVE_ONE_FP,
2978 SAVE_TWO_FP
2979 };
2980
2981 void*
2982 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2983 {
2984 guchar *code = p;
2985 int save_mode = SAVE_NONE;
2986 int offset;
2987 MonoMethod *method = cfg->method;
2988 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
2989 int rtype = ret_type->type;
2990 int save_offset = cfg->param_area;
2991 save_offset += 7;
2992 save_offset &= ~7;
2993
2994 offset = code - cfg->native_code;
2995 /* we need about 16 instructions */
2996 if (offset > (cfg->code_size - 16 * 4)) {
2997 cfg->code_size *= 2;
2998 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2999 code = cfg->native_code + offset;
3000 }
3001 switch (rtype) {
3002 case MONO_TYPE_VOID:
3003 /* special case string .ctor icall */
3004 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3005 save_mode = SAVE_ONE;
3006 else
3007 save_mode = SAVE_NONE;
3008 break;
3009 case MONO_TYPE_I8:
3010 case MONO_TYPE_U8:
3011 save_mode = SAVE_TWO;
3012 break;
3013 case MONO_TYPE_R4:
3014 if (IS_HARD_FLOAT)
3015 save_mode = SAVE_ONE_FP;
3016 else
3017 save_mode = SAVE_ONE;
3018 break;
3019 case MONO_TYPE_R8:
3020 if (IS_HARD_FLOAT)
3021 save_mode = SAVE_TWO_FP;
3022 else
3023 save_mode = SAVE_TWO;
3024 break;
3025 case MONO_TYPE_GENERICINST:
3026 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3027 save_mode = SAVE_ONE;
3028 break;
3029 }
3030 /* Fall through */
3031 case MONO_TYPE_VALUETYPE:
3032 save_mode = SAVE_STRUCT;
3033 break;
3034 default:
3035 save_mode = SAVE_ONE;
3036 break;
3037 }
3038
3039 switch (save_mode) {
3040 case SAVE_TWO:
3041 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3042 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3043 if (enable_arguments) {
3044 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3045 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3046 }
3047 break;
3048 case SAVE_ONE:
3049 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3050 if (enable_arguments) {
3051 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3052 }
3053 break;
3054 case SAVE_ONE_FP:
3055 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3056 if (enable_arguments) {
3057 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3058 }
3059 break;
3060 case SAVE_TWO_FP:
3061 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3062 if (enable_arguments) {
3063 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3064 }
3065 break;
3066 case SAVE_STRUCT:
3067 if (enable_arguments) {
3068 /* FIXME: get the actual address */
3069 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3070 }
3071 break;
3072 case SAVE_NONE:
3073 default:
3074 break;
3075 }
3076
3077 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3078 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3079 code = emit_call_reg (code, ARMREG_IP);
3080
3081 switch (save_mode) {
3082 case SAVE_TWO:
3083 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3084 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3085 break;
3086 case SAVE_ONE:
3087 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3088 break;
3089 case SAVE_ONE_FP:
3090 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3091 break;
3092 case SAVE_TWO_FP:
3093 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3094 break;
3095 case SAVE_NONE:
3096 default:
3097 break;
3098 }
3099
3100 return code;
3101 }
3102
3103 /*
3104 * The immediate field for cond branches is big enough for all reasonable methods
3105 */
3106 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3107 if (0 && ins->inst_true_bb->native_offset) { \
3108 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3109 } else { \
3110 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3111 ARM_B_COND (code, (condcode), 0); \
3112 }
3113
3114 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3115
3116 /* emit an exception if condition is fail
3117 *
3118 * We assign the extra code used to throw the implicit exceptions
3119 * to cfg->bb_exit as far as the big branch handling is concerned
3120 */
3121 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3122 do { \
3123 mono_add_patch_info (cfg, code - cfg->native_code, \
3124 MONO_PATCH_INFO_EXC, exc_name); \
3125 ARM_BL_COND (code, (condcode), 0); \
3126 } while (0);
3127
3128 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3129
3130 void
3131 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3132 {
3133 }
3134
3135 void
3136 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3137 {
3138 MonoInst *ins, *n;
3139
3140 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3141 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3142
3143 switch (ins->opcode) {
3144 case OP_MUL_IMM:
3145 case OP_IMUL_IMM:
3146 /* Already done by an arch-independent pass */
3147 break;
3148 case OP_LOAD_MEMBASE:
3149 case OP_LOADI4_MEMBASE:
3150 /*
3151 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3152 * OP_LOAD_MEMBASE offset(basereg), reg
3153 */
3154 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3155 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3156 ins->inst_basereg == last_ins->inst_destbasereg &&
3157 ins->inst_offset == last_ins->inst_offset) {
3158 if (ins->dreg == last_ins->sreg1) {
3159 MONO_DELETE_INS (bb, ins);
3160 continue;
3161 } else {
3162 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3163 ins->opcode = OP_MOVE;
3164 ins->sreg1 = last_ins->sreg1;
3165 }
3166
3167 /*
3168 * Note: reg1 must be different from the basereg in the second load
3169 * OP_LOAD_MEMBASE offset(basereg), reg1
3170 * OP_LOAD_MEMBASE offset(basereg), reg2
3171 * -->
3172 * OP_LOAD_MEMBASE offset(basereg), reg1
3173 * OP_MOVE reg1, reg2
3174 */
3175 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3176 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3177 ins->inst_basereg != last_ins->dreg &&
3178 ins->inst_basereg == last_ins->inst_basereg &&
3179 ins->inst_offset == last_ins->inst_offset) {
3180
3181 if (ins->dreg == last_ins->dreg) {
3182 MONO_DELETE_INS (bb, ins);
3183 continue;
3184 } else {
3185 ins->opcode = OP_MOVE;
3186 ins->sreg1 = last_ins->dreg;
3187 }
3188
3189 //g_assert_not_reached ();
3190
3191 #if 0
3192 /*
3193 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3194 * OP_LOAD_MEMBASE offset(basereg), reg
3195 * -->
3196 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3197 * OP_ICONST reg, imm
3198 */
3199 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3200 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3201 ins->inst_basereg == last_ins->inst_destbasereg &&
3202 ins->inst_offset == last_ins->inst_offset) {
3203 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3204 ins->opcode = OP_ICONST;
3205 ins->inst_c0 = last_ins->inst_imm;
3206 g_assert_not_reached (); // check this rule
3207 #endif
3208 }
3209 break;
3210 case OP_LOADU1_MEMBASE:
3211 case OP_LOADI1_MEMBASE:
3212 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3213 ins->inst_basereg == last_ins->inst_destbasereg &&
3214 ins->inst_offset == last_ins->inst_offset) {
3215 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3216 ins->sreg1 = last_ins->sreg1;
3217 }
3218 break;
3219 case OP_LOADU2_MEMBASE:
3220 case OP_LOADI2_MEMBASE:
3221 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3222 ins->inst_basereg == last_ins->inst_destbasereg &&
3223 ins->inst_offset == last_ins->inst_offset) {
3224 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3225 ins->sreg1 = last_ins->sreg1;
3226 }
3227 break;
3228 case OP_MOVE:
3229 ins->opcode = OP_MOVE;
3230 /*
3231 * OP_MOVE reg, reg
3232 */
3233 if (ins->dreg == ins->sreg1) {
3234 MONO_DELETE_INS (bb, ins);
3235 continue;
3236 }
3237 /*
3238 * OP_MOVE sreg, dreg
3239 * OP_MOVE dreg, sreg
3240 */
3241 if (last_ins && last_ins->opcode == OP_MOVE &&
3242 ins->sreg1 == last_ins->dreg &&
3243 ins->dreg == last_ins->sreg1) {
3244 MONO_DELETE_INS (bb, ins);
3245 continue;
3246 }
3247 break;
3248 }
3249 }
3250 }
3251
3252 /*
3253 * the branch_cc_table should maintain the order of these
3254 * opcodes.
3255 case CEE_BEQ:
3256 case CEE_BGE:
3257 case CEE_BGT:
3258 case CEE_BLE:
3259 case CEE_BLT:
3260 case CEE_BNE_UN:
3261 case CEE_BGE_UN:
3262 case CEE_BGT_UN:
3263 case CEE_BLE_UN:
3264 case CEE_BLT_UN:
3265 */
3266 static const guchar
3267 branch_cc_table [] = {
3268 ARMCOND_EQ,
3269 ARMCOND_GE,
3270 ARMCOND_GT,
3271 ARMCOND_LE,
3272 ARMCOND_LT,
3273
3274 ARMCOND_NE,
3275 ARMCOND_HS,
3276 ARMCOND_HI,
3277 ARMCOND_LS,
3278 ARMCOND_LO
3279 };
3280
3281 #define ADD_NEW_INS(cfg,dest,op) do { \
3282 MONO_INST_NEW ((cfg), (dest), (op)); \
3283 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3284 } while (0)
3285
3286 static int
3287 map_to_reg_reg_op (int op)
3288 {
3289 switch (op) {
3290 case OP_ADD_IMM:
3291 return OP_IADD;
3292 case OP_SUB_IMM:
3293 return OP_ISUB;
3294 case OP_AND_IMM:
3295 return OP_IAND;
3296 case OP_COMPARE_IMM:
3297 return OP_COMPARE;
3298 case OP_ICOMPARE_IMM:
3299 return OP_ICOMPARE;
3300 case OP_ADDCC_IMM:
3301 return OP_ADDCC;
3302 case OP_ADC_IMM:
3303 return OP_ADC;
3304 case OP_SUBCC_IMM:
3305 return OP_SUBCC;
3306 case OP_SBB_IMM:
3307 return OP_SBB;
3308 case OP_OR_IMM:
3309 return OP_IOR;
3310 case OP_XOR_IMM:
3311 return OP_IXOR;
3312 case OP_LOAD_MEMBASE:
3313 return OP_LOAD_MEMINDEX;
3314 case OP_LOADI4_MEMBASE:
3315 return OP_LOADI4_MEMINDEX;
3316 case OP_LOADU4_MEMBASE:
3317 return OP_LOADU4_MEMINDEX;
3318 case OP_LOADU1_MEMBASE:
3319 return OP_LOADU1_MEMINDEX;
3320 case OP_LOADI2_MEMBASE:
3321 return OP_LOADI2_MEMINDEX;
3322 case OP_LOADU2_MEMBASE:
3323 return OP_LOADU2_MEMINDEX;
3324 case OP_LOADI1_MEMBASE:
3325 return OP_LOADI1_MEMINDEX;
3326 case OP_STOREI1_MEMBASE_REG:
3327 return OP_STOREI1_MEMINDEX;
3328 case OP_STOREI2_MEMBASE_REG:
3329 return OP_STOREI2_MEMINDEX;
3330 case OP_STOREI4_MEMBASE_REG:
3331 return OP_STOREI4_MEMINDEX;
3332 case OP_STORE_MEMBASE_REG:
3333 return OP_STORE_MEMINDEX;
3334 case OP_STORER4_MEMBASE_REG:
3335 return OP_STORER4_MEMINDEX;
3336 case OP_STORER8_MEMBASE_REG:
3337 return OP_STORER8_MEMINDEX;
3338 case OP_STORE_MEMBASE_IMM:
3339 return OP_STORE_MEMBASE_REG;
3340 case OP_STOREI1_MEMBASE_IMM:
3341 return OP_STOREI1_MEMBASE_REG;
3342 case OP_STOREI2_MEMBASE_IMM:
3343 return OP_STOREI2_MEMBASE_REG;
3344 case OP_STOREI4_MEMBASE_IMM:
3345 return OP_STOREI4_MEMBASE_REG;
3346 }
3347 g_assert_not_reached ();
3348 }
3349
3350 /*
3351 * Remove from the instruction list the instructions that can't be
3352 * represented with very simple instructions with no register
3353 * requirements.
3354 */
3355 void
3356 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3357 {
3358 MonoInst *ins, *temp, *last_ins = NULL;
3359 int rot_amount, imm8, low_imm;
3360
3361 MONO_BB_FOR_EACH_INS (bb, ins) {
3362 loop_start:
3363 switch (ins->opcode) {
3364 case OP_ADD_IMM:
3365 case OP_SUB_IMM:
3366 case OP_AND_IMM:
3367 case OP_COMPARE_IMM:
3368 case OP_ICOMPARE_IMM:
3369 case OP_ADDCC_IMM:
3370 case OP_ADC_IMM:
3371 case OP_SUBCC_IMM:
3372 case OP_SBB_IMM:
3373 case OP_OR_IMM:
3374 case OP_XOR_IMM:
3375 case OP_IADD_IMM:
3376 case OP_ISUB_IMM:
3377 case OP_IAND_IMM:
3378 case OP_IADC_IMM:
3379 case OP_ISBB_IMM:
3380 case OP_IOR_IMM:
3381 case OP_IXOR_IMM:
3382 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3383 int opcode2 = mono_op_imm_to_op (ins->opcode);
3384 ADD_NEW_INS (cfg, temp, OP_ICONST);
3385 temp->inst_c0 = ins->inst_imm;
3386 temp->dreg = mono_alloc_ireg (cfg);
3387 ins->sreg2 = temp->dreg;
3388 if (opcode2 == -1)
3389 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3390 ins->opcode = opcode2;
3391 }
3392 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3393 goto loop_start;
3394 else
3395 break;
3396 case OP_MUL_IMM:
3397 case OP_IMUL_IMM:
3398 if (ins->inst_imm == 1) {
3399 ins->opcode = OP_MOVE;
3400 break;
3401 }
3402 if (ins->inst_imm == 0) {
3403 ins->opcode = OP_ICONST;
3404 ins->inst_c0 = 0;
3405 break;
3406 }
3407 imm8 = mono_is_power_of_two (ins->inst_imm);
3408 if (imm8 > 0) {
3409 ins->opcode = OP_SHL_IMM;
3410 ins->inst_imm = imm8;
3411 break;
3412 }
3413 ADD_NEW_INS (cfg, temp, OP_ICONST);
3414 temp->inst_c0 = ins->inst_imm;
3415 temp->dreg = mono_alloc_ireg (cfg);
3416 ins->sreg2 = temp->dreg;
3417 ins->opcode = OP_IMUL;
3418 break;
3419 case OP_SBB:
3420 case OP_ISBB:
3421 case OP_SUBCC:
3422 case OP_ISUBCC:
3423 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3424 /* ARM sets the C flag to 1 if there was _no_ overflow */
3425 ins->next->opcode = OP_COND_EXC_NC;
3426 break;
3427 case OP_IDIV_IMM:
3428 case OP_IDIV_UN_IMM:
3429 case OP_IREM_IMM:
3430 case OP_IREM_UN_IMM: {
3431 int opcode2 = mono_op_imm_to_op (ins->opcode);
3432 ADD_NEW_INS (cfg, temp, OP_ICONST);
3433 temp->inst_c0 = ins->inst_imm;
3434 temp->dreg = mono_alloc_ireg (cfg);
3435 ins->sreg2 = temp->dreg;
3436 if (opcode2 == -1)
3437 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3438 ins->opcode = opcode2;
3439 break;
3440 }
3441 case OP_LOCALLOC_IMM:
3442 ADD_NEW_INS (cfg, temp, OP_ICONST);
3443 temp->inst_c0 = ins->inst_imm;
3444 temp->dreg = mono_alloc_ireg (cfg);
3445 ins->sreg1 = temp->dreg;
3446 ins->opcode = OP_LOCALLOC;
3447 break;
3448 case OP_LOAD_MEMBASE:
3449 case OP_LOADI4_MEMBASE:
3450 case OP_LOADU4_MEMBASE:
3451 case OP_LOADU1_MEMBASE:
3452 /* we can do two things: load the immed in a register
3453 * and use an indexed load, or see if the immed can be
3454 * represented as an ad_imm + a load with a smaller offset
3455 * that fits. We just do the first for now, optimize later.
3456 */
3457 if (arm_is_imm12 (ins->inst_offset))
3458 break;
3459 ADD_NEW_INS (cfg, temp, OP_ICONST);
3460 temp->inst_c0 = ins->inst_offset;
3461 temp->dreg = mono_alloc_ireg (cfg);
3462 ins->sreg2 = temp->dreg;
3463 ins->opcode = map_to_reg_reg_op (ins->opcode);
3464 break;
3465 case OP_LOADI2_MEMBASE:
3466 case OP_LOADU2_MEMBASE:
3467 case OP_LOADI1_MEMBASE:
3468 if (arm_is_imm8 (ins->inst_offset))
3469 break;
3470 ADD_NEW_INS (cfg, temp, OP_ICONST);
3471 temp->inst_c0 = ins->inst_offset;
3472 temp->dreg = mono_alloc_ireg (cfg);
3473 ins->sreg2 = temp->dreg;
3474 ins->opcode = map_to_reg_reg_op (ins->opcode);
3475 break;
3476 case OP_LOADR4_MEMBASE:
3477 case OP_LOADR8_MEMBASE:
3478 if (arm_is_fpimm8 (ins->inst_offset))
3479 break;
3480 low_imm = ins->inst_offset & 0x1ff;
3481 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3482 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3483 temp->inst_imm = ins->inst_offset & ~0x1ff;
3484 temp->sreg1 = ins->inst_basereg;
3485 temp->dreg = mono_alloc_ireg (cfg);
3486 ins->inst_basereg = temp->dreg;
3487 ins->inst_offset = low_imm;
3488 } else {
3489 MonoInst *add_ins;
3490
3491 ADD_NEW_INS (cfg, temp, OP_ICONST);
3492 temp->inst_c0 = ins->inst_offset;
3493 temp->dreg = mono_alloc_ireg (cfg);
3494
3495 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3496 add_ins->sreg1 = ins->inst_basereg;
3497 add_ins->sreg2 = temp->dreg;
3498 add_ins->dreg = mono_alloc_ireg (cfg);
3499
3500 ins->inst_basereg = add_ins->dreg;
3501 ins->inst_offset = 0;
3502 }
3503 break;
3504 case OP_STORE_MEMBASE_REG:
3505 case OP_STOREI4_MEMBASE_REG:
3506 case OP_STOREI1_MEMBASE_REG:
3507 if (arm_is_imm12 (ins->inst_offset))
3508 break;
3509 ADD_NEW_INS (cfg, temp, OP_ICONST);
3510 temp->inst_c0 = ins->inst_offset;
3511 temp->dreg = mono_alloc_ireg (cfg);
3512 ins->sreg2 = temp->dreg;
3513 ins->opcode = map_to_reg_reg_op (ins->opcode);
3514 break;
3515 case OP_STOREI2_MEMBASE_REG:
3516 if (arm_is_imm8 (ins->inst_offset))
3517 break;
3518 ADD_NEW_INS (cfg, temp, OP_ICONST);
3519 temp->inst_c0 = ins->inst_offset;
3520 temp->dreg = mono_alloc_ireg (cfg);
3521 ins->sreg2 = temp->dreg;
3522 ins->opcode = map_to_reg_reg_op (ins->opcode);
3523 break;
3524 case OP_STORER4_MEMBASE_REG:
3525 case OP_STORER8_MEMBASE_REG:
3526 if (arm_is_fpimm8 (ins->inst_offset))
3527 break;
3528 low_imm = ins->inst_offset & 0x1ff;
3529 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3530 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3531 temp->inst_imm = ins->inst_offset & ~0x1ff;
3532 temp->sreg1 = ins->inst_destbasereg;
3533 temp->dreg = mono_alloc_ireg (cfg);
3534 ins->inst_destbasereg = temp->dreg;
3535 ins->inst_offset = low_imm;
3536 } else {
3537 MonoInst *add_ins;
3538
3539 ADD_NEW_INS (cfg, temp, OP_ICONST);
3540 temp->inst_c0 = ins->inst_offset;
3541 temp->dreg = mono_alloc_ireg (cfg);
3542
3543 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3544 add_ins->sreg1 = ins->inst_destbasereg;
3545 add_ins->sreg2 = temp->dreg;
3546 add_ins->dreg = mono_alloc_ireg (cfg);
3547
3548 ins->inst_destbasereg = add_ins->dreg;
3549 ins->inst_offset = 0;
3550 }
3551 break;
3552 case OP_STORE_MEMBASE_IMM:
3553 case OP_STOREI1_MEMBASE_IMM:
3554 case OP_STOREI2_MEMBASE_IMM:
3555 case OP_STOREI4_MEMBASE_IMM:
3556 ADD_NEW_INS (cfg, temp, OP_ICONST);
3557 temp->inst_c0 = ins->inst_imm;
3558 temp->dreg = mono_alloc_ireg (cfg);
3559 ins->sreg1 = temp->dreg;
3560 ins->opcode = map_to_reg_reg_op (ins->opcode);
3561 last_ins = temp;
3562 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3563 case OP_FCOMPARE:
3564 case OP_RCOMPARE: {
3565 gboolean swap = FALSE;
3566 int reg;
3567
3568 if (!ins->next) {
3569 /* Optimized away */
3570 NULLIFY_INS (ins);
3571 break;
3572 }
3573
3574 /* Some fp compares require swapped operands */
3575 switch (ins->next->opcode) {
3576 case OP_FBGT:
3577 ins->next->opcode = OP_FBLT;
3578 swap = TRUE;
3579 break;
3580 case OP_FBGT_UN:
3581 ins->next->opcode = OP_FBLT_UN;
3582 swap = TRUE;
3583 break;
3584 case OP_FBLE:
3585 ins->next->opcode = OP_FBGE;
3586 swap = TRUE;
3587 break;
3588 case OP_FBLE_UN:
3589 ins->next->opcode = OP_FBGE_UN;
3590 swap = TRUE;
3591 break;
3592 default:
3593 break;
3594 }
3595 if (swap) {
3596 reg = ins->sreg1;
3597 ins->sreg1 = ins->sreg2;
3598 ins->sreg2 = reg;
3599 }
3600 break;
3601 }
3602 }
3603
3604 last_ins = ins;
3605 }
3606 bb->last_ins = last_ins;
3607 bb->max_vreg = cfg->next_vreg;
3608 }
3609
3610 void
3611 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3612 {
3613 MonoInst *ins;
3614
3615 if (long_ins->opcode == OP_LNEG) {
3616 ins = long_ins;
3617 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3618 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3619 NULLIFY_INS (ins);
3620 }
3621 }
3622
3623 static guchar*
3624 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3625 {
3626 /* sreg is a float, dreg is an integer reg */
3627 if (IS_VFP) {
3628 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3629 if (is_signed)
3630 ARM_TOSIZD (code, vfp_scratch1, sreg);
3631 else
3632 ARM_TOUIZD (code, vfp_scratch1, sreg);
3633 ARM_FMRS (code, dreg, vfp_scratch1);
3634 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3635 }
3636 if (!is_signed) {
3637 if (size == 1)
3638 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3639 else if (size == 2) {
3640 ARM_SHL_IMM (code, dreg, dreg, 16);
3641 ARM_SHR_IMM (code, dreg, dreg, 16);
3642 }
3643 } else {
3644 if (size == 1) {
3645 ARM_SHL_IMM (code, dreg, dreg, 24);
3646 ARM_SAR_IMM (code, dreg, dreg, 24);
3647 } else if (size == 2) {
3648 ARM_SHL_IMM (code, dreg, dreg, 16);
3649 ARM_SAR_IMM (code, dreg, dreg, 16);
3650 }
3651 }
3652 return code;
3653 }
3654
3655 static guchar*
3656 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3657 {
3658 /* sreg is a float, dreg is an integer reg */
3659 g_assert (IS_VFP);
3660 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3661 if (is_signed)
3662 ARM_TOSIZS (code, vfp_scratch1, sreg);
3663 else
3664 ARM_TOUIZS (code, vfp_scratch1, sreg);
3665 ARM_FMRS (code, dreg, vfp_scratch1);
3666 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3667
3668 if (!is_signed) {
3669 if (size == 1)
3670 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3671 else if (size == 2) {
3672 ARM_SHL_IMM (code, dreg, dreg, 16);
3673 ARM_SHR_IMM (code, dreg, dreg, 16);
3674 }
3675 } else {
3676 if (size == 1) {
3677 ARM_SHL_IMM (code, dreg, dreg, 24);
3678 ARM_SAR_IMM (code, dreg, dreg, 24);
3679 } else if (size == 2) {
3680 ARM_SHL_IMM (code, dreg, dreg, 16);
3681 ARM_SAR_IMM (code, dreg, dreg, 16);
3682 }
3683 }
3684 return code;
3685 }
3686
3687 #endif /* #ifndef DISABLE_JIT */
3688
3689 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3690
3691 static void
3692 emit_thunk (guint8 *code, gconstpointer target)
3693 {
3694 guint8 *p = code;
3695
3696 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3697 if (thumb_supported)
3698 ARM_BX (code, ARMREG_IP);
3699 else
3700 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3701 *(guint32*)code = (guint32)target;
3702 code += 4;
3703 mono_arch_flush_icache (p, code - p);
3704 }
3705
3706 static void
3707 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3708 {
3709 MonoJitInfo *ji = NULL;
3710 MonoThunkJitInfo *info;
3711 guint8 *thunks, *p;
3712 int thunks_size;
3713 guint8 *orig_target;
3714 guint8 *target_thunk;
3715
3716 if (!domain)
3717 domain = mono_domain_get ();
3718
3719 if (cfg) {
3720 /*
3721 * This can be called multiple times during JITting,
3722 * save the current position in cfg->arch to avoid
3723 * doing a O(n^2) search.
3724 */
3725 if (!cfg->arch.thunks) {
3726 cfg->arch.thunks = cfg->thunks;
3727 cfg->arch.thunks_size = cfg->thunk_area;
3728 }
3729 thunks = cfg->arch.thunks;
3730 thunks_size = cfg->arch.thunks_size;
3731 if (!thunks_size) {
3732 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3733 g_assert_not_reached ();
3734 }
3735
3736 g_assert (*(guint32*)thunks == 0);
3737 emit_thunk (thunks, target);
3738 arm_patch (code, thunks);
3739
3740 cfg->arch.thunks += THUNK_SIZE;
3741 cfg->arch.thunks_size -= THUNK_SIZE;
3742 } else {
3743 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3744 g_assert (ji);
3745 info = mono_jit_info_get_thunk_info (ji);
3746 g_assert (info);
3747
3748 thunks = (guint8*)ji->code_start + info->thunks_offset;
3749 thunks_size = info->thunks_size;
3750
3751 orig_target = mono_arch_get_call_target (code + 4);
3752
3753 mono_mini_arch_lock ();
3754
3755 target_thunk = NULL;
3756 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3757 /* The call already points to a thunk, because of trampolines etc. */
3758 target_thunk = orig_target;
3759 } else {
3760 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3761 if (((guint32*)p) [0] == 0) {
3762 /* Free entry */
3763 target_thunk = p;
3764 break;
3765 } else if (((guint32*)p) [2] == (guint32)target) {
3766 /* Thunk already points to target */
3767 target_thunk = p;
3768 break;
3769 }
3770 }
3771 }
3772
3773 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3774
3775 if (!target_thunk) {
3776 mono_mini_arch_unlock ();
3777 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3778 g_assert_not_reached ();
3779 }
3780
3781 emit_thunk (target_thunk, target);
3782 arm_patch (code, target_thunk);
3783 mono_arch_flush_icache (code, 4);
3784
3785 mono_mini_arch_unlock ();
3786 }
3787 }
3788
3789 static void
3790 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3791 {
3792 guint32 *code32 = (void*)code;
3793 guint32 ins = *code32;
3794 guint32 prim = (ins >> 25) & 7;
3795 guint32 tval = GPOINTER_TO_UINT (target);
3796
3797 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3798 if (prim == 5) { /* 101b */
3799 /* the diff starts 8 bytes from the branch opcode */
3800 gint diff = target - code - 8;
3801 gint tbits;
3802 gint tmask = 0xffffffff;
3803 if (tval & 1) { /* entering thumb mode */
3804 diff = target - 1 - code - 8;
3805 g_assert (thumb_supported);
3806 tbits = 0xf << 28; /* bl->blx bit pattern */
3807 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3808 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3809 if (diff & 2) {
3810 tbits |= 1 << 24;
3811 }
3812 tmask = ~(1 << 24); /* clear the link bit */
3813 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3814 } else {
3815 tbits = 0;
3816 }
3817 if (diff >= 0) {
3818 if (diff <= 33554431) {
3819 diff >>= 2;
3820 ins = (ins & 0xff000000) | diff;
3821 ins &= tmask;
3822 *code32 = ins | tbits;
3823 return;
3824 }
3825 } else {
3826 /* diff between 0 and -33554432 */
3827 if (diff >= -33554432) {
3828 diff >>= 2;
3829 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3830 ins &= tmask;
3831 *code32 = ins | tbits;
3832 return;
3833 }
3834 }
3835
3836 handle_thunk (cfg, domain, code, target);
3837 return;
3838 }
3839
3840 /*
3841 * The alternative call sequences looks like this:
3842 *
3843 * ldr ip, [pc] // loads the address constant
3844 * b 1f // jumps around the constant
3845 * address constant embedded in the code
3846 * 1f:
3847 * mov lr, pc
3848 * mov pc, ip
3849 *
3850 * There are two cases for patching:
3851 * a) at the end of method emission: in this case code points to the start
3852 * of the call sequence
3853 * b) during runtime patching of the call site: in this case code points
3854 * to the mov pc, ip instruction
3855 *
3856 * We have to handle also the thunk jump code sequence:
3857 *
3858 * ldr ip, [pc]
3859 * mov pc, ip
3860 * address constant // execution never reaches here
3861 */
3862 if ((ins & 0x0ffffff0) == 0x12fff10) {
3863 /* Branch and exchange: the address is constructed in a reg
3864 * We can patch BX when the code sequence is the following:
3865 * ldr ip, [pc, #0] ; 0x8
3866 * b 0xc
3867 * .word code_ptr
3868 * mov lr, pc
3869 * bx ips
3870 * */
3871 guint32 ccode [4];
3872 guint8 *emit = (guint8*)ccode;
3873 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3874 ARM_B (emit, 0);
3875 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3876 ARM_BX (emit, ARMREG_IP);
3877
3878 /*patching from magic trampoline*/
3879 if (ins == ccode [3]) {
3880 g_assert (code32 [-4] == ccode [0]);
3881 g_assert (code32 [-3] == ccode [1]);
3882 g_assert (code32 [-1] == ccode [2]);
3883 code32 [-2] = (guint32)target;
3884 return;
3885 }
3886 /*patching from JIT*/
3887 if (ins == ccode [0]) {
3888 g_assert (code32 [1] == ccode [1]);
3889 g_assert (code32 [3] == ccode [2]);
3890 g_assert (code32 [4] == ccode [3]);
3891 code32 [2] = (guint32)target;
3892 return;
3893 }
3894 g_assert_not_reached ();
3895 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3896 /*
3897 * ldr ip, [pc, #0]
3898 * b 0xc
3899 * .word code_ptr
3900 * blx ip
3901 */
3902 guint32 ccode [4];
3903 guint8 *emit = (guint8*)ccode;
3904 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3905 ARM_B (emit, 0);
3906 ARM_BLX_REG (emit, ARMREG_IP);
3907
3908 g_assert (code32 [-3] == ccode [0]);
3909 g_assert (code32 [-2] == ccode [1]);
3910 g_assert (code32 [0] == ccode [2]);
3911
3912 code32 [-1] = (guint32)target;
3913 } else {
3914 guint32 ccode [4];
3915 guint32 *tmp = ccode;
3916 guint8 *emit = (guint8*)tmp;
3917 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3918 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3919 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3920 ARM_BX (emit, ARMREG_IP);
3921 if (ins == ccode [2]) {
3922 g_assert_not_reached (); // should be -2 ...
3923 code32 [-1] = (guint32)target;
3924 return;
3925 }
3926 if (ins == ccode [0]) {
3927 /* handles both thunk jump code and the far call sequence */
3928 code32 [2] = (guint32)target;
3929 return;
3930 }
3931 g_assert_not_reached ();
3932 }
3933 // g_print ("patched with 0x%08x\n", ins);
3934 }
3935
3936 void
3937 arm_patch (guchar *code, const guchar *target)
3938 {
3939 arm_patch_general (NULL, NULL, code, target);
3940 }
3941
3942 /*
3943 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3944 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3945 * to be used with the emit macros.
3946 * Return -1 otherwise.
3947 */
3948 int
3949 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3950 {
3951 guint32 res, i;
3952 for (i = 0; i < 31; i+= 2) {
3953 res = (val << (32 - i)) | (val >> i);
3954 if (res & ~0xff)
3955 continue;
3956 *rot_amount = i? 32 - i: 0;
3957 return res;
3958 }
3959 return -1;
3960 }
3961
3962 /*
3963 * Emits in code a sequence of instructions that load the value 'val'
3964 * into the dreg register. Uses at most 4 instructions.
3965 */
3966 guint8*
3967 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3968 {
3969 int imm8, rot_amount;
3970 #if 0
3971 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3972 /* skip the constant pool */
3973 ARM_B (code, 0);
3974 *(int*)code = val;
3975 code += 4;
3976 return code;
3977 #endif
3978 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3979 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3980 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3981 return code;
3982 }
3983
3984 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3985 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3986 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3987 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3988 } else {
3989 if (v7_supported) {
3990 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3991 if (val >> 16)
3992 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3993 return code;
3994 }
3995 if (val & 0xFF) {
3996 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3997 if (val & 0xFF00) {
3998 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3999 }
4000 if (val & 0xFF0000) {
4001 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4002 }
4003 if (val & 0xFF000000) {
4004 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4005 }
4006 } else if (val & 0xFF00) {
4007 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4008 if (val & 0xFF0000) {
4009 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4010 }
4011 if (val & 0xFF000000) {
4012 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4013 }
4014 } else if (val & 0xFF0000) {
4015 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4016 if (val & 0xFF000000) {
4017 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4018 }
4019 }
4020 //g_assert_not_reached ();
4021 }
4022 return code;
4023 }
4024
4025 gboolean
4026 mono_arm_thumb_supported (void)
4027 {
4028 return thumb_supported;
4029 }
4030
4031 #ifndef DISABLE_JIT
4032
4033 static guint8*
4034 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4035 {
4036 CallInfo *cinfo;
4037 MonoCallInst *call;
4038
4039 call = (MonoCallInst*)ins;
4040 cinfo = call->call_info;
4041
4042 switch (cinfo->ret.storage) {
4043 case RegTypeStructByVal:
4044 case RegTypeHFA: {
4045 MonoInst *loc = cfg->arch.vret_addr_loc;
4046 int i;
4047
4048 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4049 /* The JIT treats this as a normal call */
4050 break;
4051 }
4052
4053 /* Load the destination address */
4054 g_assert (loc && loc->opcode == OP_REGOFFSET);
4055
4056 if (arm_is_imm12 (loc->inst_offset)) {
4057 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4058 } else {
4059 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4060 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4061 }
4062
4063 if (cinfo->ret.storage == RegTypeStructByVal) {
4064 int rsize = cinfo->ret.struct_size;
4065
4066 for (i = 0; i < cinfo->ret.nregs; ++i) {
4067 g_assert (rsize >= 0);
4068 switch (rsize) {
4069 case 0:
4070 break;
4071 case 1:
4072 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4073 break;
4074 case 2:
4075 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4076 break;
4077 default:
4078 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4079 break;
4080 }
4081 rsize -= 4;
4082 }
4083 } else {
4084 for (i = 0; i < cinfo->ret.nregs; ++i) {
4085 if (cinfo->ret.esize == 4)
4086 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4087 else
4088 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4089 }
4090 }
4091 return code;
4092 }
4093 default:
4094 break;
4095 }
4096
4097 switch (ins->opcode) {
4098 case OP_FCALL:
4099 case OP_FCALL_REG:
4100 case OP_FCALL_MEMBASE:
4101 if (IS_VFP) {
4102 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4103 if (sig_ret->type == MONO_TYPE_R4) {
4104 if (IS_HARD_FLOAT) {
4105 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4106 } else {
4107 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4108 ARM_CVTS (code, ins->dreg, ins->dreg);
4109 }
4110 } else {
4111 if (IS_HARD_FLOAT) {
4112 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4113 } else {
4114 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4115 }
4116 }
4117 }
4118 break;
4119 case OP_RCALL:
4120 case OP_RCALL_REG:
4121 case OP_RCALL_MEMBASE: {
4122 MonoType *sig_ret;
4123
4124 g_assert (IS_VFP);
4125
4126 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4127 g_assert (sig_ret->type == MONO_TYPE_R4);
4128 if (IS_HARD_FLOAT) {
4129 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4130 } else {
4131 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4132 ARM_CPYS (code, ins->dreg, ins->dreg);
4133 }
4134 break;
4135 }
4136 default:
4137 break;
4138 }
4139
4140 return code;
4141 }
4142
4143 void
4144 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4145 {
4146 MonoInst *ins;
4147 MonoCallInst *call;
4148 guint offset;
4149 guint8 *code = cfg->native_code + cfg->code_len;
4150 MonoInst *last_ins = NULL;
4151 guint last_offset = 0;
4152 int max_len, cpos;
4153 int imm8, rot_amount;
4154
4155 /* we don't align basic blocks of loops on arm */
4156
4157 if (cfg->verbose_level > 2)
4158 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4159
4160 cpos = bb->max_offset;
4161
4162 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4163 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4164 //g_assert (!mono_compile_aot);
4165 //cpos += 6;
4166 //if (bb->cil_code)
4167 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4168 /* this is not thread save, but good enough */
4169 /* fixme: howto handle overflows? */
4170 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4171 }
4172
4173 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4174 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4175 (gpointer)"mono_break");
4176 code = emit_call_seq (cfg, code);
4177 }
4178
4179 MONO_BB_FOR_EACH_INS (bb, ins) {
4180 offset = code - cfg->native_code;
4181
4182 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4183
4184 if (offset > (cfg->code_size - max_len - 16)) {
4185 cfg->code_size *= 2;
4186 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4187 code = cfg->native_code + offset;
4188 }
4189 // if (ins->cil_code)
4190 // g_print ("cil code\n");
4191 mono_debug_record_line_number (cfg, ins, offset);
4192
4193 switch (ins->opcode) {
4194 case OP_MEMORY_BARRIER:
4195 if (v6_supported) {
4196 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4197 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4198 }
4199 break;
4200 case OP_TLS_GET:
4201 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4202 break;
4203 case OP_TLS_SET:
4204 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4205 break;
4206 case OP_ATOMIC_EXCHANGE_I4:
4207 case OP_ATOMIC_CAS_I4:
4208 case OP_ATOMIC_ADD_I4: {
4209 int tmpreg;
4210 guint8 *buf [16];
4211
4212 g_assert (v7_supported);
4213
4214 /* Free up a reg */
4215 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4216 tmpreg = ARMREG_IP;
4217 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4218 tmpreg = ARMREG_R0;
4219 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4220 tmpreg = ARMREG_R1;
4221 else
4222 tmpreg = ARMREG_R2;
4223 g_assert (cfg->arch.atomic_tmp_offset != -1);
4224 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4225
4226 switch (ins->opcode) {
4227 case OP_ATOMIC_EXCHANGE_I4:
4228 buf [0] = code;
4229 ARM_DMB (code, ARM_DMB_SY);
4230 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4231 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4232 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4233 buf [1] = code;
4234 ARM_B_COND (code, ARMCOND_NE, 0);
4235 arm_patch (buf [1], buf [0]);
4236 break;
4237 case OP_ATOMIC_CAS_I4:
4238 ARM_DMB (code, ARM_DMB_SY);
4239 buf [0] = code;
4240 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4241 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4242 buf [1] = code;
4243 ARM_B_COND (code, ARMCOND_NE, 0);
4244 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4245 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4246 buf [2] = code;
4247 ARM_B_COND (code, ARMCOND_NE, 0);
4248 arm_patch (buf [2], buf [0]);
4249 arm_patch (buf [1], code);
4250 break;
4251 case OP_ATOMIC_ADD_I4:
4252 buf [0] = code;
4253 ARM_DMB (code, ARM_DMB_SY);
4254 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4255 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4256 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4257 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4258 buf [1] = code;
4259 ARM_B_COND (code, ARMCOND_NE, 0);
4260 arm_patch (buf [1], buf [0]);
4261 break;
4262 default:
4263 g_assert_not_reached ();
4264 }
4265
4266 ARM_DMB (code, ARM_DMB_SY);
4267 if (tmpreg != ins->dreg)
4268 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4269 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4270 break;
4271 }
4272 case OP_ATOMIC_LOAD_I1:
4273 case OP_ATOMIC_LOAD_U1:
4274 case OP_ATOMIC_LOAD_I2:
4275 case OP_ATOMIC_LOAD_U2:
4276 case OP_ATOMIC_LOAD_I4:
4277 case OP_ATOMIC_LOAD_U4:
4278 case OP_ATOMIC_LOAD_R4:
4279 case OP_ATOMIC_LOAD_R8: {
4280 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4281 ARM_DMB (code, ARM_DMB_SY);
4282
4283 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4284
4285 switch (ins->opcode) {
4286 case OP_ATOMIC_LOAD_I1:
4287 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4288 break;
4289 case OP_ATOMIC_LOAD_U1:
4290 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4291 break;
4292 case OP_ATOMIC_LOAD_I2:
4293 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4294 break;
4295 case OP_ATOMIC_LOAD_U2:
4296 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4297 break;
4298 case OP_ATOMIC_LOAD_I4:
4299 case OP_ATOMIC_LOAD_U4:
4300 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4301 break;
4302 case OP_ATOMIC_LOAD_R4:
4303 if (cfg->r4fp) {
4304 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4305 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4306 } else {
4307 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4308 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4309 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4310 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4311 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4312 }
4313 break;
4314 case OP_ATOMIC_LOAD_R8:
4315 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4316 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4317 break;
4318 }
4319
4320 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4321 ARM_DMB (code, ARM_DMB_SY);
4322 break;
4323 }
4324 case OP_ATOMIC_STORE_I1:
4325 case OP_ATOMIC_STORE_U1:
4326 case OP_ATOMIC_STORE_I2:
4327 case OP_ATOMIC_STORE_U2:
4328 case OP_ATOMIC_STORE_I4:
4329 case OP_ATOMIC_STORE_U4:
4330 case OP_ATOMIC_STORE_R4:
4331 case OP_ATOMIC_STORE_R8: {
4332 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4333 ARM_DMB (code, ARM_DMB_SY);
4334
4335 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4336
4337 switch (ins->opcode) {
4338 case OP_ATOMIC_STORE_I1:
4339 case OP_ATOMIC_STORE_U1:
4340 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4341 break;
4342 case OP_ATOMIC_STORE_I2:
4343 case OP_ATOMIC_STORE_U2:
4344 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4345 break;
4346 case OP_ATOMIC_STORE_I4:
4347 case OP_ATOMIC_STORE_U4:
4348 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4349 break;
4350 case OP_ATOMIC_STORE_R4:
4351 if (cfg->r4fp) {
4352 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4353 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4354 } else {
4355 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4356 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4357 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4358 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4359 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4360 }
4361 break;
4362 case OP_ATOMIC_STORE_R8:
4363 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4364 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4365 break;
4366 }
4367
4368 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4369 ARM_DMB (code, ARM_DMB_SY);
4370 break;
4371 }
4372 case OP_BIGMUL:
4373 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4374 break;
4375 case OP_BIGMUL_UN:
4376 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4377 break;
4378 case OP_STOREI1_MEMBASE_IMM:
4379 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4380 g_assert (arm_is_imm12 (ins->inst_offset));
4381 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4382 break;
4383 case OP_STOREI2_MEMBASE_IMM:
4384 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4385 g_assert (arm_is_imm8 (ins->inst_offset));
4386 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4387 break;
4388 case OP_STORE_MEMBASE_IMM:
4389 case OP_STOREI4_MEMBASE_IMM:
4390 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4391 g_assert (arm_is_imm12 (ins->inst_offset));
4392 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4393 break;
4394 case OP_STOREI1_MEMBASE_REG:
4395 g_assert (arm_is_imm12 (ins->inst_offset));
4396 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4397 break;
4398 case OP_STOREI2_MEMBASE_REG:
4399 g_assert (arm_is_imm8 (ins->inst_offset));
4400 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4401 break;
4402 case OP_STORE_MEMBASE_REG:
4403 case OP_STOREI4_MEMBASE_REG:
4404 /* this case is special, since it happens for spill code after lowering has been called */
4405 if (arm_is_imm12 (ins->inst_offset)) {
4406 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4407 } else {
4408 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4409 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4410 }
4411 break;
4412 case OP_STOREI1_MEMINDEX:
4413 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4414 break;
4415 case OP_STOREI2_MEMINDEX:
4416 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4417 break;
4418 case OP_STORE_MEMINDEX:
4419 case OP_STOREI4_MEMINDEX:
4420 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4421 break;
4422 case OP_LOADU4_MEM:
4423 g_assert_not_reached ();
4424 break;
4425 case OP_LOAD_MEMINDEX:
4426 case OP_LOADI4_MEMINDEX:
4427 case OP_LOADU4_MEMINDEX:
4428 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4429 break;
4430 case OP_LOADI1_MEMINDEX:
4431 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4432 break;
4433 case OP_LOADU1_MEMINDEX:
4434 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4435 break;
4436 case OP_LOADI2_MEMINDEX:
4437 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4438 break;
4439 case OP_LOADU2_MEMINDEX:
4440 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4441 break;
4442 case OP_LOAD_MEMBASE:
4443 case OP_LOADI4_MEMBASE:
4444 case OP_LOADU4_MEMBASE:
4445 /* this case is special, since it happens for spill code after lowering has been called */
4446 if (arm_is_imm12 (ins->inst_offset)) {
4447 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4448 } else {
4449 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4450 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4451 }
4452 break;
4453 case OP_LOADI1_MEMBASE:
4454 g_assert (arm_is_imm8 (ins->inst_offset));
4455 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4456 break;
4457 case OP_LOADU1_MEMBASE:
4458 g_assert (arm_is_imm12 (ins->inst_offset));
4459 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4460 break;
4461 case OP_LOADU2_MEMBASE:
4462 g_assert (arm_is_imm8 (ins->inst_offset));
4463 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4464 break;
4465 case OP_LOADI2_MEMBASE:
4466 g_assert (arm_is_imm8 (ins->inst_offset));
4467 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4468 break;
4469 case OP_ICONV_TO_I1:
4470 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4471 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4472 break;
4473 case OP_ICONV_TO_I2:
4474 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4475 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4476 break;
4477 case OP_ICONV_TO_U1:
4478 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4479 break;
4480 case OP_ICONV_TO_U2:
4481 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4482 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4483 break;
4484 case OP_COMPARE:
4485 case OP_ICOMPARE:
4486 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4487 break;
4488 case OP_COMPARE_IMM:
4489 case OP_ICOMPARE_IMM:
4490 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4491 g_assert (imm8 >= 0);
4492 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4493 break;
4494 case OP_BREAK:
4495 /*
4496 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4497 * So instead of emitting a trap, we emit a call a C function and place a
4498 * breakpoint there.
4499 */
4500 //*(int*)code = 0xef9f0001;
4501 //code += 4;
4502 //ARM_DBRK (code);
4503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4504 (gpointer)"mono_break");
4505 code = emit_call_seq (cfg, code);
4506 break;
4507 case OP_RELAXED_NOP:
4508 ARM_NOP (code);
4509 break;
4510 case OP_NOP:
4511 case OP_DUMMY_USE:
4512 case OP_DUMMY_STORE:
4513 case OP_DUMMY_ICONST:
4514 case OP_DUMMY_R8CONST:
4515 case OP_NOT_REACHED:
4516 case OP_NOT_NULL:
4517 break;
4518 case OP_IL_SEQ_POINT:
4519 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4520 break;
4521 case OP_SEQ_POINT: {
4522 int i;
4523 MonoInst *info_var = cfg->arch.seq_point_info_var;
4524 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4525 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4526 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4527 MonoInst *var;
4528 int dreg = ARMREG_LR;
4529
4530 #if 0
4531 if (cfg->soft_breakpoints) {
4532 g_assert (!cfg->compile_aot);
4533 }
4534 #endif
4535
4536 /*
4537 * For AOT, we use one got slot per method, which will point to a
4538 * SeqPointInfo structure, containing all the information required
4539 * by the code below.
4540 */
4541 if (cfg->compile_aot) {
4542 g_assert (info_var);
4543 g_assert (info_var->opcode == OP_REGOFFSET);
4544 g_assert (arm_is_imm12 (info_var->inst_offset));
4545 }
4546
4547 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4548 /*
4549 * Read from the single stepping trigger page. This will cause a
4550 * SIGSEGV when single stepping is enabled.
4551 * We do this _before_ the breakpoint, so single stepping after
4552 * a breakpoint is hit will step to the next IL offset.
4553 */
4554 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4555 }
4556
4557 /* Single step check */
4558 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4559 if (cfg->soft_breakpoints) {
4560 /* Load the address of the sequence point method variable. */
4561 var = ss_method_var;
4562 g_assert (var);
4563 g_assert (var->opcode == OP_REGOFFSET);
4564 g_assert (arm_is_imm12 (var->inst_offset));
4565 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4566
4567 /* Read the value and check whether it is non-zero. */
4568 ARM_LDR_IMM (code, dreg, dreg, 0);
4569 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4570 /* Call it conditionally. */
4571 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4572 } else {
4573 if (cfg->compile_aot) {
4574 /* Load the trigger page addr from the variable initialized in the prolog */
4575 var = ss_trigger_page_var;
4576 g_assert (var);
4577 g_assert (var->opcode == OP_REGOFFSET);
4578 g_assert (arm_is_imm12 (var->inst_offset));
4579 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4580 } else {
4581 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4582 ARM_B (code, 0);
4583 *(int*)code = (int)ss_trigger_page;
4584 code += 4;
4585 }
4586 ARM_LDR_IMM (code, dreg, dreg, 0);
4587 }
4588 }
4589
4590 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4591
4592 /* Breakpoint check */
4593 if (cfg->compile_aot) {
4594 guint32 offset = code - cfg->native_code;
4595 guint32 val;
4596
4597 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4598 /* Add the offset */
4599 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4600 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4601 if (arm_is_imm12 ((int)val)) {
4602 ARM_LDR_IMM (code, dreg, dreg, val);
4603 } else {
4604 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4605 if (val & 0xFF00)
4606 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4607 if (val & 0xFF0000)
4608 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4609 g_assert (!(val & 0xFF000000));
4610
4611 ARM_LDR_IMM (code, dreg, dreg, 0);
4612 }
4613 /* What is faster, a branch or a load ? */
4614 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4615 /* The breakpoint instruction */
4616 if (cfg->soft_breakpoints)
4617 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4618 else
4619 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4620 } else if (cfg->soft_breakpoints) {
4621 /* Load the address of the breakpoint method into ip. */
4622 var = bp_method_var;
4623 g_assert (var);
4624 g_assert (var->opcode == OP_REGOFFSET);
4625 g_assert (arm_is_imm12 (var->inst_offset));
4626 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4627
4628 /*
4629 * A placeholder for a possible breakpoint inserted by
4630 * mono_arch_set_breakpoint ().
4631 */
4632 ARM_NOP (code);
4633 } else {
4634 /*
4635 * A placeholder for a possible breakpoint inserted by
4636 * mono_arch_set_breakpoint ().
4637 */
4638 for (i = 0; i < 4; ++i)
4639 ARM_NOP (code);
4640 }
4641
4642 /*
4643 * Add an additional nop so skipping the bp doesn't cause the ip to point
4644 * to another IL offset.
4645 */
4646
4647 ARM_NOP (code);
4648 break;
4649 }
4650 case OP_ADDCC:
4651 case OP_IADDCC:
4652 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4653 break;
4654 case OP_IADD:
4655 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4656 break;
4657 case OP_ADC:
4658 case OP_IADC:
4659 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4660 break;
4661 case OP_ADDCC_IMM:
4662 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4663 g_assert (imm8 >= 0);
4664 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4665 break;
4666 case OP_ADD_IMM:
4667 case OP_IADD_IMM:
4668 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4669 g_assert (imm8 >= 0);
4670 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4671 break;
4672 case OP_ADC_IMM:
4673 case OP_IADC_IMM:
4674 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4675 g_assert (imm8 >= 0);
4676 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4677 break;
4678 case OP_IADD_OVF:
4679 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4680 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4681 break;
4682 case OP_IADD_OVF_UN:
4683 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4684 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4685 break;
4686 case OP_ISUB_OVF:
4687 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4688 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4689 break;
4690 case OP_ISUB_OVF_UN:
4691 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4692 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4693 break;
4694 case OP_ADD_OVF_CARRY:
4695 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4696 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4697 break;
4698 case OP_ADD_OVF_UN_CARRY:
4699 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4700 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4701 break;
4702 case OP_SUB_OVF_CARRY:
4703 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4704 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4705 break;
4706 case OP_SUB_OVF_UN_CARRY:
4707 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4708 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4709 break;
4710 case OP_SUBCC:
4711 case OP_ISUBCC:
4712 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 break;
4714 case OP_SUBCC_IMM:
4715 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4716 g_assert (imm8 >= 0);
4717 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4718 break;
4719 case OP_ISUB:
4720 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4721 break;
4722 case OP_SBB:
4723 case OP_ISBB:
4724 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4725 break;
4726 case OP_SUB_IMM:
4727 case OP_ISUB_IMM:
4728 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4729 g_assert (imm8 >= 0);
4730 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4731 break;
4732 case OP_SBB_IMM:
4733 case OP_ISBB_IMM:
4734 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4735 g_assert (imm8 >= 0);
4736 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4737 break;
4738 case OP_ARM_RSBS_IMM:
4739 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4740 g_assert (imm8 >= 0);
4741 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4742 break;
4743 case OP_ARM_RSC_IMM:
4744 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4745 g_assert (imm8 >= 0);
4746 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 break;
4748 case OP_IAND:
4749 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 break;
4751 case OP_AND_IMM:
4752 case OP_IAND_IMM:
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4756 break;
4757 case OP_IDIV:
4758 g_assert (v7s_supported || v7k_supported);
4759 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4760 break;
4761 case OP_IDIV_UN:
4762 g_assert (v7s_supported || v7k_supported);
4763 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4764 break;
4765 case OP_IREM:
4766 g_assert (v7s_supported || v7k_supported);
4767 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4768 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4769 break;
4770 case OP_IREM_UN:
4771 g_assert (v7s_supported || v7k_supported);
4772 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4773 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4774 break;
4775 case OP_DIV_IMM:
4776 case OP_REM_IMM:
4777 g_assert_not_reached ();
4778 case OP_IOR:
4779 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4780 break;
4781 case OP_OR_IMM:
4782 case OP_IOR_IMM:
4783 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4784 g_assert (imm8 >= 0);
4785 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4786 break;
4787 case OP_IXOR:
4788 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4789 break;
4790 case OP_XOR_IMM:
4791 case OP_IXOR_IMM:
4792 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4793 g_assert (imm8 >= 0);
4794 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4795 break;
4796 case OP_ISHL:
4797 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4798 break;
4799 case OP_SHL_IMM:
4800 case OP_ISHL_IMM:
4801 if (ins->inst_imm)
4802 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4803 else if (ins->dreg != ins->sreg1)
4804 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4805 break;
4806 case OP_ISHR:
4807 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4808 break;
4809 case OP_SHR_IMM:
4810 case OP_ISHR_IMM:
4811 if (ins->inst_imm)
4812 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4813 else if (ins->dreg != ins->sreg1)
4814 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4815 break;
4816 case OP_SHR_UN_IMM:
4817 case OP_ISHR_UN_IMM:
4818 if (ins->inst_imm)
4819 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4820 else if (ins->dreg != ins->sreg1)
4821 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4822 break;
4823 case OP_ISHR_UN:
4824 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4825 break;
4826 case OP_INOT:
4827 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4828 break;
4829 case OP_INEG:
4830 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4831 break;
4832 case OP_IMUL:
4833 if (ins->dreg == ins->sreg2)
4834 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4835 else
4836 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4837 break;
4838 case OP_MUL_IMM:
4839 g_assert_not_reached ();
4840 break;
4841 case OP_IMUL_OVF:
4842 /* FIXME: handle ovf/ sreg2 != dreg */
4843 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4844 /* FIXME: MUL doesn't set the C/O flags on ARM */
4845 break;
4846 case OP_IMUL_OVF_UN:
4847 /* FIXME: handle ovf/ sreg2 != dreg */
4848 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4849 /* FIXME: MUL doesn't set the C/O flags on ARM */
4850 break;
4851 case OP_ICONST:
4852 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4853 break;
4854 case OP_AOTCONST:
4855 /* Load the GOT offset */
4856 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4857 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4858 ARM_B (code, 0);
4859 *(gpointer*)code = NULL;
4860 code += 4;
4861 /* Load the value from the GOT */
4862 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4863 break;
4864 case OP_OBJC_GET_SELECTOR:
4865 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4866 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4867 ARM_B (code, 0);
4868 *(gpointer*)code = NULL;
4869 code += 4;
4870 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4871 break;
4872 case OP_ICONV_TO_I4:
4873 case OP_ICONV_TO_U4:
4874 case OP_MOVE:
4875 if (ins->dreg != ins->sreg1)
4876 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4877 break;
4878 case OP_SETLRET: {
4879 int saved = ins->sreg2;
4880 if (ins->sreg2 == ARM_LSW_REG) {
4881 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4882 saved = ARMREG_LR;
4883 }
4884 if (ins->sreg1 != ARM_LSW_REG)
4885 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4886 if (saved != ARM_MSW_REG)
4887 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4888 break;
4889 }
4890 case OP_FMOVE:
4891 if (IS_VFP && ins->dreg != ins->sreg1)
4892 ARM_CPYD (code, ins->dreg, ins->sreg1);
4893 break;
4894 case OP_RMOVE:
4895 if (IS_VFP && ins->dreg != ins->sreg1)
4896 ARM_CPYS (code, ins->dreg, ins->sreg1);
4897 break;
4898 case OP_MOVE_F_TO_I4:
4899 if (cfg->r4fp) {
4900 ARM_FMRS (code, ins->dreg, ins->sreg1);
4901 } else {
4902 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4903 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4904 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4905 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4906 }
4907 break;
4908 case OP_MOVE_I4_TO_F:
4909 if (cfg->r4fp) {
4910 ARM_FMSR (code, ins->dreg, ins->sreg1);
4911 } else {
4912 ARM_FMSR (code, ins->dreg, ins->sreg1);
4913 ARM_CVTS (code, ins->dreg, ins->dreg);
4914 }
4915 break;
4916 case OP_FCONV_TO_R4:
4917 if (IS_VFP) {
4918 if (cfg->r4fp) {
4919 ARM_CVTD (code, ins->dreg, ins->sreg1);
4920 } else {
4921 ARM_CVTD (code, ins->dreg, ins->sreg1);
4922 ARM_CVTS (code, ins->dreg, ins->dreg);
4923 }
4924 }
4925 break;
4926 case OP_TAILCALL: {
4927 MonoCallInst *call = (MonoCallInst*)ins;
4928
4929 /*
4930 * The stack looks like the following:
4931 * <caller argument area>
4932 * <saved regs etc>
4933 * <rest of frame>
4934 * <callee argument area>
4935 * Need to copy the arguments from the callee argument area to
4936 * the caller argument area, and pop the frame.
4937 */
4938 if (call->stack_usage) {
4939 int i, prev_sp_offset = 0;
4940
4941 /* Compute size of saved registers restored below */
4942 if (iphone_abi)
4943 prev_sp_offset = 2 * 4;
4944 else
4945 prev_sp_offset = 1 * 4;
4946 for (i = 0; i < 16; ++i) {
4947 if (cfg->used_int_regs & (1 << i))
4948 prev_sp_offset += 4;
4949 }
4950
4951 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4952
4953 /* Copy arguments on the stack to our argument area */
4954 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4955 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4956 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4957 }
4958 }
4959
4960 /*
4961 * Keep in sync with mono_arch_emit_epilog
4962 */
4963 g_assert (!cfg->method->save_lmf);
4964
4965 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4966 if (iphone_abi) {
4967 if (cfg->used_int_regs)
4968 ARM_POP (code, cfg->used_int_regs);
4969 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4970 } else {
4971 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4972 }
4973
4974 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4975 if (cfg->compile_aot) {
4976 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4977 ARM_B (code, 0);
4978 *(gpointer*)code = NULL;
4979 code += 4;
4980 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4981 } else {
4982 code = mono_arm_patchable_b (code, ARMCOND_AL);
4983 cfg->thunk_area += THUNK_SIZE;
4984 }
4985 break;
4986 }
4987 case OP_CHECK_THIS:
4988 /* ensure ins->sreg1 is not NULL */
4989 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4990 break;
4991 case OP_ARGLIST: {
4992 g_assert (cfg->sig_cookie < 128);
4993 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4994 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4995 break;
4996 }
4997 case OP_FCALL:
4998 case OP_RCALL:
4999 case OP_LCALL:
5000 case OP_VCALL:
5001 case OP_VCALL2:
5002 case OP_VOIDCALL:
5003 case OP_CALL:
5004 call = (MonoCallInst*)ins;
5005
5006 if (IS_HARD_FLOAT)
5007 code = emit_float_args (cfg, call, code, &max_len, &offset);
5008
5009 if (ins->flags & MONO_INST_HAS_METHOD)
5010 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5011 else
5012 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5013 code = emit_call_seq (cfg, code);
5014 ins->flags |= MONO_INST_GC_CALLSITE;
5015 ins->backend.pc_offset = code - cfg->native_code;
5016 code = emit_move_return_value (cfg, ins, code);
5017 break;
5018 case OP_FCALL_REG:
5019 case OP_RCALL_REG:
5020 case OP_LCALL_REG:
5021 case OP_VCALL_REG:
5022 case OP_VCALL2_REG:
5023 case OP_VOIDCALL_REG:
5024 case OP_CALL_REG:
5025 if (IS_HARD_FLOAT)
5026 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5027
5028 code = emit_call_reg (code, ins->sreg1);
5029 ins->flags |= MONO_INST_GC_CALLSITE;
5030 ins->backend.pc_offset = code - cfg->native_code;
5031 code = emit_move_return_value (cfg, ins, code);
5032 break;
5033 case OP_FCALL_MEMBASE:
5034 case OP_RCALL_MEMBASE:
5035 case OP_LCALL_MEMBASE:
5036 case OP_VCALL_MEMBASE:
5037 case OP_VCALL2_MEMBASE:
5038 case OP_VOIDCALL_MEMBASE:
5039 case OP_CALL_MEMBASE: {
5040 g_assert (ins->sreg1 != ARMREG_LR);
5041 call = (MonoCallInst*)ins;
5042
5043 if (IS_HARD_FLOAT)
5044 code = emit_float_args (cfg, call, code, &max_len, &offset);
5045 if (!arm_is_imm12 (ins->inst_offset)) {
5046 /* sreg1 might be IP */
5047 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5048 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5049 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5050 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5051 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5052 } else {
5053 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5054 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5055 }
5056 ins->flags |= MONO_INST_GC_CALLSITE;
5057 ins->backend.pc_offset = code - cfg->native_code;
5058 code = emit_move_return_value (cfg, ins, code);
5059 break;
5060 }
5061 case OP_GENERIC_CLASS_INIT: {
5062 int byte_offset;
5063 guint8 *jump;
5064
5065 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5066
5067 g_assert (arm_is_imm8 (byte_offset));
5068 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5069 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5070 jump = code;
5071 ARM_B_COND (code, ARMCOND_NE, 0);
5072
5073 /* Uninitialized case */
5074 g_assert (ins->sreg1 == ARMREG_R0);
5075
5076 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5077 (gpointer)"mono_generic_class_init");
5078 code = emit_call_seq (cfg, code);
5079
5080 /* Initialized case */
5081 arm_patch (jump, code);
5082 break;
5083 }
5084 case OP_LOCALLOC: {
5085 /* round the size to 8 bytes */
5086 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5087 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5088 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5089 /* memzero the area: dreg holds the size, sp is the pointer */
5090 if (ins->flags & MONO_INST_INIT) {
5091 guint8 *start_loop, *branch_to_cond;
5092 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5093 branch_to_cond = code;
5094 ARM_B (code, 0);
5095 start_loop = code;
5096 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5097 arm_patch (branch_to_cond, code);
5098 /* decrement by 4 and set flags */
5099 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5100 ARM_B_COND (code, ARMCOND_GE, 0);
5101 arm_patch (code - 4, start_loop);
5102 }
5103 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5104 if (cfg->param_area)
5105 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5106 break;
5107 }
5108 case OP_DYN_CALL: {
5109 int i;
5110 MonoInst *var = cfg->dyn_call_var;
5111 guint8 *buf [16];
5112
5113 g_assert (var->opcode == OP_REGOFFSET);
5114 g_assert (arm_is_imm12 (var->inst_offset));
5115
5116 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5117 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5118 /* ip = ftn */
5119 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5120
5121 /* Save args buffer */
5122 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5123
5124 /* Set stack slots using R0 as scratch reg */
5125 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5126 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5127 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5128 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5129 }
5130
5131 /* Set fp argument registers */
5132 if (IS_HARD_FLOAT) {
5133 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5134 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5135 buf [0] = code;
5136 ARM_B_COND (code, ARMCOND_EQ, 0);
5137 for (i = 0; i < FP_PARAM_REGS; ++i) {
5138 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5139 g_assert (arm_is_fpimm8 (offset));
5140 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5141 }
5142 arm_patch (buf [0], code);
5143 }
5144
5145 /* Set argument registers */
5146 for (i = 0; i < PARAM_REGS; ++i)
5147 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5148
5149 /* Make the call */
5150 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5151 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5152
5153 /* Save result */
5154 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5155 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5156 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5157 if (IS_HARD_FLOAT)
5158 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5159 break;
5160 }
5161 case OP_THROW: {
5162 if (ins->sreg1 != ARMREG_R0)
5163 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5164 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5165 (gpointer)"mono_arch_throw_exception");
5166 code = emit_call_seq (cfg, code);
5167 break;
5168 }
5169 case OP_RETHROW: {
5170 if (ins->sreg1 != ARMREG_R0)
5171 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5172 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5173 (gpointer)"mono_arch_rethrow_exception");
5174 code = emit_call_seq (cfg, code);
5175 break;
5176 }
5177 case OP_START_HANDLER: {
5178 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5179 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5180 int i, rot_amount;
5181
5182 /* Reserve a param area, see filter-stack.exe */
5183 if (param_area) {
5184 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5185 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5186 } else {
5187 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5188 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5189 }
5190 }
5191
5192 if (arm_is_imm12 (spvar->inst_offset)) {
5193 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5194 } else {
5195 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5196 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5197 }
5198 break;
5199 }
5200 case OP_ENDFILTER: {
5201 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5202 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5203 int i, rot_amount;
5204
5205 /* Free the param area */
5206 if (param_area) {
5207 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5208 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5209 } else {
5210 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5211 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5212 }
5213 }
5214
5215 if (ins->sreg1 != ARMREG_R0)
5216 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5217 if (arm_is_imm12 (spvar->inst_offset)) {
5218 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5219 } else {
5220 g_assert (ARMREG_IP != spvar->inst_basereg);
5221 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5222 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5223 }
5224 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5225 break;
5226 }
5227 case OP_ENDFINALLY: {
5228 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5229 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5230 int i, rot_amount;
5231
5232 /* Free the param area */
5233 if (param_area) {
5234 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5235 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5236 } else {
5237 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5238 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5239 }
5240 }
5241
5242 if (arm_is_imm12 (spvar->inst_offset)) {
5243 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5244 } else {
5245 g_assert (ARMREG_IP != spvar->inst_basereg);
5246 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5247 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5248 }
5249 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5250 break;
5251 }
5252 case OP_CALL_HANDLER:
5253 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5254 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5255 cfg->thunk_area += THUNK_SIZE;
5256 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5257 break;
5258 case OP_GET_EX_OBJ:
5259 if (ins->dreg != ARMREG_R0)
5260 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5261 break;
5262
5263 case OP_LABEL:
5264 ins->inst_c0 = code - cfg->native_code;
5265 break;
5266 case OP_BR:
5267 /*if (ins->inst_target_bb->native_offset) {
5268 ARM_B (code, 0);
5269 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5270 } else*/ {
5271 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5272 code = mono_arm_patchable_b (code, ARMCOND_AL);
5273 }
5274 break;
5275 case OP_BR_REG:
5276 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5277 break;
5278 case OP_SWITCH:
5279 /*
5280 * In the normal case we have:
5281 * ldr pc, [pc, ins->sreg1 << 2]
5282 * nop
5283 * If aot, we have:
5284 * ldr lr, [pc, ins->sreg1 << 2]
5285 * add pc, pc, lr
5286 * After follows the data.
5287 * FIXME: add aot support.
5288 */
5289 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5290 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5291 if (offset + max_len > (cfg->code_size - 16)) {
5292 cfg->code_size += max_len;
5293 cfg->code_size *= 2;
5294 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5295 code = cfg->native_code + offset;
5296 }
5297 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5298 ARM_NOP (code);
5299 code += 4 * GPOINTER_TO_INT (ins->klass);
5300 break;
5301 case OP_CEQ:
5302 case OP_ICEQ:
5303 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5304 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5305 break;
5306 case OP_CLT:
5307 case OP_ICLT:
5308 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5309 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5310 break;
5311 case OP_CLT_UN:
5312 case OP_ICLT_UN:
5313 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5314 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5315 break;
5316 case OP_CGT:
5317 case OP_ICGT:
5318 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5319 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5320 break;
5321 case OP_CGT_UN:
5322 case OP_ICGT_UN:
5323 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5324 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5325 break;
5326 case OP_ICNEQ:
5327 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5328 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5329 break;
5330 case OP_ICGE:
5331 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5332 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5333 break;
5334 case OP_ICLE:
5335 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5336 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5337 break;
5338 case OP_ICGE_UN:
5339 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5340 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5341 break;
5342 case OP_ICLE_UN:
5343 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5344 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5345 break;
5346 case OP_COND_EXC_EQ:
5347 case OP_COND_EXC_NE_UN:
5348 case OP_COND_EXC_LT:
5349 case OP_COND_EXC_LT_UN:
5350 case OP_COND_EXC_GT:
5351 case OP_COND_EXC_GT_UN:
5352 case OP_COND_EXC_GE:
5353 case OP_COND_EXC_GE_UN:
5354 case OP_COND_EXC_LE:
5355 case OP_COND_EXC_LE_UN:
5356 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5357 break;
5358 case OP_COND_EXC_IEQ:
5359 case OP_COND_EXC_INE_UN:
5360 case OP_COND_EXC_ILT:
5361 case OP_COND_EXC_ILT_UN:
5362 case OP_COND_EXC_IGT:
5363 case OP_COND_EXC_IGT_UN:
5364 case OP_COND_EXC_IGE:
5365 case OP_COND_EXC_IGE_UN:
5366 case OP_COND_EXC_ILE:
5367 case OP_COND_EXC_ILE_UN:
5368 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5369 break;
5370 case OP_COND_EXC_C:
5371 case OP_COND_EXC_IC:
5372 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5373 break;
5374 case OP_COND_EXC_OV:
5375 case OP_COND_EXC_IOV:
5376 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5377 break;
5378 case OP_COND_EXC_NC:
5379 case OP_COND_EXC_INC:
5380 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5381 break;
5382 case OP_COND_EXC_NO:
5383 case OP_COND_EXC_INO:
5384 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5385 break;
5386 case OP_IBEQ:
5387 case OP_IBNE_UN:
5388 case OP_IBLT:
5389 case OP_IBLT_UN:
5390 case OP_IBGT:
5391 case OP_IBGT_UN:
5392 case OP_IBGE:
5393 case OP_IBGE_UN:
5394 case OP_IBLE:
5395 case OP_IBLE_UN:
5396 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5397 break;
5398
5399 /* floating point opcodes */
5400 case OP_R8CONST:
5401 if (cfg->compile_aot) {
5402 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5403 ARM_B (code, 1);
5404 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5405 code += 4;
5406 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5407 code += 4;
5408 } else {
5409 /* FIXME: we can optimize the imm load by dealing with part of
5410 * the displacement in LDFD (aligning to 512).
5411 */
5412 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5413 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5414 }
5415 break;
5416 case OP_R4CONST:
5417 if (cfg->compile_aot) {
5418 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5419 ARM_B (code, 0);
5420 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5421 code += 4;
5422 if (!cfg->r4fp)
5423 ARM_CVTS (code, ins->dreg, ins->dreg);
5424 } else {
5425 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5426 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5427 if (!cfg->r4fp)
5428 ARM_CVTS (code, ins->dreg, ins->dreg);
5429 }
5430 break;
5431 case OP_STORER8_MEMBASE_REG:
5432 /* This is generated by the local regalloc pass which runs after the lowering pass */
5433 if (!arm_is_fpimm8 (ins->inst_offset)) {
5434 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5435 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5436 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5437 } else {
5438 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5439 }
5440 break;
5441 case OP_LOADR8_MEMBASE:
5442 /* This is generated by the local regalloc pass which runs after the lowering pass */
5443 if (!arm_is_fpimm8 (ins->inst_offset)) {
5444 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5445 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5446 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5447 } else {
5448 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5449 }
5450 break;
5451 case OP_STORER4_MEMBASE_REG:
5452 g_assert (arm_is_fpimm8 (ins->inst_offset));
5453 if (cfg->r4fp) {
5454 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5455 } else {
5456 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5457 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5458 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5459 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5460 }
5461 break;
5462 case OP_LOADR4_MEMBASE:
5463 if (cfg->r4fp) {
5464 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5465 } else {
5466 g_assert (arm_is_fpimm8 (ins->inst_offset));
5467 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5468 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5469 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5470 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5471 }
5472 break;
5473 case OP_ICONV_TO_R_UN: {
5474 g_assert_not_reached ();
5475 break;
5476 }
5477 case OP_ICONV_TO_R4:
5478 if (cfg->r4fp) {
5479 ARM_FMSR (code, ins->dreg, ins->sreg1);
5480 ARM_FSITOS (code, ins->dreg, ins->dreg);
5481 } else {
5482 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5483 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5484 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5485 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5486 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5487 }
5488 break;
5489 case OP_ICONV_TO_R8:
5490 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5491 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5492 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5493 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5494 break;
5495
5496 case OP_SETFRET: {
5497 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5498 if (sig_ret->type == MONO_TYPE_R4) {
5499 if (cfg->r4fp) {
5500 if (IS_HARD_FLOAT) {
5501 if (ins->sreg1 != ARM_VFP_D0)
5502 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5503 } else {
5504 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5505 }
5506 } else {
5507 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5508
5509 if (!IS_HARD_FLOAT)
5510 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5511 }
5512 } else {
5513 if (IS_HARD_FLOAT)
5514 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5515 else
5516 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5517 }
5518 break;
5519 }
5520 case OP_FCONV_TO_I1:
5521 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5522 break;
5523 case OP_FCONV_TO_U1:
5524 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5525 break;
5526 case OP_FCONV_TO_I2:
5527 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5528 break;
5529 case OP_FCONV_TO_U2:
5530 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5531 break;
5532 case OP_FCONV_TO_I4:
5533 case OP_FCONV_TO_I:
5534 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5535 break;
5536 case OP_FCONV_TO_U4:
5537 case OP_FCONV_TO_U:
5538 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5539 break;
5540 case OP_FCONV_TO_I8:
5541 case OP_FCONV_TO_U8:
5542 g_assert_not_reached ();
5543 /* Implemented as helper calls */
5544 break;
5545 case OP_LCONV_TO_R_UN:
5546 g_assert_not_reached ();
5547 /* Implemented as helper calls */
5548 break;
5549 case OP_LCONV_TO_OVF_I4_2: {
5550 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5551 /*
5552 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5553 */
5554
5555 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5556 high_bit_not_set = code;
5557 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5558
5559 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5560 valid_negative = code;
5561 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5562 invalid_negative = code;
5563 ARM_B_COND (code, ARMCOND_AL, 0);
5564
5565 arm_patch (high_bit_not_set, code);
5566
5567 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5568 valid_positive = code;
5569 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5570
5571 arm_patch (invalid_negative, code);
5572 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5573
5574 arm_patch (valid_negative, code);
5575 arm_patch (valid_positive, code);
5576
5577 if (ins->dreg != ins->sreg1)
5578 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5579 break;
5580 }
5581 case OP_FADD:
5582 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5583 break;
5584 case OP_FSUB:
5585 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5586 break;
5587 case OP_FMUL:
5588 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5589 break;
5590 case OP_FDIV:
5591 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5592 break;
5593 case OP_FNEG:
5594 ARM_NEGD (code, ins->dreg, ins->sreg1);
5595 break;
5596 case OP_FREM:
5597 /* emulated */
5598 g_assert_not_reached ();
5599 break;
5600 case OP_FCOMPARE:
5601 if (IS_VFP) {
5602 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5603 ARM_FMSTAT (code);
5604 }
5605 break;
5606 case OP_RCOMPARE:
5607 g_assert (IS_VFP);
5608 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5609 ARM_FMSTAT (code);
5610 break;
5611 case OP_FCEQ:
5612 if (IS_VFP) {
5613 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5614 ARM_FMSTAT (code);
5615 }
5616 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5617 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5618 break;
5619 case OP_FCLT:
5620 if (IS_VFP) {
5621 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5622 ARM_FMSTAT (code);
5623 }
5624 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5625 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5626 break;
5627 case OP_FCLT_UN:
5628 if (IS_VFP) {
5629 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5630 ARM_FMSTAT (code);
5631 }
5632 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5633 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5634 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5635 break;
5636 case OP_FCGT:
5637 if (IS_VFP) {
5638 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5639 ARM_FMSTAT (code);
5640 }
5641 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5642 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5643 break;
5644 case OP_FCGT_UN:
5645 if (IS_VFP) {
5646 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5647 ARM_FMSTAT (code);
5648 }
5649 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5650 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5651 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5652 break;
5653 case OP_FCNEQ:
5654 if (IS_VFP) {
5655 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5656 ARM_FMSTAT (code);
5657 }
5658 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5659 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5660 break;
5661 case OP_FCGE:
5662 if (IS_VFP) {
5663 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5664 ARM_FMSTAT (code);
5665 }
5666 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5667 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5668 break;
5669 case OP_FCLE:
5670 if (IS_VFP) {
5671 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5672 ARM_FMSTAT (code);
5673 }
5674 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5675 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5676 break;
5677
5678 /* ARM FPA flags table:
5679 * N Less than ARMCOND_MI
5680 * Z Equal ARMCOND_EQ
5681 * C Greater Than or Equal ARMCOND_CS
5682 * V Unordered ARMCOND_VS
5683 */
5684 case OP_FBEQ:
5685 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5686 break;
5687 case OP_FBNE_UN:
5688 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5689 break;
5690 case OP_FBLT:
5691 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5692 break;
5693 case OP_FBLT_UN:
5694 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5695 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5696 break;
5697 case OP_FBGT:
5698 case OP_FBGT_UN:
5699 case OP_FBLE:
5700 case OP_FBLE_UN:
5701 g_assert_not_reached ();
5702 break;
5703 case OP_FBGE:
5704 if (IS_VFP) {
5705 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5706 } else {
5707 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5708 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5709 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5710 }
5711 break;
5712 case OP_FBGE_UN:
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5715 break;
5716
5717 case OP_CKFINITE: {
5718 if (IS_VFP) {
5719 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5720 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5721
5722 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5723 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5724 ARM_B (code, 1);
5725 *(guint32*)code = 0xffffffff;
5726 code += 4;
5727 *(guint32*)code = 0x7fefffff;
5728 code += 4;
5729 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5730 ARM_FMSTAT (code);
5731 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5732 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5733 ARM_FMSTAT (code);
5734 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5735 ARM_CPYD (code, ins->dreg, ins->sreg1);
5736
5737 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5738 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5739 }
5740 break;
5741 }
5742
5743 case OP_RCONV_TO_I1:
5744 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5745 break;
5746 case OP_RCONV_TO_U1:
5747 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5748 break;
5749 case OP_RCONV_TO_I2:
5750 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5751 break;
5752 case OP_RCONV_TO_U2:
5753 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5754 break;
5755 case OP_RCONV_TO_I4:
5756 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5757 break;
5758 case OP_RCONV_TO_U4:
5759 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5760 break;
5761 case OP_RCONV_TO_R4:
5762 g_assert (IS_VFP);
5763 if (ins->dreg != ins->sreg1)
5764 ARM_CPYS (code, ins->dreg, ins->sreg1);
5765 break;
5766 case OP_RCONV_TO_R8:
5767 g_assert (IS_VFP);
5768 ARM_CVTS (code, ins->dreg, ins->sreg1);
5769 break;
5770 case OP_RADD:
5771 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5772 break;
5773 case OP_RSUB:
5774 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5775 break;
5776 case OP_RMUL:
5777 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5778 break;
5779 case OP_RDIV:
5780 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5781 break;
5782 case OP_RNEG:
5783 ARM_NEGS (code, ins->dreg, ins->sreg1);
5784 break;
5785 case OP_RCEQ:
5786 if (IS_VFP) {
5787 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5788 ARM_FMSTAT (code);
5789 }
5790 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5791 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5792 break;
5793 case OP_RCLT:
5794 if (IS_VFP) {
5795 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5796 ARM_FMSTAT (code);
5797 }
5798 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5799 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5800 break;
5801 case OP_RCLT_UN:
5802 if (IS_VFP) {
5803 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5804 ARM_FMSTAT (code);
5805 }
5806 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5807 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5808 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5809 break;
5810 case OP_RCGT:
5811 if (IS_VFP) {
5812 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5813 ARM_FMSTAT (code);
5814 }
5815 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5816 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5817 break;
5818 case OP_RCGT_UN:
5819 if (IS_VFP) {
5820 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5821 ARM_FMSTAT (code);
5822 }
5823 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5824 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5825 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5826 break;
5827 case OP_RCNEQ:
5828 if (IS_VFP) {
5829 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5830 ARM_FMSTAT (code);
5831 }
5832 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5833 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5834 break;
5835 case OP_RCGE:
5836 if (IS_VFP) {
5837 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5838 ARM_FMSTAT (code);
5839 }
5840 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5841 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5842 break;
5843 case OP_RCLE:
5844 if (IS_VFP) {
5845 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5846 ARM_FMSTAT (code);
5847 }
5848 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5849 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5850 break;
5851
5852 case OP_GC_LIVENESS_DEF:
5853 case OP_GC_LIVENESS_USE:
5854 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5855 ins->backend.pc_offset = code - cfg->native_code;
5856 break;
5857 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5858 ins->backend.pc_offset = code - cfg->native_code;
5859 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5860 break;
5861 case OP_GC_SAFE_POINT: {
5862 guint8 *buf [1];
5863
5864 g_assert (mono_threads_is_coop_enabled ());
5865
5866 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5867 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5868 buf [0] = code;
5869 ARM_B_COND (code, ARMCOND_EQ, 0);
5870 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5871 code = emit_call_seq (cfg, code);
5872 arm_patch (buf [0], code);
5873 break;
5874 }
5875
5876 default:
5877 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5878 g_assert_not_reached ();
5879 }
5880
5881 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5882 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5883 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5884 g_assert_not_reached ();
5885 }
5886
5887 cpos += max_len;
5888
5889 last_ins = ins;
5890 last_offset = offset;
5891 }
5892
5893 cfg->code_len = code - cfg->native_code;
5894 }
5895
5896 #endif /* DISABLE_JIT */
5897
5898 void
5899 mono_arch_register_lowlevel_calls (void)
5900 {
5901 /* The signature doesn't matter */
5902 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5903 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5904 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5905 }
5906
5907 #define patch_lis_ori(ip,val) do {\
5908 guint16 *__lis_ori = (guint16*)(ip); \
5909 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5910 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5911 } while (0)
5912
5913 void
5914 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5915 {
5916 unsigned char *ip = ji->ip.i + code;
5917
5918 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5919 }
5920
5921 switch (ji->type) {
5922 case MONO_PATCH_INFO_SWITCH: {
5923 gpointer *jt = (gpointer*)(ip + 8);
5924 int i;
5925 /* jt is the inlined jump table, 2 instructions after ip
5926 * In the normal case we store the absolute addresses,
5927 * otherwise the displacements.
5928 */
5929 for (i = 0; i < ji->data.table->table_size; i++)
5930 jt [i] = code + (int)ji->data.table->table [i];
5931 break;
5932 }
5933 case MONO_PATCH_INFO_IP:
5934 g_assert_not_reached ();
5935 patch_lis_ori (ip, ip);
5936 break;
5937 case MONO_PATCH_INFO_METHOD_REL:
5938 g_assert_not_reached ();
5939 *((gpointer *)(ip)) = target;
5940 break;
5941 case MONO_PATCH_INFO_METHODCONST:
5942 case MONO_PATCH_INFO_CLASS:
5943 case MONO_PATCH_INFO_IMAGE:
5944 case MONO_PATCH_INFO_FIELD:
5945 case MONO_PATCH_INFO_VTABLE:
5946 case MONO_PATCH_INFO_IID:
5947 case MONO_PATCH_INFO_SFLDA:
5948 case MONO_PATCH_INFO_LDSTR:
5949 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5950 case MONO_PATCH_INFO_LDTOKEN:
5951 g_assert_not_reached ();
5952 /* from OP_AOTCONST : lis + ori */
5953 patch_lis_ori (ip, target);
5954 break;
5955 case MONO_PATCH_INFO_R4:
5956 case MONO_PATCH_INFO_R8:
5957 g_assert_not_reached ();
5958 *((gconstpointer *)(ip + 2)) = target;
5959 break;
5960 case MONO_PATCH_INFO_EXC_NAME:
5961 g_assert_not_reached ();
5962 *((gconstpointer *)(ip + 1)) = target;
5963 break;
5964 case MONO_PATCH_INFO_NONE:
5965 case MONO_PATCH_INFO_BB_OVF:
5966 case MONO_PATCH_INFO_EXC_OVF:
5967 /* everything is dealt with at epilog output time */
5968 break;
5969 default:
5970 arm_patch_general (cfg, domain, ip, target);
5971 break;
5972 }
5973 }
5974
5975 void
5976 mono_arm_unaligned_stack (MonoMethod *method)
5977 {
5978 g_assert_not_reached ();
5979 }
5980
5981 #ifndef DISABLE_JIT
5982
5983 /*
5984 * Stack frame layout:
5985 *
5986 * ------------------- fp
5987 * MonoLMF structure or saved registers
5988 * -------------------
5989 * locals
5990 * -------------------
5991 * spilled regs
5992 * -------------------
5993 * optional 8 bytes for tracing
5994 * -------------------
5995 * param area size is cfg->param_area
5996 * ------------------- sp
5997 */
5998 guint8 *
5999 mono_arch_emit_prolog (MonoCompile *cfg)
6000 {
6001 MonoMethod *method = cfg->method;
6002 MonoBasicBlock *bb;
6003 MonoMethodSignature *sig;
6004 MonoInst *inst;
6005 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6006 guint8 *code;
6007 CallInfo *cinfo;
6008 int tracing = 0;
6009 int lmf_offset = 0;
6010 int prev_sp_offset, reg_offset;
6011
6012 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6013 tracing = 1;
6014
6015 sig = mono_method_signature (method);
6016 cfg->code_size = 256 + sig->param_count * 64;
6017 code = cfg->native_code = g_malloc (cfg->code_size);
6018
6019 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6020
6021 alloc_size = cfg->stack_offset;
6022 pos = 0;
6023 prev_sp_offset = 0;
6024
6025 if (iphone_abi) {
6026 /*
6027 * The iphone uses R7 as the frame pointer, and it points at the saved
6028 * r7+lr:
6029 * <lr>
6030 * r7 -> <r7>
6031 * <rest of frame>
6032 * We can't use r7 as a frame pointer since it points into the middle of
6033 * the frame, so we keep using our own frame pointer.
6034 * FIXME: Optimize this.
6035 */
6036 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6037 prev_sp_offset += 8; /* r7 and lr */
6038 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6039 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6040 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6041 }
6042
6043 if (!method->save_lmf) {
6044 if (iphone_abi) {
6045 /* No need to push LR again */
6046 if (cfg->used_int_regs)
6047 ARM_PUSH (code, cfg->used_int_regs);
6048 } else {
6049 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6050 prev_sp_offset += 4;
6051 }
6052 for (i = 0; i < 16; ++i) {
6053 if (cfg->used_int_regs & (1 << i))
6054 prev_sp_offset += 4;
6055 }
6056 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6057 reg_offset = 0;
6058 for (i = 0; i < 16; ++i) {
6059 if ((cfg->used_int_regs & (1 << i))) {
6060 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6061 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6062 reg_offset += 4;
6063 }
6064 }
6065 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6066 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6067 } else {
6068 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6069 ARM_PUSH (code, 0x5ff0);
6070 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6071 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6072 reg_offset = 0;
6073 for (i = 0; i < 16; ++i) {
6074 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6075 /* The original r7 is saved at the start */
6076 if (!(iphone_abi && i == ARMREG_R7))
6077 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6078 reg_offset += 4;
6079 }
6080 }
6081 g_assert (reg_offset == 4 * 10);
6082 pos += sizeof (MonoLMF) - (4 * 10);
6083 lmf_offset = pos;
6084 }
6085 alloc_size += pos;
6086 orig_alloc_size = alloc_size;
6087 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6088 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6089 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6090 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6091 }
6092
6093 /* the stack used in the pushed regs */
6094 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6095 cfg->stack_usage = alloc_size;
6096 if (alloc_size) {
6097 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6098 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6099 } else {
6100 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6101 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6102 }
6103 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6104 }
6105 if (cfg->frame_reg != ARMREG_SP) {
6106 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6107 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6108 }
6109 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6110 prev_sp_offset += alloc_size;
6111
6112 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6113 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6114
6115 /* compute max_offset in order to use short forward jumps
6116 * we could skip do it on arm because the immediate displacement
6117 * for jumps is large enough, it may be useful later for constant pools
6118 */
6119 max_offset = 0;
6120 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6121 MonoInst *ins = bb->code;
6122 bb->max_offset = max_offset;
6123
6124 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6125 max_offset += 6;
6126
6127 MONO_BB_FOR_EACH_INS (bb, ins)
6128 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6129 }
6130
6131 /* stack alignment check */
6132 /*
6133 {
6134 guint8 *buf [16];
6135 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6136 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6137 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6138 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6139 buf [0] = code;
6140 ARM_B_COND (code, ARMCOND_EQ, 0);
6141 if (cfg->compile_aot)
6142 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6143 else
6144 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6145 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6146 code = emit_call_seq (cfg, code);
6147 arm_patch (buf [0], code);
6148 }
6149 */
6150
6151 /* store runtime generic context */
6152 if (cfg->rgctx_var) {
6153 MonoInst *ins = cfg->rgctx_var;
6154
6155 g_assert (ins->opcode == OP_REGOFFSET);
6156
6157 if (arm_is_imm12 (ins->inst_offset)) {
6158 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6159 } else {
6160 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6161 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6162 }
6163 }
6164
6165 /* load arguments allocated to register from the stack */
6166 pos = 0;
6167
6168 cinfo = get_call_info (NULL, sig);
6169
6170 if (cinfo->ret.storage == RegTypeStructByAddr) {
6171 ArgInfo *ainfo = &cinfo->ret;
6172 inst = cfg->vret_addr;
6173 g_assert (arm_is_imm12 (inst->inst_offset));
6174 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6175 }
6176
6177 if (sig->call_convention == MONO_CALL_VARARG) {
6178 ArgInfo *cookie = &cinfo->sig_cookie;
6179
6180 /* Save the sig cookie address */
6181 g_assert (cookie->storage == RegTypeBase);
6182
6183 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6184 g_assert (arm_is_imm12 (cfg->sig_cookie));
6185 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6186 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6187 }
6188
6189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6190 ArgInfo *ainfo = cinfo->args + i;
6191 inst = cfg->args [pos];
6192
6193 if (cfg->verbose_level > 2)
6194 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6195
6196 if (inst->opcode == OP_REGVAR) {
6197 if (ainfo->storage == RegTypeGeneral)
6198 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6199 else if (ainfo->storage == RegTypeFP) {
6200 g_assert_not_reached ();
6201 } else if (ainfo->storage == RegTypeBase) {
6202 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6203 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6204 } else {
6205 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6206 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6207 }
6208 } else
6209 g_assert_not_reached ();
6210
6211 if (cfg->verbose_level > 2)
6212 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6213 } else {
6214 switch (ainfo->storage) {
6215 case RegTypeHFA:
6216 for (part = 0; part < ainfo->nregs; part ++) {
6217 if (ainfo->esize == 4)
6218 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6219 else
6220 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6221 }
6222 break;
6223 case RegTypeGeneral:
6224 case RegTypeIRegPair:
6225 case RegTypeGSharedVtInReg:
6226 case RegTypeStructByAddr:
6227 switch (ainfo->size) {
6228 case 1:
6229 if (arm_is_imm12 (inst->inst_offset))
6230 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6231 else {
6232 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6233 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6234 }
6235 break;
6236 case 2:
6237 if (arm_is_imm8 (inst->inst_offset)) {
6238 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6239 } else {
6240 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6241 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6242 }
6243 break;
6244 case 8:
6245 if (arm_is_imm12 (inst->inst_offset)) {
6246 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6247 } else {
6248 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6249 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6250 }
6251 if (arm_is_imm12 (inst->inst_offset + 4)) {
6252 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6253 } else {
6254 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6255 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6256 }
6257 break;
6258 default:
6259 if (arm_is_imm12 (inst->inst_offset)) {
6260 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6261 } else {
6262 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6263 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6264 }
6265 break;
6266 }
6267 break;
6268 case RegTypeBaseGen:
6269 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6271 } else {
6272 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6273 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6274 }
6275 if (arm_is_imm12 (inst->inst_offset + 4)) {
6276 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6277 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6278 } else {
6279 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6280 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6281 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6282 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6283 }
6284 break;
6285 case RegTypeBase:
6286 case RegTypeGSharedVtOnStack:
6287 case RegTypeStructByAddrOnStack:
6288 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6289 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6290 } else {
6291 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6292 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6293 }
6294
6295 switch (ainfo->size) {
6296 case 1:
6297 if (arm_is_imm8 (inst->inst_offset)) {
6298 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6299 } else {
6300 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6301 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6302 }
6303 break;
6304 case 2:
6305 if (arm_is_imm8 (inst->inst_offset)) {
6306 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6307 } else {
6308 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6309 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6310 }
6311 break;
6312 case 8:
6313 if (arm_is_imm12 (inst->inst_offset)) {
6314 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6315 } else {
6316 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6317 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6318 }
6319 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6320 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6321 } else {
6322 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6323 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6324 }
6325 if (arm_is_imm12 (inst->inst_offset + 4)) {
6326 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6327 } else {
6328 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6329 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6330 }
6331 break;
6332 default:
6333 if (arm_is_imm12 (inst->inst_offset)) {
6334 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6335 } else {
6336 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6337 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6338 }
6339 break;
6340 }
6341 break;
6342 case RegTypeFP: {
6343 int imm8, rot_amount;
6344
6345 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6346 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6347 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6348 } else
6349 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6350
6351 if (ainfo->size == 8)
6352 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6353 else
6354 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6355 break;
6356 }
6357 case RegTypeStructByVal: {
6358 int doffset = inst->inst_offset;
6359 int soffset = 0;
6360 int cur_reg;
6361 int size = 0;
6362 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6363 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6364 if (arm_is_imm12 (doffset)) {
6365 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6366 } else {
6367 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6368 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6369 }
6370 soffset += sizeof (gpointer);
6371 doffset += sizeof (gpointer);
6372 }
6373 if (ainfo->vtsize) {
6374 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6375 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6376 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6377 }
6378 break;
6379 }
6380 default:
6381 g_assert_not_reached ();
6382 break;
6383 }
6384 }
6385 pos++;
6386 }
6387
6388 if (method->save_lmf)
6389 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6390
6391 if (tracing)
6392 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6393
6394 if (cfg->arch.seq_point_info_var) {
6395 MonoInst *ins = cfg->arch.seq_point_info_var;
6396
6397 /* Initialize the variable from a GOT slot */
6398 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6399 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6400 ARM_B (code, 0);
6401 *(gpointer*)code = NULL;
6402 code += 4;
6403 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6404
6405 g_assert (ins->opcode == OP_REGOFFSET);
6406
6407 if (arm_is_imm12 (ins->inst_offset)) {
6408 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6409 } else {
6410 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6411 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6412 }
6413 }
6414
6415 /* Initialize ss_trigger_page_var */
6416 if (!cfg->soft_breakpoints) {
6417 MonoInst *info_var = cfg->arch.seq_point_info_var;
6418 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6419 int dreg = ARMREG_LR;
6420
6421 if (info_var) {
6422 g_assert (info_var->opcode == OP_REGOFFSET);
6423 g_assert (arm_is_imm12 (info_var->inst_offset));
6424
6425 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6426 /* Load the trigger page addr */
6427 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6428 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6429 }
6430 }
6431
6432 if (cfg->arch.seq_point_ss_method_var) {
6433 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6434 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6435
6436 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6437 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6438
6439 if (cfg->compile_aot) {
6440 MonoInst *info_var = cfg->arch.seq_point_info_var;
6441 int dreg = ARMREG_LR;
6442
6443 g_assert (info_var->opcode == OP_REGOFFSET);
6444 g_assert (arm_is_imm12 (info_var->inst_offset));
6445
6446 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6447 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6448 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6449 } else {
6450 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6451 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6452
6453 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6454 ARM_B (code, 1);
6455 *(gpointer*)code = &single_step_tramp;
6456 code += 4;
6457 *(gpointer*)code = breakpoint_tramp;
6458 code += 4;
6459
6460 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6461 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6462 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6463 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6464 }
6465 }
6466
6467 cfg->code_len = code - cfg->native_code;
6468 g_assert (cfg->code_len < cfg->code_size);
6469 g_free (cinfo);
6470
6471 return code;
6472 }
6473
6474 void
6475 mono_arch_emit_epilog (MonoCompile *cfg)
6476 {
6477 MonoMethod *method = cfg->method;
6478 int pos, i, rot_amount;
6479 int max_epilog_size = 16 + 20*4;
6480 guint8 *code;
6481 CallInfo *cinfo;
6482
6483 if (cfg->method->save_lmf)
6484 max_epilog_size += 128;
6485
6486 if (mono_jit_trace_calls != NULL)
6487 max_epilog_size += 50;
6488
6489 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6490 max_epilog_size += 50;
6491
6492 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6493 cfg->code_size *= 2;
6494 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6495 cfg->stat_code_reallocs++;
6496 }
6497
6498 /*
6499 * Keep in sync with OP_JMP
6500 */
6501 code = cfg->native_code + cfg->code_len;
6502
6503 /* Save the uwind state which is needed by the out-of-line code */
6504 mono_emit_unwind_op_remember_state (cfg, code);
6505
6506 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6507 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6508 }
6509 pos = 0;
6510
6511 /* Load returned vtypes into registers if needed */
6512 cinfo = cfg->arch.cinfo;
6513 switch (cinfo->ret.storage) {
6514 case RegTypeStructByVal: {
6515 MonoInst *ins = cfg->ret;
6516
6517 if (cinfo->ret.nregs == 1) {
6518 if (arm_is_imm12 (ins->inst_offset)) {
6519 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6520 } else {
6521 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6522 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6523 }
6524 } else {
6525 for (i = 0; i < cinfo->ret.nregs; ++i) {
6526 int offset = ins->inst_offset + (i * 4);
6527 if (arm_is_imm12 (offset)) {
6528 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6529 } else {
6530 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6531 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6532 }
6533 }
6534 }
6535 break;
6536 }
6537 case RegTypeHFA: {
6538 MonoInst *ins = cfg->ret;
6539
6540 for (i = 0; i < cinfo->ret.nregs; ++i) {
6541 if (cinfo->ret.esize == 4)
6542 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6543 else
6544 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6545 }
6546 break;
6547 }
6548 default:
6549 break;
6550 }
6551
6552 if (method->save_lmf) {
6553 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6554 /* all but r0-r3, sp and pc */
6555 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6556 lmf_offset = pos;
6557
6558 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6559
6560 /* This points to r4 inside MonoLMF->iregs */
6561 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6562 reg = ARMREG_R4;
6563 regmask = 0x9ff0; /* restore lr to pc */
6564 /* Skip caller saved registers not used by the method */
6565 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6566 regmask &= ~(1 << reg);
6567 sp_adj += 4;
6568 reg ++;
6569 }
6570 if (iphone_abi)
6571 /* Restored later */
6572 regmask &= ~(1 << ARMREG_PC);
6573 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6574 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6575 for (i = 0; i < 16; i++) {
6576 if (regmask & (1 << i))
6577 nused_int_regs ++;
6578 }
6579 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6580 /* restore iregs */
6581 ARM_POP (code, regmask);
6582 if (iphone_abi) {
6583 for (i = 0; i < 16; i++) {
6584 if (regmask & (1 << i))
6585 mono_emit_unwind_op_same_value (cfg, code, i);
6586 }
6587 /* Restore saved r7, restore LR to PC */
6588 /* Skip lr from the lmf */
6589 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6590 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6591 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6592 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6593 }
6594 } else {
6595 int i, nused_int_regs = 0;
6596
6597 for (i = 0; i < 16; i++) {
6598 if (cfg->used_int_regs & (1 << i))
6599 nused_int_regs ++;
6600 }
6601
6602 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6603 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6604 } else {
6605 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6606 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6607 }
6608
6609 if (cfg->frame_reg != ARMREG_SP) {
6610 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6611 }
6612
6613 if (iphone_abi) {
6614 /* Restore saved gregs */
6615 if (cfg->used_int_regs) {
6616 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6617 ARM_POP (code, cfg->used_int_regs);
6618 for (i = 0; i < 16; i++) {
6619 if (cfg->used_int_regs & (1 << i))
6620 mono_emit_unwind_op_same_value (cfg, code, i);
6621 }
6622 }
6623 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6624 /* Restore saved r7, restore LR to PC */
6625 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6626 } else {
6627 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6628 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6629 }
6630 }
6631
6632 /* Restore the unwind state to be the same as before the epilog */
6633 mono_emit_unwind_op_restore_state (cfg, code);
6634
6635 cfg->code_len = code - cfg->native_code;
6636
6637 g_assert (cfg->code_len < cfg->code_size);
6638
6639 }
6640
6641 void
6642 mono_arch_emit_exceptions (MonoCompile *cfg)
6643 {
6644 MonoJumpInfo *patch_info;
6645 int i;
6646 guint8 *code;
6647 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6648 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6649 int max_epilog_size = 50;
6650
6651 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6652 exc_throw_pos [i] = NULL;
6653 exc_throw_found [i] = 0;
6654 }
6655
6656 /* count the number of exception infos */
6657
6658 /*
6659 * make sure we have enough space for exceptions
6660 */
6661 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6662 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6663 i = mini_exception_id_by_name (patch_info->data.target);
6664 if (!exc_throw_found [i]) {
6665 max_epilog_size += 32;
6666 exc_throw_found [i] = TRUE;
6667 }
6668 }
6669 }
6670
6671 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6672 cfg->code_size *= 2;
6673 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6674 cfg->stat_code_reallocs++;
6675 }
6676
6677 code = cfg->native_code + cfg->code_len;
6678
6679 /* add code to raise exceptions */
6680 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6681 switch (patch_info->type) {
6682 case MONO_PATCH_INFO_EXC: {
6683 MonoClass *exc_class;
6684 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6685
6686 i = mini_exception_id_by_name (patch_info->data.target);
6687 if (exc_throw_pos [i]) {
6688 arm_patch (ip, exc_throw_pos [i]);
6689 patch_info->type = MONO_PATCH_INFO_NONE;
6690 break;
6691 } else {
6692 exc_throw_pos [i] = code;
6693 }
6694 arm_patch (ip, code);
6695
6696 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6697
6698 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6699 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6700 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6701 patch_info->data.name = "mono_arch_throw_corlib_exception";
6702 patch_info->ip.i = code - cfg->native_code;
6703 ARM_BL (code, 0);
6704 cfg->thunk_area += THUNK_SIZE;
6705 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6706 code += 4;
6707 break;
6708 }
6709 default:
6710 /* do nothing */
6711 break;
6712 }
6713 }
6714
6715 cfg->code_len = code - cfg->native_code;
6716
6717 g_assert (cfg->code_len < cfg->code_size);
6718
6719 }
6720
6721 #endif /* #ifndef DISABLE_JIT */
6722
6723 void
6724 mono_arch_finish_init (void)
6725 {
6726 }
6727
6728 void
6729 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6730 {
6731 }
6732
6733 MonoInst*
6734 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6735 {
6736 /* FIXME: */
6737 return NULL;
6738 }
6739
6740 gboolean
6741 mono_arch_print_tree (MonoInst *tree, int arity)
6742 {
6743 return 0;
6744 }
6745
6746 #ifndef DISABLE_JIT
6747
6748 #endif
6749
6750 guint32
6751 mono_arch_get_patch_offset (guint8 *code)
6752 {
6753 /* OP_AOTCONST */
6754 return 8;
6755 }
6756
6757 void
6758 mono_arch_flush_register_windows (void)
6759 {
6760 }
6761
6762 MonoMethod*
6763 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6764 {
6765 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6766 }
6767
6768 MonoVTable*
6769 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6770 {
6771 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6772 }
6773
6774 GSList*
6775 mono_arch_get_cie_program (void)
6776 {
6777 GSList *l = NULL;
6778
6779 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6780
6781 return l;
6782 }
6783
6784 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6785 #define BASE_SIZE (6 * 4)
6786 #define BSEARCH_ENTRY_SIZE (4 * 4)
6787 #define CMP_SIZE (3 * 4)
6788 #define BRANCH_SIZE (1 * 4)
6789 #define CALL_SIZE (2 * 4)
6790 #define WMC_SIZE (8 * 4)
6791 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6792
6793 static arminstr_t *
6794 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6795 {
6796 guint32 delta = DISTANCE (target, code);
6797 delta -= 8;
6798 g_assert (delta >= 0 && delta <= 0xFFF);
6799 *target = *target | delta;
6800 *code = value;
6801 return code + 1;
6802 }
6803
6804 #ifdef ENABLE_WRONG_METHOD_CHECK
6805 static void
6806 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6807 {
6808 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6809 g_assert (0);
6810 }
6811 #endif
6812
6813 gpointer
6814 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6815 gpointer fail_tramp)
6816 {
6817 int size, i;
6818 arminstr_t *code, *start;
6819 gboolean large_offsets = FALSE;
6820 guint32 **constant_pool_starts;
6821 arminstr_t *vtable_target = NULL;
6822 int extra_space = 0;
6823 #ifdef ENABLE_WRONG_METHOD_CHECK
6824 char * cond;
6825 #endif
6826 GSList *unwind_ops;
6827
6828 size = BASE_SIZE;
6829 constant_pool_starts = g_new0 (guint32*, count);
6830
6831 for (i = 0; i < count; ++i) {
6832 MonoIMTCheckItem *item = imt_entries [i];
6833 if (item->is_equals) {
6834 gboolean fail_case = !item->check_target_idx && fail_tramp;
6835
6836 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6837 item->chunk_size += 32;
6838 large_offsets = TRUE;
6839 }
6840
6841 if (item->check_target_idx || fail_case) {
6842 if (!item->compare_done || fail_case)
6843 item->chunk_size += CMP_SIZE;
6844 item->chunk_size += BRANCH_SIZE;
6845 } else {
6846 #ifdef ENABLE_WRONG_METHOD_CHECK
6847 item->chunk_size += WMC_SIZE;
6848 #endif
6849 }
6850 if (fail_case) {
6851 item->chunk_size += 16;
6852 large_offsets = TRUE;
6853 }
6854 item->chunk_size += CALL_SIZE;
6855 } else {
6856 item->chunk_size += BSEARCH_ENTRY_SIZE;
6857 imt_entries [item->check_target_idx]->compare_done = TRUE;
6858 }
6859 size += item->chunk_size;
6860 }
6861
6862 if (large_offsets)
6863 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6864
6865 if (fail_tramp)
6866 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6867 else
6868 code = mono_domain_code_reserve (domain, size);
6869 start = code;
6870
6871 unwind_ops = mono_arch_get_cie_program ();
6872
6873 #ifdef DEBUG_IMT
6874 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6875 for (i = 0; i < count; ++i) {
6876 MonoIMTCheckItem *item = imt_entries [i];
6877 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6878 }
6879 #endif
6880
6881 if (large_offsets) {
6882 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6883 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6884 } else {
6885 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6886 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6887 }
6888 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6889 vtable_target = code;
6890 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6891 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6892
6893 for (i = 0; i < count; ++i) {
6894 MonoIMTCheckItem *item = imt_entries [i];
6895 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6896 gint32 vtable_offset;
6897
6898 item->code_target = (guint8*)code;
6899
6900 if (item->is_equals) {
6901 gboolean fail_case = !item->check_target_idx && fail_tramp;
6902
6903 if (item->check_target_idx || fail_case) {
6904 if (!item->compare_done || fail_case) {
6905 imt_method = code;
6906 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6907 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6908 }
6909 item->jmp_code = (guint8*)code;
6910 ARM_B_COND (code, ARMCOND_NE, 0);
6911 } else {
6912 /*Enable the commented code to assert on wrong method*/
6913 #ifdef ENABLE_WRONG_METHOD_CHECK
6914 imt_method = code;
6915 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6916 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6917 cond = code;
6918 ARM_B_COND (code, ARMCOND_EQ, 0);
6919
6920 /* Define this if your system is so bad that gdb is failing. */
6921 #ifdef BROKEN_DEV_ENV
6922 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6923 ARM_BL (code, 0);
6924 arm_patch (code - 1, mini_dump_bad_imt);
6925 #else
6926 ARM_DBRK (code);
6927 #endif
6928 arm_patch (cond, code);
6929 #endif
6930 }
6931
6932 if (item->has_target_code) {
6933 /* Load target address */
6934 target_code_ins = code;
6935 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6936 /* Save it to the fourth slot */
6937 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6938 /* Restore registers and branch */
6939 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6940
6941 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6942 } else {
6943 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6944 if (!arm_is_imm12 (vtable_offset)) {
6945 /*
6946 * We need to branch to a computed address but we don't have
6947 * a free register to store it, since IP must contain the
6948 * vtable address. So we push the two values to the stack, and
6949 * load them both using LDM.
6950 */
6951 /* Compute target address */
6952 vtable_offset_ins = code;
6953 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6954 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6955 /* Save it to the fourth slot */
6956 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6957 /* Restore registers and branch */
6958 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6959
6960 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6961 } else {
6962 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6963 if (large_offsets) {
6964 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6965 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6966 }
6967 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6968 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6969 }
6970 }
6971
6972 if (fail_case) {
6973 arm_patch (item->jmp_code, (guchar*)code);
6974
6975 target_code_ins = code;
6976 /* Load target address */
6977 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6978 /* Save it to the fourth slot */
6979 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6980 /* Restore registers and branch */
6981 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6982
6983 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6984 item->jmp_code = NULL;
6985 }
6986
6987 if (imt_method)
6988 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
6989
6990 /*must emit after unconditional branch*/
6991 if (vtable_target) {
6992 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
6993 item->chunk_size += 4;
6994 vtable_target = NULL;
6995 }
6996
6997 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
6998 constant_pool_starts [i] = code;
6999 if (extra_space) {
7000 code += extra_space;
7001 extra_space = 0;
7002 }
7003 } else {
7004 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7005 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7006
7007 item->jmp_code = (guint8*)code;
7008 ARM_B_COND (code, ARMCOND_HS, 0);
7009 ++extra_space;
7010 }
7011 }
7012
7013 for (i = 0; i < count; ++i) {
7014 MonoIMTCheckItem *item = imt_entries [i];
7015 if (item->jmp_code) {
7016 if (item->check_target_idx)
7017 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7018 }
7019 if (i > 0 && item->is_equals) {
7020 int j;
7021 arminstr_t *space_start = constant_pool_starts [i];
7022 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7023 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7024 }
7025 }
7026 }
7027
7028 #ifdef DEBUG_IMT
7029 {
7030 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7031 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7032 g_free (buff);
7033 }
7034 #endif
7035
7036 g_free (constant_pool_starts);
7037
7038 mono_arch_flush_icache ((guint8*)start, size);
7039 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7040 mono_stats.imt_trampolines_size += code - start;
7041
7042 g_assert (DISTANCE (start, code) <= size);
7043
7044 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7045
7046 return start;
7047 }
7048
7049 mgreg_t
7050 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7051 {
7052 return ctx->regs [reg];
7053 }
7054
7055 void
7056 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7057 {
7058 ctx->regs [reg] = val;
7059 }
7060
7061 /*
7062 * mono_arch_get_trampolines:
7063 *
7064 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7065 * for AOT.
7066 */
7067 GSList *
7068 mono_arch_get_trampolines (gboolean aot)
7069 {
7070 return mono_arm_get_exception_trampolines (aot);
7071 }
7072
7073 gpointer
7074 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7075 {
7076 gpointer *lr_loc;
7077 char *old_value;
7078 char *bp;
7079
7080 /*Load the spvar*/
7081 bp = MONO_CONTEXT_GET_BP (ctx);
7082 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7083
7084 old_value = *lr_loc;
7085 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7086 return old_value;
7087
7088 *lr_loc = new_value;
7089
7090 return old_value;
7091 }
7092
7093 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7094 /*
7095 * mono_arch_set_breakpoint:
7096 *
7097 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7098 * The location should contain code emitted by OP_SEQ_POINT.
7099 */
7100 void
7101 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7102 {
7103 guint8 *code = ip;
7104 guint32 native_offset = ip - (guint8*)ji->code_start;
7105 MonoDebugOptions *opt = mini_get_debug_options ();
7106
7107 if (ji->from_aot) {
7108 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7109
7110 if (!breakpoint_tramp)
7111 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7112
7113 g_assert (native_offset % 4 == 0);
7114 g_assert (info->bp_addrs [native_offset / 4] == 0);
7115 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7116 } else if (opt->soft_breakpoints) {
7117 code += 4;
7118 ARM_BLX_REG (code, ARMREG_LR);
7119 mono_arch_flush_icache (code - 4, 4);
7120 } else {
7121 int dreg = ARMREG_LR;
7122
7123 /* Read from another trigger page */
7124 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7125 ARM_B (code, 0);
7126 *(int*)code = (int)bp_trigger_page;
7127 code += 4;
7128 ARM_LDR_IMM (code, dreg, dreg, 0);
7129
7130 mono_arch_flush_icache (code - 16, 16);
7131
7132 #if 0
7133 /* This is currently implemented by emitting an SWI instruction, which
7134 * qemu/linux seems to convert to a SIGILL.
7135 */
7136 *(int*)code = (0xef << 24) | 8;
7137 code += 4;
7138 mono_arch_flush_icache (code - 4, 4);
7139 #endif
7140 }
7141 }
7142
7143 /*
7144 * mono_arch_clear_breakpoint:
7145 *
7146 * Clear the breakpoint at IP.
7147 */
7148 void
7149 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7150 {
7151 MonoDebugOptions *opt = mini_get_debug_options ();
7152 guint8 *code = ip;
7153 int i;
7154
7155 if (ji->from_aot) {
7156 guint32 native_offset = ip - (guint8*)ji->code_start;
7157 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7158
7159 if (!breakpoint_tramp)
7160 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7161
7162 g_assert (native_offset % 4 == 0);
7163 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7164 info->bp_addrs [native_offset / 4] = 0;
7165 } else if (opt->soft_breakpoints) {
7166 code += 4;
7167 ARM_NOP (code);
7168 mono_arch_flush_icache (code - 4, 4);
7169 } else {
7170 for (i = 0; i < 4; ++i)
7171 ARM_NOP (code);
7172
7173 mono_arch_flush_icache (ip, code - ip);
7174 }
7175 }
7176
7177 /*
7178 * mono_arch_start_single_stepping:
7179 *
7180 * Start single stepping.
7181 */
7182 void
7183 mono_arch_start_single_stepping (void)
7184 {
7185 if (ss_trigger_page)
7186 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7187 else
7188 single_step_tramp = mini_get_single_step_trampoline ();
7189 }
7190
7191 /*
7192 * mono_arch_stop_single_stepping:
7193 *
7194 * Stop single stepping.
7195 */
7196 void
7197 mono_arch_stop_single_stepping (void)
7198 {
7199 if (ss_trigger_page)
7200 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7201 else
7202 single_step_tramp = NULL;
7203 }
7204
7205 #if __APPLE__
7206 #define DBG_SIGNAL SIGBUS
7207 #else
7208 #define DBG_SIGNAL SIGSEGV
7209 #endif
7210
7211 /*
7212 * mono_arch_is_single_step_event:
7213 *
7214 * Return whenever the machine state in SIGCTX corresponds to a single
7215 * step event.
7216 */
7217 gboolean
7218 mono_arch_is_single_step_event (void *info, void *sigctx)
7219 {
7220 siginfo_t *sinfo = info;
7221
7222 if (!ss_trigger_page)
7223 return FALSE;
7224
7225 /* Sometimes the address is off by 4 */
7226 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7227 return TRUE;
7228 else
7229 return FALSE;
7230 }
7231
7232 /*
7233 * mono_arch_is_breakpoint_event:
7234 *
7235 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7236 */
7237 gboolean
7238 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7239 {
7240 siginfo_t *sinfo = info;
7241
7242 if (!ss_trigger_page)
7243 return FALSE;
7244
7245 if (sinfo->si_signo == DBG_SIGNAL) {
7246 /* Sometimes the address is off by 4 */
7247 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7248 return TRUE;
7249 else
7250 return FALSE;
7251 } else {
7252 return FALSE;
7253 }
7254 }
7255
7256 /*
7257 * mono_arch_skip_breakpoint:
7258 *
7259 * See mini-amd64.c for docs.
7260 */
7261 void
7262 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7263 {
7264 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7265 }
7266
7267 /*
7268 * mono_arch_skip_single_step:
7269 *
7270 * See mini-amd64.c for docs.
7271 */
7272 void
7273 mono_arch_skip_single_step (MonoContext *ctx)
7274 {
7275 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7276 }
7277
7278 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7279
7280 /*
7281 * mono_arch_get_seq_point_info:
7282 *
7283 * See mini-amd64.c for docs.
7284 */
7285 gpointer
7286 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7287 {
7288 SeqPointInfo *info;
7289 MonoJitInfo *ji;
7290
7291 // FIXME: Add a free function
7292
7293 mono_domain_lock (domain);
7294 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7295 code);
7296 mono_domain_unlock (domain);
7297
7298 if (!info) {
7299 ji = mono_jit_info_table_find (domain, (char*)code);
7300 g_assert (ji);
7301
7302 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7303
7304 info->ss_trigger_page = ss_trigger_page;
7305 info->bp_trigger_page = bp_trigger_page;
7306 info->ss_tramp_addr = &single_step_tramp;
7307
7308 mono_domain_lock (domain);
7309 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7310 code, info);
7311 mono_domain_unlock (domain);
7312 }
7313
7314 return info;
7315 }
7316
7317 void
7318 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7319 {
7320 ext->lmf.previous_lmf = prev_lmf;
7321 /* Mark that this is a MonoLMFExt */
7322 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7323 ext->lmf.sp = (gssize)ext;
7324 }
7325
7326 /*
7327 * mono_arch_set_target:
7328 *
7329 * Set the target architecture the JIT backend should generate code for, in the form
7330 * of a GNU target triplet. Only used in AOT mode.
7331 */
7332 void
7333 mono_arch_set_target (char *mtriple)
7334 {
7335 /* The GNU target triple format is not very well documented */
7336 if (strstr (mtriple, "armv7")) {
7337 v5_supported = TRUE;
7338 v6_supported = TRUE;
7339 v7_supported = TRUE;
7340 }
7341 if (strstr (mtriple, "armv6")) {
7342 v5_supported = TRUE;
7343 v6_supported = TRUE;
7344 }
7345 if (strstr (mtriple, "armv7s")) {
7346 v7s_supported = TRUE;
7347 }
7348 if (strstr (mtriple, "armv7k")) {
7349 v7k_supported = TRUE;
7350 }
7351 if (strstr (mtriple, "thumbv7s")) {
7352 v5_supported = TRUE;
7353 v6_supported = TRUE;
7354 v7_supported = TRUE;
7355 v7s_supported = TRUE;
7356 thumb_supported = TRUE;
7357 thumb2_supported = TRUE;
7358 }
7359 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7360 v5_supported = TRUE;
7361 v6_supported = TRUE;
7362 thumb_supported = TRUE;
7363 iphone_abi = TRUE;
7364 }
7365 if (strstr (mtriple, "gnueabi"))
7366 eabi_supported = TRUE;
7367 }
7368
7369 gboolean
7370 mono_arch_opcode_supported (int opcode)
7371 {
7372 switch (opcode) {
7373 case OP_ATOMIC_ADD_I4:
7374 case OP_ATOMIC_EXCHANGE_I4:
7375 case OP_ATOMIC_CAS_I4:
7376 case OP_ATOMIC_LOAD_I1:
7377 case OP_ATOMIC_LOAD_I2:
7378 case OP_ATOMIC_LOAD_I4:
7379 case OP_ATOMIC_LOAD_U1:
7380 case OP_ATOMIC_LOAD_U2:
7381 case OP_ATOMIC_LOAD_U4:
7382 case OP_ATOMIC_STORE_I1:
7383 case OP_ATOMIC_STORE_I2:
7384 case OP_ATOMIC_STORE_I4:
7385 case OP_ATOMIC_STORE_U1:
7386 case OP_ATOMIC_STORE_U2:
7387 case OP_ATOMIC_STORE_U4:
7388 return v7_supported;
7389 case OP_ATOMIC_LOAD_R4:
7390 case OP_ATOMIC_LOAD_R8:
7391 case OP_ATOMIC_STORE_R4:
7392 case OP_ATOMIC_STORE_R8:
7393 return v7_supported && IS_VFP;
7394 default:
7395 return FALSE;
7396 }
7397 }
7398
7399 CallInfo*
7400 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7401 {
7402 return get_call_info (mp, sig);
7403 }
7404
7405 gpointer
7406 mono_arch_get_get_tls_tramp (void)
7407 {
7408 return NULL;
7409 }
7410
7411 static guint8*
7412 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7413 {
7414 /* OP_AOTCONST */
7415 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7416 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7417 ARM_B (code, 0);
7418 *(gpointer*)code = NULL;
7419 code += 4;
7420 /* Load the value from the GOT */
7421 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7422 return code;
7423 }
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