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[interp] Fix interp logging (#17636)
[mono-project.git] / mono / mini / mini-arm.c
blob00c0be5fdfebb7501e472f909dd6a7f2b43fc493
1 /**
2 * \file
3 * ARM backend for the Mono code generator
4 *
5 * Authors:
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
8 *
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
13 */
14 #include "mini.h"
15 #include <string.h>
16
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
25 #include <mono/utils/unlocked.h>
26
27 #include "interp/interp.h"
28
29 #include "mini-arm.h"
30 #include "cpu-arm.h"
31 #include "ir-emit.h"
32 #include "debugger-agent.h"
33 #include "mini-gc.h"
34 #include "mini-runtime.h"
35 #include "aot-runtime.h"
36 #include "mono/arch/arm/arm-vfp-codegen.h"
37 #include "mono/utils/mono-tls-inline.h"
38
39 /* Sanity check: This makes no sense */
40 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
41 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
42 #endif
43
44 /*
45 * IS_SOFT_FLOAT: Is full software floating point used?
46 * IS_HARD_FLOAT: Is full hardware floating point used?
47 * IS_VFP: Is hardware floating point with software ABI used?
48 *
49 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
50 * IS_VFP may delegate to mono_arch_is_soft_float ().
51 */
52
53 #if defined(ARM_FPU_VFP_HARD)
54 #define IS_SOFT_FLOAT (FALSE)
55 #define IS_HARD_FLOAT (TRUE)
56 #define IS_VFP (TRUE)
57 #elif defined(ARM_FPU_NONE)
58 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
59 #define IS_HARD_FLOAT (FALSE)
60 #define IS_VFP (!mono_arch_is_soft_float ())
61 #else
62 #define IS_SOFT_FLOAT (FALSE)
63 #define IS_HARD_FLOAT (FALSE)
64 #define IS_VFP (TRUE)
65 #endif
66
67 #define THUNK_SIZE (3 * 4)
68
69 #if __APPLE__
70 G_BEGIN_DECLS
71 void sys_icache_invalidate (void *start, size_t len);
72 G_END_DECLS
73 #endif
74
75 /* This mutex protects architecture specific caches */
76 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
77 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
78 static mono_mutex_t mini_arch_mutex;
79
80 static gboolean v5_supported = FALSE;
81 static gboolean v6_supported = FALSE;
82 static gboolean v7_supported = FALSE;
83 static gboolean v7s_supported = FALSE;
84 static gboolean v7k_supported = FALSE;
85 static gboolean thumb_supported = FALSE;
86 static gboolean thumb2_supported = FALSE;
87 /*
88 * Whenever to use the ARM EABI
89 */
90 static gboolean eabi_supported = FALSE;
91
92 /*
93 * Whenever to use the iphone ABI extensions:
94 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
95 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
96 * This is required for debugging/profiling tools to work, but it has some overhead so it should
97 * only be turned on in debug builds.
98 */
99 static gboolean iphone_abi = FALSE;
100
101 /*
102 * The FPU we are generating code for. This is NOT runtime configurable right now,
103 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
104 */
105 static MonoArmFPU arm_fpu;
106
107 #if defined(ARM_FPU_VFP_HARD)
108 /*
109 * On armhf, d0-d7 are used for argument passing and d8-d15
110 * must be preserved across calls, which leaves us no room
111 * for scratch registers. So we use d14-d15 but back up their
112 * previous contents to a stack slot before using them - see
113 * mono_arm_emit_vfp_scratch_save/_restore ().
114 */
115 static int vfp_scratch1 = ARM_VFP_D14;
116 static int vfp_scratch2 = ARM_VFP_D15;
117 #else
118 /*
119 * On armel, d0-d7 do not need to be preserved, so we can
120 * freely make use of them as scratch registers.
121 */
122 static int vfp_scratch1 = ARM_VFP_D0;
123 static int vfp_scratch2 = ARM_VFP_D1;
124 #endif
125
126 static int i8_align;
127
128 static gpointer single_step_tramp, breakpoint_tramp;
129
130 /*
131 * The code generated for sequence points reads from this location, which is
132 * made read-only when single stepping is enabled.
133 */
134 static gpointer ss_trigger_page;
135
136 /* Enabled breakpoints read from this trigger page */
137 static gpointer bp_trigger_page;
138
139 /*
140 * TODO:
141 * floating point support: on ARM it is a mess, there are at least 3
142 * different setups, each of which binary incompat with the other.
143 * 1) FPA: old and ugly, but unfortunately what current distros use
144 * the double binary format has the two words swapped. 8 double registers.
145 * Implemented usually by kernel emulation.
146 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
147 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
148 * 3) VFP: the new and actually sensible and useful FP support. Implemented
149 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
150 *
151 * We do not care about FPA. We will support soft float and VFP.
152 */
153 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
154 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
155 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
156
157 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
158 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
159 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
160
161 //#define DEBUG_IMT 0
162
163 #ifndef DISABLE_JIT
164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165 #endif
166
167 static guint8*
168 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169
170 const char*
171 mono_arch_regname (int reg)
172 {
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 "arm_pc"
178 };
179 if (reg >= 0 && reg < 16)
180 return rnames [reg];
181 return "unknown";
182 }
183
184 const char*
185 mono_arch_fregname (int reg)
186 {
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 "arm_f30", "arm_f31"
195 };
196 if (reg >= 0 && reg < 32)
197 return rnames [reg];
198 return "unknown";
199 }
200
201
202 #ifndef DISABLE_JIT
203 static guint8*
204 emit_big_add_temp (guint8 *code, int dreg, int sreg, int imm, int temp)
205 {
206 int imm8, rot_amount;
207
208 g_assert (temp == ARMREG_IP || temp == ARMREG_LR);
209
210 if (imm == 0) {
211 if (sreg != dreg)
212 ARM_MOV_REG_REG (code, dreg, sreg);
213 } else if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
214 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
215 return code;
216 }
217 if (dreg == sreg) {
218 code = mono_arm_emit_load_imm (code, temp, imm);
219 ARM_ADD_REG_REG (code, dreg, sreg, temp);
220 } else {
221 code = mono_arm_emit_load_imm (code, dreg, imm);
222 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
223 }
224 return code;
225 }
226
227 static guint8*
228 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
229 {
230 return emit_big_add_temp (code, dreg, sreg, imm, ARMREG_IP);
231 }
232
233 static guint8*
234 emit_ldr_imm (guint8 *code, int dreg, int sreg, int imm)
235 {
236 if (!arm_is_imm12 (imm)) {
237 g_assert (dreg != sreg);
238 code = emit_big_add (code, dreg, sreg, imm);
239 ARM_LDR_IMM (code, dreg, dreg, 0);
240 } else {
241 ARM_LDR_IMM (code, dreg, sreg, imm);
242 }
243 return code;
244 }
245
246 /* If dreg == sreg, this clobbers IP */
247 static guint8*
248 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
249 {
250 int imm8, rot_amount;
251 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
252 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
253 return code;
254 }
255 if (dreg == sreg) {
256 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
257 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
258 } else {
259 code = mono_arm_emit_load_imm (code, dreg, imm);
260 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
261 }
262 return code;
263 }
264
265 static guint8*
266 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
267 {
268 /* we can use r0-r3, since this is called only for incoming args on the stack */
269 if (size > sizeof (target_mgreg_t) * 4) {
270 guint8 *start_loop;
271 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
272 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
273 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
274 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
275 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
276 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
277 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
278 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
279 ARM_B_COND (code, ARMCOND_NE, 0);
280 arm_patch (code - 4, start_loop);
281 return code;
282 }
283 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
284 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
285 while (size >= 4) {
286 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
287 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
288 doffset += 4;
289 soffset += 4;
290 size -= 4;
291 }
292 } else if (size) {
293 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
294 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
295 doffset = soffset = 0;
296 while (size >= 4) {
297 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
298 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
299 doffset += 4;
300 soffset += 4;
301 size -= 4;
302 }
303 }
304 g_assert (size == 0);
305 return code;
306 }
307
308 static guint8*
309 emit_jmp_reg (guint8 *code, int reg)
310 {
311 if (thumb_supported)
312 ARM_BX (code, reg);
313 else
314 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
315 return code;
316 }
317
318 static guint8*
319 emit_call_reg (guint8 *code, int reg)
320 {
321 if (v5_supported) {
322 ARM_BLX_REG (code, reg);
323 } else {
324 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
325 return emit_jmp_reg (code, reg);
326 }
327 return code;
328 }
329
330 static guint8*
331 emit_call_seq (MonoCompile *cfg, guint8 *code)
332 {
333 if (cfg->method->dynamic) {
334 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
335 ARM_B (code, 0);
336 *(gpointer*)code = NULL;
337 code += 4;
338 code = emit_call_reg (code, ARMREG_IP);
339 } else {
340 ARM_BL (code, 0);
341 }
342 cfg->thunk_area += THUNK_SIZE;
343 return code;
344 }
345
346 guint8*
347 mono_arm_patchable_b (guint8 *code, int cond)
348 {
349 ARM_B_COND (code, cond, 0);
350 return code;
351 }
352
353 guint8*
354 mono_arm_patchable_bl (guint8 *code, int cond)
355 {
356 ARM_BL_COND (code, cond, 0);
357 return code;
358 }
359
360 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(HOST_ANDROID) && !defined(MONO_CROSS_COMPILE)
361 #define HAVE_AEABI_READ_TP 1
362 #endif
363
364 #ifdef HAVE_AEABI_READ_TP
365 G_BEGIN_DECLS
366 gpointer __aeabi_read_tp (void);
367 G_END_DECLS
368 #endif
369
370 gboolean
371 mono_arch_have_fast_tls (void)
372 {
373 #ifdef HAVE_AEABI_READ_TP
374 static gboolean have_fast_tls = FALSE;
375 static gboolean inited = FALSE;
376
377 if (mini_debug_options.use_fallback_tls)
378 return FALSE;
379
380 if (inited)
381 return have_fast_tls;
382
383 if (v7_supported) {
384 gpointer tp1, tp2;
385
386 tp1 = __aeabi_read_tp ();
387 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
388
389 have_fast_tls = tp1 && tp1 == tp2;
390 }
391 inited = TRUE;
392 return have_fast_tls;
393 #else
394 return FALSE;
395 #endif
396 }
397
398 static guint8*
399 emit_tls_get (guint8 *code, int dreg, int tls_offset)
400 {
401 g_assert (v7_supported);
402 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
403 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
404 return code;
405 }
406
407 static guint8*
408 emit_tls_set (guint8 *code, int sreg, int tls_offset)
409 {
410 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
411 g_assert (v7_supported);
412 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
413 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
414 return code;
415 }
416
417 /*
418 * emit_save_lmf:
419 *
420 * Emit code to push an LMF structure on the LMF stack.
421 * On arm, this is intermixed with the initialization of other fields of the structure.
422 */
423 static guint8*
424 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
425 {
426 int i;
427
428 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
429 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
430 } else {
431 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
432 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_tls_get_lmf_addr_extern));
433 code = emit_call_seq (cfg, code);
434 }
435 /* we build the MonoLMF structure on the stack - see mini-arm.h */
436 /* lmf_offset is the offset from the previous stack pointer,
437 * alloc_size is the total stack space allocated, so the offset
438 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
439 * The pointer to the struct is put in r1 (new_lmf).
440 * ip is used as scratch
441 * The callee-saved registers are already in the MonoLMF structure
442 */
443 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
444 /* r0 is the result from mono_get_lmf_addr () */
445 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
446 /* new_lmf->previous_lmf = *lmf_addr */
447 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
448 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
449 /* *(lmf_addr) = r1 */
450 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
451 /* Skip method (only needed for trampoline LMF frames) */
452 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
453 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
454 /* save the current IP */
455 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
456 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
457
458 for (i = 0; i < MONO_ABI_SIZEOF (MonoLMF); i += sizeof (target_mgreg_t))
459 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
460
461 return code;
462 }
463
464 typedef struct {
465 gint32 vreg;
466 gint32 hreg;
467 } FloatArgData;
468
469 static guint8 *
470 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
471 {
472 GSList *list;
473
474 set_code_cursor (cfg, code);
475
476 for (list = inst->float_args; list; list = list->next) {
477 FloatArgData *fad = (FloatArgData*)list->data;
478 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
479 gboolean imm = arm_is_fpimm8 (var->inst_offset);
480
481 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
482 if (!imm)
483 *max_len += 20 + 4;
484
485 *max_len += 4;
486
487 code = realloc_code (cfg, *max_len);
488
489 if (!imm) {
490 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
491 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
492 } else
493 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
494
495 set_code_cursor (cfg, code);
496 *offset = code - cfg->native_code;
497 }
498
499 return code;
500 }
501
502 static guint8 *
503 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
504 {
505 MonoInst *inst;
506
507 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
508
509 inst = cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
510
511 if (IS_HARD_FLOAT) {
512 if (!arm_is_fpimm8 (inst->inst_offset)) {
513 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
514 ARM_FSTD (code, reg, ARMREG_LR, 0);
515 } else
516 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
517 }
518
519 return code;
520 }
521
522 static guint8 *
523 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
524 {
525 MonoInst *inst;
526
527 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
528
529 inst = cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
530
531 if (IS_HARD_FLOAT) {
532 if (!arm_is_fpimm8 (inst->inst_offset)) {
533 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
534 ARM_FLDD (code, reg, ARMREG_LR, 0);
535 } else
536 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
537 }
538
539 return code;
540 }
541
542 /*
543 * emit_restore_lmf:
544 *
545 * Emit code to pop an LMF structure from the LMF stack.
546 */
547 static guint8*
548 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
549 {
550 int basereg, offset;
551
552 if (lmf_offset < 32) {
553 basereg = cfg->frame_reg;
554 offset = lmf_offset;
555 } else {
556 basereg = ARMREG_R2;
557 offset = 0;
558 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
559 }
560
561 /* ip = previous_lmf */
562 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
563 /* lr = lmf_addr */
564 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
565 /* *(lmf_addr) = previous_lmf */
566 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
567
568 return code;
569 }
570
571 #endif /* #ifndef DISABLE_JIT */
572
573 /*
574 * mono_arch_get_argument_info:
575 * @csig: a method signature
576 * @param_count: the number of parameters to consider
577 * @arg_info: an array to store the result infos
578 *
579 * Gathers information on parameters such as size, alignment and
580 * padding. arg_info should be large enought to hold param_count + 1 entries.
581 *
582 * Returns the size of the activation frame.
583 */
584 int
585 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
586 {
587 int k, frame_size = 0;
588 guint32 size, align, pad;
589 int offset = 8;
590 MonoType *t;
591
592 t = mini_get_underlying_type (csig->ret);
593 if (MONO_TYPE_ISSTRUCT (t)) {
594 frame_size += sizeof (target_mgreg_t);
595 offset += 4;
596 }
597
598 arg_info [0].offset = offset;
599
600 if (csig->hasthis) {
601 frame_size += sizeof (target_mgreg_t);
602 offset += 4;
603 }
604
605 arg_info [0].size = frame_size;
606
607 for (k = 0; k < param_count; k++) {
608 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
609
610 /* ignore alignment for now */
611 align = 1;
612
613 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
614 arg_info [k].pad = pad;
615 frame_size += size;
616 arg_info [k + 1].pad = 0;
617 arg_info [k + 1].size = size;
618 offset += pad;
619 arg_info [k + 1].offset = offset;
620 offset += size;
621 }
622
623 align = MONO_ARCH_FRAME_ALIGNMENT;
624 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
625 arg_info [k].pad = pad;
626
627 return frame_size;
628 }
629
630 #define MAX_ARCH_DELEGATE_PARAMS 3
631
632 static guint8*
633 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
634 {
635 guint8 *code, *start;
636 GSList *unwind_ops = mono_arch_get_cie_program ();
637
638 if (has_target) {
639 start = code = mono_global_codeman_reserve (12);
640
641 /* Replace the this argument with the target */
642 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
643 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
644 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
645
646 g_assert ((code - start) <= 12);
647
648 mono_arch_flush_icache (start, 12);
649 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
650 } else {
651 int size, i;
652
653 size = 8 + param_count * 4;
654 start = code = mono_global_codeman_reserve (size);
655
656 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
657 /* slide down the arguments */
658 for (i = 0; i < param_count; ++i) {
659 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
660 }
661 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
662
663 g_assert ((code - start) <= size);
664
665 mono_arch_flush_icache (start, size);
666 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
667 }
668
669 if (has_target) {
670 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
671 } else {
672 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
673 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
674 g_free (name);
675 }
676
677 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
678
679 return start;
680 }
681
682 /*
683 * mono_arch_get_delegate_invoke_impls:
684 *
685 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
686 * trampolines.
687 */
688 GSList*
689 mono_arch_get_delegate_invoke_impls (void)
690 {
691 GSList *res = NULL;
692 MonoTrampInfo *info;
693 int i;
694
695 get_delegate_invoke_impl (&info, TRUE, 0);
696 res = g_slist_prepend (res, info);
697
698 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
699 get_delegate_invoke_impl (&info, FALSE, i);
700 res = g_slist_prepend (res, info);
701 }
702
703 return res;
704 }
705
706 gpointer
707 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
708 {
709 guint8 *code, *start;
710 MonoType *sig_ret;
711
712 /* FIXME: Support more cases */
713 sig_ret = mini_get_underlying_type (sig->ret);
714 if (MONO_TYPE_ISSTRUCT (sig_ret))
715 return NULL;
716
717 if (has_target) {
718 static guint8* cached = NULL;
719 mono_mini_arch_lock ();
720 if (cached) {
721 mono_mini_arch_unlock ();
722 return cached;
723 }
724
725 if (mono_ee_features.use_aot_trampolines) {
726 start = (guint8*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
727 } else {
728 MonoTrampInfo *info;
729 start = get_delegate_invoke_impl (&info, TRUE, 0);
730 mono_tramp_info_register (info, NULL);
731 }
732 cached = start;
733 mono_mini_arch_unlock ();
734 return cached;
735 } else {
736 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
737 int i;
738
739 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
740 return NULL;
741 for (i = 0; i < sig->param_count; ++i)
742 if (!mono_is_regsize_var (sig->params [i]))
743 return NULL;
744
745 mono_mini_arch_lock ();
746 code = cache [sig->param_count];
747 if (code) {
748 mono_mini_arch_unlock ();
749 return code;
750 }
751
752 if (mono_ee_features.use_aot_trampolines) {
753 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
754 start = (guint8*)mono_aot_get_trampoline (name);
755 g_free (name);
756 } else {
757 MonoTrampInfo *info;
758 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
759 mono_tramp_info_register (info, NULL);
760 }
761 cache [sig->param_count] = start;
762 mono_mini_arch_unlock ();
763 return start;
764 }
765
766 return NULL;
767 }
768
769 gpointer
770 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
771 {
772 return NULL;
773 }
774
775 gpointer
776 mono_arch_get_this_arg_from_call (host_mgreg_t *regs, guint8 *code)
777 {
778 return (gpointer)regs [ARMREG_R0];
779 }
780
781 /*
782 * Initialize the cpu to execute managed code.
783 */
784 void
785 mono_arch_cpu_init (void)
786 {
787 i8_align = MONO_ABI_ALIGNOF (gint64);
788 #ifdef MONO_CROSS_COMPILE
789 /* Need to set the alignment of i8 since it can different on the target */
790 #ifdef TARGET_ANDROID
791 /* linux gnueabi */
792 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
793 #endif
794 #endif
795 }
796
797 /*
798 * Initialize architecture specific code.
799 */
800 void
801 mono_arch_init (void)
802 {
803 char *cpu_arch;
804
805 #ifdef TARGET_WATCHOS
806 mini_debug_options.soft_breakpoints = TRUE;
807 #endif
808
809 mono_os_mutex_init_recursive (&mini_arch_mutex);
810 if (mini_debug_options.soft_breakpoints) {
811 if (!mono_aot_only)
812 breakpoint_tramp = mini_get_breakpoint_trampoline ();
813 } else {
814 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ, MONO_MEM_ACCOUNT_OTHER);
815 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ, MONO_MEM_ACCOUNT_OTHER);
816 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
817 }
818
819 #if defined(__ARM_EABI__)
820 eabi_supported = TRUE;
821 #endif
822
823 #if defined(ARM_FPU_VFP_HARD)
824 arm_fpu = MONO_ARM_FPU_VFP_HARD;
825 #else
826 arm_fpu = MONO_ARM_FPU_VFP;
827
828 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
829 /*
830 * If we're compiling with a soft float fallback and it
831 * turns out that no VFP unit is available, we need to
832 * switch to soft float. We don't do this for iOS, since
833 * iOS devices always have a VFP unit.
834 */
835 if (!mono_hwcap_arm_has_vfp)
836 arm_fpu = MONO_ARM_FPU_NONE;
837
838 /*
839 * This environment variable can be useful in testing
840 * environments to make sure the soft float fallback
841 * works. Most ARM devices have VFP units these days, so
842 * normally soft float code would not be exercised much.
843 */
844 char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
845
846 if (soft && !strncmp (soft, "1", 1))
847 arm_fpu = MONO_ARM_FPU_NONE;
848 g_free (soft);
849 #endif
850 #endif
851
852 v5_supported = mono_hwcap_arm_is_v5;
853 v6_supported = mono_hwcap_arm_is_v6;
854 v7_supported = mono_hwcap_arm_is_v7;
855
856 /*
857 * On weird devices, the hwcap code may fail to detect
858 * the ARM version. In that case, we can at least safely
859 * assume the version the runtime was compiled for.
860 */
861 #ifdef HAVE_ARMV5
862 v5_supported = TRUE;
863 #endif
864 #ifdef HAVE_ARMV6
865 v6_supported = TRUE;
866 #endif
867 #ifdef HAVE_ARMV7
868 v7_supported = TRUE;
869 #endif
870
871 #if defined(TARGET_IOS)
872 /* iOS is special-cased here because we don't yet
873 have a way to properly detect CPU features on it. */
874 thumb_supported = TRUE;
875 iphone_abi = TRUE;
876 #else
877 thumb_supported = mono_hwcap_arm_has_thumb;
878 thumb2_supported = mono_hwcap_arm_has_thumb2;
879 #endif
880
881 /* Format: armv(5|6|7[s])[-thumb[2]] */
882 cpu_arch = g_getenv ("MONO_CPU_ARCH");
883
884 /* Do this here so it overrides any detection. */
885 if (cpu_arch) {
886 if (strncmp (cpu_arch, "armv", 4) == 0) {
887 v5_supported = cpu_arch [4] >= '5';
888 v6_supported = cpu_arch [4] >= '6';
889 v7_supported = cpu_arch [4] >= '7';
890 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
891 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
892 }
893
894 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
895 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
896 g_free (cpu_arch);
897 }
898 }
899
900 /*
901 * Cleanup architecture specific code.
902 */
903 void
904 mono_arch_cleanup (void)
905 {
906 }
907
908 /*
909 * This function returns the optimizations supported on this cpu.
910 */
911 guint32
912 mono_arch_cpu_optimizations (guint32 *exclude_mask)
913 {
914 /* no arm-specific optimizations yet */
915 *exclude_mask = 0;
916 return 0;
917 }
918
919 /*
920 * This function test for all SIMD functions supported.
921 *
922 * Returns a bitmask corresponding to all supported versions.
923 *
924 */
925 guint32
926 mono_arch_cpu_enumerate_simd_versions (void)
927 {
928 /* SIMD is currently unimplemented */
929 return 0;
930 }
931
932 gboolean
933 mono_arm_is_hard_float (void)
934 {
935 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
936 }
937
938 #ifndef DISABLE_JIT
939
940 gboolean
941 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
942 {
943 if (v7s_supported || v7k_supported) {
944 switch (opcode) {
945 case OP_IDIV:
946 case OP_IREM:
947 case OP_IDIV_UN:
948 case OP_IREM_UN:
949 return FALSE;
950 default:
951 break;
952 }
953 }
954 return TRUE;
955 }
956
957 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
958 gboolean
959 mono_arch_is_soft_float (void)
960 {
961 return arm_fpu == MONO_ARM_FPU_NONE;
962 }
963 #endif
964
965 static gboolean
966 is_regsize_var (MonoType *t)
967 {
968 if (t->byref)
969 return TRUE;
970 t = mini_get_underlying_type (t);
971 switch (t->type) {
972 case MONO_TYPE_I4:
973 case MONO_TYPE_U4:
974 case MONO_TYPE_I:
975 case MONO_TYPE_U:
976 case MONO_TYPE_PTR:
977 case MONO_TYPE_FNPTR:
978 return TRUE;
979 case MONO_TYPE_OBJECT:
980 return TRUE;
981 case MONO_TYPE_GENERICINST:
982 if (!mono_type_generic_inst_is_valuetype (t))
983 return TRUE;
984 return FALSE;
985 case MONO_TYPE_VALUETYPE:
986 return FALSE;
987 }
988 return FALSE;
989 }
990
991 GList *
992 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
993 {
994 GList *vars = NULL;
995 int i;
996
997 for (i = 0; i < cfg->num_varinfo; i++) {
998 MonoInst *ins = cfg->varinfo [i];
999 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1000
1001 /* unused vars */
1002 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1003 continue;
1004
1005 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1006 continue;
1007
1008 /* we can only allocate 32 bit values */
1009 if (is_regsize_var (ins->inst_vtype)) {
1010 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1011 g_assert (i == vmv->idx);
1012 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1013 }
1014 }
1015
1016 return vars;
1017 }
1018
1019 GList *
1020 mono_arch_get_global_int_regs (MonoCompile *cfg)
1021 {
1022 GList *regs = NULL;
1023
1024 mono_arch_compute_omit_fp (cfg);
1025
1026 /*
1027 * FIXME: Interface calls might go through a static rgctx trampoline which
1028 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1029 * avoid using it.
1030 */
1031 if (cfg->flags & MONO_CFG_HAS_CALLS)
1032 cfg->uses_rgctx_reg = TRUE;
1033
1034 if (cfg->arch.omit_fp)
1035 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1036 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1037 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1038 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1039 if (iphone_abi)
1040 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1041 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1042 else
1043 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1044 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1045 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1046 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1047 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1048 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1049
1050 return regs;
1051 }
1052
1053 /*
1054 * mono_arch_regalloc_cost:
1055 *
1056 * Return the cost, in number of memory references, of the action of
1057 * allocating the variable VMV into a register during global register
1058 * allocation.
1059 */
1060 guint32
1061 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1062 {
1063 /* FIXME: */
1064 return 2;
1065 }
1066
1067 #endif /* #ifndef DISABLE_JIT */
1068
1069 void
1070 mono_arch_flush_icache (guint8 *code, gint size)
1071 {
1072 #if defined(MONO_CROSS_COMPILE)
1073 #elif __APPLE__
1074 sys_icache_invalidate (code, size);
1075 #else
1076 __builtin___clear_cache ((char*)code, (char*)code + size);
1077 #endif
1078 }
1079
1080 #define DEBUG(a)
1081
1082 static void inline
1083 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1084 {
1085 if (simple) {
1086 if (*gr > ARMREG_R3) {
1087 ainfo->size = 4;
1088 ainfo->offset = *stack_size;
1089 ainfo->reg = ARMREG_SP; /* in the caller */
1090 ainfo->storage = RegTypeBase;
1091 *stack_size += 4;
1092 } else {
1093 ainfo->storage = RegTypeGeneral;
1094 ainfo->reg = *gr;
1095 }
1096 } else {
1097 gboolean split;
1098
1099 if (eabi_supported)
1100 split = i8_align == 4;
1101 else
1102 split = TRUE;
1103
1104 ainfo->size = 8;
1105 if (*gr == ARMREG_R3 && split) {
1106 /* first word in r3 and the second on the stack */
1107 ainfo->offset = *stack_size;
1108 ainfo->reg = ARMREG_SP; /* in the caller */
1109 ainfo->storage = RegTypeBaseGen;
1110 *stack_size += 4;
1111 } else if (*gr >= ARMREG_R3) {
1112 if (eabi_supported) {
1113 /* darwin aligns longs to 4 byte only */
1114 if (i8_align == 8) {
1115 *stack_size += 7;
1116 *stack_size &= ~7;
1117 }
1118 }
1119 ainfo->offset = *stack_size;
1120 ainfo->reg = ARMREG_SP; /* in the caller */
1121 ainfo->storage = RegTypeBase;
1122 *stack_size += 8;
1123 } else {
1124 if (eabi_supported) {
1125 if (i8_align == 8 && ((*gr) & 1))
1126 (*gr) ++;
1127 }
1128 ainfo->storage = RegTypeIRegPair;
1129 ainfo->reg = *gr;
1130 }
1131 (*gr) ++;
1132 }
1133 (*gr) ++;
1134 }
1135
1136 static void inline
1137 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1138 {
1139 /*
1140 * If we're calling a function like this:
1141 *
1142 * void foo(float a, double b, float c)
1143 *
1144 * We pass a in s0 and b in d1. That leaves us
1145 * with s1 being unused. The armhf ABI recognizes
1146 * this and requires register assignment to then
1147 * use that for the next single-precision arg,
1148 * i.e. c in this example. So float_spare either
1149 * tells us which reg to use for the next single-
1150 * precision arg, or it's -1, meaning use *fpr.
1151 *
1152 * Note that even though most of the JIT speaks
1153 * double-precision, fpr represents single-
1154 * precision registers.
1155 *
1156 * See parts 5.5 and 6.1.2 of the AAPCS for how
1157 * this all works.
1158 */
1159
1160 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1161 ainfo->storage = RegTypeFP;
1162
1163 if (is_double) {
1164 /*
1165 * If we're passing a double-precision value
1166 * and *fpr is odd (e.g. it's s1, s3, ...)
1167 * we need to use the next even register. So
1168 * we mark the current *fpr as a spare that
1169 * can be used for the next single-precision
1170 * value.
1171 */
1172 if (*fpr % 2) {
1173 *float_spare = *fpr;
1174 (*fpr)++;
1175 }
1176
1177 /*
1178 * At this point, we have an even register
1179 * so we assign that and move along.
1180 */
1181 ainfo->reg = *fpr;
1182 *fpr += 2;
1183 } else if (*float_spare >= 0) {
1184 /*
1185 * We're passing a single-precision value
1186 * and it looks like a spare single-
1187 * precision register is available. Let's
1188 * use it.
1189 */
1190
1191 ainfo->reg = *float_spare;
1192 *float_spare = -1;
1193 } else {
1194 /*
1195 * If we hit this branch, we're passing a
1196 * single-precision value and we can simply
1197 * use the next available register.
1198 */
1199
1200 ainfo->reg = *fpr;
1201 (*fpr)++;
1202 }
1203 } else {
1204 /*
1205 * We've exhausted available floating point
1206 * regs, so pass the rest on the stack.
1207 */
1208
1209 if (is_double) {
1210 *stack_size += 7;
1211 *stack_size &= ~7;
1212 }
1213
1214 ainfo->offset = *stack_size;
1215 ainfo->reg = ARMREG_SP;
1216 ainfo->storage = RegTypeBase;
1217
1218 *stack_size += is_double ? 8 : 4;
1219 }
1220 }
1221
1222 static gboolean
1223 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1224 {
1225 MonoClass *klass;
1226 gpointer iter;
1227 MonoClassField *field;
1228 MonoType *ftype, *prev_ftype = NULL;
1229 int nfields = 0;
1230
1231 klass = mono_class_from_mono_type_internal (t);
1232 iter = NULL;
1233 while ((field = mono_class_get_fields_internal (klass, &iter))) {
1234 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1235 continue;
1236 ftype = mono_field_get_type_internal (field);
1237 ftype = mini_get_underlying_type (ftype);
1238
1239 if (MONO_TYPE_ISSTRUCT (ftype)) {
1240 int nested_nfields, nested_esize;
1241
1242 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1243 return FALSE;
1244 if (nested_esize == 4)
1245 ftype = m_class_get_byval_arg (mono_defaults.single_class);
1246 else
1247 ftype = m_class_get_byval_arg (mono_defaults.double_class);
1248 if (prev_ftype && prev_ftype->type != ftype->type)
1249 return FALSE;
1250 prev_ftype = ftype;
1251 nfields += nested_nfields;
1252 } else {
1253 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1254 return FALSE;
1255 if (prev_ftype && prev_ftype->type != ftype->type)
1256 return FALSE;
1257 prev_ftype = ftype;
1258 nfields ++;
1259 }
1260 }
1261 if (nfields == 0 || nfields > 4)
1262 return FALSE;
1263 *out_nfields = nfields;
1264 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1265 return TRUE;
1266 }
1267
1268 static CallInfo*
1269 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1270 {
1271 guint i, gr, fpr, pstart;
1272 gint float_spare;
1273 int n = sig->hasthis + sig->param_count;
1274 int nfields, esize;
1275 guint32 align;
1276 MonoType *t;
1277 guint32 stack_size = 0;
1278 CallInfo *cinfo;
1279 gboolean is_pinvoke = sig->pinvoke;
1280 gboolean vtype_retaddr = FALSE;
1281
1282 if (mp)
1283 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1284 else
1285 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1286
1287 cinfo->nargs = n;
1288 gr = ARMREG_R0;
1289 fpr = ARM_VFP_F0;
1290 float_spare = -1;
1291
1292 t = mini_get_underlying_type (sig->ret);
1293 switch (t->type) {
1294 case MONO_TYPE_I1:
1295 case MONO_TYPE_U1:
1296 case MONO_TYPE_I2:
1297 case MONO_TYPE_U2:
1298 case MONO_TYPE_I4:
1299 case MONO_TYPE_U4:
1300 case MONO_TYPE_I:
1301 case MONO_TYPE_U:
1302 case MONO_TYPE_PTR:
1303 case MONO_TYPE_FNPTR:
1304 case MONO_TYPE_OBJECT:
1305 cinfo->ret.storage = RegTypeGeneral;
1306 cinfo->ret.reg = ARMREG_R0;
1307 break;
1308 case MONO_TYPE_U8:
1309 case MONO_TYPE_I8:
1310 cinfo->ret.storage = RegTypeIRegPair;
1311 cinfo->ret.reg = ARMREG_R0;
1312 break;
1313 case MONO_TYPE_R4:
1314 case MONO_TYPE_R8:
1315 cinfo->ret.storage = RegTypeFP;
1316
1317 if (t->type == MONO_TYPE_R4)
1318 cinfo->ret.size = 4;
1319 else
1320 cinfo->ret.size = 8;
1321
1322 if (IS_HARD_FLOAT) {
1323 cinfo->ret.reg = ARM_VFP_F0;
1324 } else {
1325 cinfo->ret.reg = ARMREG_R0;
1326 }
1327 break;
1328 case MONO_TYPE_GENERICINST:
1329 if (!mono_type_generic_inst_is_valuetype (t)) {
1330 cinfo->ret.storage = RegTypeGeneral;
1331 cinfo->ret.reg = ARMREG_R0;
1332 break;
1333 }
1334 if (mini_is_gsharedvt_variable_type (t)) {
1335 cinfo->ret.storage = RegTypeStructByAddr;
1336 break;
1337 }
1338 /* Fall through */
1339 case MONO_TYPE_VALUETYPE:
1340 case MONO_TYPE_TYPEDBYREF:
1341 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1342 cinfo->ret.storage = RegTypeHFA;
1343 cinfo->ret.reg = 0;
1344 cinfo->ret.nregs = nfields;
1345 cinfo->ret.esize = esize;
1346 } else {
1347 if (is_pinvoke) {
1348 int native_size = mono_class_native_size (mono_class_from_mono_type_internal (t), &align);
1349 int max_size;
1350
1351 #ifdef TARGET_WATCHOS
1352 max_size = 16;
1353 #else
1354 max_size = 4;
1355 #endif
1356 if (native_size <= max_size) {
1357 cinfo->ret.storage = RegTypeStructByVal;
1358 cinfo->ret.struct_size = native_size;
1359 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1360 } else {
1361 cinfo->ret.storage = RegTypeStructByAddr;
1362 }
1363 } else {
1364 cinfo->ret.storage = RegTypeStructByAddr;
1365 }
1366 }
1367 break;
1368 case MONO_TYPE_VAR:
1369 case MONO_TYPE_MVAR:
1370 g_assert (mini_is_gsharedvt_type (t));
1371 cinfo->ret.storage = RegTypeStructByAddr;
1372 break;
1373 case MONO_TYPE_VOID:
1374 break;
1375 default:
1376 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1377 }
1378
1379 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1380
1381 pstart = 0;
1382 n = 0;
1383 /*
1384 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1385 * the first argument, allowing 'this' to be always passed in the first arg reg.
1386 * Also do this if the first argument is a reference type, since virtual calls
1387 * are sometimes made using calli without sig->hasthis set, like in the delegate
1388 * invoke wrappers.
1389 */
1390 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1391 if (sig->hasthis) {
1392 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1393 } else {
1394 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1395 pstart = 1;
1396 }
1397 n ++;
1398 cinfo->ret.reg = gr;
1399 gr ++;
1400 cinfo->vret_arg_index = 1;
1401 } else {
1402 /* this */
1403 if (sig->hasthis) {
1404 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1405 n ++;
1406 }
1407 if (vtype_retaddr) {
1408 cinfo->ret.reg = gr;
1409 gr ++;
1410 }
1411 }
1412
1413 DEBUG(g_print("params: %d\n", sig->param_count));
1414 for (i = pstart; i < sig->param_count; ++i) {
1415 ArgInfo *ainfo = &cinfo->args [n];
1416
1417 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1418 /* Prevent implicit arguments and sig_cookie from
1419 being passed in registers */
1420 gr = ARMREG_R3 + 1;
1421 fpr = ARM_VFP_F16;
1422 /* Emit the signature cookie just before the implicit arguments */
1423 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1424 }
1425 DEBUG(g_print("param %d: ", i));
1426 if (sig->params [i]->byref) {
1427 DEBUG(g_print("byref\n"));
1428 add_general (&gr, &stack_size, ainfo, TRUE);
1429 n++;
1430 continue;
1431 }
1432 t = mini_get_underlying_type (sig->params [i]);
1433 switch (t->type) {
1434 case MONO_TYPE_I1:
1435 cinfo->args [n].is_signed = 1;
1436 case MONO_TYPE_U1:
1437 cinfo->args [n].size = 1;
1438 add_general (&gr, &stack_size, ainfo, TRUE);
1439 break;
1440 case MONO_TYPE_I2:
1441 cinfo->args [n].is_signed = 1;
1442 case MONO_TYPE_U2:
1443 cinfo->args [n].size = 2;
1444 add_general (&gr, &stack_size, ainfo, TRUE);
1445 break;
1446 case MONO_TYPE_I4:
1447 case MONO_TYPE_U4:
1448 cinfo->args [n].size = 4;
1449 add_general (&gr, &stack_size, ainfo, TRUE);
1450 break;
1451 case MONO_TYPE_I:
1452 case MONO_TYPE_U:
1453 case MONO_TYPE_PTR:
1454 case MONO_TYPE_FNPTR:
1455 case MONO_TYPE_OBJECT:
1456 cinfo->args [n].size = sizeof (target_mgreg_t);
1457 add_general (&gr, &stack_size, ainfo, TRUE);
1458 break;
1459 case MONO_TYPE_GENERICINST:
1460 if (!mono_type_generic_inst_is_valuetype (t)) {
1461 cinfo->args [n].size = sizeof (target_mgreg_t);
1462 add_general (&gr, &stack_size, ainfo, TRUE);
1463 break;
1464 }
1465 if (mini_is_gsharedvt_variable_type (t)) {
1466 /* gsharedvt arguments are passed by ref */
1467 g_assert (mini_is_gsharedvt_type (t));
1468 add_general (&gr, &stack_size, ainfo, TRUE);
1469 switch (ainfo->storage) {
1470 case RegTypeGeneral:
1471 ainfo->storage = RegTypeGSharedVtInReg;
1472 break;
1473 case RegTypeBase:
1474 ainfo->storage = RegTypeGSharedVtOnStack;
1475 break;
1476 default:
1477 g_assert_not_reached ();
1478 }
1479 break;
1480 }
1481 /* Fall through */
1482 case MONO_TYPE_TYPEDBYREF:
1483 case MONO_TYPE_VALUETYPE: {
1484 gint size;
1485 int align_size;
1486 int nwords, nfields, esize;
1487 guint32 align;
1488
1489 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1490 if (fpr + nfields < ARM_VFP_F16) {
1491 ainfo->storage = RegTypeHFA;
1492 ainfo->reg = fpr;
1493 ainfo->nregs = nfields;
1494 ainfo->esize = esize;
1495 if (esize == 4)
1496 fpr += nfields;
1497 else
1498 fpr += nfields * 2;
1499 break;
1500 } else {
1501 fpr = ARM_VFP_F16;
1502 }
1503 }
1504
1505 if (t->type == MONO_TYPE_TYPEDBYREF) {
1506 size = MONO_ABI_SIZEOF (MonoTypedRef);
1507 align = sizeof (target_mgreg_t);
1508 } else {
1509 MonoClass *klass = mono_class_from_mono_type_internal (sig->params [i]);
1510 if (is_pinvoke)
1511 size = mono_class_native_size (klass, &align);
1512 else
1513 size = mini_type_stack_size_full (t, &align, FALSE);
1514 }
1515 DEBUG(g_print ("load %d bytes struct\n", size));
1516
1517 #ifdef TARGET_WATCHOS
1518 /* Watchos pass large structures by ref */
1519 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1520 if (sig->pinvoke && size > 16) {
1521 add_general (&gr, &stack_size, ainfo, TRUE);
1522 switch (ainfo->storage) {
1523 case RegTypeGeneral:
1524 ainfo->storage = RegTypeStructByAddr;
1525 break;
1526 case RegTypeBase:
1527 ainfo->storage = RegTypeStructByAddrOnStack;
1528 break;
1529 default:
1530 g_assert_not_reached ();
1531 break;
1532 }
1533 break;
1534 }
1535 #endif
1536
1537 align_size = size;
1538 nwords = 0;
1539 align_size += (sizeof (target_mgreg_t) - 1);
1540 align_size &= ~(sizeof (target_mgreg_t) - 1);
1541 nwords = (align_size + sizeof (target_mgreg_t) -1 ) / sizeof (target_mgreg_t);
1542 ainfo->storage = RegTypeStructByVal;
1543 ainfo->struct_size = size;
1544 ainfo->align = align;
1545
1546 if (eabi_supported) {
1547 if (align >= 8 && (gr & 1))
1548 gr ++;
1549 }
1550 if (gr > ARMREG_R3) {
1551 ainfo->size = 0;
1552 ainfo->vtsize = nwords;
1553 } else {
1554 int rest = ARMREG_R3 - gr + 1;
1555 int n_in_regs = rest >= nwords? nwords: rest;
1556
1557 ainfo->size = n_in_regs;
1558 ainfo->vtsize = nwords - n_in_regs;
1559 ainfo->reg = gr;
1560 gr += n_in_regs;
1561 nwords -= n_in_regs;
1562 }
1563 stack_size = ALIGN_TO (stack_size, align);
1564
1565 ainfo->offset = stack_size;
1566 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1567 stack_size += nwords * sizeof (target_mgreg_t);
1568 break;
1569 }
1570 case MONO_TYPE_U8:
1571 case MONO_TYPE_I8:
1572 ainfo->size = 8;
1573 add_general (&gr, &stack_size, ainfo, FALSE);
1574 break;
1575 case MONO_TYPE_R4:
1576 ainfo->size = 4;
1577
1578 if (IS_HARD_FLOAT)
1579 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1580 else
1581 add_general (&gr, &stack_size, ainfo, TRUE);
1582 break;
1583 case MONO_TYPE_R8:
1584 ainfo->size = 8;
1585
1586 if (IS_HARD_FLOAT)
1587 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1588 else
1589 add_general (&gr, &stack_size, ainfo, FALSE);
1590 break;
1591 case MONO_TYPE_VAR:
1592 case MONO_TYPE_MVAR:
1593 /* gsharedvt arguments are passed by ref */
1594 g_assert (mini_is_gsharedvt_type (t));
1595 add_general (&gr, &stack_size, ainfo, TRUE);
1596 switch (ainfo->storage) {
1597 case RegTypeGeneral:
1598 ainfo->storage = RegTypeGSharedVtInReg;
1599 break;
1600 case RegTypeBase:
1601 ainfo->storage = RegTypeGSharedVtOnStack;
1602 break;
1603 default:
1604 g_assert_not_reached ();
1605 }
1606 break;
1607 default:
1608 g_error ("Can't handle 0x%x", sig->params [i]->type);
1609 }
1610 n ++;
1611 }
1612
1613 /* Handle the case where there are no implicit arguments */
1614 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1615 /* Prevent implicit arguments and sig_cookie from
1616 being passed in registers */
1617 gr = ARMREG_R3 + 1;
1618 fpr = ARM_VFP_F16;
1619 /* Emit the signature cookie just before the implicit arguments */
1620 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1621 }
1622
1623 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1624 stack_size = ALIGN_TO (stack_size, MONO_ARCH_FRAME_ALIGNMENT);
1625
1626 cinfo->stack_usage = stack_size;
1627 return cinfo;
1628 }
1629
1630 /*
1631 * We need to create a temporary value if the argument is not stored in
1632 * a linear memory range in the ccontext (this normally happens for
1633 * value types if they are passed both by stack and regs).
1634 */
1635 static int
1636 arg_need_temp (ArgInfo *ainfo)
1637 {
1638 if (ainfo->storage == RegTypeStructByVal && ainfo->vtsize)
1639 return ainfo->struct_size;
1640 return 0;
1641 }
1642
1643 static gpointer
1644 arg_get_storage (CallContext *ccontext, ArgInfo *ainfo)
1645 {
1646 switch (ainfo->storage) {
1647 case RegTypeIRegPair:
1648 case RegTypeGeneral:
1649 case RegTypeStructByVal:
1650 return &ccontext->gregs [ainfo->reg];
1651 case RegTypeHFA:
1652 case RegTypeFP:
1653 return &ccontext->fregs [ainfo->reg];
1654 case RegTypeBase:
1655 return ccontext->stack + ainfo->offset;
1656 default:
1657 g_error ("Arg storage type not yet supported");
1658 }
1659 }
1660
1661 static void
1662 arg_get_val (CallContext *ccontext, ArgInfo *ainfo, gpointer dest)
1663 {
1664 int reg_size = ainfo->size * sizeof (host_mgreg_t);
1665 g_assert (arg_need_temp (ainfo));
1666 memcpy (dest, &ccontext->gregs [ainfo->reg], reg_size);
1667 memcpy ((host_mgreg_t*)dest + ainfo->size, ccontext->stack + ainfo->offset, ainfo->struct_size - reg_size);
1668 }
1669
1670 static void
1671 arg_set_val (CallContext *ccontext, ArgInfo *ainfo, gpointer src)
1672 {
1673 int reg_size = ainfo->size * sizeof (host_mgreg_t);
1674 g_assert (arg_need_temp (ainfo));
1675 memcpy (&ccontext->gregs [ainfo->reg], src, reg_size);
1676 memcpy (ccontext->stack + ainfo->offset, (host_mgreg_t*)src + ainfo->size, ainfo->struct_size - reg_size);
1677 }
1678
1679 /* Set arguments in the ccontext (for i2n entry) */
1680 void
1681 mono_arch_set_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1682 {
1683 const MonoEECallbacks *interp_cb = mini_get_interp_callbacks ();
1684 CallInfo *cinfo = get_call_info (NULL, sig);
1685 gpointer storage;
1686 ArgInfo *ainfo;
1687
1688 memset (ccontext, 0, sizeof (CallContext));
1689
1690 ccontext->stack_size = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1691 if (ccontext->stack_size)
1692 ccontext->stack = (guint8*)g_calloc (1, ccontext->stack_size);
1693
1694 if (sig->ret->type != MONO_TYPE_VOID) {
1695 ainfo = &cinfo->ret;
1696 if (ainfo->storage == RegTypeStructByAddr) {
1697 storage = interp_cb->frame_arg_to_storage ((MonoInterpFrameHandle)frame, sig, -1);
1698 ccontext->gregs [cinfo->ret.reg] = (host_mgreg_t)(gsize)storage;
1699 }
1700 }
1701
1702 g_assert (!sig->hasthis);
1703
1704 for (int i = 0; i < sig->param_count; i++) {
1705 ainfo = &cinfo->args [i];
1706 int temp_size = arg_need_temp (ainfo);
1707
1708 if (temp_size)
1709 storage = alloca (temp_size); // FIXME? alloca in a loop
1710 else
1711 storage = arg_get_storage (ccontext, ainfo);
1712
1713 interp_cb->frame_arg_to_data ((MonoInterpFrameHandle)frame, sig, i, storage);
1714 if (temp_size)
1715 arg_set_val (ccontext, ainfo, storage);
1716 }
1717
1718 g_free (cinfo);
1719 }
1720
1721 /* Set return value in the ccontext (for n2i return) */
1722 void
1723 mono_arch_set_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1724 {
1725 const MonoEECallbacks *interp_cb;
1726 CallInfo *cinfo;
1727 gpointer storage;
1728 ArgInfo *ainfo;
1729
1730 if (sig->ret->type == MONO_TYPE_VOID)
1731 return;
1732
1733 interp_cb = mini_get_interp_callbacks ();
1734 cinfo = get_call_info (NULL, sig);
1735 ainfo = &cinfo->ret;
1736
1737 if (ainfo->storage != RegTypeStructByAddr) {
1738 g_assert (!arg_need_temp (ainfo));
1739 storage = arg_get_storage (ccontext, ainfo);
1740 memset (ccontext, 0, sizeof (CallContext)); // FIXME
1741 interp_cb->frame_arg_to_data ((MonoInterpFrameHandle)frame, sig, -1, storage);
1742 }
1743
1744 g_free (cinfo);
1745 }
1746
1747 /* Gets the arguments from ccontext (for n2i entry) */
1748 void
1749 mono_arch_get_native_call_context_args (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1750 {
1751 const MonoEECallbacks *interp_cb = mini_get_interp_callbacks ();
1752 CallInfo *cinfo = get_call_info (NULL, sig);
1753 gpointer storage;
1754 ArgInfo *ainfo;
1755
1756 if (sig->ret->type != MONO_TYPE_VOID) {
1757 ainfo = &cinfo->ret;
1758 if (ainfo->storage == RegTypeStructByAddr) {
1759 storage = (gpointer)(gsize)ccontext->gregs [cinfo->ret.reg];
1760 interp_cb->frame_arg_set_storage ((MonoInterpFrameHandle)frame, sig, -1, storage);
1761 }
1762 }
1763
1764 for (int i = 0; i < sig->param_count + sig->hasthis; i++) {
1765 ainfo = &cinfo->args [i];
1766 int temp_size = arg_need_temp (ainfo);
1767
1768 if (temp_size) {
1769 storage = alloca (temp_size); // FIXME? alloca in a loop
1770 arg_get_val (ccontext, ainfo, storage);
1771 } else {
1772 storage = arg_get_storage (ccontext, ainfo);
1773 }
1774 interp_cb->data_to_frame_arg ((MonoInterpFrameHandle)frame, sig, i, storage);
1775 }
1776
1777 g_free (cinfo);
1778 }
1779
1780 /* Gets the return value from ccontext (for i2n exit) */
1781 void
1782 mono_arch_get_native_call_context_ret (CallContext *ccontext, gpointer frame, MonoMethodSignature *sig)
1783 {
1784 const MonoEECallbacks *interp_cb;
1785 CallInfo *cinfo;
1786 ArgInfo *ainfo;
1787 gpointer storage;
1788
1789 if (sig->ret->type == MONO_TYPE_VOID)
1790 return;
1791
1792 interp_cb = mini_get_interp_callbacks ();
1793 cinfo = get_call_info (NULL, sig);
1794 ainfo = &cinfo->ret;
1795
1796 if (ainfo->storage != RegTypeStructByAddr) {
1797 g_assert (!arg_need_temp (ainfo));
1798 storage = arg_get_storage (ccontext, ainfo);
1799 interp_cb->data_to_frame_arg ((MonoInterpFrameHandle)frame, sig, -1, storage);
1800 }
1801
1802 g_free (cinfo);
1803 }
1804
1805 #ifndef DISABLE_JIT
1806
1807 gboolean
1808 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
1809 {
1810 g_assert (caller_sig);
1811 g_assert (callee_sig);
1812
1813 CallInfo *caller_info = get_call_info (NULL, caller_sig);
1814 CallInfo *callee_info = get_call_info (NULL, callee_sig);
1815
1816 /*
1817 * Tailcalls with more callee stack usage than the caller cannot be supported, since
1818 * the extra stack space would be left on the stack after the tailcall.
1819 */
1820 gboolean res = IS_SUPPORTED_TAILCALL (callee_info->stack_usage <= caller_info->stack_usage)
1821 && IS_SUPPORTED_TAILCALL (caller_info->ret.storage == callee_info->ret.storage);
1822
1823 // FIXME The limit here is that moving the parameters requires addressing the parameters
1824 // with 12bit (4K) immediate offsets. - 4 for TAILCALL_REG/MEMBASE
1825 res &= IS_SUPPORTED_TAILCALL (callee_info->stack_usage < (4096 - 4));
1826 res &= IS_SUPPORTED_TAILCALL (caller_info->stack_usage < (4096 - 4));
1827
1828 g_free (caller_info);
1829 g_free (callee_info);
1830
1831 return res;
1832 }
1833
1834 static gboolean
1835 debug_omit_fp (void)
1836 {
1837 #if 0
1838 return mono_debug_count ();
1839 #else
1840 return TRUE;
1841 #endif
1842 }
1843
1844 /**
1845 * mono_arch_compute_omit_fp:
1846 * Determine whether the frame pointer can be eliminated.
1847 */
1848 static void
1849 mono_arch_compute_omit_fp (MonoCompile *cfg)
1850 {
1851 MonoMethodSignature *sig;
1852 MonoMethodHeader *header;
1853 int i, locals_size;
1854 CallInfo *cinfo;
1855
1856 if (cfg->arch.omit_fp_computed)
1857 return;
1858
1859 header = cfg->header;
1860
1861 sig = mono_method_signature_internal (cfg->method);
1862
1863 if (!cfg->arch.cinfo)
1864 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1865 cinfo = cfg->arch.cinfo;
1866
1867 /*
1868 * FIXME: Remove some of the restrictions.
1869 */
1870 cfg->arch.omit_fp = TRUE;
1871 cfg->arch.omit_fp_computed = TRUE;
1872
1873 if (cfg->disable_omit_fp)
1874 cfg->arch.omit_fp = FALSE;
1875 if (!debug_omit_fp ())
1876 cfg->arch.omit_fp = FALSE;
1877 /*
1878 if (cfg->method->save_lmf)
1879 cfg->arch.omit_fp = FALSE;
1880 */
1881 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1882 cfg->arch.omit_fp = FALSE;
1883 if (header->num_clauses)
1884 cfg->arch.omit_fp = FALSE;
1885 if (cfg->param_area)
1886 cfg->arch.omit_fp = FALSE;
1887 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1888 cfg->arch.omit_fp = FALSE;
1889 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1890 cfg->arch.omit_fp = FALSE;
1891 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1892 ArgInfo *ainfo = &cinfo->args [i];
1893
1894 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1895 /*
1896 * The stack offset can only be determined when the frame
1897 * size is known.
1898 */
1899 cfg->arch.omit_fp = FALSE;
1900 }
1901 }
1902
1903 locals_size = 0;
1904 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1905 MonoInst *ins = cfg->varinfo [i];
1906 int ialign;
1907
1908 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1909 }
1910 }
1911
1912 /*
1913 * Set var information according to the calling convention. arm version.
1914 * The locals var stuff should most likely be split in another method.
1915 */
1916 void
1917 mono_arch_allocate_vars (MonoCompile *cfg)
1918 {
1919 MonoMethodSignature *sig;
1920 MonoMethodHeader *header;
1921 MonoInst *ins;
1922 MonoType *sig_ret;
1923 int i, offset, size, align, curinst;
1924 CallInfo *cinfo;
1925 ArgInfo *ainfo;
1926 guint32 ualign;
1927
1928 sig = mono_method_signature_internal (cfg->method);
1929
1930 if (!cfg->arch.cinfo)
1931 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1932 cinfo = cfg->arch.cinfo;
1933 sig_ret = mini_get_underlying_type (sig->ret);
1934
1935 mono_arch_compute_omit_fp (cfg);
1936
1937 if (cfg->arch.omit_fp)
1938 cfg->frame_reg = ARMREG_SP;
1939 else
1940 cfg->frame_reg = ARMREG_FP;
1941
1942 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1943
1944 /* allow room for the vararg method args: void* and long/double */
1945 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1946 cfg->param_area = MAX (cfg->param_area, sizeof (target_mgreg_t)*8);
1947
1948 header = cfg->header;
1949
1950 /* See mono_arch_get_global_int_regs () */
1951 if (cfg->flags & MONO_CFG_HAS_CALLS)
1952 cfg->uses_rgctx_reg = TRUE;
1953
1954 if (cfg->frame_reg != ARMREG_SP)
1955 cfg->used_int_regs |= 1 << cfg->frame_reg;
1956
1957 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1958 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1959 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1960
1961 offset = 0;
1962 curinst = 0;
1963 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1964 if (sig_ret->type != MONO_TYPE_VOID) {
1965 cfg->ret->opcode = OP_REGVAR;
1966 cfg->ret->inst_c0 = ARMREG_R0;
1967 }
1968 }
1969 /* local vars are at a positive offset from the stack pointer */
1970 /*
1971 * also note that if the function uses alloca, we use FP
1972 * to point at the local variables.
1973 */
1974 offset = 0; /* linkage area */
1975 /* align the offset to 16 bytes: not sure this is needed here */
1976 //offset += 8 - 1;
1977 //offset &= ~(8 - 1);
1978
1979 /* add parameter area size for called functions */
1980 offset += cfg->param_area;
1981 offset += 8 - 1;
1982 offset &= ~(8 - 1);
1983 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1984 offset += 8;
1985
1986 /* allow room to save the return value */
1987 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1988 offset += 8;
1989
1990 switch (cinfo->ret.storage) {
1991 case RegTypeStructByVal:
1992 case RegTypeHFA:
1993 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1994 offset = ALIGN_TO (offset, 8);
1995 cfg->ret->opcode = OP_REGOFFSET;
1996 cfg->ret->inst_basereg = cfg->frame_reg;
1997 cfg->ret->inst_offset = offset;
1998 if (cinfo->ret.storage == RegTypeStructByVal)
1999 offset += cinfo->ret.nregs * sizeof (target_mgreg_t);
2000 else
2001 offset += 32;
2002 break;
2003 case RegTypeStructByAddr:
2004 ins = cfg->vret_addr;
2005 offset += sizeof (target_mgreg_t) - 1;
2006 offset &= ~(sizeof (target_mgreg_t) - 1);
2007 ins->inst_offset = offset;
2008 ins->opcode = OP_REGOFFSET;
2009 ins->inst_basereg = cfg->frame_reg;
2010 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2011 g_print ("vret_addr =");
2012 mono_print_ins (cfg->vret_addr);
2013 }
2014 offset += sizeof (target_mgreg_t);
2015 break;
2016 default:
2017 break;
2018 }
2019
2020 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2021 if (cfg->arch.seq_point_info_var) {
2022 MonoInst *ins;
2023
2024 ins = cfg->arch.seq_point_info_var;
2025
2026 size = 4;
2027 align = 4;
2028 offset += align - 1;
2029 offset &= ~(align - 1);
2030 ins->opcode = OP_REGOFFSET;
2031 ins->inst_basereg = cfg->frame_reg;
2032 ins->inst_offset = offset;
2033 offset += size;
2034 }
2035 if (cfg->arch.ss_trigger_page_var) {
2036 MonoInst *ins;
2037
2038 ins = cfg->arch.ss_trigger_page_var;
2039 size = 4;
2040 align = 4;
2041 offset += align - 1;
2042 offset &= ~(align - 1);
2043 ins->opcode = OP_REGOFFSET;
2044 ins->inst_basereg = cfg->frame_reg;
2045 ins->inst_offset = offset;
2046 offset += size;
2047 }
2048
2049 if (cfg->arch.seq_point_ss_method_var) {
2050 MonoInst *ins;
2051
2052 ins = cfg->arch.seq_point_ss_method_var;
2053 size = 4;
2054 align = 4;
2055 offset += align - 1;
2056 offset &= ~(align - 1);
2057 ins->opcode = OP_REGOFFSET;
2058 ins->inst_basereg = cfg->frame_reg;
2059 ins->inst_offset = offset;
2060 offset += size;
2061 }
2062 if (cfg->arch.seq_point_bp_method_var) {
2063 MonoInst *ins;
2064
2065 ins = cfg->arch.seq_point_bp_method_var;
2066 size = 4;
2067 align = 4;
2068 offset += align - 1;
2069 offset &= ~(align - 1);
2070 ins->opcode = OP_REGOFFSET;
2071 ins->inst_basereg = cfg->frame_reg;
2072 ins->inst_offset = offset;
2073 offset += size;
2074 }
2075
2076 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2077 /* Allocate a temporary used by the atomic ops */
2078 size = 4;
2079 align = 4;
2080
2081 /* Allocate a local slot to hold the sig cookie address */
2082 offset += align - 1;
2083 offset &= ~(align - 1);
2084 cfg->arch.atomic_tmp_offset = offset;
2085 offset += size;
2086 } else {
2087 cfg->arch.atomic_tmp_offset = -1;
2088 }
2089
2090 cfg->locals_min_stack_offset = offset;
2091
2092 curinst = cfg->locals_start;
2093 for (i = curinst; i < cfg->num_varinfo; ++i) {
2094 MonoType *t;
2095
2096 ins = cfg->varinfo [i];
2097 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2098 continue;
2099
2100 t = ins->inst_vtype;
2101 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2102 continue;
2103
2104 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2105 * pinvoke wrappers when they call functions returning structure */
2106 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2107 size = mono_class_native_size (mono_class_from_mono_type_internal (t), &ualign);
2108 align = ualign;
2109 }
2110 else
2111 size = mono_type_size (t, &align);
2112
2113 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2114 * since it loads/stores misaligned words, which don't do the right thing.
2115 */
2116 if (align < 4 && size >= 4)
2117 align = 4;
2118 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2119 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2120 offset += align - 1;
2121 offset &= ~(align - 1);
2122 ins->opcode = OP_REGOFFSET;
2123 ins->inst_offset = offset;
2124 ins->inst_basereg = cfg->frame_reg;
2125 offset += size;
2126 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2127 }
2128
2129 cfg->locals_max_stack_offset = offset;
2130
2131 curinst = 0;
2132 if (sig->hasthis) {
2133 ins = cfg->args [curinst];
2134 if (ins->opcode != OP_REGVAR) {
2135 ins->opcode = OP_REGOFFSET;
2136 ins->inst_basereg = cfg->frame_reg;
2137 offset += sizeof (target_mgreg_t) - 1;
2138 offset &= ~(sizeof (target_mgreg_t) - 1);
2139 ins->inst_offset = offset;
2140 offset += sizeof (target_mgreg_t);
2141 }
2142 curinst++;
2143 }
2144
2145 if (sig->call_convention == MONO_CALL_VARARG) {
2146 size = 4;
2147 align = 4;
2148
2149 /* Allocate a local slot to hold the sig cookie address */
2150 offset += align - 1;
2151 offset &= ~(align - 1);
2152 cfg->sig_cookie = offset;
2153 offset += size;
2154 }
2155
2156 for (i = 0; i < sig->param_count; ++i) {
2157 ainfo = cinfo->args + i;
2158
2159 ins = cfg->args [curinst];
2160
2161 switch (ainfo->storage) {
2162 case RegTypeHFA:
2163 offset = ALIGN_TO (offset, 8);
2164 ins->opcode = OP_REGOFFSET;
2165 ins->inst_basereg = cfg->frame_reg;
2166 /* These arguments are saved to the stack in the prolog */
2167 ins->inst_offset = offset;
2168 if (cfg->verbose_level >= 2)
2169 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2170 // FIXME:
2171 offset += 32;
2172 break;
2173 default:
2174 break;
2175 }
2176
2177 if (ins->opcode != OP_REGVAR) {
2178 ins->opcode = OP_REGOFFSET;
2179 ins->inst_basereg = cfg->frame_reg;
2180 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2181 align = ualign;
2182 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2183 * since it loads/stores misaligned words, which don't do the right thing.
2184 */
2185 if (align < 4 && size >= 4)
2186 align = 4;
2187 /* The code in the prolog () stores words when storing vtypes received in a register */
2188 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2189 align = 4;
2190 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2191 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2192 offset += align - 1;
2193 offset &= ~(align - 1);
2194 ins->inst_offset = offset;
2195 offset += size;
2196 }
2197 curinst++;
2198 }
2199
2200 /* align the offset to 8 bytes */
2201 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2202 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2203 offset += 8 - 1;
2204 offset &= ~(8 - 1);
2205
2206 /* change sign? */
2207 cfg->stack_offset = offset;
2208 }
2209
2210 void
2211 mono_arch_create_vars (MonoCompile *cfg)
2212 {
2213 MonoMethodSignature *sig;
2214 CallInfo *cinfo;
2215 int i;
2216
2217 sig = mono_method_signature_internal (cfg->method);
2218
2219 if (!cfg->arch.cinfo)
2220 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2221 cinfo = cfg->arch.cinfo;
2222
2223 if (IS_HARD_FLOAT) {
2224 for (i = 0; i < 2; i++) {
2225 MonoInst *inst = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
2226 inst->flags |= MONO_INST_VOLATILE;
2227
2228 cfg->arch.vfp_scratch_slots [i] = inst;
2229 }
2230 }
2231
2232 if (cinfo->ret.storage == RegTypeStructByVal)
2233 cfg->ret_var_is_local = TRUE;
2234
2235 if (cinfo->ret.storage == RegTypeStructByAddr) {
2236 cfg->vret_addr = mono_compile_create_var (cfg, mono_get_int_type (), OP_ARG);
2237 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2238 g_print ("vret_addr = ");
2239 mono_print_ins (cfg->vret_addr);
2240 }
2241 }
2242
2243 if (cfg->gen_sdb_seq_points) {
2244 if (cfg->compile_aot) {
2245 MonoInst *ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
2246 ins->flags |= MONO_INST_VOLATILE;
2247 cfg->arch.seq_point_info_var = ins;
2248
2249 if (!cfg->soft_breakpoints) {
2250 /* Allocate a separate variable for this to save 1 load per seq point */
2251 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
2252 ins->flags |= MONO_INST_VOLATILE;
2253 cfg->arch.ss_trigger_page_var = ins;
2254 }
2255 }
2256 if (cfg->soft_breakpoints) {
2257 MonoInst *ins;
2258
2259 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
2260 ins->flags |= MONO_INST_VOLATILE;
2261 cfg->arch.seq_point_ss_method_var = ins;
2262
2263 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
2264 ins->flags |= MONO_INST_VOLATILE;
2265 cfg->arch.seq_point_bp_method_var = ins;
2266 }
2267 }
2268 }
2269
2270 static void
2271 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2272 {
2273 MonoMethodSignature *tmp_sig;
2274 int sig_reg;
2275
2276 if (MONO_IS_TAILCALL_OPCODE (call))
2277 NOT_IMPLEMENTED;
2278
2279 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2280
2281 /*
2282 * mono_ArgIterator_Setup assumes the signature cookie is
2283 * passed first and all the arguments which were before it are
2284 * passed on the stack after the signature. So compensate by
2285 * passing a different signature.
2286 */
2287 tmp_sig = mono_metadata_signature_dup (call->signature);
2288 tmp_sig->param_count -= call->signature->sentinelpos;
2289 tmp_sig->sentinelpos = 0;
2290 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2291
2292 sig_reg = mono_alloc_ireg (cfg);
2293 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2294
2295 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2296 }
2297
2298 #ifdef ENABLE_LLVM
2299 LLVMCallInfo*
2300 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2301 {
2302 int i, n;
2303 CallInfo *cinfo;
2304 ArgInfo *ainfo;
2305 LLVMCallInfo *linfo;
2306
2307 n = sig->param_count + sig->hasthis;
2308
2309 cinfo = get_call_info (cfg->mempool, sig);
2310
2311 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2312
2313 /*
2314 * LLVM always uses the native ABI while we use our own ABI, the
2315 * only difference is the handling of vtypes:
2316 * - we only pass/receive them in registers in some cases, and only
2317 * in 1 or 2 integer registers.
2318 */
2319 switch (cinfo->ret.storage) {
2320 case RegTypeGeneral:
2321 case RegTypeNone:
2322 case RegTypeFP:
2323 case RegTypeIRegPair:
2324 break;
2325 case RegTypeStructByAddr:
2326 if (sig->pinvoke) {
2327 linfo->ret.storage = LLVMArgVtypeByRef;
2328 } else {
2329 /* Vtype returned using a hidden argument */
2330 linfo->ret.storage = LLVMArgVtypeRetAddr;
2331 linfo->vret_arg_index = cinfo->vret_arg_index;
2332 }
2333 break;
2334 #if TARGET_WATCHOS
2335 case RegTypeStructByVal:
2336 /* LLVM models this by returning an int array */
2337 linfo->ret.storage = LLVMArgAsIArgs;
2338 linfo->ret.nslots = cinfo->ret.nregs;
2339 break;
2340 #endif
2341 case RegTypeHFA:
2342 linfo->ret.storage = LLVMArgFpStruct;
2343 linfo->ret.nslots = cinfo->ret.nregs;
2344 linfo->ret.esize = cinfo->ret.esize;
2345 break;
2346 default:
2347 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2348 cfg->disable_llvm = TRUE;
2349 return linfo;
2350 }
2351
2352 for (i = 0; i < n; ++i) {
2353 LLVMArgInfo *lainfo = &linfo->args [i];
2354 ainfo = cinfo->args + i;
2355
2356 lainfo->storage = LLVMArgNone;
2357
2358 switch (ainfo->storage) {
2359 case RegTypeGeneral:
2360 case RegTypeIRegPair:
2361 case RegTypeBase:
2362 case RegTypeBaseGen:
2363 case RegTypeFP:
2364 lainfo->storage = LLVMArgNormal;
2365 break;
2366 case RegTypeStructByVal: {
2367 lainfo->storage = LLVMArgAsIArgs;
2368 int slotsize = eabi_supported && ainfo->align == 8 ? 8 : 4;
2369 lainfo->nslots = ALIGN_TO (ainfo->struct_size, slotsize) / slotsize;
2370 lainfo->esize = slotsize;
2371 break;
2372 }
2373 case RegTypeStructByAddr:
2374 case RegTypeStructByAddrOnStack:
2375 lainfo->storage = LLVMArgVtypeByRef;
2376 break;
2377 case RegTypeHFA: {
2378 int j;
2379
2380 lainfo->storage = LLVMArgAsFpArgs;
2381 lainfo->nslots = ainfo->nregs;
2382 lainfo->esize = ainfo->esize;
2383 for (j = 0; j < ainfo->nregs; ++j)
2384 lainfo->pair_storage [j] = LLVMArgInFPReg;
2385 break;
2386 }
2387 default:
2388 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2389 cfg->disable_llvm = TRUE;
2390 break;
2391 }
2392 }
2393
2394 return linfo;
2395 }
2396 #endif
2397
2398 void
2399 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2400 {
2401 MonoInst *in, *ins;
2402 MonoMethodSignature *sig;
2403 int i, n;
2404 CallInfo *cinfo;
2405
2406 sig = call->signature;
2407 n = sig->param_count + sig->hasthis;
2408
2409 cinfo = get_call_info (cfg->mempool, sig);
2410
2411 switch (cinfo->ret.storage) {
2412 case RegTypeStructByVal:
2413 case RegTypeHFA:
2414 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2415 /* The JIT will transform this into a normal call */
2416 call->vret_in_reg = TRUE;
2417 break;
2418 }
2419 if (MONO_IS_TAILCALL_OPCODE (call))
2420 break;
2421 /*
2422 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2423 * the location pointed to by it after call in emit_move_return_value ().
2424 */
2425 if (!cfg->arch.vret_addr_loc) {
2426 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
2427 /* Prevent it from being register allocated or optimized away */
2428 cfg->arch.vret_addr_loc->flags |= MONO_INST_VOLATILE;
2429 }
2430
2431 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->arch.vret_addr_loc->dreg, call->vret_var->dreg);
2432 break;
2433 case RegTypeStructByAddr: {
2434 MonoInst *vtarg;
2435 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2436 vtarg->sreg1 = call->vret_var->dreg;
2437 vtarg->dreg = mono_alloc_preg (cfg);
2438 MONO_ADD_INS (cfg->cbb, vtarg);
2439
2440 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2441 break;
2442 }
2443 default:
2444 break;
2445 }
2446
2447 for (i = 0; i < n; ++i) {
2448 ArgInfo *ainfo = cinfo->args + i;
2449 MonoType *t;
2450
2451 if (i >= sig->hasthis)
2452 t = sig->params [i - sig->hasthis];
2453 else
2454 t = mono_get_int_type ();
2455 t = mini_get_underlying_type (t);
2456
2457 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2458 /* Emit the signature cookie just before the implicit arguments */
2459 emit_sig_cookie (cfg, call, cinfo);
2460 }
2461
2462 in = call->args [i];
2463
2464 switch (ainfo->storage) {
2465 case RegTypeGeneral:
2466 case RegTypeIRegPair:
2467 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2468 MONO_INST_NEW (cfg, ins, OP_MOVE);
2469 ins->dreg = mono_alloc_ireg (cfg);
2470 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2471 MONO_ADD_INS (cfg->cbb, ins);
2472 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2473
2474 MONO_INST_NEW (cfg, ins, OP_MOVE);
2475 ins->dreg = mono_alloc_ireg (cfg);
2476 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2477 MONO_ADD_INS (cfg->cbb, ins);
2478 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2479 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2480 if (ainfo->size == 4) {
2481 if (IS_SOFT_FLOAT) {
2482 /* mono_emit_call_args () have already done the r8->r4 conversion */
2483 /* The converted value is in an int vreg */
2484 MONO_INST_NEW (cfg, ins, OP_MOVE);
2485 ins->dreg = mono_alloc_ireg (cfg);
2486 ins->sreg1 = in->dreg;
2487 MONO_ADD_INS (cfg->cbb, ins);
2488 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2489 } else {
2490 int creg;
2491
2492 cfg->param_area = MAX (cfg->param_area, 8);
2493 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2494 creg = mono_alloc_ireg (cfg);
2495 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2496 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2497 }
2498 } else {
2499 if (IS_SOFT_FLOAT) {
2500 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2501 ins->dreg = mono_alloc_ireg (cfg);
2502 ins->sreg1 = in->dreg;
2503 MONO_ADD_INS (cfg->cbb, ins);
2504 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2505
2506 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2507 ins->dreg = mono_alloc_ireg (cfg);
2508 ins->sreg1 = in->dreg;
2509 MONO_ADD_INS (cfg->cbb, ins);
2510 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2511 } else {
2512 int creg;
2513
2514 cfg->param_area = MAX (cfg->param_area, 8);
2515 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2516 creg = mono_alloc_ireg (cfg);
2517 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2518 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2519 creg = mono_alloc_ireg (cfg);
2520 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2521 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2522 }
2523 }
2524 cfg->flags |= MONO_CFG_HAS_FPOUT;
2525 } else {
2526 MONO_INST_NEW (cfg, ins, OP_MOVE);
2527 ins->dreg = mono_alloc_ireg (cfg);
2528 ins->sreg1 = in->dreg;
2529 MONO_ADD_INS (cfg->cbb, ins);
2530
2531 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2532 }
2533 break;
2534 case RegTypeStructByVal:
2535 case RegTypeGSharedVtInReg:
2536 case RegTypeGSharedVtOnStack:
2537 case RegTypeHFA:
2538 case RegTypeStructByAddr:
2539 case RegTypeStructByAddrOnStack:
2540 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2541 ins->opcode = OP_OUTARG_VT;
2542 ins->sreg1 = in->dreg;
2543 ins->klass = in->klass;
2544 ins->inst_p0 = call;
2545 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2546 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2547 mono_call_inst_add_outarg_vt (cfg, call, ins);
2548 MONO_ADD_INS (cfg->cbb, ins);
2549 break;
2550 case RegTypeBase:
2551 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2552 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2553 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2554 if (t->type == MONO_TYPE_R8) {
2555 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2556 } else {
2557 if (IS_SOFT_FLOAT)
2558 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2559 else
2560 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2561 }
2562 } else {
2563 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2564 }
2565 break;
2566 case RegTypeBaseGen:
2567 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2568 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2569 MONO_INST_NEW (cfg, ins, OP_MOVE);
2570 ins->dreg = mono_alloc_ireg (cfg);
2571 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2572 MONO_ADD_INS (cfg->cbb, ins);
2573 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2574 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2575 int creg;
2576
2577 /* This should work for soft-float as well */
2578
2579 cfg->param_area = MAX (cfg->param_area, 8);
2580 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2581 creg = mono_alloc_ireg (cfg);
2582 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2583 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2584 creg = mono_alloc_ireg (cfg);
2585 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2586 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2587 cfg->flags |= MONO_CFG_HAS_FPOUT;
2588 } else {
2589 g_assert_not_reached ();
2590 }
2591 break;
2592 case RegTypeFP: {
2593 int fdreg = mono_alloc_freg (cfg);
2594
2595 if (ainfo->size == 8) {
2596 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2597 ins->sreg1 = in->dreg;
2598 ins->dreg = fdreg;
2599 MONO_ADD_INS (cfg->cbb, ins);
2600
2601 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2602 } else {
2603 FloatArgData *fad;
2604
2605 /*
2606 * Mono's register allocator doesn't speak single-precision registers that
2607 * overlap double-precision registers (i.e. armhf). So we have to work around
2608 * the register allocator and load the value from memory manually.
2609 *
2610 * So we create a variable for the float argument and an instruction to store
2611 * the argument into the variable. We then store the list of these arguments
2612 * in call->float_args. This list is then used by emit_float_args later to
2613 * pass the arguments in the various call opcodes.
2614 *
2615 * This is not very nice, and we should really try to fix the allocator.
2616 */
2617
2618 MonoInst *float_arg = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.single_class), OP_LOCAL);
2619
2620 /* Make sure the instruction isn't seen as pointless and removed.
2621 */
2622 float_arg->flags |= MONO_INST_VOLATILE;
2623
2624 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2625
2626 /* We use the dreg to look up the instruction later. The hreg is used to
2627 * emit the instruction that loads the value into the FP reg.
2628 */
2629 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2630 fad->vreg = float_arg->dreg;
2631 fad->hreg = ainfo->reg;
2632
2633 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2634 }
2635
2636 call->used_iregs |= 1 << ainfo->reg;
2637 cfg->flags |= MONO_CFG_HAS_FPOUT;
2638 break;
2639 }
2640 default:
2641 g_assert_not_reached ();
2642 }
2643 }
2644
2645 /* Handle the case where there are no implicit arguments */
2646 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2647 emit_sig_cookie (cfg, call, cinfo);
2648
2649 call->call_info = cinfo;
2650 call->stack_usage = cinfo->stack_usage;
2651 }
2652
2653 static void
2654 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2655 {
2656 MonoInst *ins;
2657
2658 switch (storage) {
2659 case RegTypeFP:
2660 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2661 ins->dreg = mono_alloc_freg (cfg);
2662 ins->sreg1 = arg->dreg;
2663 MONO_ADD_INS (cfg->cbb, ins);
2664 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2665 break;
2666 default:
2667 g_assert_not_reached ();
2668 break;
2669 }
2670 }
2671
2672 void
2673 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2674 {
2675 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2676 MonoInst *load;
2677 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2678 int ovf_size = ainfo->vtsize;
2679 int doffset = ainfo->offset;
2680 int struct_size = ainfo->struct_size;
2681 int i, soffset, dreg, tmpreg;
2682
2683 switch (ainfo->storage) {
2684 case RegTypeGSharedVtInReg:
2685 case RegTypeStructByAddr:
2686 /* Pass by addr */
2687 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2688 break;
2689 case RegTypeGSharedVtOnStack:
2690 case RegTypeStructByAddrOnStack:
2691 /* Pass by addr on stack */
2692 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2693 break;
2694 case RegTypeHFA:
2695 for (i = 0; i < ainfo->nregs; ++i) {
2696 if (ainfo->esize == 4)
2697 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2698 else
2699 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2700 load->dreg = mono_alloc_freg (cfg);
2701 load->inst_basereg = src->dreg;
2702 load->inst_offset = i * ainfo->esize;
2703 MONO_ADD_INS (cfg->cbb, load);
2704
2705 if (ainfo->esize == 4) {
2706 FloatArgData *fad;
2707
2708 /* See RegTypeFP in mono_arch_emit_call () */
2709 MonoInst *float_arg = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.single_class), OP_LOCAL);
2710 float_arg->flags |= MONO_INST_VOLATILE;
2711 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2712
2713 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2714 fad->vreg = float_arg->dreg;
2715 fad->hreg = ainfo->reg + i;
2716
2717 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2718 } else {
2719 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2720 }
2721 }
2722 break;
2723 default:
2724 soffset = 0;
2725 for (i = 0; i < ainfo->size; ++i) {
2726 dreg = mono_alloc_ireg (cfg);
2727 switch (struct_size) {
2728 case 1:
2729 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2730 break;
2731 case 2:
2732 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2733 break;
2734 case 3:
2735 tmpreg = mono_alloc_ireg (cfg);
2736 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2737 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2738 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2739 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2740 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2741 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2742 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2743 break;
2744 default:
2745 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2746 break;
2747 }
2748 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2749 soffset += sizeof (target_mgreg_t);
2750 struct_size -= sizeof (target_mgreg_t);
2751 }
2752 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2753 if (ovf_size != 0)
2754 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (target_mgreg_t), struct_size), struct_size < 4 ? 1 : 4);
2755 break;
2756 }
2757 }
2758
2759 void
2760 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2761 {
2762 MonoType *ret = mini_get_underlying_type (mono_method_signature_internal (method)->ret);
2763
2764 if (!ret->byref) {
2765 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2766 MonoInst *ins;
2767
2768 if (COMPILE_LLVM (cfg)) {
2769 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2770 } else {
2771 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2772 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2773 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2774 MONO_ADD_INS (cfg->cbb, ins);
2775 }
2776 return;
2777 }
2778 switch (arm_fpu) {
2779 case MONO_ARM_FPU_NONE:
2780 if (ret->type == MONO_TYPE_R8) {
2781 MonoInst *ins;
2782
2783 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2784 ins->dreg = cfg->ret->dreg;
2785 ins->sreg1 = val->dreg;
2786 MONO_ADD_INS (cfg->cbb, ins);
2787 return;
2788 }
2789 if (ret->type == MONO_TYPE_R4) {
2790 /* Already converted to an int in method_to_ir () */
2791 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2792 return;
2793 }
2794 break;
2795 case MONO_ARM_FPU_VFP:
2796 case MONO_ARM_FPU_VFP_HARD:
2797 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2798 MonoInst *ins;
2799
2800 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2801 ins->dreg = cfg->ret->dreg;
2802 ins->sreg1 = val->dreg;
2803 MONO_ADD_INS (cfg->cbb, ins);
2804 return;
2805 }
2806 break;
2807 default:
2808 g_assert_not_reached ();
2809 }
2810 }
2811
2812 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2813 }
2814
2815 #endif /* #ifndef DISABLE_JIT */
2816
2817 gboolean
2818 mono_arch_is_inst_imm (int opcode, int imm_opcode, gint64 imm)
2819 {
2820 return TRUE;
2821 }
2822
2823 typedef struct {
2824 MonoMethodSignature *sig;
2825 CallInfo *cinfo;
2826 MonoType *rtype;
2827 MonoType **param_types;
2828 } ArchDynCallInfo;
2829
2830 static gboolean
2831 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2832 {
2833 int i;
2834
2835 switch (cinfo->ret.storage) {
2836 case RegTypeNone:
2837 case RegTypeGeneral:
2838 case RegTypeIRegPair:
2839 case RegTypeStructByAddr:
2840 break;
2841 case RegTypeFP:
2842 if (IS_VFP)
2843 break;
2844 else
2845 return FALSE;
2846 default:
2847 return FALSE;
2848 }
2849
2850 for (i = 0; i < cinfo->nargs; ++i) {
2851 ArgInfo *ainfo = &cinfo->args [i];
2852 int last_slot;
2853
2854 switch (ainfo->storage) {
2855 case RegTypeGeneral:
2856 case RegTypeIRegPair:
2857 case RegTypeBaseGen:
2858 case RegTypeFP:
2859 break;
2860 case RegTypeBase:
2861 break;
2862 case RegTypeStructByVal:
2863 if (ainfo->size == 0)
2864 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2865 else
2866 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2867 break;
2868 default:
2869 return FALSE;
2870 }
2871 }
2872
2873 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2874 for (i = 0; i < sig->param_count; ++i) {
2875 MonoType *t = sig->params [i];
2876
2877 if (t->byref)
2878 continue;
2879
2880 t = mini_get_underlying_type (t);
2881
2882 switch (t->type) {
2883 case MONO_TYPE_R4:
2884 case MONO_TYPE_R8:
2885 if (IS_SOFT_FLOAT)
2886 return FALSE;
2887 else
2888 break;
2889 /*
2890 case MONO_TYPE_I8:
2891 case MONO_TYPE_U8:
2892 return FALSE;
2893 */
2894 default:
2895 break;
2896 }
2897 }
2898
2899 return TRUE;
2900 }
2901
2902 MonoDynCallInfo*
2903 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2904 {
2905 ArchDynCallInfo *info;
2906 CallInfo *cinfo;
2907 int i;
2908
2909 cinfo = get_call_info (NULL, sig);
2910
2911 if (!dyn_call_supported (cinfo, sig)) {
2912 g_free (cinfo);
2913 return NULL;
2914 }
2915
2916 info = g_new0 (ArchDynCallInfo, 1);
2917 // FIXME: Preprocess the info to speed up start_dyn_call ()
2918 info->sig = sig;
2919 info->cinfo = cinfo;
2920 info->rtype = mini_get_underlying_type (sig->ret);
2921 info->param_types = g_new0 (MonoType*, sig->param_count);
2922 for (i = 0; i < sig->param_count; ++i)
2923 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2924
2925 return (MonoDynCallInfo*)info;
2926 }
2927
2928 void
2929 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2930 {
2931 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2932
2933 g_free (ainfo->cinfo);
2934 g_free (ainfo);
2935 }
2936
2937 int
2938 mono_arch_dyn_call_get_buf_size (MonoDynCallInfo *info)
2939 {
2940 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2941
2942 g_assert (ainfo->cinfo->stack_usage % MONO_ARCH_FRAME_ALIGNMENT == 0);
2943 return sizeof (DynCallArgs) + ainfo->cinfo->stack_usage;
2944 }
2945
2946 void
2947 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf)
2948 {
2949 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2950 CallInfo *cinfo = dinfo->cinfo;
2951 DynCallArgs *p = (DynCallArgs*)buf;
2952 int arg_index, greg, i, j, pindex;
2953 MonoMethodSignature *sig = dinfo->sig;
2954
2955 p->res = 0;
2956 p->ret = ret;
2957 p->has_fpregs = 0;
2958 p->n_stackargs = cinfo->stack_usage / sizeof (host_mgreg_t);
2959
2960 arg_index = 0;
2961 greg = 0;
2962 pindex = 0;
2963
2964 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2965 p->regs [greg ++] = (host_mgreg_t)(gsize)*(args [arg_index ++]);
2966 if (!sig->hasthis)
2967 pindex = 1;
2968 }
2969
2970 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2971 p->regs [greg ++] = (host_mgreg_t)(gsize)ret;
2972
2973 for (i = pindex; i < sig->param_count; i++) {
2974 MonoType *t = dinfo->param_types [i];
2975 gpointer *arg = args [arg_index ++];
2976 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2977 int slot = -1;
2978
2979 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2980 slot = ainfo->reg;
2981 } else if (ainfo->storage == RegTypeFP) {
2982 } else if (ainfo->storage == RegTypeBase) {
2983 slot = PARAM_REGS + (ainfo->offset / 4);
2984 } else if (ainfo->storage == RegTypeBaseGen) {
2985 /* slot + 1 is the first stack slot, so the code below will work */
2986 slot = 3;
2987 } else {
2988 g_assert_not_reached ();
2989 }
2990
2991 if (t->byref) {
2992 p->regs [slot] = (host_mgreg_t)(gsize)*arg;
2993 continue;
2994 }
2995
2996 switch (t->type) {
2997 case MONO_TYPE_OBJECT:
2998 case MONO_TYPE_PTR:
2999 case MONO_TYPE_I:
3000 case MONO_TYPE_U:
3001 p->regs [slot] = (host_mgreg_t)(gsize)*arg;
3002 break;
3003 case MONO_TYPE_U1:
3004 p->regs [slot] = *(guint8*)arg;
3005 break;
3006 case MONO_TYPE_I1:
3007 p->regs [slot] = *(gint8*)arg;
3008 break;
3009 case MONO_TYPE_I2:
3010 p->regs [slot] = *(gint16*)arg;
3011 break;
3012 case MONO_TYPE_U2:
3013 p->regs [slot] = *(guint16*)arg;
3014 break;
3015 case MONO_TYPE_I4:
3016 p->regs [slot] = *(gint32*)arg;
3017 break;
3018 case MONO_TYPE_U4:
3019 p->regs [slot] = *(guint32*)arg;
3020 break;
3021 case MONO_TYPE_I8:
3022 case MONO_TYPE_U8:
3023 p->regs [slot ++] = (host_mgreg_t)(gsize)arg [0];
3024 p->regs [slot] = (host_mgreg_t)(gsize)arg [1];
3025 break;
3026 case MONO_TYPE_R4:
3027 if (ainfo->storage == RegTypeFP) {
3028 float f = *(float*)arg;
3029 p->fpregs [ainfo->reg / 2] = *(double*)&f;
3030 p->has_fpregs = 1;
3031 } else {
3032 p->regs [slot] = *(host_mgreg_t*)arg;
3033 }
3034 break;
3035 case MONO_TYPE_R8:
3036 if (ainfo->storage == RegTypeFP) {
3037 p->fpregs [ainfo->reg / 2] = *(double*)arg;
3038 p->has_fpregs = 1;
3039 } else {
3040 p->regs [slot ++] = (host_mgreg_t)(gsize)arg [0];
3041 p->regs [slot] = (host_mgreg_t)(gsize)arg [1];
3042 }
3043 break;
3044 case MONO_TYPE_GENERICINST:
3045 if (MONO_TYPE_IS_REFERENCE (t)) {
3046 p->regs [slot] = (host_mgreg_t)(gsize)*arg;
3047 break;
3048 } else {
3049 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type_internal (t))) {
3050 MonoClass *klass = mono_class_from_mono_type_internal (t);
3051 guint8 *nullable_buf;
3052 int size;
3053
3054 size = mono_class_value_size (klass, NULL);
3055 nullable_buf = g_alloca (size);
3056 g_assert (nullable_buf);
3057
3058 /* The argument pointed to by arg is either a boxed vtype or null */
3059 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
3060
3061 arg = (gpointer*)nullable_buf;
3062 /* Fall though */
3063 } else {
3064 /* Fall though */
3065 }
3066 }
3067 case MONO_TYPE_VALUETYPE:
3068 g_assert (ainfo->storage == RegTypeStructByVal);
3069
3070 if (ainfo->size == 0)
3071 slot = PARAM_REGS + (ainfo->offset / 4);
3072 else
3073 slot = ainfo->reg;
3074
3075 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
3076 p->regs [slot ++] = ((host_mgreg_t*)arg) [j];
3077 break;
3078 default:
3079 g_assert_not_reached ();
3080 }
3081 }
3082 }
3083
3084 void
3085 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
3086 {
3087 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
3088 DynCallArgs *p = (DynCallArgs*)buf;
3089 MonoType *ptype = ainfo->rtype;
3090 guint8 *ret = p->ret;
3091 host_mgreg_t res = p->res;
3092 host_mgreg_t res2 = p->res2;
3093
3094 switch (ptype->type) {
3095 case MONO_TYPE_VOID:
3096 *(gpointer*)ret = NULL;
3097 break;
3098 case MONO_TYPE_OBJECT:
3099 case MONO_TYPE_I:
3100 case MONO_TYPE_U:
3101 case MONO_TYPE_PTR:
3102 *(gpointer*)ret = (gpointer)(gsize)res;
3103 break;
3104 case MONO_TYPE_I1:
3105 *(gint8*)ret = res;
3106 break;
3107 case MONO_TYPE_U1:
3108 *(guint8*)ret = res;
3109 break;
3110 case MONO_TYPE_I2:
3111 *(gint16*)ret = res;
3112 break;
3113 case MONO_TYPE_U2:
3114 *(guint16*)ret = res;
3115 break;
3116 case MONO_TYPE_I4:
3117 *(gint32*)ret = res;
3118 break;
3119 case MONO_TYPE_U4:
3120 *(guint32*)ret = res;
3121 break;
3122 case MONO_TYPE_I8:
3123 case MONO_TYPE_U8:
3124 /* This handles endianness as well */
3125 ((gint32*)ret) [0] = res;
3126 ((gint32*)ret) [1] = res2;
3127 break;
3128 case MONO_TYPE_GENERICINST:
3129 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3130 *(gpointer*)ret = (gpointer)res;
3131 break;
3132 } else {
3133 /* Fall though */
3134 }
3135 case MONO_TYPE_VALUETYPE:
3136 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3137 /* Nothing to do */
3138 break;
3139 case MONO_TYPE_R4:
3140 g_assert (IS_VFP);
3141 if (IS_HARD_FLOAT)
3142 *(float*)ret = *(float*)&p->fpregs [0];
3143 else
3144 *(float*)ret = *(float*)&res;
3145 break;
3146 case MONO_TYPE_R8: {
3147 host_mgreg_t regs [2];
3148
3149 g_assert (IS_VFP);
3150 if (IS_HARD_FLOAT) {
3151 *(double*)ret = p->fpregs [0];
3152 } else {
3153 regs [0] = res;
3154 regs [1] = res2;
3155
3156 *(double*)ret = *(double*)&regs;
3157 }
3158 break;
3159 }
3160 default:
3161 g_assert_not_reached ();
3162 }
3163 }
3164
3165 #ifndef DISABLE_JIT
3166
3167 /*
3168 * The immediate field for cond branches is big enough for all reasonable methods
3169 */
3170 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3171 if (0 && ins->inst_true_bb->native_offset) { \
3172 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3173 } else { \
3174 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3175 ARM_B_COND (code, (condcode), 0); \
3176 }
3177
3178 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3179
3180 /* emit an exception if condition is fail
3181 *
3182 * We assign the extra code used to throw the implicit exceptions
3183 * to cfg->bb_exit as far as the big branch handling is concerned
3184 */
3185 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3186 do { \
3187 mono_add_patch_info (cfg, code - cfg->native_code, \
3188 MONO_PATCH_INFO_EXC, exc_name); \
3189 ARM_BL_COND (code, (condcode), 0); \
3190 } while (0);
3191
3192 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3193
3194 void
3195 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3196 {
3197 }
3198
3199 void
3200 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3201 {
3202 MonoInst *ins, *n;
3203
3204 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3205 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3206
3207 switch (ins->opcode) {
3208 case OP_MUL_IMM:
3209 case OP_IMUL_IMM:
3210 /* Already done by an arch-independent pass */
3211 break;
3212 case OP_LOAD_MEMBASE:
3213 case OP_LOADI4_MEMBASE:
3214 /*
3215 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3216 * OP_LOAD_MEMBASE offset(basereg), reg
3217 */
3218 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3219 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3220 ins->inst_basereg == last_ins->inst_destbasereg &&
3221 ins->inst_offset == last_ins->inst_offset) {
3222 if (ins->dreg == last_ins->sreg1) {
3223 MONO_DELETE_INS (bb, ins);
3224 continue;
3225 } else {
3226 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3227 ins->opcode = OP_MOVE;
3228 ins->sreg1 = last_ins->sreg1;
3229 }
3230
3231 /*
3232 * Note: reg1 must be different from the basereg in the second load
3233 * OP_LOAD_MEMBASE offset(basereg), reg1
3234 * OP_LOAD_MEMBASE offset(basereg), reg2
3235 * -->
3236 * OP_LOAD_MEMBASE offset(basereg), reg1
3237 * OP_MOVE reg1, reg2
3238 */
3239 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3240 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3241 ins->inst_basereg != last_ins->dreg &&
3242 ins->inst_basereg == last_ins->inst_basereg &&
3243 ins->inst_offset == last_ins->inst_offset) {
3244
3245 if (ins->dreg == last_ins->dreg) {
3246 MONO_DELETE_INS (bb, ins);
3247 continue;
3248 } else {
3249 ins->opcode = OP_MOVE;
3250 ins->sreg1 = last_ins->dreg;
3251 }
3252
3253 //g_assert_not_reached ();
3254
3255 #if 0
3256 /*
3257 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3258 * OP_LOAD_MEMBASE offset(basereg), reg
3259 * -->
3260 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3261 * OP_ICONST reg, imm
3262 */
3263 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3264 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3265 ins->inst_basereg == last_ins->inst_destbasereg &&
3266 ins->inst_offset == last_ins->inst_offset) {
3267 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3268 ins->opcode = OP_ICONST;
3269 ins->inst_c0 = last_ins->inst_imm;
3270 g_assert_not_reached (); // check this rule
3271 #endif
3272 }
3273 break;
3274 case OP_LOADU1_MEMBASE:
3275 case OP_LOADI1_MEMBASE:
3276 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3277 ins->inst_basereg == last_ins->inst_destbasereg &&
3278 ins->inst_offset == last_ins->inst_offset) {
3279 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3280 ins->sreg1 = last_ins->sreg1;
3281 }
3282 break;
3283 case OP_LOADU2_MEMBASE:
3284 case OP_LOADI2_MEMBASE:
3285 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3286 ins->inst_basereg == last_ins->inst_destbasereg &&
3287 ins->inst_offset == last_ins->inst_offset) {
3288 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3289 ins->sreg1 = last_ins->sreg1;
3290 }
3291 break;
3292 case OP_MOVE:
3293 ins->opcode = OP_MOVE;
3294 /*
3295 * OP_MOVE reg, reg
3296 */
3297 if (ins->dreg == ins->sreg1) {
3298 MONO_DELETE_INS (bb, ins);
3299 continue;
3300 }
3301 /*
3302 * OP_MOVE sreg, dreg
3303 * OP_MOVE dreg, sreg
3304 */
3305 if (last_ins && last_ins->opcode == OP_MOVE &&
3306 ins->sreg1 == last_ins->dreg &&
3307 ins->dreg == last_ins->sreg1) {
3308 MONO_DELETE_INS (bb, ins);
3309 continue;
3310 }
3311 break;
3312 }
3313 }
3314 }
3315
3316 /*
3317 * the branch_cc_table should maintain the order of these
3318 * opcodes.
3319 case CEE_BEQ:
3320 case CEE_BGE:
3321 case CEE_BGT:
3322 case CEE_BLE:
3323 case CEE_BLT:
3324 case CEE_BNE_UN:
3325 case CEE_BGE_UN:
3326 case CEE_BGT_UN:
3327 case CEE_BLE_UN:
3328 case CEE_BLT_UN:
3329 */
3330 static const guchar
3331 branch_cc_table [] = {
3332 ARMCOND_EQ,
3333 ARMCOND_GE,
3334 ARMCOND_GT,
3335 ARMCOND_LE,
3336 ARMCOND_LT,
3337
3338 ARMCOND_NE,
3339 ARMCOND_HS,
3340 ARMCOND_HI,
3341 ARMCOND_LS,
3342 ARMCOND_LO
3343 };
3344
3345 #define ADD_NEW_INS(cfg,dest,op) do { \
3346 MONO_INST_NEW ((cfg), (dest), (op)); \
3347 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3348 } while (0)
3349
3350 static int
3351 map_to_reg_reg_op (int op)
3352 {
3353 switch (op) {
3354 case OP_ADD_IMM:
3355 return OP_IADD;
3356 case OP_SUB_IMM:
3357 return OP_ISUB;
3358 case OP_AND_IMM:
3359 return OP_IAND;
3360 case OP_COMPARE_IMM:
3361 return OP_COMPARE;
3362 case OP_ICOMPARE_IMM:
3363 return OP_ICOMPARE;
3364 case OP_ADDCC_IMM:
3365 return OP_ADDCC;
3366 case OP_ADC_IMM:
3367 return OP_ADC;
3368 case OP_SUBCC_IMM:
3369 return OP_SUBCC;
3370 case OP_SBB_IMM:
3371 return OP_SBB;
3372 case OP_OR_IMM:
3373 return OP_IOR;
3374 case OP_XOR_IMM:
3375 return OP_IXOR;
3376 case OP_LOAD_MEMBASE:
3377 return OP_LOAD_MEMINDEX;
3378 case OP_LOADI4_MEMBASE:
3379 return OP_LOADI4_MEMINDEX;
3380 case OP_LOADU4_MEMBASE:
3381 return OP_LOADU4_MEMINDEX;
3382 case OP_LOADU1_MEMBASE:
3383 return OP_LOADU1_MEMINDEX;
3384 case OP_LOADI2_MEMBASE:
3385 return OP_LOADI2_MEMINDEX;
3386 case OP_LOADU2_MEMBASE:
3387 return OP_LOADU2_MEMINDEX;
3388 case OP_LOADI1_MEMBASE:
3389 return OP_LOADI1_MEMINDEX;
3390 case OP_STOREI1_MEMBASE_REG:
3391 return OP_STOREI1_MEMINDEX;
3392 case OP_STOREI2_MEMBASE_REG:
3393 return OP_STOREI2_MEMINDEX;
3394 case OP_STOREI4_MEMBASE_REG:
3395 return OP_STOREI4_MEMINDEX;
3396 case OP_STORE_MEMBASE_REG:
3397 return OP_STORE_MEMINDEX;
3398 case OP_STORER4_MEMBASE_REG:
3399 return OP_STORER4_MEMINDEX;
3400 case OP_STORER8_MEMBASE_REG:
3401 return OP_STORER8_MEMINDEX;
3402 case OP_STORE_MEMBASE_IMM:
3403 return OP_STORE_MEMBASE_REG;
3404 case OP_STOREI1_MEMBASE_IMM:
3405 return OP_STOREI1_MEMBASE_REG;
3406 case OP_STOREI2_MEMBASE_IMM:
3407 return OP_STOREI2_MEMBASE_REG;
3408 case OP_STOREI4_MEMBASE_IMM:
3409 return OP_STOREI4_MEMBASE_REG;
3410 }
3411 g_assert_not_reached ();
3412 }
3413
3414 /*
3415 * Remove from the instruction list the instructions that can't be
3416 * represented with very simple instructions with no register
3417 * requirements.
3418 */
3419 void
3420 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3421 {
3422 MonoInst *ins, *temp, *last_ins = NULL;
3423 int rot_amount, imm8, low_imm;
3424
3425 MONO_BB_FOR_EACH_INS (bb, ins) {
3426 loop_start:
3427 switch (ins->opcode) {
3428 case OP_ADD_IMM:
3429 case OP_SUB_IMM:
3430 case OP_AND_IMM:
3431 case OP_COMPARE_IMM:
3432 case OP_ICOMPARE_IMM:
3433 case OP_ADDCC_IMM:
3434 case OP_ADC_IMM:
3435 case OP_SUBCC_IMM:
3436 case OP_SBB_IMM:
3437 case OP_OR_IMM:
3438 case OP_XOR_IMM:
3439 case OP_IADD_IMM:
3440 case OP_ISUB_IMM:
3441 case OP_IAND_IMM:
3442 case OP_IADC_IMM:
3443 case OP_ISBB_IMM:
3444 case OP_IOR_IMM:
3445 case OP_IXOR_IMM:
3446 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3447 int opcode2 = mono_op_imm_to_op (ins->opcode);
3448 ADD_NEW_INS (cfg, temp, OP_ICONST);
3449 temp->inst_c0 = ins->inst_imm;
3450 temp->dreg = mono_alloc_ireg (cfg);
3451 ins->sreg2 = temp->dreg;
3452 if (opcode2 == -1)
3453 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3454 ins->opcode = opcode2;
3455 }
3456 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3457 goto loop_start;
3458 else
3459 break;
3460 case OP_MUL_IMM:
3461 case OP_IMUL_IMM:
3462 if (ins->inst_imm == 1) {
3463 ins->opcode = OP_MOVE;
3464 break;
3465 }
3466 if (ins->inst_imm == 0) {
3467 ins->opcode = OP_ICONST;
3468 ins->inst_c0 = 0;
3469 break;
3470 }
3471 imm8 = mono_is_power_of_two (ins->inst_imm);
3472 if (imm8 > 0) {
3473 ins->opcode = OP_SHL_IMM;
3474 ins->inst_imm = imm8;
3475 break;
3476 }
3477 ADD_NEW_INS (cfg, temp, OP_ICONST);
3478 temp->inst_c0 = ins->inst_imm;
3479 temp->dreg = mono_alloc_ireg (cfg);
3480 ins->sreg2 = temp->dreg;
3481 ins->opcode = OP_IMUL;
3482 break;
3483 case OP_SBB:
3484 case OP_ISBB:
3485 case OP_SUBCC:
3486 case OP_ISUBCC: {
3487 int try_count = 2;
3488 MonoInst *current = ins;
3489
3490 /* may require a look-ahead of a couple instructions due to spilling */
3491 while (try_count-- && current->next) {
3492 if (current->next->opcode == OP_COND_EXC_C || current->next->opcode == OP_COND_EXC_IC) {
3493 /* ARM sets the C flag to 1 if there was _no_ overflow */
3494 current->next->opcode = OP_COND_EXC_NC;
3495 break;
3496 }
3497 current = current->next;
3498 }
3499 break;
3500 }
3501 case OP_IDIV_IMM:
3502 case OP_IDIV_UN_IMM:
3503 case OP_IREM_IMM:
3504 case OP_IREM_UN_IMM: {
3505 int opcode2 = mono_op_imm_to_op (ins->opcode);
3506 ADD_NEW_INS (cfg, temp, OP_ICONST);
3507 temp->inst_c0 = ins->inst_imm;
3508 temp->dreg = mono_alloc_ireg (cfg);
3509 ins->sreg2 = temp->dreg;
3510 if (opcode2 == -1)
3511 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3512 ins->opcode = opcode2;
3513 break;
3514 }
3515 case OP_LOCALLOC_IMM:
3516 ADD_NEW_INS (cfg, temp, OP_ICONST);
3517 temp->inst_c0 = ins->inst_imm;
3518 temp->dreg = mono_alloc_ireg (cfg);
3519 ins->sreg1 = temp->dreg;
3520 ins->opcode = OP_LOCALLOC;
3521 break;
3522 case OP_LOAD_MEMBASE:
3523 case OP_LOADI4_MEMBASE:
3524 case OP_LOADU4_MEMBASE:
3525 case OP_LOADU1_MEMBASE:
3526 /* we can do two things: load the immed in a register
3527 * and use an indexed load, or see if the immed can be
3528 * represented as an ad_imm + a load with a smaller offset
3529 * that fits. We just do the first for now, optimize later.
3530 */
3531 if (arm_is_imm12 (ins->inst_offset))
3532 break;
3533 ADD_NEW_INS (cfg, temp, OP_ICONST);
3534 temp->inst_c0 = ins->inst_offset;
3535 temp->dreg = mono_alloc_ireg (cfg);
3536 ins->sreg2 = temp->dreg;
3537 ins->opcode = map_to_reg_reg_op (ins->opcode);
3538 break;
3539 case OP_LOADI2_MEMBASE:
3540 case OP_LOADU2_MEMBASE:
3541 case OP_LOADI1_MEMBASE:
3542 if (arm_is_imm8 (ins->inst_offset))
3543 break;
3544 ADD_NEW_INS (cfg, temp, OP_ICONST);
3545 temp->inst_c0 = ins->inst_offset;
3546 temp->dreg = mono_alloc_ireg (cfg);
3547 ins->sreg2 = temp->dreg;
3548 ins->opcode = map_to_reg_reg_op (ins->opcode);
3549 break;
3550 case OP_LOADR4_MEMBASE:
3551 case OP_LOADR8_MEMBASE:
3552 if (arm_is_fpimm8 (ins->inst_offset))
3553 break;
3554 low_imm = ins->inst_offset & 0x1ff;
3555 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3556 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3557 temp->inst_imm = ins->inst_offset & ~0x1ff;
3558 temp->sreg1 = ins->inst_basereg;
3559 temp->dreg = mono_alloc_ireg (cfg);
3560 ins->inst_basereg = temp->dreg;
3561 ins->inst_offset = low_imm;
3562 } else {
3563 MonoInst *add_ins;
3564
3565 ADD_NEW_INS (cfg, temp, OP_ICONST);
3566 temp->inst_c0 = ins->inst_offset;
3567 temp->dreg = mono_alloc_ireg (cfg);
3568
3569 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3570 add_ins->sreg1 = ins->inst_basereg;
3571 add_ins->sreg2 = temp->dreg;
3572 add_ins->dreg = mono_alloc_ireg (cfg);
3573
3574 ins->inst_basereg = add_ins->dreg;
3575 ins->inst_offset = 0;
3576 }
3577 break;
3578 case OP_STORE_MEMBASE_REG:
3579 case OP_STOREI4_MEMBASE_REG:
3580 case OP_STOREI1_MEMBASE_REG:
3581 if (arm_is_imm12 (ins->inst_offset))
3582 break;
3583 ADD_NEW_INS (cfg, temp, OP_ICONST);
3584 temp->inst_c0 = ins->inst_offset;
3585 temp->dreg = mono_alloc_ireg (cfg);
3586 ins->sreg2 = temp->dreg;
3587 ins->opcode = map_to_reg_reg_op (ins->opcode);
3588 break;
3589 case OP_STOREI2_MEMBASE_REG:
3590 if (arm_is_imm8 (ins->inst_offset))
3591 break;
3592 ADD_NEW_INS (cfg, temp, OP_ICONST);
3593 temp->inst_c0 = ins->inst_offset;
3594 temp->dreg = mono_alloc_ireg (cfg);
3595 ins->sreg2 = temp->dreg;
3596 ins->opcode = map_to_reg_reg_op (ins->opcode);
3597 break;
3598 case OP_STORER4_MEMBASE_REG:
3599 case OP_STORER8_MEMBASE_REG:
3600 if (arm_is_fpimm8 (ins->inst_offset))
3601 break;
3602 low_imm = ins->inst_offset & 0x1ff;
3603 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3604 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3605 temp->inst_imm = ins->inst_offset & ~0x1ff;
3606 temp->sreg1 = ins->inst_destbasereg;
3607 temp->dreg = mono_alloc_ireg (cfg);
3608 ins->inst_destbasereg = temp->dreg;
3609 ins->inst_offset = low_imm;
3610 } else {
3611 MonoInst *add_ins;
3612
3613 ADD_NEW_INS (cfg, temp, OP_ICONST);
3614 temp->inst_c0 = ins->inst_offset;
3615 temp->dreg = mono_alloc_ireg (cfg);
3616
3617 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3618 add_ins->sreg1 = ins->inst_destbasereg;
3619 add_ins->sreg2 = temp->dreg;
3620 add_ins->dreg = mono_alloc_ireg (cfg);
3621
3622 ins->inst_destbasereg = add_ins->dreg;
3623 ins->inst_offset = 0;
3624 }
3625 break;
3626 case OP_STORE_MEMBASE_IMM:
3627 case OP_STOREI1_MEMBASE_IMM:
3628 case OP_STOREI2_MEMBASE_IMM:
3629 case OP_STOREI4_MEMBASE_IMM:
3630 ADD_NEW_INS (cfg, temp, OP_ICONST);
3631 temp->inst_c0 = ins->inst_imm;
3632 temp->dreg = mono_alloc_ireg (cfg);
3633 ins->sreg1 = temp->dreg;
3634 ins->opcode = map_to_reg_reg_op (ins->opcode);
3635 last_ins = temp;
3636 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3637 case OP_FCOMPARE:
3638 case OP_RCOMPARE: {
3639 gboolean swap = FALSE;
3640 int reg;
3641
3642 if (!ins->next) {
3643 /* Optimized away */
3644 NULLIFY_INS (ins);
3645 break;
3646 }
3647
3648 /* Some fp compares require swapped operands */
3649 switch (ins->next->opcode) {
3650 case OP_FBGT:
3651 ins->next->opcode = OP_FBLT;
3652 swap = TRUE;
3653 break;
3654 case OP_FBGT_UN:
3655 ins->next->opcode = OP_FBLT_UN;
3656 swap = TRUE;
3657 break;
3658 case OP_FBLE:
3659 ins->next->opcode = OP_FBGE;
3660 swap = TRUE;
3661 break;
3662 case OP_FBLE_UN:
3663 ins->next->opcode = OP_FBGE_UN;
3664 swap = TRUE;
3665 break;
3666 default:
3667 break;
3668 }
3669 if (swap) {
3670 reg = ins->sreg1;
3671 ins->sreg1 = ins->sreg2;
3672 ins->sreg2 = reg;
3673 }
3674 break;
3675 }
3676 }
3677
3678 last_ins = ins;
3679 }
3680 bb->last_ins = last_ins;
3681 bb->max_vreg = cfg->next_vreg;
3682 }
3683
3684 void
3685 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3686 {
3687 MonoInst *ins;
3688
3689 if (long_ins->opcode == OP_LNEG) {
3690 ins = long_ins;
3691 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3692 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3693 NULLIFY_INS (ins);
3694 }
3695 }
3696
3697 static guchar*
3698 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3699 {
3700 /* sreg is a float, dreg is an integer reg */
3701 if (IS_VFP) {
3702 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3703 if (is_signed)
3704 ARM_TOSIZD (code, vfp_scratch1, sreg);
3705 else
3706 ARM_TOUIZD (code, vfp_scratch1, sreg);
3707 ARM_FMRS (code, dreg, vfp_scratch1);
3708 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3709 }
3710 if (!is_signed) {
3711 if (size == 1)
3712 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3713 else if (size == 2) {
3714 ARM_SHL_IMM (code, dreg, dreg, 16);
3715 ARM_SHR_IMM (code, dreg, dreg, 16);
3716 }
3717 } else {
3718 if (size == 1) {
3719 ARM_SHL_IMM (code, dreg, dreg, 24);
3720 ARM_SAR_IMM (code, dreg, dreg, 24);
3721 } else if (size == 2) {
3722 ARM_SHL_IMM (code, dreg, dreg, 16);
3723 ARM_SAR_IMM (code, dreg, dreg, 16);
3724 }
3725 }
3726 return code;
3727 }
3728
3729 static guchar*
3730 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3731 {
3732 /* sreg is a float, dreg is an integer reg */
3733 g_assert (IS_VFP);
3734 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3735 if (is_signed)
3736 ARM_TOSIZS (code, vfp_scratch1, sreg);
3737 else
3738 ARM_TOUIZS (code, vfp_scratch1, sreg);
3739 ARM_FMRS (code, dreg, vfp_scratch1);
3740 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3741
3742 if (!is_signed) {
3743 if (size == 1)
3744 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3745 else if (size == 2) {
3746 ARM_SHL_IMM (code, dreg, dreg, 16);
3747 ARM_SHR_IMM (code, dreg, dreg, 16);
3748 }
3749 } else {
3750 if (size == 1) {
3751 ARM_SHL_IMM (code, dreg, dreg, 24);
3752 ARM_SAR_IMM (code, dreg, dreg, 24);
3753 } else if (size == 2) {
3754 ARM_SHL_IMM (code, dreg, dreg, 16);
3755 ARM_SAR_IMM (code, dreg, dreg, 16);
3756 }
3757 }
3758 return code;
3759 }
3760
3761 #endif /* #ifndef DISABLE_JIT */
3762
3763 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3764
3765 static void
3766 emit_thunk (guint8 *code, gconstpointer target)
3767 {
3768 guint8 *p = code;
3769
3770 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3771 if (thumb_supported)
3772 ARM_BX (code, ARMREG_IP);
3773 else
3774 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3775 *(guint32*)code = (guint32)(gsize)target;
3776 code += 4;
3777 mono_arch_flush_icache (p, code - p);
3778 }
3779
3780 static void
3781 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3782 {
3783 MonoJitInfo *ji = NULL;
3784 MonoThunkJitInfo *info;
3785 guint8 *thunks, *p;
3786 int thunks_size;
3787 guint8 *orig_target;
3788 guint8 *target_thunk;
3789
3790 if (!domain)
3791 domain = mono_domain_get ();
3792
3793 if (cfg) {
3794 /*
3795 * This can be called multiple times during JITting,
3796 * save the current position in cfg->arch to avoid
3797 * doing a O(n^2) search.
3798 */
3799 if (!cfg->arch.thunks) {
3800 cfg->arch.thunks = cfg->thunks;
3801 cfg->arch.thunks_size = cfg->thunk_area;
3802 }
3803 thunks = cfg->arch.thunks;
3804 thunks_size = cfg->arch.thunks_size;
3805 if (!thunks_size) {
3806 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3807 g_assert_not_reached ();
3808 }
3809
3810 g_assert (*(guint32*)thunks == 0);
3811 emit_thunk (thunks, target);
3812 arm_patch (code, thunks);
3813
3814 cfg->arch.thunks += THUNK_SIZE;
3815 cfg->arch.thunks_size -= THUNK_SIZE;
3816 } else {
3817 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3818 g_assert (ji);
3819 info = mono_jit_info_get_thunk_info (ji);
3820 g_assert (info);
3821
3822 thunks = (guint8*)ji->code_start + info->thunks_offset;
3823 thunks_size = info->thunks_size;
3824
3825 orig_target = mono_arch_get_call_target (code + 4);
3826
3827 mono_mini_arch_lock ();
3828
3829 target_thunk = NULL;
3830 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3831 /* The call already points to a thunk, because of trampolines etc. */
3832 target_thunk = orig_target;
3833 } else {
3834 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3835 if (((guint32*)p) [0] == 0) {
3836 /* Free entry */
3837 target_thunk = p;
3838 break;
3839 } else if (((guint32*)p) [2] == (guint32)(gsize)target) {
3840 /* Thunk already points to target */
3841 target_thunk = p;
3842 break;
3843 }
3844 }
3845 }
3846
3847 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3848
3849 if (!target_thunk) {
3850 mono_mini_arch_unlock ();
3851 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3852 g_assert_not_reached ();
3853 }
3854
3855 emit_thunk (target_thunk, target);
3856 arm_patch (code, target_thunk);
3857 mono_arch_flush_icache (code, 4);
3858
3859 mono_mini_arch_unlock ();
3860 }
3861 }
3862
3863 static void
3864 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3865 {
3866 guint32 *code32 = (guint32*)code;
3867 guint32 ins = *code32;
3868 guint32 prim = (ins >> 25) & 7;
3869 guint32 tval = GPOINTER_TO_UINT (target);
3870
3871 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3872 if (prim == 5) { /* 101b */
3873 /* the diff starts 8 bytes from the branch opcode */
3874 gint diff = target - code - 8;
3875 gint tbits;
3876 gint tmask = 0xffffffff;
3877 if (tval & 1) { /* entering thumb mode */
3878 diff = target - 1 - code - 8;
3879 g_assert (thumb_supported);
3880 tbits = 0xf << 28; /* bl->blx bit pattern */
3881 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3882 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3883 if (diff & 2) {
3884 tbits |= 1 << 24;
3885 }
3886 tmask = ~(1 << 24); /* clear the link bit */
3887 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3888 } else {
3889 tbits = 0;
3890 }
3891 if (diff >= 0) {
3892 if (diff <= 33554431) {
3893 diff >>= 2;
3894 ins = (ins & 0xff000000) | diff;
3895 ins &= tmask;
3896 *code32 = ins | tbits;
3897 return;
3898 }
3899 } else {
3900 /* diff between 0 and -33554432 */
3901 if (diff >= -33554432) {
3902 diff >>= 2;
3903 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3904 ins &= tmask;
3905 *code32 = ins | tbits;
3906 return;
3907 }
3908 }
3909
3910 handle_thunk (cfg, domain, code, target);
3911 return;
3912 }
3913
3914 /*
3915 * The alternative call sequences looks like this:
3916 *
3917 * ldr ip, [pc] // loads the address constant
3918 * b 1f // jumps around the constant
3919 * address constant embedded in the code
3920 * 1f:
3921 * mov lr, pc
3922 * mov pc, ip
3923 *
3924 * There are two cases for patching:
3925 * a) at the end of method emission: in this case code points to the start
3926 * of the call sequence
3927 * b) during runtime patching of the call site: in this case code points
3928 * to the mov pc, ip instruction
3929 *
3930 * We have to handle also the thunk jump code sequence:
3931 *
3932 * ldr ip, [pc]
3933 * mov pc, ip
3934 * address constant // execution never reaches here
3935 */
3936 if ((ins & 0x0ffffff0) == 0x12fff10) {
3937 /* Branch and exchange: the address is constructed in a reg
3938 * We can patch BX when the code sequence is the following:
3939 * ldr ip, [pc, #0] ; 0x8
3940 * b 0xc
3941 * .word code_ptr
3942 * mov lr, pc
3943 * bx ips
3944 * */
3945 guint32 ccode [4];
3946 guint8 *emit = (guint8*)ccode;
3947 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3948 ARM_B (emit, 0);
3949 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3950 ARM_BX (emit, ARMREG_IP);
3951
3952 /*patching from magic trampoline*/
3953 if (ins == ccode [3]) {
3954 g_assert (code32 [-4] == ccode [0]);
3955 g_assert (code32 [-3] == ccode [1]);
3956 g_assert (code32 [-1] == ccode [2]);
3957 code32 [-2] = (guint32)(gsize)target;
3958 return;
3959 }
3960 /*patching from JIT*/
3961 if (ins == ccode [0]) {
3962 g_assert (code32 [1] == ccode [1]);
3963 g_assert (code32 [3] == ccode [2]);
3964 g_assert (code32 [4] == ccode [3]);
3965 code32 [2] = (guint32)(gsize)target;
3966 return;
3967 }
3968 g_assert_not_reached ();
3969 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3970 /*
3971 * ldr ip, [pc, #0]
3972 * b 0xc
3973 * .word code_ptr
3974 * blx ip
3975 */
3976 guint32 ccode [4];
3977 guint8 *emit = (guint8*)ccode;
3978 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3979 ARM_B (emit, 0);
3980 ARM_BLX_REG (emit, ARMREG_IP);
3981
3982 g_assert (code32 [-3] == ccode [0]);
3983 g_assert (code32 [-2] == ccode [1]);
3984 g_assert (code32 [0] == ccode [2]);
3985
3986 code32 [-1] = (guint32)(gsize)target;
3987 } else {
3988 guint32 ccode [4];
3989 guint32 *tmp = ccode;
3990 guint8 *emit = (guint8*)tmp;
3991 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3992 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3993 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3994 ARM_BX (emit, ARMREG_IP);
3995 if (ins == ccode [2]) {
3996 g_assert_not_reached (); // should be -2 ...
3997 code32 [-1] = (guint32)(gsize)target;
3998 return;
3999 }
4000 if (ins == ccode [0]) {
4001 /* handles both thunk jump code and the far call sequence */
4002 code32 [2] = (guint32)(gsize)target;
4003 return;
4004 }
4005 g_assert_not_reached ();
4006 }
4007 // g_print ("patched with 0x%08x\n", ins);
4008 }
4009
4010 void
4011 arm_patch (guchar *code, const guchar *target)
4012 {
4013 arm_patch_general (NULL, NULL, code, target);
4014 }
4015
4016 /*
4017 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4018 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4019 * to be used with the emit macros.
4020 * Return -1 otherwise.
4021 */
4022 int
4023 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4024 {
4025 guint32 res, i;
4026 for (i = 0; i < 31; i+= 2) {
4027 if (i == 0)
4028 res = val;
4029 else
4030 res = (val << (32 - i)) | (val >> i);
4031 if (res & ~0xff)
4032 continue;
4033 *rot_amount = i? 32 - i: 0;
4034 return res;
4035 }
4036 return -1;
4037 }
4038
4039 /*
4040 * Emits in code a sequence of instructions that load the value 'val'
4041 * into the dreg register. Uses at most 4 instructions.
4042 */
4043 guint8*
4044 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4045 {
4046 int imm8, rot_amount;
4047 #if 0
4048 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4049 /* skip the constant pool */
4050 ARM_B (code, 0);
4051 *(int*)code = val;
4052 code += 4;
4053 return code;
4054 #endif
4055 if (mini_debug_options.single_imm_size && v7_supported) {
4056 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4057 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4058 return code;
4059 }
4060
4061 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4062 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4063 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4064 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4065 } else {
4066 if (v7_supported) {
4067 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4068 if (val >> 16)
4069 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4070 return code;
4071 }
4072 if (val & 0xFF) {
4073 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4074 if (val & 0xFF00) {
4075 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4076 }
4077 if (val & 0xFF0000) {
4078 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4079 }
4080 if (val & 0xFF000000) {
4081 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4082 }
4083 } else if (val & 0xFF00) {
4084 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4085 if (val & 0xFF0000) {
4086 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4087 }
4088 if (val & 0xFF000000) {
4089 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4090 }
4091 } else if (val & 0xFF0000) {
4092 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4093 if (val & 0xFF000000) {
4094 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4095 }
4096 }
4097 //g_assert_not_reached ();
4098 }
4099 return code;
4100 }
4101
4102 gboolean
4103 mono_arm_thumb_supported (void)
4104 {
4105 return thumb_supported;
4106 }
4107
4108 gboolean
4109 mono_arm_eabi_supported (void)
4110 {
4111 return eabi_supported;
4112 }
4113
4114 int
4115 mono_arm_i8_align (void)
4116 {
4117 return i8_align;
4118 }
4119
4120 #ifndef DISABLE_JIT
4121
4122 static guint8*
4123 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4124 {
4125 CallInfo *cinfo;
4126 MonoCallInst *call;
4127
4128 call = (MonoCallInst*)ins;
4129 cinfo = call->call_info;
4130
4131 switch (cinfo->ret.storage) {
4132 case RegTypeStructByVal:
4133 case RegTypeHFA: {
4134 MonoInst *loc = cfg->arch.vret_addr_loc;
4135 int i;
4136
4137 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4138 /* The JIT treats this as a normal call */
4139 break;
4140 }
4141
4142 /* Load the destination address */
4143 g_assert (loc && loc->opcode == OP_REGOFFSET);
4144
4145 if (arm_is_imm12 (loc->inst_offset)) {
4146 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4147 } else {
4148 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4149 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4150 }
4151
4152 if (cinfo->ret.storage == RegTypeStructByVal) {
4153 int rsize = cinfo->ret.struct_size;
4154
4155 for (i = 0; i < cinfo->ret.nregs; ++i) {
4156 g_assert (rsize >= 0);
4157 switch (rsize) {
4158 case 0:
4159 break;
4160 case 1:
4161 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4162 break;
4163 case 2:
4164 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4165 break;
4166 default:
4167 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4168 break;
4169 }
4170 rsize -= 4;
4171 }
4172 } else {
4173 for (i = 0; i < cinfo->ret.nregs; ++i) {
4174 if (cinfo->ret.esize == 4)
4175 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4176 else
4177 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4178 }
4179 }
4180 return code;
4181 }
4182 default:
4183 break;
4184 }
4185
4186 switch (ins->opcode) {
4187 case OP_FCALL:
4188 case OP_FCALL_REG:
4189 case OP_FCALL_MEMBASE:
4190 if (IS_VFP) {
4191 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4192 if (sig_ret->type == MONO_TYPE_R4) {
4193 if (IS_HARD_FLOAT) {
4194 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4195 } else {
4196 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4197 ARM_CVTS (code, ins->dreg, ins->dreg);
4198 }
4199 } else {
4200 if (IS_HARD_FLOAT) {
4201 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4202 } else {
4203 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4204 }
4205 }
4206 }
4207 break;
4208 case OP_RCALL:
4209 case OP_RCALL_REG:
4210 case OP_RCALL_MEMBASE: {
4211 MonoType *sig_ret;
4212
4213 g_assert (IS_VFP);
4214
4215 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4216 g_assert (sig_ret->type == MONO_TYPE_R4);
4217 if (IS_HARD_FLOAT) {
4218 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4219 } else {
4220 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4221 ARM_CPYS (code, ins->dreg, ins->dreg);
4222 }
4223 break;
4224 }
4225 default:
4226 break;
4227 }
4228
4229 return code;
4230 }
4231
4232 void
4233 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4234 {
4235 MonoInst *ins;
4236 MonoCallInst *call;
4237 guint8 *code = cfg->native_code + cfg->code_len;
4238 MonoInst *last_ins = NULL;
4239 int max_len, cpos;
4240 int imm8, rot_amount;
4241
4242 /* we don't align basic blocks of loops on arm */
4243
4244 if (cfg->verbose_level > 2)
4245 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4246
4247 cpos = bb->max_offset;
4248
4249 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4250 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
4251 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_break));
4252 code = emit_call_seq (cfg, code);
4253 }
4254
4255 MONO_BB_FOR_EACH_INS (bb, ins) {
4256 guint offset = code - cfg->native_code;
4257 set_code_cursor (cfg, code);
4258 max_len = ins_get_size (ins->opcode);
4259 code = realloc_code (cfg, max_len);
4260 // if (ins->cil_code)
4261 // g_print ("cil code\n");
4262 mono_debug_record_line_number (cfg, ins, offset);
4263
4264 switch (ins->opcode) {
4265 case OP_MEMORY_BARRIER:
4266 if (v7_supported) {
4267 ARM_DMB (code, ARM_DMB_ISH);
4268 } else if (v6_supported) {
4269 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4270 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4271 }
4272 break;
4273 case OP_TLS_GET:
4274 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4275 break;
4276 case OP_TLS_SET:
4277 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4278 break;
4279 case OP_ATOMIC_EXCHANGE_I4:
4280 case OP_ATOMIC_CAS_I4:
4281 case OP_ATOMIC_ADD_I4: {
4282 int tmpreg;
4283 guint8 *buf [16];
4284
4285 g_assert (v7_supported);
4286
4287 /* Free up a reg */
4288 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4289 tmpreg = ARMREG_IP;
4290 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4291 tmpreg = ARMREG_R0;
4292 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4293 tmpreg = ARMREG_R1;
4294 else
4295 tmpreg = ARMREG_R2;
4296 g_assert (cfg->arch.atomic_tmp_offset != -1);
4297 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4298
4299 switch (ins->opcode) {
4300 case OP_ATOMIC_EXCHANGE_I4:
4301 buf [0] = code;
4302 ARM_DMB (code, ARM_DMB_ISH);
4303 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4304 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4305 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4306 buf [1] = code;
4307 ARM_B_COND (code, ARMCOND_NE, 0);
4308 arm_patch (buf [1], buf [0]);
4309 break;
4310 case OP_ATOMIC_CAS_I4:
4311 ARM_DMB (code, ARM_DMB_ISH);
4312 buf [0] = code;
4313 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4314 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4315 buf [1] = code;
4316 ARM_B_COND (code, ARMCOND_NE, 0);
4317 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4318 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4319 buf [2] = code;
4320 ARM_B_COND (code, ARMCOND_NE, 0);
4321 arm_patch (buf [2], buf [0]);
4322 arm_patch (buf [1], code);
4323 break;
4324 case OP_ATOMIC_ADD_I4:
4325 buf [0] = code;
4326 ARM_DMB (code, ARM_DMB_ISH);
4327 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4328 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4329 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4330 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4331 buf [1] = code;
4332 ARM_B_COND (code, ARMCOND_NE, 0);
4333 arm_patch (buf [1], buf [0]);
4334 break;
4335 default:
4336 g_assert_not_reached ();
4337 }
4338
4339 ARM_DMB (code, ARM_DMB_ISH);
4340 if (tmpreg != ins->dreg)
4341 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4342 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4343 break;
4344 }
4345 case OP_ATOMIC_LOAD_I1:
4346 case OP_ATOMIC_LOAD_U1:
4347 case OP_ATOMIC_LOAD_I2:
4348 case OP_ATOMIC_LOAD_U2:
4349 case OP_ATOMIC_LOAD_I4:
4350 case OP_ATOMIC_LOAD_U4:
4351 case OP_ATOMIC_LOAD_R4:
4352 case OP_ATOMIC_LOAD_R8: {
4353 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4354 ARM_DMB (code, ARM_DMB_ISH);
4355
4356 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4357
4358 switch (ins->opcode) {
4359 case OP_ATOMIC_LOAD_I1:
4360 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4361 break;
4362 case OP_ATOMIC_LOAD_U1:
4363 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4364 break;
4365 case OP_ATOMIC_LOAD_I2:
4366 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4367 break;
4368 case OP_ATOMIC_LOAD_U2:
4369 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4370 break;
4371 case OP_ATOMIC_LOAD_I4:
4372 case OP_ATOMIC_LOAD_U4:
4373 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4374 break;
4375 case OP_ATOMIC_LOAD_R4:
4376 if (cfg->r4fp) {
4377 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4378 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4379 } else {
4380 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4381 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4382 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4383 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4384 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4385 }
4386 break;
4387 case OP_ATOMIC_LOAD_R8:
4388 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4389 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4390 break;
4391 }
4392
4393 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4394 ARM_DMB (code, ARM_DMB_ISH);
4395 break;
4396 }
4397 case OP_ATOMIC_STORE_I1:
4398 case OP_ATOMIC_STORE_U1:
4399 case OP_ATOMIC_STORE_I2:
4400 case OP_ATOMIC_STORE_U2:
4401 case OP_ATOMIC_STORE_I4:
4402 case OP_ATOMIC_STORE_U4:
4403 case OP_ATOMIC_STORE_R4:
4404 case OP_ATOMIC_STORE_R8: {
4405 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4406 ARM_DMB (code, ARM_DMB_ISH);
4407
4408 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4409
4410 switch (ins->opcode) {
4411 case OP_ATOMIC_STORE_I1:
4412 case OP_ATOMIC_STORE_U1:
4413 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4414 break;
4415 case OP_ATOMIC_STORE_I2:
4416 case OP_ATOMIC_STORE_U2:
4417 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4418 break;
4419 case OP_ATOMIC_STORE_I4:
4420 case OP_ATOMIC_STORE_U4:
4421 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4422 break;
4423 case OP_ATOMIC_STORE_R4:
4424 if (cfg->r4fp) {
4425 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4426 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4427 } else {
4428 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4429 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4430 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4431 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4432 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4433 }
4434 break;
4435 case OP_ATOMIC_STORE_R8:
4436 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4437 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4438 break;
4439 }
4440
4441 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4442 ARM_DMB (code, ARM_DMB_ISH);
4443 break;
4444 }
4445 case OP_BIGMUL:
4446 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4447 break;
4448 case OP_BIGMUL_UN:
4449 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4450 break;
4451 case OP_STOREI1_MEMBASE_IMM:
4452 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4453 g_assert (arm_is_imm12 (ins->inst_offset));
4454 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4455 break;
4456 case OP_STOREI2_MEMBASE_IMM:
4457 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4458 g_assert (arm_is_imm8 (ins->inst_offset));
4459 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4460 break;
4461 case OP_STORE_MEMBASE_IMM:
4462 case OP_STOREI4_MEMBASE_IMM:
4463 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4464 g_assert (arm_is_imm12 (ins->inst_offset));
4465 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4466 break;
4467 case OP_STOREI1_MEMBASE_REG:
4468 g_assert (arm_is_imm12 (ins->inst_offset));
4469 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4470 break;
4471 case OP_STOREI2_MEMBASE_REG:
4472 g_assert (arm_is_imm8 (ins->inst_offset));
4473 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4474 break;
4475 case OP_STORE_MEMBASE_REG:
4476 case OP_STOREI4_MEMBASE_REG:
4477 /* this case is special, since it happens for spill code after lowering has been called */
4478 if (arm_is_imm12 (ins->inst_offset)) {
4479 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4480 } else {
4481 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4482 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4483 }
4484 break;
4485 case OP_STOREI1_MEMINDEX:
4486 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4487 break;
4488 case OP_STOREI2_MEMINDEX:
4489 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4490 break;
4491 case OP_STORE_MEMINDEX:
4492 case OP_STOREI4_MEMINDEX:
4493 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4494 break;
4495 case OP_LOADU4_MEM:
4496 g_assert_not_reached ();
4497 break;
4498 case OP_LOAD_MEMINDEX:
4499 case OP_LOADI4_MEMINDEX:
4500 case OP_LOADU4_MEMINDEX:
4501 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4502 break;
4503 case OP_LOADI1_MEMINDEX:
4504 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4505 break;
4506 case OP_LOADU1_MEMINDEX:
4507 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4508 break;
4509 case OP_LOADI2_MEMINDEX:
4510 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4511 break;
4512 case OP_LOADU2_MEMINDEX:
4513 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4514 break;
4515 case OP_LOAD_MEMBASE:
4516 case OP_LOADI4_MEMBASE:
4517 case OP_LOADU4_MEMBASE:
4518 /* this case is special, since it happens for spill code after lowering has been called */
4519 if (arm_is_imm12 (ins->inst_offset)) {
4520 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4521 } else {
4522 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4523 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4524 }
4525 break;
4526 case OP_LOADI1_MEMBASE:
4527 g_assert (arm_is_imm8 (ins->inst_offset));
4528 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4529 break;
4530 case OP_LOADU1_MEMBASE:
4531 g_assert (arm_is_imm12 (ins->inst_offset));
4532 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4533 break;
4534 case OP_LOADU2_MEMBASE:
4535 g_assert (arm_is_imm8 (ins->inst_offset));
4536 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4537 break;
4538 case OP_LOADI2_MEMBASE:
4539 g_assert (arm_is_imm8 (ins->inst_offset));
4540 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4541 break;
4542 case OP_ICONV_TO_I1:
4543 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4544 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4545 break;
4546 case OP_ICONV_TO_I2:
4547 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4548 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4549 break;
4550 case OP_ICONV_TO_U1:
4551 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4552 break;
4553 case OP_ICONV_TO_U2:
4554 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4555 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4556 break;
4557 case OP_COMPARE:
4558 case OP_ICOMPARE:
4559 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4560 break;
4561 case OP_COMPARE_IMM:
4562 case OP_ICOMPARE_IMM:
4563 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4564 g_assert (imm8 >= 0);
4565 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4566 break;
4567 case OP_BREAK:
4568 /*
4569 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4570 * So instead of emitting a trap, we emit a call a C function and place a
4571 * breakpoint there.
4572 */
4573 //*(int*)code = 0xef9f0001;
4574 //code += 4;
4575 //ARM_DBRK (code);
4576 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
4577 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_break));
4578 code = emit_call_seq (cfg, code);
4579 break;
4580 case OP_RELAXED_NOP:
4581 ARM_NOP (code);
4582 break;
4583 case OP_NOP:
4584 case OP_DUMMY_USE:
4585 case OP_DUMMY_ICONST:
4586 case OP_DUMMY_R8CONST:
4587 case OP_DUMMY_R4CONST:
4588 case OP_NOT_REACHED:
4589 case OP_NOT_NULL:
4590 break;
4591 case OP_IL_SEQ_POINT:
4592 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4593 break;
4594 case OP_SEQ_POINT: {
4595 int i;
4596 MonoInst *info_var = cfg->arch.seq_point_info_var;
4597 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4598 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4599 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4600 MonoInst *var;
4601 int dreg = ARMREG_LR;
4602
4603 #if 0
4604 if (cfg->soft_breakpoints) {
4605 g_assert (!cfg->compile_aot);
4606 }
4607 #endif
4608
4609 /*
4610 * For AOT, we use one got slot per method, which will point to a
4611 * SeqPointInfo structure, containing all the information required
4612 * by the code below.
4613 */
4614 if (cfg->compile_aot) {
4615 g_assert (info_var);
4616 g_assert (info_var->opcode == OP_REGOFFSET);
4617 }
4618
4619 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4620 /*
4621 * Read from the single stepping trigger page. This will cause a
4622 * SIGSEGV when single stepping is enabled.
4623 * We do this _before_ the breakpoint, so single stepping after
4624 * a breakpoint is hit will step to the next IL offset.
4625 */
4626 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4627 }
4628
4629 /* Single step check */
4630 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4631 if (cfg->soft_breakpoints) {
4632 /* Load the address of the sequence point method variable. */
4633 var = ss_method_var;
4634 g_assert (var);
4635 g_assert (var->opcode == OP_REGOFFSET);
4636 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4637 /* Read the value and check whether it is non-zero. */
4638 ARM_LDR_IMM (code, dreg, dreg, 0);
4639 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4640 /* Call it conditionally. */
4641 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4642 } else {
4643 if (cfg->compile_aot) {
4644 /* Load the trigger page addr from the variable initialized in the prolog */
4645 var = ss_trigger_page_var;
4646 g_assert (var);
4647 g_assert (var->opcode == OP_REGOFFSET);
4648 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4649 } else {
4650 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4651 ARM_B (code, 0);
4652 *(int*)code = (int)(gsize)ss_trigger_page;
4653 code += 4;
4654 }
4655 ARM_LDR_IMM (code, dreg, dreg, 0);
4656 }
4657 }
4658
4659 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4660
4661 /* Breakpoint check */
4662 if (cfg->compile_aot) {
4663 const guint32 offset = code - cfg->native_code;
4664 guint32 val;
4665
4666 var = info_var;
4667 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4668 /* Add the offset */
4669 val = ((offset / 4) * sizeof (target_mgreg_t)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4670 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4671 if (arm_is_imm12 ((int)val)) {
4672 ARM_LDR_IMM (code, dreg, dreg, val);
4673 } else {
4674 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4675 if (val & 0xFF00)
4676 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4677 if (val & 0xFF0000)
4678 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4679 g_assert (!(val & 0xFF000000));
4680
4681 ARM_LDR_IMM (code, dreg, dreg, 0);
4682 }
4683 /* What is faster, a branch or a load ? */
4684 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4685 /* The breakpoint instruction */
4686 if (cfg->soft_breakpoints)
4687 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4688 else
4689 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4690 } else if (cfg->soft_breakpoints) {
4691 /* Load the address of the breakpoint method into ip. */
4692 var = bp_method_var;
4693 g_assert (var);
4694 g_assert (var->opcode == OP_REGOFFSET);
4695 g_assert (arm_is_imm12 (var->inst_offset));
4696 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4697
4698 /*
4699 * A placeholder for a possible breakpoint inserted by
4700 * mono_arch_set_breakpoint ().
4701 */
4702 ARM_NOP (code);
4703 } else {
4704 /*
4705 * A placeholder for a possible breakpoint inserted by
4706 * mono_arch_set_breakpoint ().
4707 */
4708 for (i = 0; i < 4; ++i)
4709 ARM_NOP (code);
4710 }
4711
4712 /*
4713 * Add an additional nop so skipping the bp doesn't cause the ip to point
4714 * to another IL offset.
4715 */
4716
4717 ARM_NOP (code);
4718 break;
4719 }
4720 case OP_ADDCC:
4721 case OP_IADDCC:
4722 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 break;
4724 case OP_IADD:
4725 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 break;
4727 case OP_ADC:
4728 case OP_IADC:
4729 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 break;
4731 case OP_ADDCC_IMM:
4732 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4733 g_assert (imm8 >= 0);
4734 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4735 break;
4736 case OP_ADD_IMM:
4737 case OP_IADD_IMM:
4738 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4739 g_assert (imm8 >= 0);
4740 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4741 break;
4742 case OP_ADC_IMM:
4743 case OP_IADC_IMM:
4744 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4745 g_assert (imm8 >= 0);
4746 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4747 break;
4748 case OP_IADD_OVF:
4749 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4751 break;
4752 case OP_IADD_OVF_UN:
4753 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4754 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4755 break;
4756 case OP_ISUB_OVF:
4757 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4759 break;
4760 case OP_ISUB_OVF_UN:
4761 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4762 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4763 break;
4764 case OP_ADD_OVF_CARRY:
4765 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4766 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4767 break;
4768 case OP_ADD_OVF_UN_CARRY:
4769 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4770 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4771 break;
4772 case OP_SUB_OVF_CARRY:
4773 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4774 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4775 break;
4776 case OP_SUB_OVF_UN_CARRY:
4777 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4779 break;
4780 case OP_SUBCC:
4781 case OP_ISUBCC:
4782 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4783 break;
4784 case OP_SUBCC_IMM:
4785 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4786 g_assert (imm8 >= 0);
4787 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4788 break;
4789 case OP_ISUB:
4790 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 break;
4792 case OP_SBB:
4793 case OP_ISBB:
4794 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4795 break;
4796 case OP_SUB_IMM:
4797 case OP_ISUB_IMM:
4798 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4799 g_assert (imm8 >= 0);
4800 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4801 break;
4802 case OP_SBB_IMM:
4803 case OP_ISBB_IMM:
4804 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4805 g_assert (imm8 >= 0);
4806 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4807 break;
4808 case OP_ARM_RSBS_IMM:
4809 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4810 g_assert (imm8 >= 0);
4811 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4812 break;
4813 case OP_ARM_RSC_IMM:
4814 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4815 g_assert (imm8 >= 0);
4816 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4817 break;
4818 case OP_IAND:
4819 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4820 break;
4821 case OP_AND_IMM:
4822 case OP_IAND_IMM:
4823 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4824 g_assert (imm8 >= 0);
4825 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4826 break;
4827 case OP_IDIV:
4828 g_assert (v7s_supported || v7k_supported);
4829 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4830 break;
4831 case OP_IDIV_UN:
4832 g_assert (v7s_supported || v7k_supported);
4833 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 break;
4835 case OP_IREM:
4836 g_assert (v7s_supported || v7k_supported);
4837 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4838 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4839 break;
4840 case OP_IREM_UN:
4841 g_assert (v7s_supported || v7k_supported);
4842 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4843 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4844 break;
4845 case OP_DIV_IMM:
4846 case OP_REM_IMM:
4847 g_assert_not_reached ();
4848 case OP_IOR:
4849 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 break;
4851 case OP_OR_IMM:
4852 case OP_IOR_IMM:
4853 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4854 g_assert (imm8 >= 0);
4855 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4856 break;
4857 case OP_IXOR:
4858 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 break;
4860 case OP_XOR_IMM:
4861 case OP_IXOR_IMM:
4862 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4863 g_assert (imm8 >= 0);
4864 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4865 break;
4866 case OP_ISHL:
4867 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4868 break;
4869 case OP_SHL_IMM:
4870 case OP_ISHL_IMM:
4871 if (ins->inst_imm)
4872 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4873 else if (ins->dreg != ins->sreg1)
4874 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4875 break;
4876 case OP_ISHR:
4877 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4878 break;
4879 case OP_SHR_IMM:
4880 case OP_ISHR_IMM:
4881 if (ins->inst_imm)
4882 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4883 else if (ins->dreg != ins->sreg1)
4884 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4885 break;
4886 case OP_SHR_UN_IMM:
4887 case OP_ISHR_UN_IMM:
4888 if (ins->inst_imm)
4889 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4890 else if (ins->dreg != ins->sreg1)
4891 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4892 break;
4893 case OP_ISHR_UN:
4894 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4895 break;
4896 case OP_INOT:
4897 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4898 break;
4899 case OP_INEG:
4900 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4901 break;
4902 case OP_IMUL:
4903 if (ins->dreg == ins->sreg2)
4904 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4905 else
4906 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4907 break;
4908 case OP_MUL_IMM:
4909 g_assert_not_reached ();
4910 break;
4911 case OP_IMUL_OVF:
4912 /* FIXME: handle ovf/ sreg2 != dreg */
4913 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4914 /* FIXME: MUL doesn't set the C/O flags on ARM */
4915 break;
4916 case OP_IMUL_OVF_UN:
4917 /* FIXME: handle ovf/ sreg2 != dreg */
4918 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4919 /* FIXME: MUL doesn't set the C/O flags on ARM */
4920 break;
4921 case OP_ICONST:
4922 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4923 break;
4924 case OP_AOTCONST:
4925 /* Load the GOT offset */
4926 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
4927 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4928 ARM_B (code, 0);
4929 *(gpointer*)code = NULL;
4930 code += 4;
4931 /* Load the value from the GOT */
4932 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4933 break;
4934 case OP_OBJC_GET_SELECTOR:
4935 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4936 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4937 ARM_B (code, 0);
4938 *(gpointer*)code = NULL;
4939 code += 4;
4940 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4941 break;
4942 case OP_ICONV_TO_I4:
4943 case OP_ICONV_TO_U4:
4944 case OP_MOVE:
4945 if (ins->dreg != ins->sreg1)
4946 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4947 break;
4948 case OP_SETLRET: {
4949 int saved = ins->sreg2;
4950 if (ins->sreg2 == ARM_LSW_REG) {
4951 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4952 saved = ARMREG_LR;
4953 }
4954 if (ins->sreg1 != ARM_LSW_REG)
4955 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4956 if (saved != ARM_MSW_REG)
4957 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4958 break;
4959 }
4960 case OP_FMOVE:
4961 if (IS_VFP && ins->dreg != ins->sreg1)
4962 ARM_CPYD (code, ins->dreg, ins->sreg1);
4963 break;
4964 case OP_RMOVE:
4965 if (IS_VFP && ins->dreg != ins->sreg1)
4966 ARM_CPYS (code, ins->dreg, ins->sreg1);
4967 break;
4968 case OP_MOVE_F_TO_I4:
4969 if (cfg->r4fp) {
4970 ARM_FMRS (code, ins->dreg, ins->sreg1);
4971 } else {
4972 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4973 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4974 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4975 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4976 }
4977 break;
4978 case OP_MOVE_I4_TO_F:
4979 if (cfg->r4fp) {
4980 ARM_FMSR (code, ins->dreg, ins->sreg1);
4981 } else {
4982 ARM_FMSR (code, ins->dreg, ins->sreg1);
4983 ARM_CVTS (code, ins->dreg, ins->dreg);
4984 }
4985 break;
4986 case OP_FCONV_TO_R4:
4987 if (IS_VFP) {
4988 if (cfg->r4fp) {
4989 ARM_CVTD (code, ins->dreg, ins->sreg1);
4990 } else {
4991 ARM_CVTD (code, ins->dreg, ins->sreg1);
4992 ARM_CVTS (code, ins->dreg, ins->dreg);
4993 }
4994 }
4995 break;
4996
4997 case OP_TAILCALL_PARAMETER:
4998 // This opcode helps compute sizes, i.e.
4999 // of the subsequent OP_TAILCALL, but contributes no code.
5000 g_assert (ins->next);
5001 break;
5002
5003 case OP_TAILCALL:
5004 case OP_TAILCALL_MEMBASE:
5005 case OP_TAILCALL_REG: {
5006 gboolean const tailcall_membase = ins->opcode == OP_TAILCALL_MEMBASE;
5007 gboolean const tailcall_reg = ins->opcode == OP_TAILCALL_REG;
5008 MonoCallInst *call = (MonoCallInst*)ins;
5009
5010 max_len += call->stack_usage / sizeof (target_mgreg_t) * ins_get_size (OP_TAILCALL_PARAMETER);
5011
5012 if (IS_HARD_FLOAT)
5013 code = emit_float_args (cfg, call, code, &max_len, &offset);
5014
5015 code = realloc_code (cfg, max_len);
5016
5017 // For reg and membase, get destination in IP.
5018
5019 if (tailcall_reg) {
5020 g_assert (ins->sreg1 > -1);
5021 if (ins->sreg1 != ARMREG_IP)
5022 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg1);
5023 } else if (tailcall_membase) {
5024 g_assert (ins->sreg1 > -1);
5025 if (!arm_is_imm12 (ins->inst_offset)) {
5026 g_assert (ins->sreg1 != ARMREG_IP); // temp in emit_big_add
5027 code = emit_big_add (code, ARMREG_IP, ins->sreg1, ins->inst_offset);
5028 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, 0);
5029 } else {
5030 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, ins->inst_offset);
5031 }
5032 }
5033
5034 /*
5035 * The stack looks like the following:
5036 * <caller argument area>
5037 * <saved regs etc>
5038 * <rest of frame>
5039 * <callee argument area>
5040 * <optionally saved IP> (about to be)
5041 * Need to copy the arguments from the callee argument area to
5042 * the caller argument area, and pop the frame.
5043 */
5044 if (call->stack_usage) {
5045 int i, prev_sp_offset = 0;
5046
5047 // When we get here, the parameters to the tailcall are already formed,
5048 // in registers and at the bottom of the grow-down stack.
5049 //
5050 // Our goal is generally preserve parameters, and trim the stack,
5051 // and, before trimming stack, move parameters from the bottom of the
5052 // frame to the bottom of the trimmed frame.
5053
5054 // For the case of large frames, and presently therefore always,
5055 // IP is used as an adjusted frame_reg.
5056 // Be conservative and save IP around the movement
5057 // of parameters from the bottom of frame to top of the frame.
5058 const gboolean save_ip = tailcall_membase || tailcall_reg;
5059 if (save_ip)
5060 ARM_PUSH (code, 1 << ARMREG_IP);
5061
5062 // When moving stacked parameters from the bottom
5063 // of the frame (sp) to the top of the frame (ip),
5064 // account, 0 or 4, for the conditional save of IP.
5065 const int offset_sp = save_ip ? 4 : 0;
5066 const int offset_ip = (save_ip && (cfg->frame_reg == ARMREG_SP)) ? 4 : 0;
5067
5068 /* Compute size of saved registers restored below */
5069 if (iphone_abi)
5070 prev_sp_offset = 2 * 4;
5071 else
5072 prev_sp_offset = 1 * 4;
5073 for (i = 0; i < 16; ++i) {
5074 if (cfg->used_int_regs & (1 << i))
5075 prev_sp_offset += 4;
5076 }
5077
5078 // Point IP at the start of where the parameters will go after trimming stack.
5079 // After locals and saved registers.
5080 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5081
5082 /* Copy arguments on the stack to our argument area */
5083 // FIXME a fixed size memcpy is desirable here,
5084 // at least for larger values of stack_usage.
5085 //
5086 // FIXME For most functions, with frames < 4K, we can use frame_reg directly here instead of IP.
5087 // See https://github.com/mono/mono/pull/12079
5088 // See https://github.com/mono/mono/pull/12079/commits/93e7007a9567b78fa8152ce404b372b26e735516
5089 for (i = 0; i < call->stack_usage; i += sizeof (target_mgreg_t)) {
5090 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i + offset_sp);
5091 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i + offset_ip);
5092 }
5093
5094 if (save_ip)
5095 ARM_POP (code, 1 << ARMREG_IP);
5096 }
5097
5098 /*
5099 * Keep in sync with mono_arch_emit_epilog
5100 */
5101 g_assert (!cfg->method->save_lmf);
5102 code = emit_big_add_temp (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage, ARMREG_LR);
5103 if (iphone_abi) {
5104 if (cfg->used_int_regs)
5105 ARM_POP (code, cfg->used_int_regs);
5106 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5107 } else {
5108 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5109 }
5110
5111 if (tailcall_reg || tailcall_membase) {
5112 code = emit_jmp_reg (code, ARMREG_IP);
5113 } else {
5114 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5115
5116 if (cfg->compile_aot) {
5117 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5118 ARM_B (code, 0);
5119 *(gpointer*)code = NULL;
5120 code += 4;
5121 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5122 } else {
5123 code = mono_arm_patchable_b (code, ARMCOND_AL);
5124 cfg->thunk_area += THUNK_SIZE;
5125 }
5126 }
5127 break;
5128 }
5129 case OP_CHECK_THIS:
5130 /* ensure ins->sreg1 is not NULL */
5131 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5132 break;
5133 case OP_ARGLIST: {
5134 g_assert (cfg->sig_cookie < 128);
5135 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5136 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5137 break;
5138 }
5139 case OP_FCALL:
5140 case OP_RCALL:
5141 case OP_LCALL:
5142 case OP_VCALL:
5143 case OP_VCALL2:
5144 case OP_VOIDCALL:
5145 case OP_CALL:
5146 call = (MonoCallInst*)ins;
5147
5148 if (IS_HARD_FLOAT)
5149 code = emit_float_args (cfg, call, code, &max_len, &offset);
5150
5151 mono_call_add_patch_info (cfg, call, code - cfg->native_code);
5152
5153 code = emit_call_seq (cfg, code);
5154 ins->flags |= MONO_INST_GC_CALLSITE;
5155 ins->backend.pc_offset = code - cfg->native_code;
5156 code = emit_move_return_value (cfg, ins, code);
5157 break;
5158 case OP_FCALL_REG:
5159 case OP_RCALL_REG:
5160 case OP_LCALL_REG:
5161 case OP_VCALL_REG:
5162 case OP_VCALL2_REG:
5163 case OP_VOIDCALL_REG:
5164 case OP_CALL_REG:
5165 if (IS_HARD_FLOAT)
5166 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5167
5168 code = emit_call_reg (code, ins->sreg1);
5169 ins->flags |= MONO_INST_GC_CALLSITE;
5170 ins->backend.pc_offset = code - cfg->native_code;
5171 code = emit_move_return_value (cfg, ins, code);
5172 break;
5173 case OP_FCALL_MEMBASE:
5174 case OP_RCALL_MEMBASE:
5175 case OP_LCALL_MEMBASE:
5176 case OP_VCALL_MEMBASE:
5177 case OP_VCALL2_MEMBASE:
5178 case OP_VOIDCALL_MEMBASE:
5179 case OP_CALL_MEMBASE: {
5180 g_assert (ins->sreg1 != ARMREG_LR);
5181 call = (MonoCallInst*)ins;
5182
5183 if (IS_HARD_FLOAT)
5184 code = emit_float_args (cfg, call, code, &max_len, &offset);
5185 if (!arm_is_imm12 (ins->inst_offset)) {
5186 /* sreg1 might be IP */
5187 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5188 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5189 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5190 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5191 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5192 } else {
5193 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5194 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5195 }
5196 ins->flags |= MONO_INST_GC_CALLSITE;
5197 ins->backend.pc_offset = code - cfg->native_code;
5198 code = emit_move_return_value (cfg, ins, code);
5199 break;
5200 }
5201 case OP_GENERIC_CLASS_INIT: {
5202 int byte_offset;
5203 guint8 *jump;
5204
5205 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5206
5207 g_assert (arm_is_imm8 (byte_offset));
5208 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5209 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5210 jump = code;
5211 ARM_B_COND (code, ARMCOND_NE, 0);
5212
5213 /* Uninitialized case */
5214 g_assert (ins->sreg1 == ARMREG_R0);
5215
5216 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
5217 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_generic_class_init));
5218 code = emit_call_seq (cfg, code);
5219
5220 /* Initialized case */
5221 arm_patch (jump, code);
5222 break;
5223 }
5224 case OP_LOCALLOC: {
5225 /* round the size to 8 bytes */
5226 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5227 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5228 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5229 /* memzero the area: dreg holds the size, sp is the pointer */
5230 if (ins->flags & MONO_INST_INIT) {
5231 guint8 *start_loop, *branch_to_cond;
5232 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5233 branch_to_cond = code;
5234 ARM_B (code, 0);
5235 start_loop = code;
5236 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5237 arm_patch (branch_to_cond, code);
5238 /* decrement by 4 and set flags */
5239 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (target_mgreg_t));
5240 ARM_B_COND (code, ARMCOND_GE, 0);
5241 arm_patch (code - 4, start_loop);
5242 }
5243 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5244 if (cfg->param_area)
5245 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5246 break;
5247 }
5248 case OP_DYN_CALL: {
5249 int i;
5250 MonoInst *var = cfg->dyn_call_var;
5251 guint8 *labels [16];
5252
5253 g_assert (var->opcode == OP_REGOFFSET);
5254 g_assert (arm_is_imm12 (var->inst_offset));
5255
5256 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5257 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5258 /* ip = ftn */
5259 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5260
5261 /* Save args buffer */
5262 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5263
5264 /* Set fp argument registers */
5265 if (IS_HARD_FLOAT) {
5266 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5267 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5268 labels [0] = code;
5269 ARM_B_COND (code, ARMCOND_EQ, 0);
5270 for (i = 0; i < FP_PARAM_REGS; ++i) {
5271 const int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5272 g_assert (arm_is_fpimm8 (offset));
5273 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5274 }
5275 arm_patch (labels [0], code);
5276 }
5277
5278 /* Allocate callee area */
5279 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_stackargs));
5280 ARM_SHL_IMM (code, ARMREG_R1, ARMREG_R1, 2);
5281 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_R1);
5282
5283 /* Set stack args */
5284 /* R1 = limit */
5285 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_stackargs));
5286 /* R2 = pointer into regs */
5287 code = emit_big_add (code, ARMREG_R2, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (PARAM_REGS * sizeof (target_mgreg_t)));
5288 /* R3 = pointer to stack */
5289 ARM_MOV_REG_REG (code, ARMREG_R3, ARMREG_SP);
5290 /* Loop */
5291 labels [0] = code;
5292 ARM_B_COND (code, ARMCOND_AL, 0);
5293 labels [1] = code;
5294 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R2, 0);
5295 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R3, 0);
5296 ARM_ADD_REG_IMM (code, ARMREG_R2, ARMREG_R2, sizeof (target_mgreg_t), 0);
5297 ARM_ADD_REG_IMM (code, ARMREG_R3, ARMREG_R3, sizeof (target_mgreg_t), 0);
5298 ARM_SUB_REG_IMM (code, ARMREG_R1, ARMREG_R1, 1, 0);
5299 arm_patch (labels [0], code);
5300 ARM_CMP_REG_IMM (code, ARMREG_R1, 0, 0);
5301 labels [2] = code;
5302 ARM_B_COND (code, ARMCOND_GT, 0);
5303 arm_patch (labels [2], labels [1]);
5304
5305 /* Set argument registers */
5306 for (i = 0; i < PARAM_REGS; ++i)
5307 ARM_LDR_IMM (code, i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof (target_mgreg_t)));
5308
5309 /* Make the call */
5310 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5311 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5312
5313 /* Save result */
5314 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5315 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5316 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5317 if (IS_HARD_FLOAT)
5318 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5319 break;
5320 }
5321 case OP_THROW: {
5322 if (ins->sreg1 != ARMREG_R0)
5323 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5324 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
5325 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_throw_exception));
5326 code = emit_call_seq (cfg, code);
5327 break;
5328 }
5329 case OP_RETHROW: {
5330 if (ins->sreg1 != ARMREG_R0)
5331 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID,
5333 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_rethrow_exception));
5334 code = emit_call_seq (cfg, code);
5335 break;
5336 }
5337 case OP_START_HANDLER: {
5338 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5339 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5340 int i, rot_amount;
5341
5342 /* Reserve a param area, see filter-stack.exe */
5343 if (param_area) {
5344 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5345 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5346 } else {
5347 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5348 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5349 }
5350 }
5351
5352 if (arm_is_imm12 (spvar->inst_offset)) {
5353 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5354 } else {
5355 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5356 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5357 }
5358 break;
5359 }
5360 case OP_ENDFILTER: {
5361 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5362 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5363 int i, rot_amount;
5364
5365 /* Free the param area */
5366 if (param_area) {
5367 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5368 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5369 } else {
5370 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5371 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5372 }
5373 }
5374
5375 if (ins->sreg1 != ARMREG_R0)
5376 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5377 if (arm_is_imm12 (spvar->inst_offset)) {
5378 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5379 } else {
5380 g_assert (ARMREG_IP != spvar->inst_basereg);
5381 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5382 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5383 }
5384 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5385 break;
5386 }
5387 case OP_ENDFINALLY: {
5388 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5389 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5390 int i, rot_amount;
5391
5392 /* Free the param area */
5393 if (param_area) {
5394 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5395 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5396 } else {
5397 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5398 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5399 }
5400 }
5401
5402 if (arm_is_imm12 (spvar->inst_offset)) {
5403 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5404 } else {
5405 g_assert (ARMREG_IP != spvar->inst_basereg);
5406 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5407 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5408 }
5409 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5410 break;
5411 }
5412 case OP_CALL_HANDLER:
5413 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5414 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5415 cfg->thunk_area += THUNK_SIZE;
5416 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
5417 mono_cfg_add_try_hole (cfg, ((MonoLeaveClause *) tmp->data)->clause, code, bb);
5418 break;
5419 case OP_GET_EX_OBJ:
5420 if (ins->dreg != ARMREG_R0)
5421 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5422 break;
5423
5424 case OP_LABEL:
5425 ins->inst_c0 = code - cfg->native_code;
5426 break;
5427 case OP_BR:
5428 /*if (ins->inst_target_bb->native_offset) {
5429 ARM_B (code, 0);
5430 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5431 } else*/ {
5432 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5433 code = mono_arm_patchable_b (code, ARMCOND_AL);
5434 }
5435 break;
5436 case OP_BR_REG:
5437 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5438 break;
5439 case OP_SWITCH:
5440 /*
5441 * In the normal case we have:
5442 * ldr pc, [pc, ins->sreg1 << 2]
5443 * nop
5444 * If aot, we have:
5445 * ldr lr, [pc, ins->sreg1 << 2]
5446 * add pc, pc, lr
5447 * After follows the data.
5448 * FIXME: add aot support.
5449 */
5450 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5451 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5452 code = realloc_code (cfg, max_len);
5453 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5454 ARM_NOP (code);
5455 code += 4 * GPOINTER_TO_INT (ins->klass);
5456 break;
5457 case OP_CEQ:
5458 case OP_ICEQ:
5459 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5460 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5461 break;
5462 case OP_CLT:
5463 case OP_ICLT:
5464 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5465 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5466 break;
5467 case OP_CLT_UN:
5468 case OP_ICLT_UN:
5469 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5470 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5471 break;
5472 case OP_CGT:
5473 case OP_ICGT:
5474 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5475 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5476 break;
5477 case OP_CGT_UN:
5478 case OP_ICGT_UN:
5479 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5480 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5481 break;
5482 case OP_ICNEQ:
5483 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5484 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5485 break;
5486 case OP_ICGE:
5487 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5488 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5489 break;
5490 case OP_ICLE:
5491 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5492 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5493 break;
5494 case OP_ICGE_UN:
5495 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5496 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5497 break;
5498 case OP_ICLE_UN:
5499 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5500 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5501 break;
5502 case OP_COND_EXC_EQ:
5503 case OP_COND_EXC_NE_UN:
5504 case OP_COND_EXC_LT:
5505 case OP_COND_EXC_LT_UN:
5506 case OP_COND_EXC_GT:
5507 case OP_COND_EXC_GT_UN:
5508 case OP_COND_EXC_GE:
5509 case OP_COND_EXC_GE_UN:
5510 case OP_COND_EXC_LE:
5511 case OP_COND_EXC_LE_UN:
5512 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5513 break;
5514 case OP_COND_EXC_IEQ:
5515 case OP_COND_EXC_INE_UN:
5516 case OP_COND_EXC_ILT:
5517 case OP_COND_EXC_ILT_UN:
5518 case OP_COND_EXC_IGT:
5519 case OP_COND_EXC_IGT_UN:
5520 case OP_COND_EXC_IGE:
5521 case OP_COND_EXC_IGE_UN:
5522 case OP_COND_EXC_ILE:
5523 case OP_COND_EXC_ILE_UN:
5524 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5525 break;
5526 case OP_COND_EXC_C:
5527 case OP_COND_EXC_IC:
5528 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5529 break;
5530 case OP_COND_EXC_OV:
5531 case OP_COND_EXC_IOV:
5532 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5533 break;
5534 case OP_COND_EXC_NC:
5535 case OP_COND_EXC_INC:
5536 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5537 break;
5538 case OP_COND_EXC_NO:
5539 case OP_COND_EXC_INO:
5540 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5541 break;
5542 case OP_IBEQ:
5543 case OP_IBNE_UN:
5544 case OP_IBLT:
5545 case OP_IBLT_UN:
5546 case OP_IBGT:
5547 case OP_IBGT_UN:
5548 case OP_IBGE:
5549 case OP_IBGE_UN:
5550 case OP_IBLE:
5551 case OP_IBLE_UN:
5552 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5553 break;
5554
5555 /* floating point opcodes */
5556 case OP_R8CONST:
5557 if (cfg->compile_aot) {
5558 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5559 ARM_B (code, 1);
5560 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5561 code += 4;
5562 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5563 code += 4;
5564 } else {
5565 /* FIXME: we can optimize the imm load by dealing with part of
5566 * the displacement in LDFD (aligning to 512).
5567 */
5568 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)(gsize)ins->inst_p0);
5569 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5570 }
5571 break;
5572 case OP_R4CONST:
5573 if (cfg->compile_aot) {
5574 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5575 ARM_B (code, 0);
5576 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5577 code += 4;
5578 if (!cfg->r4fp)
5579 ARM_CVTS (code, ins->dreg, ins->dreg);
5580 } else {
5581 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)(gsize)ins->inst_p0);
5582 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5583 if (!cfg->r4fp)
5584 ARM_CVTS (code, ins->dreg, ins->dreg);
5585 }
5586 break;
5587 case OP_STORER8_MEMBASE_REG:
5588 /* This is generated by the local regalloc pass which runs after the lowering pass */
5589 if (!arm_is_fpimm8 (ins->inst_offset)) {
5590 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5591 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5592 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5593 } else {
5594 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5595 }
5596 break;
5597 case OP_LOADR8_MEMBASE:
5598 /* This is generated by the local regalloc pass which runs after the lowering pass */
5599 if (!arm_is_fpimm8 (ins->inst_offset)) {
5600 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5601 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5602 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5603 } else {
5604 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5605 }
5606 break;
5607 case OP_STORER4_MEMBASE_REG:
5608 g_assert (arm_is_fpimm8 (ins->inst_offset));
5609 if (cfg->r4fp) {
5610 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5611 } else {
5612 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5613 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5614 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5615 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5616 }
5617 break;
5618 case OP_LOADR4_MEMBASE:
5619 if (cfg->r4fp) {
5620 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5621 } else {
5622 g_assert (arm_is_fpimm8 (ins->inst_offset));
5623 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5624 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5625 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5626 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5627 }
5628 break;
5629 case OP_ICONV_TO_R_UN: {
5630 g_assert_not_reached ();
5631 break;
5632 }
5633 case OP_ICONV_TO_R4:
5634 if (cfg->r4fp) {
5635 ARM_FMSR (code, ins->dreg, ins->sreg1);
5636 ARM_FSITOS (code, ins->dreg, ins->dreg);
5637 } else {
5638 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5639 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5640 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5641 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5642 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5643 }
5644 break;
5645 case OP_ICONV_TO_R8:
5646 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5647 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5648 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5649 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5650 break;
5651
5652 case OP_SETFRET: {
5653 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature_internal (cfg->method)->ret);
5654 if (sig_ret->type == MONO_TYPE_R4) {
5655 if (cfg->r4fp) {
5656 if (IS_HARD_FLOAT) {
5657 if (ins->sreg1 != ARM_VFP_D0)
5658 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5659 } else {
5660 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5661 }
5662 } else {
5663 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5664
5665 if (!IS_HARD_FLOAT)
5666 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5667 }
5668 } else {
5669 if (IS_HARD_FLOAT)
5670 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5671 else
5672 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5673 }
5674 break;
5675 }
5676 case OP_FCONV_TO_I1:
5677 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5678 break;
5679 case OP_FCONV_TO_U1:
5680 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5681 break;
5682 case OP_FCONV_TO_I2:
5683 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5684 break;
5685 case OP_FCONV_TO_U2:
5686 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5687 break;
5688 case OP_FCONV_TO_I4:
5689 case OP_FCONV_TO_I:
5690 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5691 break;
5692 case OP_FCONV_TO_U4:
5693 case OP_FCONV_TO_U:
5694 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5695 break;
5696 case OP_FCONV_TO_I8:
5697 case OP_FCONV_TO_U8:
5698 g_assert_not_reached ();
5699 /* Implemented as helper calls */
5700 break;
5701 case OP_LCONV_TO_R_UN:
5702 g_assert_not_reached ();
5703 /* Implemented as helper calls */
5704 break;
5705 case OP_LCONV_TO_OVF_I4_2: {
5706 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5707 /*
5708 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5709 */
5710
5711 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5712 high_bit_not_set = code;
5713 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5714
5715 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5716 valid_negative = code;
5717 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5718 invalid_negative = code;
5719 ARM_B_COND (code, ARMCOND_AL, 0);
5720
5721 arm_patch (high_bit_not_set, code);
5722
5723 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5724 valid_positive = code;
5725 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5726
5727 arm_patch (invalid_negative, code);
5728 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5729
5730 arm_patch (valid_negative, code);
5731 arm_patch (valid_positive, code);
5732
5733 if (ins->dreg != ins->sreg1)
5734 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5735 break;
5736 }
5737 case OP_FADD:
5738 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5739 break;
5740 case OP_FSUB:
5741 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5742 break;
5743 case OP_FMUL:
5744 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5745 break;
5746 case OP_FDIV:
5747 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5748 break;
5749 case OP_FNEG:
5750 ARM_NEGD (code, ins->dreg, ins->sreg1);
5751 break;
5752 case OP_FREM:
5753 /* emulated */
5754 g_assert_not_reached ();
5755 break;
5756 case OP_FCOMPARE:
5757 if (IS_VFP) {
5758 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5759 ARM_FMSTAT (code);
5760 }
5761 break;
5762 case OP_RCOMPARE:
5763 g_assert (IS_VFP);
5764 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5765 ARM_FMSTAT (code);
5766 break;
5767 case OP_FCEQ:
5768 if (IS_VFP) {
5769 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5770 ARM_FMSTAT (code);
5771 }
5772 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5773 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5774 break;
5775 case OP_FCLT:
5776 if (IS_VFP) {
5777 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5778 ARM_FMSTAT (code);
5779 }
5780 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5781 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5782 break;
5783 case OP_FCLT_UN:
5784 if (IS_VFP) {
5785 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5786 ARM_FMSTAT (code);
5787 }
5788 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5789 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5790 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5791 break;
5792 case OP_FCGT:
5793 if (IS_VFP) {
5794 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5795 ARM_FMSTAT (code);
5796 }
5797 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5798 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5799 break;
5800 case OP_FCGT_UN:
5801 if (IS_VFP) {
5802 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5803 ARM_FMSTAT (code);
5804 }
5805 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5806 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5807 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5808 break;
5809 case OP_FCNEQ:
5810 if (IS_VFP) {
5811 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5812 ARM_FMSTAT (code);
5813 }
5814 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5815 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5816 break;
5817 case OP_FCGE:
5818 if (IS_VFP) {
5819 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5820 ARM_FMSTAT (code);
5821 }
5822 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5823 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5824 break;
5825 case OP_FCLE:
5826 if (IS_VFP) {
5827 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5828 ARM_FMSTAT (code);
5829 }
5830 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5831 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5832 break;
5833
5834 /* ARM FPA flags table:
5835 * N Less than ARMCOND_MI
5836 * Z Equal ARMCOND_EQ
5837 * C Greater Than or Equal ARMCOND_CS
5838 * V Unordered ARMCOND_VS
5839 */
5840 case OP_FBEQ:
5841 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5842 break;
5843 case OP_FBNE_UN:
5844 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5845 break;
5846 case OP_FBLT:
5847 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5848 break;
5849 case OP_FBLT_UN:
5850 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5851 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5852 break;
5853 case OP_FBGT:
5854 case OP_FBGT_UN:
5855 case OP_FBLE:
5856 case OP_FBLE_UN:
5857 g_assert_not_reached ();
5858 break;
5859 case OP_FBGE:
5860 if (IS_VFP) {
5861 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5862 } else {
5863 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5864 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5865 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5866 }
5867 break;
5868 case OP_FBGE_UN:
5869 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5870 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5871 break;
5872
5873 case OP_CKFINITE: {
5874 if (IS_VFP) {
5875 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5876 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5877
5878 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5879 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5880 ARM_B (code, 1);
5881 *(guint32*)code = 0xffffffff;
5882 code += 4;
5883 *(guint32*)code = 0x7fefffff;
5884 code += 4;
5885 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5886 ARM_FMSTAT (code);
5887 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5888 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5889 ARM_FMSTAT (code);
5890 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5891 ARM_CPYD (code, ins->dreg, ins->sreg1);
5892
5893 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5894 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5895 }
5896 break;
5897 }
5898
5899 case OP_RCONV_TO_I1:
5900 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5901 break;
5902 case OP_RCONV_TO_U1:
5903 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5904 break;
5905 case OP_RCONV_TO_I2:
5906 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5907 break;
5908 case OP_RCONV_TO_U2:
5909 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5910 break;
5911 case OP_RCONV_TO_I4:
5912 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5913 break;
5914 case OP_RCONV_TO_U4:
5915 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5916 break;
5917 case OP_RCONV_TO_R4:
5918 g_assert (IS_VFP);
5919 if (ins->dreg != ins->sreg1)
5920 ARM_CPYS (code, ins->dreg, ins->sreg1);
5921 break;
5922 case OP_RCONV_TO_R8:
5923 g_assert (IS_VFP);
5924 ARM_CVTS (code, ins->dreg, ins->sreg1);
5925 break;
5926 case OP_RADD:
5927 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5928 break;
5929 case OP_RSUB:
5930 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5931 break;
5932 case OP_RMUL:
5933 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5934 break;
5935 case OP_RDIV:
5936 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5937 break;
5938 case OP_RNEG:
5939 ARM_NEGS (code, ins->dreg, ins->sreg1);
5940 break;
5941 case OP_RCEQ:
5942 if (IS_VFP) {
5943 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5944 ARM_FMSTAT (code);
5945 }
5946 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5947 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5948 break;
5949 case OP_RCLT:
5950 if (IS_VFP) {
5951 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5952 ARM_FMSTAT (code);
5953 }
5954 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5955 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5956 break;
5957 case OP_RCLT_UN:
5958 if (IS_VFP) {
5959 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5960 ARM_FMSTAT (code);
5961 }
5962 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5963 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5964 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5965 break;
5966 case OP_RCGT:
5967 if (IS_VFP) {
5968 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5969 ARM_FMSTAT (code);
5970 }
5971 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5972 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5973 break;
5974 case OP_RCGT_UN:
5975 if (IS_VFP) {
5976 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5977 ARM_FMSTAT (code);
5978 }
5979 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5980 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5981 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5982 break;
5983 case OP_RCNEQ:
5984 if (IS_VFP) {
5985 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5986 ARM_FMSTAT (code);
5987 }
5988 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5989 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5990 break;
5991 case OP_RCGE:
5992 if (IS_VFP) {
5993 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5994 ARM_FMSTAT (code);
5995 }
5996 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5997 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5998 break;
5999 case OP_RCLE:
6000 if (IS_VFP) {
6001 ARM_CMPS (code, ins->sreg2, ins->sreg1);
6002 ARM_FMSTAT (code);
6003 }
6004 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
6005 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
6006 break;
6007
6008 case OP_GC_LIVENESS_DEF:
6009 case OP_GC_LIVENESS_USE:
6010 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6011 ins->backend.pc_offset = code - cfg->native_code;
6012 break;
6013 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6014 ins->backend.pc_offset = code - cfg->native_code;
6015 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6016 break;
6017 case OP_LIVERANGE_START: {
6018 if (cfg->verbose_level > 1)
6019 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6020 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6021 break;
6022 }
6023 case OP_LIVERANGE_END: {
6024 if (cfg->verbose_level > 1)
6025 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6026 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6027 break;
6028 }
6029 case OP_GC_SAFE_POINT: {
6030 guint8 *buf [1];
6031
6032 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
6033 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
6034 buf [0] = code;
6035 ARM_B_COND (code, ARMCOND_EQ, 0);
6036 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_threads_state_poll));
6037 code = emit_call_seq (cfg, code);
6038 arm_patch (buf [0], code);
6039 break;
6040 }
6041 case OP_FILL_PROF_CALL_CTX:
6042 for (int i = 0; i < ARMREG_MAX; i++)
6043 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) || i == ARMREG_SP || i == ARMREG_FP)
6044 ARM_STR_IMM (code, i, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, regs) + i * sizeof (target_mgreg_t));
6045 break;
6046 default:
6047 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6048 g_assert_not_reached ();
6049 }
6050
6051 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
6052 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
6053 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6054 g_assert_not_reached ();
6055 }
6056
6057 cpos += max_len;
6058
6059 last_ins = ins;
6060 }
6061
6062 set_code_cursor (cfg, code);
6063 }
6064
6065 #endif /* DISABLE_JIT */
6066
6067 void
6068 mono_arch_register_lowlevel_calls (void)
6069 {
6070 /* The signature doesn't matter */
6071 mono_register_jit_icall (mono_arm_throw_exception, mono_icall_sig_void, TRUE);
6072 mono_register_jit_icall (mono_arm_throw_exception_by_token, mono_icall_sig_void, TRUE);
6073 mono_register_jit_icall (mono_arm_unaligned_stack, mono_icall_sig_void, TRUE);
6074 }
6075
6076 #define patch_lis_ori(ip,val) do {\
6077 guint16 *__lis_ori = (guint16*)(ip); \
6078 __lis_ori [1] = (((guint32)(gsize)(val)) >> 16) & 0xffff; \
6079 __lis_ori [3] = ((guint32)(gsize)(val)) & 0xffff; \
6080 } while (0)
6081
6082 void
6083 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6084 {
6085 unsigned char *ip = ji->ip.i + code;
6086
6087 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6088 }
6089
6090 switch (ji->type) {
6091 case MONO_PATCH_INFO_SWITCH: {
6092 gpointer *jt = (gpointer*)(ip + 8);
6093 int i;
6094 /* jt is the inlined jump table, 2 instructions after ip
6095 * In the normal case we store the absolute addresses,
6096 * otherwise the displacements.
6097 */
6098 for (i = 0; i < ji->data.table->table_size; i++)
6099 jt [i] = code + (int)(gsize)ji->data.table->table [i];
6100 break;
6101 }
6102 case MONO_PATCH_INFO_IP:
6103 g_assert_not_reached ();
6104 patch_lis_ori (ip, ip);
6105 break;
6106 case MONO_PATCH_INFO_METHODCONST:
6107 case MONO_PATCH_INFO_CLASS:
6108 case MONO_PATCH_INFO_IMAGE:
6109 case MONO_PATCH_INFO_FIELD:
6110 case MONO_PATCH_INFO_VTABLE:
6111 case MONO_PATCH_INFO_IID:
6112 case MONO_PATCH_INFO_SFLDA:
6113 case MONO_PATCH_INFO_LDSTR:
6114 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6115 case MONO_PATCH_INFO_LDTOKEN:
6116 g_assert_not_reached ();
6117 /* from OP_AOTCONST : lis + ori */
6118 patch_lis_ori (ip, target);
6119 break;
6120 case MONO_PATCH_INFO_R4:
6121 case MONO_PATCH_INFO_R8:
6122 g_assert_not_reached ();
6123 *((gconstpointer *)(ip + 2)) = target;
6124 break;
6125 case MONO_PATCH_INFO_EXC_NAME:
6126 g_assert_not_reached ();
6127 *((gconstpointer *)(ip + 1)) = target;
6128 break;
6129 case MONO_PATCH_INFO_NONE:
6130 case MONO_PATCH_INFO_BB_OVF:
6131 case MONO_PATCH_INFO_EXC_OVF:
6132 /* everything is dealt with at epilog output time */
6133 break;
6134 default:
6135 arm_patch_general (cfg, domain, ip, (const guchar*)target);
6136 break;
6137 }
6138 }
6139
6140 void
6141 mono_arm_unaligned_stack (MonoMethod *method)
6142 {
6143 g_assert_not_reached ();
6144 }
6145
6146 #ifndef DISABLE_JIT
6147
6148 /*
6149 * Stack frame layout:
6150 *
6151 * ------------------- fp
6152 * MonoLMF structure or saved registers
6153 * -------------------
6154 * locals
6155 * -------------------
6156 * spilled regs
6157 * -------------------
6158 * param area size is cfg->param_area
6159 * ------------------- sp
6160 */
6161 guint8 *
6162 mono_arch_emit_prolog (MonoCompile *cfg)
6163 {
6164 MonoMethod *method = cfg->method;
6165 MonoBasicBlock *bb;
6166 MonoMethodSignature *sig;
6167 MonoInst *inst;
6168 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6169 guint8 *code;
6170 CallInfo *cinfo;
6171 int lmf_offset = 0;
6172 int prev_sp_offset, reg_offset;
6173
6174 sig = mono_method_signature_internal (method);
6175 cfg->code_size = 256 + sig->param_count * 64;
6176 code = cfg->native_code = g_malloc (cfg->code_size);
6177
6178 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6179
6180 alloc_size = cfg->stack_offset;
6181 pos = 0;
6182 prev_sp_offset = 0;
6183
6184 if (iphone_abi) {
6185 /*
6186 * The iphone uses R7 as the frame pointer, and it points at the saved
6187 * r7+lr:
6188 * <lr>
6189 * r7 -> <r7>
6190 * <rest of frame>
6191 * We can't use r7 as a frame pointer since it points into the middle of
6192 * the frame, so we keep using our own frame pointer.
6193 * FIXME: Optimize this.
6194 */
6195 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6196 prev_sp_offset += 8; /* r7 and lr */
6197 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6198 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6199 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6200 }
6201
6202 if (!method->save_lmf) {
6203 if (iphone_abi) {
6204 /* No need to push LR again */
6205 if (cfg->used_int_regs)
6206 ARM_PUSH (code, cfg->used_int_regs);
6207 } else {
6208 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6209 prev_sp_offset += 4;
6210 }
6211 for (i = 0; i < 16; ++i) {
6212 if (cfg->used_int_regs & (1 << i))
6213 prev_sp_offset += 4;
6214 }
6215 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6216 reg_offset = 0;
6217 for (i = 0; i < 16; ++i) {
6218 if ((cfg->used_int_regs & (1 << i))) {
6219 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6220 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6221 reg_offset += 4;
6222 }
6223 }
6224 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6225 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6226 } else {
6227 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6228 ARM_PUSH (code, 0x5ff0);
6229 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6230 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6231 reg_offset = 0;
6232 for (i = 0; i < 16; ++i) {
6233 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6234 /* The original r7 is saved at the start */
6235 if (!(iphone_abi && i == ARMREG_R7))
6236 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6237 reg_offset += 4;
6238 }
6239 }
6240 g_assert (reg_offset == 4 * 10);
6241 pos += MONO_ABI_SIZEOF (MonoLMF) - (4 * 10);
6242 lmf_offset = pos;
6243 }
6244 alloc_size += pos;
6245 orig_alloc_size = alloc_size;
6246 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6247 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6248 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6249 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6250 }
6251
6252 /* the stack used in the pushed regs */
6253 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6254 cfg->stack_usage = alloc_size;
6255 if (alloc_size) {
6256 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6257 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6258 } else {
6259 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6260 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6261 }
6262 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6263 }
6264 if (cfg->frame_reg != ARMREG_SP) {
6265 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6266 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6267 }
6268 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6269 prev_sp_offset += alloc_size;
6270
6271 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6272 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6273
6274 /* compute max_offset in order to use short forward jumps
6275 * we could skip do it on arm because the immediate displacement
6276 * for jumps is large enough, it may be useful later for constant pools
6277 */
6278 max_offset = 0;
6279 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6280 MonoInst *ins = bb->code;
6281 bb->max_offset = max_offset;
6282
6283 MONO_BB_FOR_EACH_INS (bb, ins)
6284 max_offset += ins_get_size (ins->opcode);
6285 }
6286
6287 /* stack alignment check */
6288 /*
6289 {
6290 guint8 *buf [16];
6291 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6292 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6293 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6294 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6295 buf [0] = code;
6296 ARM_B_COND (code, ARMCOND_EQ, 0);
6297 if (cfg->compile_aot)
6298 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6299 else
6300 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6301 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_JIT_ICALL_ID, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arm_unaligned_stack));
6302 code = emit_call_seq (cfg, code);
6303 arm_patch (buf [0], code);
6304 }
6305 */
6306
6307 /* store runtime generic context */
6308 if (cfg->rgctx_var) {
6309 MonoInst *ins = cfg->rgctx_var;
6310
6311 g_assert (ins->opcode == OP_REGOFFSET);
6312
6313 if (arm_is_imm12 (ins->inst_offset)) {
6314 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6315 } else {
6316 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6317 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6318 }
6319
6320 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6321 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6322 }
6323
6324 /* load arguments allocated to register from the stack */
6325 cinfo = get_call_info (NULL, sig);
6326
6327 if (cinfo->ret.storage == RegTypeStructByAddr) {
6328 ArgInfo *ainfo = &cinfo->ret;
6329 inst = cfg->vret_addr;
6330 g_assert (arm_is_imm12 (inst->inst_offset));
6331 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6332 }
6333
6334 if (sig->call_convention == MONO_CALL_VARARG) {
6335 ArgInfo *cookie = &cinfo->sig_cookie;
6336
6337 /* Save the sig cookie address */
6338 g_assert (cookie->storage == RegTypeBase);
6339
6340 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6341 g_assert (arm_is_imm12 (cfg->sig_cookie));
6342 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6343 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6344 }
6345
6346 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6347 ArgInfo *ainfo = cinfo->args + i;
6348 inst = cfg->args [i];
6349
6350 if (cfg->verbose_level > 2)
6351 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6352
6353 if (inst->opcode == OP_REGVAR) {
6354 if (ainfo->storage == RegTypeGeneral)
6355 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6356 else if (ainfo->storage == RegTypeFP) {
6357 g_assert_not_reached ();
6358 } else if (ainfo->storage == RegTypeBase) {
6359 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6360 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6361 } else {
6362 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6363 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6364 }
6365 } else
6366 g_assert_not_reached ();
6367
6368 if (i == 0 && sig->hasthis) {
6369 g_assert (ainfo->storage == RegTypeGeneral);
6370 mono_add_var_location (cfg, inst, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6371 mono_add_var_location (cfg, inst, TRUE, inst->dreg, 0, code - cfg->native_code, 0);
6372 }
6373
6374 if (cfg->verbose_level > 2)
6375 g_print ("Argument %d assigned to register %s\n", i, mono_arch_regname (inst->dreg));
6376 } else {
6377 switch (ainfo->storage) {
6378 case RegTypeHFA:
6379 for (part = 0; part < ainfo->nregs; part ++) {
6380 if (ainfo->esize == 4)
6381 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6382 else
6383 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6384 }
6385 break;
6386 case RegTypeGeneral:
6387 case RegTypeIRegPair:
6388 case RegTypeGSharedVtInReg:
6389 case RegTypeStructByAddr:
6390 switch (ainfo->size) {
6391 case 1:
6392 if (arm_is_imm12 (inst->inst_offset))
6393 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6394 else {
6395 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6396 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6397 }
6398 break;
6399 case 2:
6400 if (arm_is_imm8 (inst->inst_offset)) {
6401 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6402 } else {
6403 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6404 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6405 }
6406 break;
6407 case 8:
6408 if (arm_is_imm12 (inst->inst_offset)) {
6409 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6410 } else {
6411 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6412 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6413 }
6414 if (arm_is_imm12 (inst->inst_offset + 4)) {
6415 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6416 } else {
6417 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6418 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6419 }
6420 break;
6421 default:
6422 if (arm_is_imm12 (inst->inst_offset)) {
6423 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6424 } else {
6425 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6426 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6427 }
6428 break;
6429 }
6430 if (i == 0 && sig->hasthis) {
6431 g_assert (ainfo->storage == RegTypeGeneral);
6432 mono_add_var_location (cfg, inst, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6433 mono_add_var_location (cfg, inst, FALSE, inst->inst_basereg, inst->inst_offset, code - cfg->native_code, 0);
6434 }
6435 break;
6436 case RegTypeBaseGen:
6437 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6438 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6439 } else {
6440 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6441 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6442 }
6443 if (arm_is_imm12 (inst->inst_offset + 4)) {
6444 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6445 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6446 } else {
6447 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6448 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6449 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6450 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6451 }
6452 break;
6453 case RegTypeBase:
6454 case RegTypeGSharedVtOnStack:
6455 case RegTypeStructByAddrOnStack:
6456 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6457 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6458 } else {
6459 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6460 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6461 }
6462
6463 switch (ainfo->size) {
6464 case 1:
6465 if (arm_is_imm8 (inst->inst_offset)) {
6466 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6467 } else {
6468 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6469 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6470 }
6471 break;
6472 case 2:
6473 if (arm_is_imm8 (inst->inst_offset)) {
6474 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6475 } else {
6476 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6477 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6478 }
6479 break;
6480 case 8:
6481 if (arm_is_imm12 (inst->inst_offset)) {
6482 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6483 } else {
6484 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6485 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6486 }
6487 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6488 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6489 } else {
6490 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6491 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6492 }
6493 if (arm_is_imm12 (inst->inst_offset + 4)) {
6494 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6495 } else {
6496 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6497 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6498 }
6499 break;
6500 default:
6501 if (arm_is_imm12 (inst->inst_offset)) {
6502 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6503 } else {
6504 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6505 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6506 }
6507 break;
6508 }
6509 break;
6510 case RegTypeFP: {
6511 int imm8, rot_amount;
6512
6513 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6514 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6515 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6516 } else
6517 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6518
6519 if (ainfo->size == 8)
6520 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6521 else
6522 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6523 break;
6524 }
6525 case RegTypeStructByVal: {
6526 int doffset = inst->inst_offset;
6527 int soffset = 0;
6528 int cur_reg;
6529 int size = 0;
6530 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6531 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6532 if (arm_is_imm12 (doffset)) {
6533 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6534 } else {
6535 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6536 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6537 }
6538 soffset += sizeof (target_mgreg_t);
6539 doffset += sizeof (target_mgreg_t);
6540 }
6541 if (ainfo->vtsize) {
6542 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6543 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6544 code = emit_memcpy (code, ainfo->vtsize * sizeof (target_mgreg_t), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6545 }
6546 break;
6547 }
6548 default:
6549 g_assert_not_reached ();
6550 break;
6551 }
6552 }
6553 }
6554
6555 if (method->save_lmf)
6556 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6557
6558 if (cfg->arch.seq_point_info_var) {
6559 MonoInst *ins = cfg->arch.seq_point_info_var;
6560
6561 /* Initialize the variable from a GOT slot */
6562 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6563 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6564 ARM_B (code, 0);
6565 *(gpointer*)code = NULL;
6566 code += 4;
6567 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6568
6569 g_assert (ins->opcode == OP_REGOFFSET);
6570
6571 if (arm_is_imm12 (ins->inst_offset)) {
6572 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6573 } else {
6574 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6575 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6576 }
6577 }
6578
6579 /* Initialize ss_trigger_page_var */
6580 if (!cfg->soft_breakpoints) {
6581 MonoInst *info_var = cfg->arch.seq_point_info_var;
6582 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6583 int dreg = ARMREG_LR;
6584
6585 if (info_var) {
6586 g_assert (info_var->opcode == OP_REGOFFSET);
6587
6588 code = emit_ldr_imm (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6589 /* Load the trigger page addr */
6590 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6591 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6592 }
6593 }
6594
6595 if (cfg->arch.seq_point_ss_method_var) {
6596 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6597 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6598
6599 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6600 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6601
6602 if (cfg->compile_aot) {
6603 MonoInst *info_var = cfg->arch.seq_point_info_var;
6604 int dreg = ARMREG_LR;
6605
6606 g_assert (info_var->opcode == OP_REGOFFSET);
6607 g_assert (arm_is_imm12 (info_var->inst_offset));
6608
6609 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6610 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6611 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6612 } else {
6613 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6614 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6615
6616 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6617 ARM_B (code, 1);
6618 *(gpointer*)code = &single_step_tramp;
6619 code += 4;
6620 *(gpointer*)code = breakpoint_tramp;
6621 code += 4;
6622
6623 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6624 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6625 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6626 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6627 }
6628 }
6629
6630 set_code_cursor (cfg, code);
6631 g_free (cinfo);
6632
6633 return code;
6634 }
6635
6636 void
6637 mono_arch_emit_epilog (MonoCompile *cfg)
6638 {
6639 MonoMethod *method = cfg->method;
6640 int pos, i, rot_amount;
6641 int max_epilog_size = 16 + 20*4;
6642 guint8 *code;
6643 CallInfo *cinfo;
6644
6645 if (cfg->method->save_lmf)
6646 max_epilog_size += 128;
6647
6648 code = realloc_code (cfg, max_epilog_size);
6649
6650 /* Save the uwind state which is needed by the out-of-line code */
6651 mono_emit_unwind_op_remember_state (cfg, code);
6652
6653 pos = 0;
6654
6655 /* Load returned vtypes into registers if needed */
6656 cinfo = cfg->arch.cinfo;
6657 switch (cinfo->ret.storage) {
6658 case RegTypeStructByVal: {
6659 MonoInst *ins = cfg->ret;
6660
6661 if (cinfo->ret.nregs == 1) {
6662 if (arm_is_imm12 (ins->inst_offset)) {
6663 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6664 } else {
6665 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6666 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6667 }
6668 } else {
6669 for (i = 0; i < cinfo->ret.nregs; ++i) {
6670 int offset = ins->inst_offset + (i * 4);
6671 if (arm_is_imm12 (offset)) {
6672 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6673 } else {
6674 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6675 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6676 }
6677 }
6678 }
6679 break;
6680 }
6681 case RegTypeHFA: {
6682 MonoInst *ins = cfg->ret;
6683
6684 for (i = 0; i < cinfo->ret.nregs; ++i) {
6685 if (cinfo->ret.esize == 4)
6686 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6687 else
6688 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6689 }
6690 break;
6691 }
6692 default:
6693 break;
6694 }
6695
6696 if (method->save_lmf) {
6697 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6698 /* all but r0-r3, sp and pc */
6699 pos += MONO_ABI_SIZEOF (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (target_mgreg_t));
6700 lmf_offset = pos;
6701
6702 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6703
6704 /* This points to r4 inside MonoLMF->iregs */
6705 sp_adj = (MONO_ABI_SIZEOF (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (target_mgreg_t));
6706 reg = ARMREG_R4;
6707 regmask = 0x9ff0; /* restore lr to pc */
6708 /* Skip caller saved registers not used by the method */
6709 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6710 regmask &= ~(1 << reg);
6711 sp_adj += 4;
6712 reg ++;
6713 }
6714 if (iphone_abi)
6715 /* Restored later */
6716 regmask &= ~(1 << ARMREG_PC);
6717 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6718 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6719 for (i = 0; i < 16; i++) {
6720 if (regmask & (1 << i))
6721 nused_int_regs ++;
6722 }
6723 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6724 /* restore iregs */
6725 ARM_POP (code, regmask);
6726 if (iphone_abi) {
6727 for (i = 0; i < 16; i++) {
6728 if (regmask & (1 << i))
6729 mono_emit_unwind_op_same_value (cfg, code, i);
6730 }
6731 /* Restore saved r7, restore LR to PC */
6732 /* Skip lr from the lmf */
6733 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6734 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (target_mgreg_t), 0);
6735 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6736 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6737 }
6738 } else {
6739 int i, nused_int_regs = 0;
6740
6741 for (i = 0; i < 16; i++) {
6742 if (cfg->used_int_regs & (1 << i))
6743 nused_int_regs ++;
6744 }
6745
6746 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6747 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6748 } else {
6749 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6750 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6751 }
6752
6753 if (cfg->frame_reg != ARMREG_SP) {
6754 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6755 }
6756
6757 if (iphone_abi) {
6758 /* Restore saved gregs */
6759 if (cfg->used_int_regs) {
6760 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6761 ARM_POP (code, cfg->used_int_regs);
6762 for (i = 0; i < 16; i++) {
6763 if (cfg->used_int_regs & (1 << i))
6764 mono_emit_unwind_op_same_value (cfg, code, i);
6765 }
6766 }
6767 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6768 /* Restore saved r7, restore LR to PC */
6769 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6770 } else {
6771 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6772 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6773 }
6774 }
6775
6776 /* Restore the unwind state to be the same as before the epilog */
6777 mono_emit_unwind_op_restore_state (cfg, code);
6778
6779 set_code_cursor (cfg, code);
6780
6781 }
6782
6783 void
6784 mono_arch_emit_exceptions (MonoCompile *cfg)
6785 {
6786 MonoJumpInfo *patch_info;
6787 int i;
6788 guint8 *code;
6789 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6790 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6791 int max_epilog_size = 50;
6792
6793 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6794 exc_throw_pos [i] = NULL;
6795 exc_throw_found [i] = 0;
6796 }
6797
6798 /* count the number of exception infos */
6799
6800 /*
6801 * make sure we have enough space for exceptions
6802 */
6803 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6804 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6805 i = mini_exception_id_by_name ((const char*)patch_info->data.target);
6806 if (!exc_throw_found [i]) {
6807 max_epilog_size += 32;
6808 exc_throw_found [i] = TRUE;
6809 }
6810 }
6811 }
6812
6813 code = realloc_code (cfg, max_epilog_size);
6814
6815 /* add code to raise exceptions */
6816 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6817 switch (patch_info->type) {
6818 case MONO_PATCH_INFO_EXC: {
6819 MonoClass *exc_class;
6820 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6821
6822 i = mini_exception_id_by_name ((const char*)patch_info->data.target);
6823 if (exc_throw_pos [i]) {
6824 arm_patch (ip, exc_throw_pos [i]);
6825 patch_info->type = MONO_PATCH_INFO_NONE;
6826 break;
6827 } else {
6828 exc_throw_pos [i] = code;
6829 }
6830 arm_patch (ip, code);
6831
6832 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6833
6834 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6835 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6836 patch_info->type = MONO_PATCH_INFO_JIT_ICALL_ID;
6837 patch_info->data.jit_icall_id = MONO_JIT_ICALL_mono_arch_throw_corlib_exception;
6838 patch_info->ip.i = code - cfg->native_code;
6839 ARM_BL (code, 0);
6840 cfg->thunk_area += THUNK_SIZE;
6841 *(guint32*)(gpointer)code = m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF;
6842 code += 4;
6843 break;
6844 }
6845 default:
6846 /* do nothing */
6847 break;
6848 }
6849 }
6850
6851 set_code_cursor (cfg, code);
6852 }
6853
6854 #endif /* #ifndef DISABLE_JIT */
6855
6856 void
6857 mono_arch_finish_init (void)
6858 {
6859 }
6860
6861 MonoInst*
6862 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6863 {
6864 /* FIXME: */
6865 return NULL;
6866 }
6867
6868 #ifndef DISABLE_JIT
6869
6870 #endif
6871
6872 guint32
6873 mono_arch_get_patch_offset (guint8 *code)
6874 {
6875 /* OP_AOTCONST */
6876 return 8;
6877 }
6878
6879 void
6880 mono_arch_flush_register_windows (void)
6881 {
6882 }
6883
6884 MonoMethod*
6885 mono_arch_find_imt_method (host_mgreg_t *regs, guint8 *code)
6886 {
6887 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6888 }
6889
6890 MonoVTable*
6891 mono_arch_find_static_call_vtable (host_mgreg_t *regs, guint8 *code)
6892 {
6893 return (MonoVTable*)(gsize)regs [MONO_ARCH_RGCTX_REG];
6894 }
6895
6896 GSList*
6897 mono_arch_get_cie_program (void)
6898 {
6899 GSList *l = NULL;
6900
6901 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6902
6903 return l;
6904 }
6905
6906 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6907 #define BASE_SIZE (6 * 4)
6908 #define BSEARCH_ENTRY_SIZE (4 * 4)
6909 #define CMP_SIZE (3 * 4)
6910 #define BRANCH_SIZE (1 * 4)
6911 #define CALL_SIZE (2 * 4)
6912 #define WMC_SIZE (8 * 4)
6913 #define DISTANCE(A, B) (((gint32)(gssize)(B)) - ((gint32)(gssize)(A)))
6914
6915 static arminstr_t *
6916 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6917 {
6918 guint32 delta = DISTANCE (target, code);
6919 delta -= 8;
6920 g_assert (delta >= 0 && delta <= 0xFFF);
6921 *target = *target | delta;
6922 *code = value;
6923 return code + 1;
6924 }
6925
6926 #ifdef ENABLE_WRONG_METHOD_CHECK
6927 static void
6928 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6929 {
6930 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6931 g_assert (0);
6932 }
6933 #endif
6934
6935 gpointer
6936 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6937 gpointer fail_tramp)
6938 {
6939 int size, i;
6940 arminstr_t *code, *start;
6941 gboolean large_offsets = FALSE;
6942 guint32 **constant_pool_starts;
6943 arminstr_t *vtable_target = NULL;
6944 int extra_space = 0;
6945 #ifdef ENABLE_WRONG_METHOD_CHECK
6946 char * cond;
6947 #endif
6948 GSList *unwind_ops;
6949
6950 size = BASE_SIZE;
6951 constant_pool_starts = g_new0 (guint32*, count);
6952
6953 for (i = 0; i < count; ++i) {
6954 MonoIMTCheckItem *item = imt_entries [i];
6955 if (item->is_equals) {
6956 gboolean fail_case = !item->check_target_idx && fail_tramp;
6957
6958 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6959 item->chunk_size += 32;
6960 large_offsets = TRUE;
6961 }
6962
6963 if (item->check_target_idx || fail_case) {
6964 if (!item->compare_done || fail_case)
6965 item->chunk_size += CMP_SIZE;
6966 item->chunk_size += BRANCH_SIZE;
6967 } else {
6968 #ifdef ENABLE_WRONG_METHOD_CHECK
6969 item->chunk_size += WMC_SIZE;
6970 #endif
6971 }
6972 if (fail_case) {
6973 item->chunk_size += 16;
6974 large_offsets = TRUE;
6975 }
6976 item->chunk_size += CALL_SIZE;
6977 } else {
6978 item->chunk_size += BSEARCH_ENTRY_SIZE;
6979 imt_entries [item->check_target_idx]->compare_done = TRUE;
6980 }
6981 size += item->chunk_size;
6982 }
6983
6984 if (large_offsets)
6985 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6986
6987 if (fail_tramp)
6988 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6989 else
6990 code = mono_domain_code_reserve (domain, size);
6991 start = code;
6992
6993 unwind_ops = mono_arch_get_cie_program ();
6994
6995 #ifdef DEBUG_IMT
6996 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6997 for (i = 0; i < count; ++i) {
6998 MonoIMTCheckItem *item = imt_entries [i];
6999 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7000 }
7001 #endif
7002
7003 if (large_offsets) {
7004 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7005 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (target_mgreg_t));
7006 } else {
7007 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7008 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (target_mgreg_t));
7009 }
7010 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7011 vtable_target = code;
7012 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7013 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7014
7015 for (i = 0; i < count; ++i) {
7016 MonoIMTCheckItem *item = imt_entries [i];
7017 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7018 gint32 vtable_offset;
7019
7020 item->code_target = (guint8*)code;
7021
7022 if (item->is_equals) {
7023 gboolean fail_case = !item->check_target_idx && fail_tramp;
7024
7025 if (item->check_target_idx || fail_case) {
7026 if (!item->compare_done || fail_case) {
7027 imt_method = code;
7028 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7029 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7030 }
7031 item->jmp_code = (guint8*)code;
7032 ARM_B_COND (code, ARMCOND_NE, 0);
7033 } else {
7034 /*Enable the commented code to assert on wrong method*/
7035 #ifdef ENABLE_WRONG_METHOD_CHECK
7036 imt_method = code;
7037 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7038 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7039 cond = code;
7040 ARM_B_COND (code, ARMCOND_EQ, 0);
7041
7042 /* Define this if your system is so bad that gdb is failing. */
7043 #ifdef BROKEN_DEV_ENV
7044 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7045 ARM_BL (code, 0);
7046 arm_patch (code - 1, mini_dump_bad_imt);
7047 #else
7048 ARM_DBRK (code);
7049 #endif
7050 arm_patch (cond, code);
7051 #endif
7052 }
7053
7054 if (item->has_target_code) {
7055 /* Load target address */
7056 target_code_ins = code;
7057 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7058 /* Save it to the fourth slot */
7059 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (target_mgreg_t));
7060 /* Restore registers and branch */
7061 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7062
7063 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7064 } else {
7065 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7066 if (!arm_is_imm12 (vtable_offset)) {
7067 /*
7068 * We need to branch to a computed address but we don't have
7069 * a free register to store it, since IP must contain the
7070 * vtable address. So we push the two values to the stack, and
7071 * load them both using LDM.
7072 */
7073 /* Compute target address */
7074 vtable_offset_ins = code;
7075 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7076 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7077 /* Save it to the fourth slot */
7078 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (target_mgreg_t));
7079 /* Restore registers and branch */
7080 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7081
7082 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7083 } else {
7084 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7085 if (large_offsets) {
7086 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (target_mgreg_t));
7087 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (target_mgreg_t));
7088 }
7089 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7090 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7091 }
7092 }
7093
7094 if (fail_case) {
7095 arm_patch (item->jmp_code, (guchar*)code);
7096
7097 target_code_ins = code;
7098 /* Load target address */
7099 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7100 /* Save it to the fourth slot */
7101 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (target_mgreg_t));
7102 /* Restore registers and branch */
7103 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7104
7105 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7106 item->jmp_code = NULL;
7107 }
7108
7109 if (imt_method)
7110 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)(gsize)item->key);
7111
7112 /*must emit after unconditional branch*/
7113 if (vtable_target) {
7114 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)(gsize)vtable);
7115 item->chunk_size += 4;
7116 vtable_target = NULL;
7117 }
7118
7119 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7120 constant_pool_starts [i] = code;
7121 if (extra_space) {
7122 code += extra_space;
7123 extra_space = 0;
7124 }
7125 } else {
7126 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7127 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7128
7129 item->jmp_code = (guint8*)code;
7130 ARM_B_COND (code, ARMCOND_HS, 0);
7131 ++extra_space;
7132 }
7133 }
7134
7135 for (i = 0; i < count; ++i) {
7136 MonoIMTCheckItem *item = imt_entries [i];
7137 if (item->jmp_code) {
7138 if (item->check_target_idx)
7139 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7140 }
7141 if (i > 0 && item->is_equals) {
7142 int j;
7143 arminstr_t *space_start = constant_pool_starts [i];
7144 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7145 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)(gsize)imt_entries [j]->key);
7146 }
7147 }
7148 }
7149
7150 #ifdef DEBUG_IMT
7151 {
7152 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
7153 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7154 g_free (buff);
7155 }
7156 #endif
7157
7158 g_free (constant_pool_starts);
7159
7160 mono_arch_flush_icache ((guint8*)start, size);
7161 MONO_PROFILER_RAISE (jit_code_buffer, ((guint8*)start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
7162 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
7163
7164 g_assert (DISTANCE (start, code) <= size);
7165
7166 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7167
7168 return start;
7169 }
7170
7171 host_mgreg_t
7172 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7173 {
7174 return ctx->regs [reg];
7175 }
7176
7177 void
7178 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, host_mgreg_t val)
7179 {
7180 ctx->regs [reg] = val;
7181 }
7182
7183 /*
7184 * mono_arch_get_trampolines:
7185 *
7186 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7187 * for AOT.
7188 */
7189 GSList *
7190 mono_arch_get_trampolines (gboolean aot)
7191 {
7192 return mono_arm_get_exception_trampolines (aot);
7193 }
7194
7195 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7196 /*
7197 * mono_arch_set_breakpoint:
7198 *
7199 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7200 * The location should contain code emitted by OP_SEQ_POINT.
7201 */
7202 void
7203 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7204 {
7205 guint8 *code = ip;
7206 guint32 native_offset = ip - (guint8*)ji->code_start;
7207
7208 if (ji->from_aot) {
7209 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8*)ji->code_start);
7210
7211 if (!breakpoint_tramp)
7212 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7213
7214 g_assert (native_offset % 4 == 0);
7215 g_assert (info->bp_addrs [native_offset / 4] == 0);
7216 info->bp_addrs [native_offset / 4] = (guint8*)(mini_debug_options.soft_breakpoints ? breakpoint_tramp : bp_trigger_page);
7217 } else if (mini_debug_options.soft_breakpoints) {
7218 code += 4;
7219 ARM_BLX_REG (code, ARMREG_LR);
7220 mono_arch_flush_icache (code - 4, 4);
7221 } else {
7222 int dreg = ARMREG_LR;
7223
7224 /* Read from another trigger page */
7225 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7226 ARM_B (code, 0);
7227 *(int*)code = (int)(gssize)bp_trigger_page;
7228 code += 4;
7229 ARM_LDR_IMM (code, dreg, dreg, 0);
7230
7231 mono_arch_flush_icache (code - 16, 16);
7232
7233 #if 0
7234 /* This is currently implemented by emitting an SWI instruction, which
7235 * qemu/linux seems to convert to a SIGILL.
7236 */
7237 *(int*)code = (0xef << 24) | 8;
7238 code += 4;
7239 mono_arch_flush_icache (code - 4, 4);
7240 #endif
7241 }
7242 }
7243
7244 /*
7245 * mono_arch_clear_breakpoint:
7246 *
7247 * Clear the breakpoint at IP.
7248 */
7249 void
7250 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7251 {
7252 guint8 *code = ip;
7253 int i;
7254
7255 if (ji->from_aot) {
7256 guint32 native_offset = ip - (guint8*)ji->code_start;
7257 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), (guint8*)ji->code_start);
7258
7259 if (!breakpoint_tramp)
7260 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7261
7262 g_assert (native_offset % 4 == 0);
7263 g_assert (info->bp_addrs [native_offset / 4] == (guint8*)(mini_debug_options.soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7264 info->bp_addrs [native_offset / 4] = 0;
7265 } else if (mini_debug_options.soft_breakpoints) {
7266 code += 4;
7267 ARM_NOP (code);
7268 mono_arch_flush_icache (code - 4, 4);
7269 } else {
7270 for (i = 0; i < 4; ++i)
7271 ARM_NOP (code);
7272
7273 mono_arch_flush_icache (ip, code - ip);
7274 }
7275 }
7276
7277 /*
7278 * mono_arch_start_single_stepping:
7279 *
7280 * Start single stepping.
7281 */
7282 void
7283 mono_arch_start_single_stepping (void)
7284 {
7285 if (ss_trigger_page)
7286 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7287 else
7288 single_step_tramp = mini_get_single_step_trampoline ();
7289 }
7290
7291 /*
7292 * mono_arch_stop_single_stepping:
7293 *
7294 * Stop single stepping.
7295 */
7296 void
7297 mono_arch_stop_single_stepping (void)
7298 {
7299 if (ss_trigger_page)
7300 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7301 else
7302 single_step_tramp = NULL;
7303 }
7304
7305 #if __APPLE__
7306 #define DBG_SIGNAL SIGBUS
7307 #else
7308 #define DBG_SIGNAL SIGSEGV
7309 #endif
7310
7311 /*
7312 * mono_arch_is_single_step_event:
7313 *
7314 * Return whenever the machine state in SIGCTX corresponds to a single
7315 * step event.
7316 */
7317 gboolean
7318 mono_arch_is_single_step_event (void *info, void *sigctx)
7319 {
7320 siginfo_t *sinfo = (siginfo_t*)info;
7321
7322 if (!ss_trigger_page)
7323 return FALSE;
7324
7325 /* Sometimes the address is off by 4 */
7326 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7327 return TRUE;
7328 else
7329 return FALSE;
7330 }
7331
7332 /*
7333 * mono_arch_is_breakpoint_event:
7334 *
7335 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7336 */
7337 gboolean
7338 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7339 {
7340 siginfo_t *sinfo = (siginfo_t*)info;
7341
7342 if (!ss_trigger_page)
7343 return FALSE;
7344
7345 if (sinfo->si_signo == DBG_SIGNAL) {
7346 /* Sometimes the address is off by 4 */
7347 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7348 return TRUE;
7349 else
7350 return FALSE;
7351 } else {
7352 return FALSE;
7353 }
7354 }
7355
7356 /*
7357 * mono_arch_skip_breakpoint:
7358 *
7359 * See mini-amd64.c for docs.
7360 */
7361 void
7362 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7363 {
7364 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7365 }
7366
7367 /*
7368 * mono_arch_skip_single_step:
7369 *
7370 * See mini-amd64.c for docs.
7371 */
7372 void
7373 mono_arch_skip_single_step (MonoContext *ctx)
7374 {
7375 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7376 }
7377
7378 /*
7379 * mono_arch_get_seq_point_info:
7380 *
7381 * See mini-amd64.c for docs.
7382 */
7383 SeqPointInfo*
7384 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7385 {
7386 SeqPointInfo *info;
7387 MonoJitInfo *ji;
7388
7389 // FIXME: Add a free function
7390
7391 mono_domain_lock (domain);
7392 info = (SeqPointInfo*)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7393 code);
7394 mono_domain_unlock (domain);
7395
7396 if (!info) {
7397 ji = mono_jit_info_table_find (domain, code);
7398 g_assert (ji);
7399
7400 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7401
7402 info->ss_trigger_page = ss_trigger_page;
7403 info->bp_trigger_page = bp_trigger_page;
7404 info->ss_tramp_addr = &single_step_tramp;
7405
7406 mono_domain_lock (domain);
7407 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7408 code, info);
7409 mono_domain_unlock (domain);
7410 }
7411
7412 return info;
7413 }
7414
7415 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7416
7417 /*
7418 * mono_arch_set_target:
7419 *
7420 * Set the target architecture the JIT backend should generate code for, in the form
7421 * of a GNU target triplet. Only used in AOT mode.
7422 */
7423 void
7424 mono_arch_set_target (char *mtriple)
7425 {
7426 /* The GNU target triple format is not very well documented */
7427 if (strstr (mtriple, "armv7")) {
7428 v5_supported = TRUE;
7429 v6_supported = TRUE;
7430 v7_supported = TRUE;
7431 }
7432 if (strstr (mtriple, "armv6")) {
7433 v5_supported = TRUE;
7434 v6_supported = TRUE;
7435 }
7436 if (strstr (mtriple, "armv7s")) {
7437 v7s_supported = TRUE;
7438 }
7439 if (strstr (mtriple, "armv7k")) {
7440 v7k_supported = TRUE;
7441 }
7442 if (strstr (mtriple, "thumbv7s")) {
7443 v5_supported = TRUE;
7444 v6_supported = TRUE;
7445 v7_supported = TRUE;
7446 v7s_supported = TRUE;
7447 thumb_supported = TRUE;
7448 thumb2_supported = TRUE;
7449 }
7450 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7451 v5_supported = TRUE;
7452 v6_supported = TRUE;
7453 thumb_supported = TRUE;
7454 iphone_abi = TRUE;
7455 }
7456 if (strstr (mtriple, "gnueabi"))
7457 eabi_supported = TRUE;
7458 }
7459
7460 gboolean
7461 mono_arch_opcode_supported (int opcode)
7462 {
7463 switch (opcode) {
7464 case OP_ATOMIC_ADD_I4:
7465 case OP_ATOMIC_EXCHANGE_I4:
7466 case OP_ATOMIC_CAS_I4:
7467 case OP_ATOMIC_LOAD_I1:
7468 case OP_ATOMIC_LOAD_I2:
7469 case OP_ATOMIC_LOAD_I4:
7470 case OP_ATOMIC_LOAD_U1:
7471 case OP_ATOMIC_LOAD_U2:
7472 case OP_ATOMIC_LOAD_U4:
7473 case OP_ATOMIC_STORE_I1:
7474 case OP_ATOMIC_STORE_I2:
7475 case OP_ATOMIC_STORE_I4:
7476 case OP_ATOMIC_STORE_U1:
7477 case OP_ATOMIC_STORE_U2:
7478 case OP_ATOMIC_STORE_U4:
7479 return v7_supported;
7480 case OP_ATOMIC_LOAD_R4:
7481 case OP_ATOMIC_LOAD_R8:
7482 case OP_ATOMIC_STORE_R4:
7483 case OP_ATOMIC_STORE_R8:
7484 return v7_supported && IS_VFP;
7485 default:
7486 return FALSE;
7487 }
7488 }
7489
7490 CallInfo*
7491 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7492 {
7493 return get_call_info (mp, sig);
7494 }
7495
7496 gpointer
7497 mono_arch_get_get_tls_tramp (void)
7498 {
7499 return NULL;
7500 }
7501
7502 static G_GNUC_UNUSED guint8*
7503 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7504 {
7505 /* OP_AOTCONST */
7506 mono_add_patch_info (cfg, code - cfg->native_code, (MonoJumpInfoType)patch_type, data);
7507 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7508 ARM_B (code, 0);
7509 *(gpointer*)code = NULL;
7510 code += 4;
7511 /* Load the value from the GOT */
7512 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7513 return code;
7514 }
7515
7516 guint8*
7517 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7518 {
7519 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7520
7521 *ji = mono_patch_info_list_prepend (*ji, code - buf, (MonoJumpInfoType)patch_type, data);
7522 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7523 ARM_B (code, 0);
7524 *(gpointer*)code = NULL;
7525 code += 4;
7526 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7527 return code;
7528 }
7529
7530 gpointer
7531 mono_arch_load_function (MonoJitICallId jit_icall_id)
7532 {
7533 gpointer target = NULL;
7534 switch (jit_icall_id) {
7535 #undef MONO_AOT_ICALL
7536 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
7537 MONO_AOT_ICALL (mono_arm_resume_unwind)
7538 MONO_AOT_ICALL (mono_arm_start_gsharedvt_call)
7539 MONO_AOT_ICALL (mono_arm_throw_exception)
7540 MONO_AOT_ICALL (mono_arm_throw_exception_by_token)
7541 MONO_AOT_ICALL (mono_arm_unaligned_stack)
7542 }
7543 return target;
7544 }
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