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[tests] Reenable enum equals test on interpreter (#18673)
[mono-project.git] / mono / mini / mini-codegen.c
blobf6745409d97f80967c65cec13c6dbb133b393336
1 /**
2 * \file
3 * Arch independent code generation functionality
4 *
5 * (C) 2003 Ximian, Inc.
6 */
7
8 #include "config.h"
9
10 #include <string.h>
11 #include <math.h>
12 #ifdef HAVE_UNISTD_H
13 #include <unistd.h>
14 #endif
15
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/debug-helpers.h>
18 #include <mono/metadata/threads.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/mempool-internals.h>
21 #include <mono/utils/mono-math.h>
22
23 #include "mini.h"
24 #include "mini-runtime.h"
25 #include "trace.h"
26 #include "mini-arch.h"
27
28 #ifndef DISABLE_JIT
29
30 #ifndef MONO_MAX_XREGS
31
32 #define MONO_MAX_XREGS 0
33 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
34 #define MONO_ARCH_CALLEE_XREGS 0
35
36 #endif
37
38 #define MONO_ARCH_BANK_MIRRORED -2
39
40 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
41
42 #ifndef MONO_ARCH_NEED_SIMD_BANK
43 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
44 #endif
45
46 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
47
48 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
49
50
51 #else
52
53
54 #define get_mirrored_bank(bank) (-1)
55
56 #define is_hreg_mirrored(rs, bank, hreg) (0)
57
58 #endif
59
60
61 /* If the bank is mirrored return the true logical bank that the register in the
62 * physical register bank is allocated to.
63 */
64 static int translate_bank (MonoRegState *rs, int bank, int hreg) {
65 return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
66 }
67
68 /*
69 * Every hardware register belongs to a register type or register bank. bank 0
70 * contains the int registers, bank 1 contains the fp registers.
71 * int registers are used 99% of the time, so they are special cased in a lot of
72 * places.
73 */
74
75 static const int regbank_size [] = {
76 MONO_MAX_IREGS,
77 MONO_MAX_FREGS,
78 MONO_MAX_IREGS,
79 MONO_MAX_IREGS,
80 MONO_MAX_XREGS
81 };
82
83 static const int regbank_load_ops [] = {
84 OP_LOADR_MEMBASE,
85 OP_LOADR8_MEMBASE,
86 OP_LOADR_MEMBASE,
87 OP_LOADR_MEMBASE,
88 OP_LOADX_MEMBASE
89 };
90
91 static const int regbank_store_ops [] = {
92 OP_STORER_MEMBASE_REG,
93 OP_STORER8_MEMBASE_REG,
94 OP_STORER_MEMBASE_REG,
95 OP_STORER_MEMBASE_REG,
96 OP_STOREX_MEMBASE
97 };
98
99 static const int regbank_move_ops [] = {
100 OP_MOVE,
101 OP_FMOVE,
102 OP_MOVE,
103 OP_MOVE,
104 OP_XMOVE
105 };
106
107 #define regmask(reg) (((regmask_t)1) << (reg))
108
109 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
110 static const regmask_t regbank_callee_saved_regs [] = {
111 MONO_ARCH_CALLEE_SAVED_REGS,
112 MONO_ARCH_CALLEE_SAVED_FREGS,
113 MONO_ARCH_CALLEE_SAVED_REGS,
114 MONO_ARCH_CALLEE_SAVED_REGS,
115 MONO_ARCH_CALLEE_SAVED_XREGS,
116 };
117 #endif
118
119 static const regmask_t regbank_callee_regs [] = {
120 MONO_ARCH_CALLEE_REGS,
121 MONO_ARCH_CALLEE_FREGS,
122 MONO_ARCH_CALLEE_REGS,
123 MONO_ARCH_CALLEE_REGS,
124 MONO_ARCH_CALLEE_XREGS,
125 };
126
127 static const int regbank_spill_var_size[] = {
128 sizeof (target_mgreg_t),
129 sizeof (double),
130 sizeof (target_mgreg_t),
131 sizeof (target_mgreg_t),
132 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
133 };
134
135 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
136
137 static void
138 mono_regstate_assign (MonoRegState *rs)
139 {
140 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
141 /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
142 * if the values here are not the same.
143 */
144 g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
145 g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
146 g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
147 #endif
148
149 if (rs->next_vreg > rs->vassign_size) {
150 g_free (rs->vassign);
151 rs->vassign_size = MAX (rs->next_vreg, 256);
152 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
153 }
154
155 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
156 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
157
158 rs->symbolic [MONO_REG_INT] = rs->isymbolic;
159 rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
160
161 #ifdef MONO_ARCH_NEED_SIMD_BANK
162 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
163 rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
164 #endif
165 }
166
167 static int
168 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
169 {
170 regmask_t mask = allow & rs->ifree_mask;
171
172 #if defined(__x86_64__) && defined(__GNUC__)
173 {
174 guint64 i;
175
176 if (mask == 0)
177 return -1;
178
179 __asm__("bsfq %1,%0\n\t"
180 : "=r" (i) : "rm" (mask));
181
182 rs->ifree_mask &= ~ ((regmask_t)1 << i);
183 return i;
184 }
185 #else
186 int i;
187
188 for (i = 0; i < MONO_MAX_IREGS; ++i) {
189 if (mask & ((regmask_t)1 << i)) {
190 rs->ifree_mask &= ~ ((regmask_t)1 << i);
191 return i;
192 }
193 }
194 return -1;
195 #endif
196 }
197
198 static void
199 mono_regstate_free_int (MonoRegState *rs, int reg)
200 {
201 if (reg >= 0) {
202 rs->ifree_mask |= (regmask_t)1 << reg;
203 rs->isymbolic [reg] = 0;
204 }
205 }
206
207 static int
208 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
209 {
210 int i;
211 int mirrored_bank;
212 regmask_t mask = allow & rs->free_mask [bank];
213 for (i = 0; i < regbank_size [bank]; ++i) {
214 if (mask & ((regmask_t)1 << i)) {
215 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
216
217 mirrored_bank = get_mirrored_bank (bank);
218 if (mirrored_bank == -1)
219 return i;
220
221 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
222 return i;
223 }
224 }
225 return -1;
226 }
227
228 static void
229 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
230 {
231 int mirrored_bank;
232
233 if (reg >= 0) {
234 rs->free_mask [bank] |= (regmask_t)1 << reg;
235 rs->symbolic [bank][reg] = 0;
236
237 mirrored_bank = get_mirrored_bank (bank);
238 if (mirrored_bank == -1)
239 return;
240 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
241 rs->symbolic [mirrored_bank][reg] = 0;
242 }
243 }
244
245 const char*
246 mono_regname_full (int reg, int bank)
247 {
248 if (G_UNLIKELY (bank)) {
249 #if MONO_ARCH_NEED_SIMD_BANK
250 if (bank == MONO_REG_SIMD)
251 return mono_arch_xregname (reg);
252 #endif
253 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
254 return mono_arch_regname (reg);
255 g_assert (bank == MONO_REG_DOUBLE);
256 return mono_arch_fregname (reg);
257 } else {
258 return mono_arch_regname (reg);
259 }
260 }
261
262 void
263 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
264 {
265 guint32 regpair;
266
267 regpair = (((guint32)hreg) << 24) + vreg;
268 if (G_UNLIKELY (bank)) {
269 g_assert (vreg >= regbank_size [bank]);
270 g_assert (hreg < regbank_size [bank]);
271 call->used_fregs |= (regmask_t)1 << hreg;
272 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
273 } else {
274 g_assert (vreg >= MONO_MAX_IREGS);
275 g_assert (hreg < MONO_MAX_IREGS);
276 call->used_iregs |= (regmask_t)1 << hreg;
277 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
278 }
279 }
280
281 /*
282 * mono_call_inst_add_outarg_vt:
283 *
284 * Register OUTARG_VT as belonging to CALL.
285 */
286 void
287 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
288 {
289 call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
290 }
291
292 static void
293 resize_spill_info (MonoCompile *cfg, int bank)
294 {
295 MonoSpillInfo *orig_info = cfg->spill_info [bank];
296 int orig_len = cfg->spill_info_len [bank];
297 int new_len = orig_len ? orig_len * 2 : 16;
298 MonoSpillInfo *new_info;
299 int i;
300
301 g_assert (bank < MONO_NUM_REGBANKS);
302
303 new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
304 if (orig_info)
305 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
306 for (i = orig_len; i < new_len; ++i)
307 new_info [i].offset = -1;
308
309 cfg->spill_info [bank] = new_info;
310 cfg->spill_info_len [bank] = new_len;
311 }
312
313 /*
314 * returns the offset used by spillvar. It allocates a new
315 * spill variable if necessary.
316 */
317 static int
318 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
319 {
320 MonoSpillInfo *info;
321 int size;
322
323 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
324 while (spillvar >= cfg->spill_info_len [bank])
325 resize_spill_info (cfg, bank);
326 }
327
328 /*
329 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
330 */
331 info = &cfg->spill_info [bank][spillvar];
332 if (info->offset == -1) {
333 cfg->stack_offset += sizeof (target_mgreg_t) - 1;
334 cfg->stack_offset &= ~(sizeof (target_mgreg_t) - 1);
335
336 g_assert (bank < MONO_NUM_REGBANKS);
337 if (G_UNLIKELY (bank))
338 size = regbank_spill_var_size [bank];
339 else
340 size = sizeof (target_mgreg_t);
341
342 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
343 cfg->stack_offset += size - 1;
344 cfg->stack_offset &= ~(size - 1);
345 info->offset = cfg->stack_offset;
346 cfg->stack_offset += size;
347 } else {
348 cfg->stack_offset += size - 1;
349 cfg->stack_offset &= ~(size - 1);
350 cfg->stack_offset += size;
351 info->offset = - cfg->stack_offset;
352 }
353 }
354
355 return info->offset;
356 }
357
358 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
359 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
360 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
361 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
362 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
363 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
364
365 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
366 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
367 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
368 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
369 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
370
371 #ifndef MONO_ARCH_INST_IS_FLOAT
372 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
373 #endif
374
375 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
376 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
377 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
378 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
379 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
380
381 #define reg_is_simd(desc) ((desc) == 'x')
382
383 #ifdef MONO_ARCH_NEED_SIMD_BANK
384
385 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
386
387 #else
388
389 #define reg_bank(desc) reg_is_fp ((desc))
390
391 #endif
392
393 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
394 #define sreg1_bank(spec) sreg_bank (0, (spec))
395 #define sreg2_bank(spec) sreg_bank (1, (spec))
396 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
397
398 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
399 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
400 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
401 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
402
403 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
404
405 #ifdef MONO_ARCH_IS_GLOBAL_IREG
406 #undef is_global_ireg
407 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
408 #endif
409
410 typedef struct {
411 int born_in;
412 int killed_in;
413 /* Not (yet) used */
414 //int last_use;
415 //int prev_use;
416 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
417 } RegTrack;
418
419 #if !defined(DISABLE_LOGGING)
420
421 void
422 mono_print_ins_index (int i, MonoInst *ins)
423 {
424 GString *buf = mono_print_ins_index_strbuf (i, ins);
425 printf ("%s\n", buf->str);
426 g_string_free (buf, TRUE);
427 }
428
429 GString *
430 mono_print_ins_index_strbuf (int i, MonoInst *ins)
431 {
432 const char *spec = ins_get_spec (ins->opcode);
433 GString *sbuf = g_string_new (NULL);
434 int num_sregs, j;
435 int sregs [MONO_MAX_SRC_REGS];
436
437 if (i != -1)
438 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
439 else
440 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
441 if (spec == (gpointer)/*FIXME*/MONO_ARCH_CPU_SPEC) {
442 gboolean dest_base = FALSE;
443 switch (ins->opcode) {
444 case OP_STOREV_MEMBASE:
445 dest_base = TRUE;
446 break;
447 default:
448 break;
449 }
450
451 /* This is a lowered opcode */
452 if (ins->dreg != -1) {
453 if (dest_base)
454 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
455 else
456 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
457 }
458 if (ins->sreg1 != -1)
459 g_string_append_printf (sbuf, " R%d", ins->sreg1);
460 if (ins->sreg2 != -1)
461 g_string_append_printf (sbuf, " R%d", ins->sreg2);
462 if (ins->sreg3 != -1)
463 g_string_append_printf (sbuf, " R%d", ins->sreg3);
464
465 switch (ins->opcode) {
466 case OP_LBNE_UN:
467 case OP_LBEQ:
468 case OP_LBLT:
469 case OP_LBLT_UN:
470 case OP_LBGT:
471 case OP_LBGT_UN:
472 case OP_LBGE:
473 case OP_LBGE_UN:
474 case OP_LBLE:
475 case OP_LBLE_UN:
476 if (!ins->inst_false_bb)
477 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
478 else
479 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
480 break;
481 case OP_PHI:
482 case OP_VPHI:
483 case OP_XPHI:
484 case OP_FPHI: {
485 int i;
486 g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
487 for (i = 0; i < ins->inst_phi_args [0]; i++) {
488 if (i)
489 g_string_append_printf (sbuf, ", ");
490 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
491 }
492 g_string_append_printf (sbuf, ")]");
493 break;
494 }
495 case OP_LDADDR:
496 case OP_OUTARG_VTRETADDR:
497 g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
498 break;
499 case OP_REGOFFSET:
500 case OP_GSHAREDVT_ARG_REGOFFSET:
501 g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
502 break;
503 case OP_ISINST:
504 case OP_CASTCLASS:
505 g_string_append_printf (sbuf, " %s", m_class_get_name (ins->klass));
506 break;
507 default:
508 break;
509 }
510
511 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
512 return sbuf;
513 }
514
515 if (spec [MONO_INST_DEST]) {
516 int bank = dreg_bank (spec);
517 if (is_soft_reg (ins->dreg, bank)) {
518 if (spec [MONO_INST_DEST] == 'b') {
519 if (ins->inst_offset == 0)
520 g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
521 else
522 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
523 }
524 else
525 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
526 } else if (spec [MONO_INST_DEST] == 'b') {
527 if (ins->inst_offset == 0)
528 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
529 else
530 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
531 } else
532 g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
533 }
534 if (spec [MONO_INST_SRC1]) {
535 int bank = sreg1_bank (spec);
536 if (is_soft_reg (ins->sreg1, bank)) {
537 if (spec [MONO_INST_SRC1] == 'b')
538 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
539 else
540 g_string_append_printf (sbuf, " R%d", ins->sreg1);
541 } else if (spec [MONO_INST_SRC1] == 'b')
542 g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
543 else
544 g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
545 }
546 num_sregs = mono_inst_get_src_registers (ins, sregs);
547 for (j = 1; j < num_sregs; ++j) {
548 int bank = sreg_bank (j, spec);
549 if (is_soft_reg (sregs [j], bank))
550 g_string_append_printf (sbuf, " R%d", sregs [j]);
551 else
552 g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
553 }
554
555 switch (ins->opcode) {
556 case OP_ICONST:
557 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
558 break;
559 #if defined(TARGET_X86) || defined(TARGET_AMD64)
560 case OP_X86_PUSH_IMM:
561 #endif
562 case OP_ICOMPARE_IMM:
563 case OP_COMPARE_IMM:
564 case OP_IADD_IMM:
565 case OP_ISUB_IMM:
566 case OP_IAND_IMM:
567 case OP_IOR_IMM:
568 case OP_IXOR_IMM:
569 case OP_SUB_IMM:
570 case OP_MUL_IMM:
571 case OP_STORE_MEMBASE_IMM:
572 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
573 break;
574 case OP_ADD_IMM:
575 case OP_LADD_IMM:
576 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
577 break;
578 case OP_I8CONST:
579 g_string_append_printf (sbuf, " [%" PRId64 "]", (gint64)ins->inst_l);
580 break;
581 case OP_R8CONST:
582 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
583 break;
584 case OP_R4CONST:
585 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
586 break;
587 case OP_CALL:
588 case OP_CALL_MEMBASE:
589 case OP_CALL_REG:
590 case OP_FCALL:
591 case OP_LCALL:
592 case OP_VCALL:
593 case OP_VCALL_REG:
594 case OP_VCALL_MEMBASE:
595 case OP_VCALL2:
596 case OP_VCALL2_REG:
597 case OP_VCALL2_MEMBASE:
598 case OP_VOIDCALL:
599 case OP_VOIDCALL_MEMBASE:
600 case OP_TAILCALL:
601 case OP_TAILCALL_MEMBASE:
602 case OP_RCALL:
603 case OP_RCALL_REG:
604 case OP_RCALL_MEMBASE: {
605 MonoCallInst *call = (MonoCallInst*)ins;
606 GSList *list;
607 MonoJitICallId jit_icall_id;
608 MonoMethod *method;
609
610 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
611 /*
612 * These are lowered opcodes, but they are in the .md files since the old
613 * JIT passes them to backends.
614 */
615 if (ins->dreg != -1)
616 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
617 }
618
619 if ((method = call->method)) {
620 char *full_name = mono_method_get_full_name (method);
621 g_string_append_printf (sbuf, " [%s]", full_name);
622 g_free (full_name);
623 } else if (call->fptr_is_patch) {
624 MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
625
626 g_string_append_printf (sbuf, " ");
627 mono_print_ji (ji);
628 } else if ((jit_icall_id = call->jit_icall_id)) {
629 g_string_append_printf (sbuf, " [%s]", mono_find_jit_icall_info (jit_icall_id)->name);
630 }
631
632 list = call->out_ireg_args;
633 while (list) {
634 guint32 regpair;
635 int reg, hreg;
636
637 regpair = (guint32)(gssize)(list->data);
638 hreg = regpair >> 24;
639 reg = regpair & 0xffffff;
640
641 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
642
643 list = g_slist_next (list);
644 }
645 list = call->out_freg_args;
646 while (list) {
647 guint32 regpair;
648 int reg, hreg;
649
650 regpair = (guint32)(gssize)(list->data);
651 hreg = regpair >> 24;
652 reg = regpair & 0xffffff;
653
654 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
655
656 list = g_slist_next (list);
657 }
658 break;
659 }
660 case OP_BR:
661 case OP_CALL_HANDLER:
662 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
663 break;
664 case OP_IBNE_UN:
665 case OP_IBEQ:
666 case OP_IBLT:
667 case OP_IBLT_UN:
668 case OP_IBGT:
669 case OP_IBGT_UN:
670 case OP_IBGE:
671 case OP_IBGE_UN:
672 case OP_IBLE:
673 case OP_IBLE_UN:
674 case OP_LBNE_UN:
675 case OP_LBEQ:
676 case OP_LBLT:
677 case OP_LBLT_UN:
678 case OP_LBGT:
679 case OP_LBGT_UN:
680 case OP_LBGE:
681 case OP_LBGE_UN:
682 case OP_LBLE:
683 case OP_LBLE_UN:
684 if (!ins->inst_false_bb)
685 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
686 else
687 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
688 break;
689 case OP_LIVERANGE_START:
690 case OP_LIVERANGE_END:
691 case OP_GC_LIVENESS_DEF:
692 case OP_GC_LIVENESS_USE:
693 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
694 break;
695 case OP_IL_SEQ_POINT:
696 case OP_SEQ_POINT:
697 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
698 break;
699 case OP_COND_EXC_EQ:
700 case OP_COND_EXC_GE:
701 case OP_COND_EXC_GT:
702 case OP_COND_EXC_LE:
703 case OP_COND_EXC_LT:
704 case OP_COND_EXC_NE_UN:
705 case OP_COND_EXC_GE_UN:
706 case OP_COND_EXC_GT_UN:
707 case OP_COND_EXC_LE_UN:
708 case OP_COND_EXC_LT_UN:
709 case OP_COND_EXC_OV:
710 case OP_COND_EXC_NO:
711 case OP_COND_EXC_C:
712 case OP_COND_EXC_NC:
713 case OP_COND_EXC_IEQ:
714 case OP_COND_EXC_IGE:
715 case OP_COND_EXC_IGT:
716 case OP_COND_EXC_ILE:
717 case OP_COND_EXC_ILT:
718 case OP_COND_EXC_INE_UN:
719 case OP_COND_EXC_IGE_UN:
720 case OP_COND_EXC_IGT_UN:
721 case OP_COND_EXC_ILE_UN:
722 case OP_COND_EXC_ILT_UN:
723 case OP_COND_EXC_IOV:
724 case OP_COND_EXC_INO:
725 case OP_COND_EXC_IC:
726 case OP_COND_EXC_INC:
727 g_string_append_printf (sbuf, " %s", (const char*)ins->inst_p1);
728 break;
729 default:
730 break;
731 }
732
733 if (spec [MONO_INST_CLOB])
734 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
735 return sbuf;
736 }
737
738 static void
739 print_regtrack (RegTrack *t, int num)
740 {
741 int i;
742 char buf [32];
743 const char *r;
744
745 for (i = 0; i < num; ++i) {
746 if (!t [i].born_in)
747 continue;
748 if (i >= MONO_MAX_IREGS) {
749 g_snprintf (buf, sizeof (buf), "R%d", i);
750 r = buf;
751 } else
752 r = mono_arch_regname (i);
753 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
754 }
755 }
756 #else
757
758 void
759 mono_print_ins_index (int i, MonoInst *ins)
760 {
761 }
762 #endif /* !defined(DISABLE_LOGGING) */
763
764 void
765 mono_print_ins (MonoInst *ins)
766 {
767 mono_print_ins_index (-1, ins);
768 }
769
770 static void
771 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
772 {
773 /*
774 * If this function is called multiple times, the new instructions are inserted
775 * in the proper order.
776 */
777 mono_bblock_insert_before_ins (bb, ins, to_insert);
778 }
779
780 static void
781 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
782 {
783 /*
784 * If this function is called multiple times, the new instructions are inserted in
785 * proper order.
786 */
787 mono_bblock_insert_after_ins (bb, *last, to_insert);
788
789 *last = to_insert;
790 }
791
792 static int
793 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
794 {
795 if (vreg_is_ref (cfg, reg))
796 return MONO_REG_INT_REF;
797 else if (vreg_is_mp (cfg, reg))
798 return MONO_REG_INT_MP;
799 else
800 return bank;
801 }
802
803 /*
804 * Force the spilling of the variable in the symbolic register 'reg', and free
805 * the hreg it was assigned to.
806 */
807 static void
808 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
809 {
810 MonoInst *load;
811 int i, sel, spill;
812 MonoRegState *rs = cfg->rs;
813
814 sel = rs->vassign [reg];
815
816 /* the vreg we need to spill lives in another logical reg bank */
817 bank = translate_bank (cfg->rs, bank, sel);
818
819 /*i = rs->isymbolic [sel];
820 g_assert (i == reg);*/
821 i = reg;
822 spill = ++cfg->spill_count;
823 rs->vassign [i] = -spill - 1;
824 if (G_UNLIKELY (bank))
825 mono_regstate_free_general (rs, sel, bank);
826 else
827 mono_regstate_free_int (rs, sel);
828 /* we need to create a spill var and insert a load to sel after the current instruction */
829 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
830 load->dreg = sel;
831 load->inst_basereg = cfg->frame_reg;
832 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
833 insert_after_ins (bb, ins, last, load);
834 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
835 if (G_UNLIKELY (bank))
836 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
837 else
838 i = mono_regstate_alloc_int (rs, regmask (sel));
839 g_assert (i == sel);
840
841 if (G_UNLIKELY (bank))
842 mono_regstate_free_general (rs, sel, bank);
843 else
844 mono_regstate_free_int (rs, sel);
845 }
846
847 static int
848 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
849 {
850 MonoInst *load;
851 int i, sel, spill, num_sregs;
852 int sregs [MONO_MAX_SRC_REGS];
853 MonoRegState *rs = cfg->rs;
854
855 g_assert (bank < MONO_NUM_REGBANKS);
856
857 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" PRIu64 " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
858 /* exclude the registers in the current instruction */
859 num_sregs = mono_inst_get_src_registers (ins, sregs);
860 for (i = 0; i < num_sregs; ++i) {
861 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
862 if (is_soft_reg (sregs [i], bank))
863 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
864 else
865 regmask &= ~ (regmask (sregs [i]));
866 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
867 }
868 }
869 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
870 regmask &= ~ (regmask (ins->dreg));
871 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
872 }
873
874 DEBUG (printf ("\t\tavailable regmask: 0x%08" PRIu64 "\n", (guint64)regmask));
875 g_assert (regmask); /* need at least a register we can free */
876 sel = 0;
877 /* we should track prev_use and spill the register that's farther */
878 if (G_UNLIKELY (bank)) {
879 for (i = 0; i < regbank_size [bank]; ++i) {
880 if (regmask & (regmask (i))) {
881 sel = i;
882
883 /* the vreg we need to load lives in another logical bank */
884 bank = translate_bank (cfg->rs, bank, sel);
885
886 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
887 break;
888 }
889 }
890
891 i = rs->symbolic [bank] [sel];
892 spill = ++cfg->spill_count;
893 rs->vassign [i] = -spill - 1;
894 mono_regstate_free_general (rs, sel, bank);
895 }
896 else {
897 for (i = 0; i < MONO_MAX_IREGS; ++i) {
898 if (regmask & (regmask (i))) {
899 sel = i;
900 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
901 break;
902 }
903 }
904
905 i = rs->isymbolic [sel];
906 spill = ++cfg->spill_count;
907 rs->vassign [i] = -spill - 1;
908 mono_regstate_free_int (rs, sel);
909 }
910
911 /* we need to create a spill var and insert a load to sel after the current instruction */
912 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
913 load->dreg = sel;
914 load->inst_basereg = cfg->frame_reg;
915 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
916 insert_after_ins (bb, ins, last, load);
917 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
918 if (G_UNLIKELY (bank))
919 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
920 else
921 i = mono_regstate_alloc_int (rs, regmask (sel));
922 g_assert (i == sel);
923
924 return sel;
925 }
926
927 /*
928 * free_up_hreg:
929 *
930 * Free up the hreg HREG by spilling the vreg allocated to it.
931 */
932 static void
933 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
934 {
935 if (G_UNLIKELY (bank)) {
936 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
937 bank = translate_bank (cfg->rs, bank, hreg);
938 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
939 spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
940 }
941 }
942 else {
943 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
944 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
945 spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
946 }
947 }
948 }
949
950 static MonoInst*
951 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
952 {
953 MonoInst *copy;
954
955 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
956
957 copy->dreg = dest;
958 copy->sreg1 = src;
959 copy->cil_code = ip;
960 if (ins) {
961 mono_bblock_insert_after_ins (bb, ins, copy);
962 *last = copy;
963 }
964 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
965 return copy;
966 }
967
968 static const char*
969 regbank_to_string (int bank)
970 {
971 if (bank == MONO_REG_INT_REF)
972 return "REF ";
973 else if (bank == MONO_REG_INT_MP)
974 return "MP ";
975 else
976 return "";
977 }
978
979 static void
980 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
981 {
982 MonoInst *store, *def;
983
984 bank = get_vreg_bank (cfg, prev_reg, bank);
985
986 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
987 store->sreg1 = reg;
988 store->inst_destbasereg = cfg->frame_reg;
989 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
990 if (ins) {
991 mono_bblock_insert_after_ins (bb, ins, store);
992 *last = store;
993 } else if (insert_before) {
994 insert_before_ins (bb, insert_before, store);
995 } else {
996 g_assert_not_reached ();
997 }
998 DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
999
1000 if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1001 g_assert (prev_reg != -1);
1002 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1003 def->inst_c0 = spill;
1004 def->inst_c1 = bank;
1005 mono_bblock_insert_after_ins (bb, store, def);
1006 }
1007 }
1008
1009 /* flags used in reginfo->flags */
1010 enum {
1011 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
1012 MONO_FP_NEEDS_SPILL = regmask (1),
1013 MONO_FP_NEEDS_LOAD = regmask (2)
1014 };
1015
1016 static int
1017 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1018 {
1019 int val;
1020
1021 if (info && info->preferred_mask) {
1022 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1023 if (val >= 0) {
1024 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1025 return val;
1026 }
1027 }
1028
1029 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1030 if (val < 0)
1031 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1032
1033 return val;
1034 }
1035
1036 static int
1037 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1038 {
1039 int val;
1040
1041 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1042
1043 if (val < 0)
1044 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1045
1046 #ifdef MONO_ARCH_HAVE_TRACK_FPREGS
1047 cfg->arch.used_fp_regs |= 1 << val;
1048 #endif
1049 return val;
1050 }
1051
1052 static int
1053 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1054 {
1055 if (G_UNLIKELY (bank))
1056 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1057 else
1058 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1059 }
1060
1061 static void
1062 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1063 {
1064 if (G_UNLIKELY (bank)) {
1065 int mirrored_bank;
1066
1067 g_assert (reg >= regbank_size [bank]);
1068 g_assert (hreg < regbank_size [bank]);
1069 g_assert (! is_global_freg (hreg));
1070
1071 rs->vassign [reg] = hreg;
1072 rs->symbolic [bank] [hreg] = reg;
1073 rs->free_mask [bank] &= ~ (regmask (hreg));
1074
1075 mirrored_bank = get_mirrored_bank (bank);
1076 if (mirrored_bank == -1)
1077 return;
1078
1079 /* Make sure the other logical reg bank that this bank shares
1080 * a single hard reg bank knows that this hard reg is not free.
1081 */
1082 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1083
1084 /* Mark the other logical bank that the this bank shares
1085 * a single hard reg bank with as mirrored.
1086 */
1087 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1088
1089 }
1090 else {
1091 g_assert (reg >= MONO_MAX_IREGS);
1092 g_assert (hreg < MONO_MAX_IREGS);
1093 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1094 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1095 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1096 g_assert (! is_global_ireg (hreg));
1097 #endif
1098
1099 rs->vassign [reg] = hreg;
1100 rs->isymbolic [hreg] = reg;
1101 rs->ifree_mask &= ~ (regmask (hreg));
1102 }
1103 }
1104
1105 static regmask_t
1106 get_callee_mask (const char spec)
1107 {
1108 if (G_UNLIKELY (reg_bank (spec)))
1109 return regbank_callee_regs [reg_bank (spec)];
1110 return MONO_ARCH_CALLEE_REGS;
1111 }
1112
1113 static gint8 desc_to_fixed_reg [256];
1114 static gboolean desc_to_fixed_reg_inited = FALSE;
1115
1116 /*
1117 * Local register allocation.
1118 * We first scan the list of instructions and we save the liveness info of
1119 * each register (when the register is first used, when it's value is set etc.).
1120 * We also reverse the list of instructions because assigning registers backwards allows
1121 * for more tricks to be used.
1122 */
1123 void
1124 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1125 {
1126 MonoInst *ins, *prev, *last;
1127 MonoInst **tmp;
1128 MonoRegState *rs = cfg->rs;
1129 int i, j, val, max;
1130 RegTrack *reginfo;
1131 const char *spec;
1132 unsigned char spec_src1, spec_dest;
1133 int bank = 0;
1134 #if MONO_ARCH_USE_FPSTACK
1135 gboolean has_fp = FALSE;
1136 int fpstack [8];
1137 int sp = 0;
1138 #endif
1139 int num_sregs = 0;
1140 int sregs [MONO_MAX_SRC_REGS];
1141
1142 if (!bb->code)
1143 return;
1144
1145 if (!desc_to_fixed_reg_inited) {
1146 for (i = 0; i < 256; ++i)
1147 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1148 desc_to_fixed_reg_inited = TRUE;
1149
1150 /* Validate the cpu description against the info in mini-ops.h */
1151 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64) || defined (TARGET_RISCV)
1152 for (i = OP_LOAD; i < OP_LAST; ++i) {
1153 const char *ispec;
1154
1155 spec = ins_get_spec (i);
1156 ispec = INS_INFO (i);
1157
1158 if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1159 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1160 if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1161 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1162 if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1163 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1164 }
1165 #endif
1166 }
1167
1168 rs->next_vreg = bb->max_vreg;
1169 mono_regstate_assign (rs);
1170
1171 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1172 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1173 rs->free_mask [i] = regbank_callee_regs [i];
1174
1175 max = rs->next_vreg;
1176
1177 if (cfg->reginfo && cfg->reginfo_len < max)
1178 cfg->reginfo = NULL;
1179
1180 reginfo = (RegTrack *)cfg->reginfo;
1181 if (!reginfo) {
1182 cfg->reginfo_len = MAX (1024, max * 2);
1183 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1184 cfg->reginfo = reginfo;
1185 }
1186 else
1187 g_assert (cfg->reginfo_len >= rs->next_vreg);
1188
1189 if (cfg->verbose_level > 1) {
1190 /* print_regtrack reads the info of all variables */
1191 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1192 }
1193
1194 /*
1195 * For large methods, next_vreg can be very large, so g_malloc0 time can
1196 * be prohibitive. So we manually init the reginfo entries used by the
1197 * bblock.
1198 */
1199 for (ins = bb->code; ins; ins = ins->next) {
1200 gboolean modify = FALSE;
1201
1202 spec = ins_get_spec (ins->opcode);
1203
1204 if ((ins->dreg != -1) && (ins->dreg < max)) {
1205 memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1206 #if SIZEOF_REGISTER == 4
1207 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1208 /**
1209 * In the new IR, the two vregs of the regpair do not alias the
1210 * original long vreg. shift the vreg here so the rest of the
1211 * allocator doesn't have to care about it.
1212 */
1213 ins->dreg ++;
1214 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1215 }
1216 #endif
1217 }
1218
1219 num_sregs = mono_inst_get_src_registers (ins, sregs);
1220 for (j = 0; j < num_sregs; ++j) {
1221 g_assert (sregs [j] != -1);
1222 if (sregs [j] < max) {
1223 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1224 #if SIZEOF_REGISTER == 4
1225 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1226 sregs [j]++;
1227 modify = TRUE;
1228 memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1229 }
1230 #endif
1231 }
1232 }
1233 if (modify)
1234 mono_inst_set_src_registers (ins, sregs);
1235 }
1236
1237 /*if (cfg->opt & MONO_OPT_COPYPROP)
1238 local_copy_prop (cfg, ins);*/
1239
1240 i = 1;
1241 DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1242 /* forward pass on the instructions to collect register liveness info */
1243 MONO_BB_FOR_EACH_INS (bb, ins) {
1244 spec = ins_get_spec (ins->opcode);
1245 spec_dest = spec [MONO_INST_DEST];
1246
1247 if (G_UNLIKELY (spec == (gpointer)/*FIXME*/MONO_ARCH_CPU_SPEC)) {
1248 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1249 }
1250
1251 DEBUG (mono_print_ins_index (i, ins));
1252
1253 num_sregs = mono_inst_get_src_registers (ins, sregs);
1254
1255 #if MONO_ARCH_USE_FPSTACK
1256 if (dreg_is_fp (spec)) {
1257 has_fp = TRUE;
1258 } else {
1259 for (j = 0; j < num_sregs; ++j) {
1260 if (sreg_is_fp (j, spec))
1261 has_fp = TRUE;
1262 }
1263 }
1264 #endif
1265
1266 for (j = 0; j < num_sregs; ++j) {
1267 int sreg = sregs [j];
1268 int sreg_spec = spec [MONO_INST_SRC1 + j];
1269 if (sreg_spec) {
1270 bank = sreg_bank (j, spec);
1271 g_assert (sreg != -1);
1272 if (is_soft_reg (sreg, bank))
1273 /* This means the vreg is not local to this bb */
1274 g_assert (reginfo [sreg].born_in > 0);
1275 rs->vassign [sreg] = -1;
1276 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1277 //reginfo [ins->sreg2].last_use = i;
1278 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1279 /* The virtual register is allocated sequentially */
1280 rs->vassign [sreg + 1] = -1;
1281 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1282 //reginfo [ins->sreg2 + 1].last_use = i;
1283 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1284 reginfo [sreg + 1].born_in = i;
1285 }
1286 } else {
1287 sregs [j] = -1;
1288 }
1289 }
1290 mono_inst_set_src_registers (ins, sregs);
1291
1292 if (spec_dest) {
1293 int dest_dreg;
1294
1295 bank = dreg_bank (spec);
1296 if (spec_dest != 'b') /* it's not just a base register */
1297 reginfo [ins->dreg].killed_in = i;
1298 g_assert (ins->dreg != -1);
1299 rs->vassign [ins->dreg] = -1;
1300 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1301 //reginfo [ins->dreg].last_use = i;
1302 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1303 reginfo [ins->dreg].born_in = i;
1304
1305 dest_dreg = desc_to_fixed_reg [spec_dest];
1306 if (dest_dreg != -1)
1307 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1308
1309 #ifdef MONO_ARCH_INST_FIXED_MASK
1310 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1311 #endif
1312
1313 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1314 /* The virtual register is allocated sequentially */
1315 rs->vassign [ins->dreg + 1] = -1;
1316 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1317 //reginfo [ins->dreg + 1].last_use = i;
1318 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1319 reginfo [ins->dreg + 1].born_in = i;
1320 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1321 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1322 }
1323 } else {
1324 ins->dreg = -1;
1325 }
1326
1327 ++i;
1328 }
1329
1330 tmp = &last;
1331
1332 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1333 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1334 int prev_dreg;
1335 int dest_dreg, clob_reg;
1336 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1337 int dreg_high, sreg1_high;
1338 regmask_t dreg_mask, mask;
1339 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1340 regmask_t dreg_fixed_mask;
1341 const unsigned char *ip;
1342 --i;
1343 spec = ins_get_spec (ins->opcode);
1344 spec_src1 = spec [MONO_INST_SRC1];
1345 spec_dest = spec [MONO_INST_DEST];
1346 prev_dreg = -1;
1347 clob_reg = -1;
1348 dest_dreg = -1;
1349 dreg_high = -1;
1350 sreg1_high = -1;
1351 dreg_mask = get_callee_mask (spec_dest);
1352 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1353 prev_sregs [j] = -1;
1354 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1355 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1356 #ifdef MONO_ARCH_INST_FIXED_MASK
1357 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1358 #else
1359 sreg_fixed_masks [j] = 0;
1360 #endif
1361 }
1362
1363 DEBUG (printf ("processing:"));
1364 DEBUG (mono_print_ins_index (i, ins));
1365
1366 ip = ins->cil_code;
1367
1368 last = ins;
1369
1370 /*
1371 * FIXED REGS
1372 */
1373 dest_dreg = desc_to_fixed_reg [spec_dest];
1374 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1375 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1376
1377 #ifdef MONO_ARCH_INST_FIXED_MASK
1378 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1379 #else
1380 dreg_fixed_mask = 0;
1381 #endif
1382
1383 num_sregs = mono_inst_get_src_registers (ins, sregs);
1384
1385 /*
1386 * TRACK FIXED SREG2, 3, ...
1387 */
1388 for (j = 1; j < num_sregs; ++j) {
1389 int sreg = sregs [j];
1390 int dest_sreg = dest_sregs [j];
1391
1392 if (dest_sreg == -1)
1393 continue;
1394
1395 if (j == 2) {
1396 int k;
1397
1398 /*
1399 * CAS.
1400 * We need to special case this, since on x86, there are only 3
1401 * free registers, and the code below assigns one of them to
1402 * sreg, so we can run out of registers when trying to assign
1403 * dreg. Instead, we just set up the register masks, and let the
1404 * normal sreg2 assignment code handle this. It would be nice to
1405 * do this for all the fixed reg cases too, but there is too much
1406 * risk of breakage.
1407 */
1408
1409 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1410 sreg_masks [j] = regmask (dest_sreg);
1411 for (k = 0; k < num_sregs; ++k) {
1412 if (k != j)
1413 sreg_masks [k] &= ~ (regmask (dest_sreg));
1414 }
1415
1416 /*
1417 * Spill sreg1/2 if they are assigned to dest_sreg.
1418 */
1419 for (k = 0; k < num_sregs; ++k) {
1420 if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1421 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1422 }
1423
1424 /*
1425 * We can also run out of registers while processing sreg2 if sreg3 is
1426 * assigned to another hreg, so spill sreg3 now.
1427 */
1428 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1429 spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1430 }
1431 continue;
1432 }
1433
1434 if (rs->ifree_mask & (regmask (dest_sreg))) {
1435 if (is_global_ireg (sreg)) {
1436 int k;
1437 /* Argument already in hard reg, need to copy */
1438 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1439 insert_before_ins (bb, ins, copy);
1440 for (k = 0; k < num_sregs; ++k) {
1441 if (k != j)
1442 sreg_masks [k] &= ~ (regmask (dest_sreg));
1443 }
1444 /* See below */
1445 dreg_mask &= ~ (regmask (dest_sreg));
1446 } else {
1447 val = rs->vassign [sreg];
1448 if (val == -1) {
1449 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1450 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1451 } else if (val < -1) {
1452 /* FIXME: */
1453 g_assert_not_reached ();
1454 } else {
1455 /* Argument already in hard reg, need to copy */
1456 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1457 int k;
1458
1459 insert_before_ins (bb, ins, copy);
1460 for (k = 0; k < num_sregs; ++k) {
1461 if (k != j)
1462 sreg_masks [k] &= ~ (regmask (dest_sreg));
1463 }
1464 /*
1465 * Prevent the dreg from being allocated to dest_sreg
1466 * too, since it could force sreg1 to be allocated to
1467 * the same reg on x86.
1468 */
1469 dreg_mask &= ~ (regmask (dest_sreg));
1470 }
1471 }
1472 } else {
1473 gboolean need_spill = TRUE;
1474 gboolean need_assign = TRUE;
1475 int k;
1476
1477 dreg_mask &= ~ (regmask (dest_sreg));
1478 for (k = 0; k < num_sregs; ++k) {
1479 if (k != j)
1480 sreg_masks [k] &= ~ (regmask (dest_sreg));
1481 }
1482
1483 /*
1484 * First check if dreg is assigned to dest_sreg2, since we
1485 * can't spill a dreg.
1486 */
1487 if (spec [MONO_INST_DEST])
1488 val = rs->vassign [ins->dreg];
1489 else
1490 val = -1;
1491 if (val == dest_sreg && ins->dreg != sreg) {
1492 /*
1493 * the destination register is already assigned to
1494 * dest_sreg2: we need to allocate another register for it
1495 * and then copy from this to dest_sreg2.
1496 */
1497 int new_dest;
1498 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1499 g_assert (new_dest >= 0);
1500 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1501
1502 prev_dreg = ins->dreg;
1503 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1504 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1505 mono_regstate_free_int (rs, dest_sreg);
1506 need_spill = FALSE;
1507 }
1508
1509 if (is_global_ireg (sreg)) {
1510 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1511 insert_before_ins (bb, ins, copy);
1512 need_assign = FALSE;
1513 }
1514 else {
1515 val = rs->vassign [sreg];
1516 if (val == dest_sreg) {
1517 /* sreg2 is already assigned to the correct register */
1518 need_spill = FALSE;
1519 } else if (val < -1) {
1520 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1521 } else if (val >= 0) {
1522 /* sreg2 already assigned to another register */
1523 /*
1524 * We couldn't emit a copy from val to dest_sreg2, because
1525 * val might be spilled later while processing this
1526 * instruction. So we spill sreg2 so it can be allocated to
1527 * dest_sreg2.
1528 */
1529 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1530 }
1531 }
1532
1533 if (need_spill) {
1534 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1535 }
1536
1537 if (need_assign) {
1538 if (rs->vassign [sreg] < -1) {
1539 int spill;
1540
1541 /* Need to emit a spill store */
1542 spill = - rs->vassign [sreg] - 1;
1543 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1544 }
1545 /* force-set sreg2 */
1546 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1547 }
1548 }
1549 sregs [j] = dest_sreg;
1550 }
1551 mono_inst_set_src_registers (ins, sregs);
1552
1553 /*
1554 * TRACK DREG
1555 */
1556 bank = dreg_bank (spec);
1557 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1558 prev_dreg = ins->dreg;
1559 }
1560
1561 if (spec_dest == 'b') {
1562 /*
1563 * The dest reg is read by the instruction, not written, so
1564 * avoid allocating sreg1/sreg2 to the same reg.
1565 */
1566 if (dest_sregs [0] != -1)
1567 dreg_mask &= ~ (regmask (dest_sregs [0]));
1568 for (j = 1; j < num_sregs; ++j) {
1569 if (dest_sregs [j] != -1)
1570 dreg_mask &= ~ (regmask (dest_sregs [j]));
1571 }
1572
1573 val = rs->vassign [ins->dreg];
1574 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1575 /* DREG is already allocated to a register needed for sreg1 */
1576 spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1577 }
1578 }
1579
1580 /*
1581 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1582 * various complex situations.
1583 */
1584 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1585 guint32 dreg2, dest_dreg2;
1586
1587 g_assert (is_soft_reg (ins->dreg, bank));
1588
1589 if (dest_dreg != -1) {
1590 if (rs->vassign [ins->dreg] != dest_dreg)
1591 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1592
1593 dreg2 = ins->dreg + 1;
1594 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1595 if (dest_dreg2 != -1) {
1596 if (rs->vassign [dreg2] != dest_dreg2)
1597 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1598 }
1599 }
1600 }
1601
1602 if (dreg_fixed_mask) {
1603 g_assert (!bank);
1604 if (is_global_ireg (ins->dreg)) {
1605 /*
1606 * The argument is already in a hard reg, but that reg is
1607 * not usable by this instruction, so allocate a new one.
1608 */
1609 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1610 if (val < 0)
1611 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1612 mono_regstate_free_int (rs, val);
1613 dest_dreg = val;
1614
1615 /* Fall through */
1616 }
1617 else
1618 dreg_mask &= dreg_fixed_mask;
1619 }
1620
1621 if (is_soft_reg (ins->dreg, bank)) {
1622 val = rs->vassign [ins->dreg];
1623
1624 if (val < 0) {
1625 int spill = 0;
1626 if (val < -1) {
1627 /* the register gets spilled after this inst */
1628 spill = -val -1;
1629 }
1630 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1631 assign_reg (cfg, rs, ins->dreg, val, bank);
1632 if (spill)
1633 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1634 }
1635
1636 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1637 ins->dreg = val;
1638 }
1639
1640 /* Handle regpairs */
1641 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1642 int reg2 = prev_dreg + 1;
1643
1644 g_assert (!bank);
1645 g_assert (prev_dreg > -1);
1646 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1647 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1648 #ifdef TARGET_X86
1649 /* bug #80489 */
1650 mask &= ~regmask (X86_ECX);
1651 #endif
1652 val = rs->vassign [reg2];
1653 if (val < 0) {
1654 int spill = 0;
1655 if (val < -1) {
1656 /* the register gets spilled after this inst */
1657 spill = -val -1;
1658 }
1659 val = mono_regstate_alloc_int (rs, mask);
1660 if (val < 0)
1661 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1662 if (spill)
1663 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1664 }
1665 else {
1666 if (! (mask & (regmask (val)))) {
1667 val = mono_regstate_alloc_int (rs, mask);
1668 if (val < 0)
1669 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1670
1671 /* Reallocate hreg to the correct register */
1672 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1673
1674 mono_regstate_free_int (rs, rs->vassign [reg2]);
1675 }
1676 }
1677
1678 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1679 assign_reg (cfg, rs, reg2, val, bank);
1680
1681 dreg_high = val;
1682 ins->backend.reg3 = val;
1683
1684 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1685 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1686 mono_regstate_free_int (rs, val);
1687 }
1688 }
1689
1690 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1691 /*
1692 * In theory, we could free up the hreg even if the vreg is alive,
1693 * but branches inside bblocks force us to assign the same hreg
1694 * to a vreg every time it is encountered.
1695 */
1696 int dreg = rs->vassign [prev_dreg];
1697 g_assert (dreg >= 0);
1698 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1699 if (G_UNLIKELY (bank))
1700 mono_regstate_free_general (rs, dreg, bank);
1701 else
1702 mono_regstate_free_int (rs, dreg);
1703 rs->vassign [prev_dreg] = -1;
1704 }
1705
1706 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1707 /* this instruction only outputs to dest_dreg, need to copy */
1708 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1709 ins->dreg = dest_dreg;
1710
1711 if (G_UNLIKELY (bank)) {
1712 /* the register we need to free up may be used in another logical regbank
1713 * so do a translate just in case.
1714 */
1715 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1716 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1717 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1718 }
1719 else {
1720 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1721 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1722 }
1723 }
1724
1725 if (spec_dest == 'b') {
1726 /*
1727 * The dest reg is read by the instruction, not written, so
1728 * avoid allocating sreg1/sreg2 to the same reg.
1729 */
1730 for (j = 0; j < num_sregs; ++j)
1731 if (!sreg_bank (j, spec))
1732 sreg_masks [j] &= ~ (regmask (ins->dreg));
1733 }
1734
1735 /*
1736 * TRACK CLOBBERING
1737 */
1738 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1739 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1740 free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1741 }
1742
1743 if (spec [MONO_INST_CLOB] == 'c') {
1744 int j, s, dreg, dreg2, cur_bank;
1745 guint64 clob_mask;
1746
1747 clob_mask = MONO_ARCH_CALLEE_REGS;
1748
1749 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1750 /*
1751 * Need to avoid spilling the dreg since the dreg is not really
1752 * clobbered by the call.
1753 */
1754 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1755 dreg = rs->vassign [prev_dreg];
1756 else
1757 dreg = -1;
1758
1759 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1760 dreg2 = rs->vassign [prev_dreg + 1];
1761 else
1762 dreg2 = -1;
1763
1764 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1765 s = regmask (j);
1766 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1767 if ((j != dreg) && (j != dreg2))
1768 free_up_hreg (cfg, bb, tmp, ins, j, 0);
1769 else if (rs->isymbolic [j])
1770 /* The hreg is assigned to the dreg of this instruction */
1771 rs->vassign [rs->isymbolic [j]] = -1;
1772 mono_regstate_free_int (rs, j);
1773 }
1774 }
1775 }
1776
1777 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1778 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1779 clob_mask = regbank_callee_regs [cur_bank];
1780 if ((prev_dreg != -1) && reg_bank (spec_dest))
1781 dreg = rs->vassign [prev_dreg];
1782 else
1783 dreg = -1;
1784
1785 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1786
1787 /* we are looping though the banks in the outer loop
1788 * so, we don't need to deal with mirrored hregs
1789 * because we will get them in one of the other bank passes.
1790 */
1791 if (is_hreg_mirrored (rs, cur_bank, j))
1792 continue;
1793
1794 s = regmask (j);
1795 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1796 if (j != dreg)
1797 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1798 else if (rs->symbolic [cur_bank] [j])
1799 /* The hreg is assigned to the dreg of this instruction */
1800 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1801 mono_regstate_free_general (rs, j, cur_bank);
1802 }
1803 }
1804 }
1805 }
1806 }
1807
1808 /*
1809 * TRACK ARGUMENT REGS
1810 */
1811 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1812 MonoCallInst *call = (MonoCallInst*)ins;
1813 GSList *list;
1814
1815 /*
1816 * This needs to be done before assigning sreg1, so sreg1 will
1817 * not be assigned one of the argument regs.
1818 */
1819
1820 /*
1821 * Assign all registers in call->out_reg_args to the proper
1822 * argument registers.
1823 */
1824
1825 list = call->out_ireg_args;
1826 if (list) {
1827 while (list) {
1828 guint32 regpair;
1829 int reg, hreg;
1830
1831 regpair = (guint32)(gssize)(list->data);
1832 hreg = regpair >> 24;
1833 reg = regpair & 0xffffff;
1834
1835 assign_reg (cfg, rs, reg, hreg, 0);
1836
1837 sreg_masks [0] &= ~(regmask (hreg));
1838
1839 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1840
1841 list = g_slist_next (list);
1842 }
1843 }
1844
1845 list = call->out_freg_args;
1846 if (list) {
1847 while (list) {
1848 guint32 regpair;
1849 int reg, hreg;
1850
1851 regpair = (guint32)(gssize)(list->data);
1852 hreg = regpair >> 24;
1853 reg = regpair & 0xffffff;
1854
1855 assign_reg (cfg, rs, reg, hreg, 1);
1856
1857 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1858
1859 list = g_slist_next (list);
1860 }
1861 }
1862 }
1863
1864 /*
1865 * TRACK SREG1
1866 */
1867 bank = sreg1_bank (spec);
1868 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1869 int sreg1 = sregs [0];
1870 int dest_sreg1 = dest_sregs [0];
1871
1872 g_assert (is_soft_reg (sreg1, bank));
1873
1874 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1875 if (dest_sreg1 != -1)
1876 g_assert (dest_sreg1 == ins->dreg);
1877 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1878 g_assert (val >= 0);
1879
1880 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1881 // FIXME:
1882 g_assert_not_reached ();
1883
1884 assign_reg (cfg, rs, sreg1, val, bank);
1885
1886 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1887
1888 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1889 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1890 g_assert (val >= 0);
1891
1892 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1893 // FIXME:
1894 g_assert_not_reached ();
1895
1896 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1897
1898 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1899
1900 /* Skip rest of this section */
1901 dest_sregs [0] = -1;
1902 }
1903
1904 if (sreg_fixed_masks [0]) {
1905 g_assert (!bank);
1906 if (is_global_ireg (sregs [0])) {
1907 /*
1908 * The argument is already in a hard reg, but that reg is
1909 * not usable by this instruction, so allocate a new one.
1910 */
1911 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1912 if (val < 0)
1913 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1914 mono_regstate_free_int (rs, val);
1915 dest_sregs [0] = val;
1916
1917 /* Fall through to the dest_sreg1 != -1 case */
1918 }
1919 else
1920 sreg_masks [0] &= sreg_fixed_masks [0];
1921 }
1922
1923 if (dest_sregs [0] != -1) {
1924 sreg_masks [0] = regmask (dest_sregs [0]);
1925
1926 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1927 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1928 }
1929 if (is_global_ireg (sregs [0])) {
1930 /* The argument is already in a hard reg, need to copy */
1931 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1932 insert_before_ins (bb, ins, copy);
1933 sregs [0] = dest_sregs [0];
1934 }
1935 }
1936
1937 if (is_soft_reg (sregs [0], bank)) {
1938 val = rs->vassign [sregs [0]];
1939 prev_sregs [0] = sregs [0];
1940 if (val < 0) {
1941 int spill = 0;
1942 if (val < -1) {
1943 /* the register gets spilled after this inst */
1944 spill = -val -1;
1945 }
1946
1947 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1948 /*
1949 * Allocate the same hreg to sreg1 as well so the
1950 * peephole can get rid of the move.
1951 */
1952 sreg_masks [0] = regmask (ins->dreg);
1953 }
1954
1955 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1956 /* Allocate the same reg to sreg1 to avoid a copy later */
1957 sreg_masks [0] = regmask (ins->dreg);
1958
1959 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1960 assign_reg (cfg, rs, sregs [0], val, bank);
1961 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1962
1963 if (spill) {
1964 /*
1965 * Need to insert before the instruction since it can
1966 * overwrite sreg1.
1967 */
1968 create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1969 }
1970 }
1971 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1972 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1973 insert_before_ins (bb, ins, copy);
1974 for (j = 1; j < num_sregs; ++j)
1975 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1976 val = dest_sregs [0];
1977 }
1978
1979 sregs [0] = val;
1980 }
1981 else {
1982 prev_sregs [0] = -1;
1983 }
1984 mono_inst_set_src_registers (ins, sregs);
1985
1986 for (j = 1; j < num_sregs; ++j)
1987 sreg_masks [j] &= ~(regmask (sregs [0]));
1988
1989 /* Handle the case when sreg1 is a regpair but dreg is not */
1990 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1991 int reg2 = prev_sregs [0] + 1;
1992
1993 g_assert (!bank);
1994 g_assert (prev_sregs [0] > -1);
1995 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1996 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1997 val = rs->vassign [reg2];
1998 if (val < 0) {
1999 int spill = 0;
2000 if (val < -1) {
2001 /* the register gets spilled after this inst */
2002 spill = -val -1;
2003 }
2004 val = mono_regstate_alloc_int (rs, mask);
2005 if (val < 0)
2006 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2007 if (spill)
2008 g_assert_not_reached ();
2009 }
2010 else {
2011 if (! (mask & (regmask (val)))) {
2012 /* The vreg is already allocated to a wrong hreg */
2013 /* FIXME: */
2014 g_assert_not_reached ();
2015 #if 0
2016 val = mono_regstate_alloc_int (rs, mask);
2017 if (val < 0)
2018 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2019
2020 /* Reallocate hreg to the correct register */
2021 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2022
2023 mono_regstate_free_int (rs, rs->vassign [reg2]);
2024 #endif
2025 }
2026 }
2027
2028 sreg1_high = val;
2029 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2030 assign_reg (cfg, rs, reg2, val, bank);
2031 }
2032
2033 /* Handle dreg==sreg1 */
2034 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2035 MonoInst *sreg2_copy = NULL;
2036 MonoInst *copy;
2037 int bank = reg_bank (spec_src1);
2038
2039 if (ins->dreg == sregs [1]) {
2040 /*
2041 * copying sreg1 to dreg could clobber sreg2, so allocate a new
2042 * register for it.
2043 */
2044 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2045
2046 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2047 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2048 prev_sregs [1] = sregs [1] = reg2;
2049
2050 if (G_UNLIKELY (bank))
2051 mono_regstate_free_general (rs, reg2, bank);
2052 else
2053 mono_regstate_free_int (rs, reg2);
2054 }
2055
2056 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2057 /* Copying sreg1_high to dreg could also clobber sreg2 */
2058 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2059 /* FIXME: */
2060 g_assert_not_reached ();
2061
2062 /*
2063 * sreg1 and dest are already allocated to the same regpair by the
2064 * SREG1 allocation code.
2065 */
2066 g_assert (sregs [0] == ins->dreg);
2067 g_assert (dreg_high == sreg1_high);
2068 }
2069
2070 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2071 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2072 insert_before_ins (bb, ins, copy);
2073
2074 if (sreg2_copy)
2075 insert_before_ins (bb, copy, sreg2_copy);
2076
2077 /*
2078 * Need to prevent sreg2 to be allocated to sreg1, since that
2079 * would screw up the previous copy.
2080 */
2081 sreg_masks [1] &= ~ (regmask (sregs [0]));
2082 /* we set sreg1 to dest as well */
2083 prev_sregs [0] = sregs [0] = ins->dreg;
2084 sreg_masks [1] &= ~ (regmask (ins->dreg));
2085 }
2086 mono_inst_set_src_registers (ins, sregs);
2087
2088 /*
2089 * TRACK SREG2, 3, ...
2090 */
2091 for (j = 1; j < num_sregs; ++j) {
2092 int k;
2093
2094 bank = sreg_bank (j, spec);
2095 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2096 g_assert_not_reached ();
2097
2098 if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2099 /*
2100 * Argument already in a global hard reg, copy it to the fixed reg, without
2101 * allocating it to the fixed reg.
2102 */
2103 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2104 insert_before_ins (bb, ins, copy);
2105 sregs [j] = dest_sregs [j];
2106 } else if (is_soft_reg (sregs [j], bank)) {
2107 val = rs->vassign [sregs [j]];
2108
2109 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2110 /*
2111 * The sreg is already allocated to a hreg, but not to the fixed
2112 * reg required by the instruction. Spill the sreg, so it can be
2113 * allocated to the fixed reg by the code below.
2114 */
2115 /* Currently, this code should only be hit for CAS */
2116 spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2117 val = rs->vassign [sregs [j]];
2118 }
2119
2120 if (val < 0) {
2121 int spill = 0;
2122 if (val < -1) {
2123 /* the register gets spilled after this inst */
2124 spill = -val -1;
2125 }
2126 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2127 assign_reg (cfg, rs, sregs [j], val, bank);
2128 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2129 if (spill) {
2130 /*
2131 * Need to insert before the instruction since it can
2132 * overwrite sreg2.
2133 */
2134 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2135 }
2136 }
2137 sregs [j] = val;
2138 for (k = j + 1; k < num_sregs; ++k)
2139 sreg_masks [k] &= ~ (regmask (sregs [j]));
2140 }
2141 else {
2142 prev_sregs [j] = -1;
2143 }
2144 }
2145 mono_inst_set_src_registers (ins, sregs);
2146
2147 /* Sanity check */
2148 /* Do this only for CAS for now */
2149 for (j = 1; j < num_sregs; ++j) {
2150 int sreg = sregs [j];
2151 int dest_sreg = dest_sregs [j];
2152
2153 if (j == 2 && dest_sreg != -1) {
2154 int k;
2155
2156 g_assert (sreg == dest_sreg);
2157
2158 for (k = 0; k < num_sregs; ++k) {
2159 if (k != j)
2160 g_assert (sregs [k] != dest_sreg);
2161 }
2162 }
2163 }
2164
2165 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2166 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2167 mono_regstate_free_int (rs, ins->sreg1);
2168 }
2169 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2170 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2171 mono_regstate_free_int (rs, ins->sreg2);
2172 }*/
2173
2174 DEBUG (mono_print_ins_index (i, ins));
2175 }
2176
2177 // FIXME: Set MAX_FREGS to 8
2178 // FIXME: Optimize generated code
2179 #if MONO_ARCH_USE_FPSTACK
2180 /*
2181 * Make a forward pass over the code, simulating the fp stack, making sure the
2182 * arguments required by the fp opcodes are at the top of the stack.
2183 */
2184 if (has_fp) {
2185 MonoInst *prev = NULL;
2186 MonoInst *fxch;
2187 int tmp;
2188
2189 g_assert (num_sregs <= 2);
2190
2191 for (ins = bb->code; ins; ins = ins->next) {
2192 spec = ins_get_spec (ins->opcode);
2193
2194 DEBUG (printf ("processing:"));
2195 DEBUG (mono_print_ins_index (0, ins));
2196
2197 if (ins->opcode == OP_FMOVE) {
2198 /* Do it by renaming the source to the destination on the stack */
2199 // FIXME: Is this correct ?
2200 for (i = 0; i < sp; ++i)
2201 if (fpstack [i] == ins->sreg1)
2202 fpstack [i] = ins->dreg;
2203 prev = ins;
2204 continue;
2205 }
2206
2207 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2208 /* Arg1 must be in %st(1) */
2209 g_assert (prev);
2210
2211 i = 0;
2212 while ((i < sp) && (fpstack [i] != ins->sreg1))
2213 i ++;
2214 g_assert (i < sp);
2215
2216 if (sp - 1 - i > 0) {
2217 /* First move it to %st(0) */
2218 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2219
2220 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2221 fxch->inst_imm = sp - 1 - i;
2222
2223 mono_bblock_insert_after_ins (bb, prev, fxch);
2224 prev = fxch;
2225
2226 tmp = fpstack [sp - 1];
2227 fpstack [sp - 1] = fpstack [i];
2228 fpstack [i] = tmp;
2229 }
2230
2231 /* Then move it to %st(1) */
2232 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2233
2234 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2235 fxch->inst_imm = 1;
2236
2237 mono_bblock_insert_after_ins (bb, prev, fxch);
2238 prev = fxch;
2239
2240 tmp = fpstack [sp - 1];
2241 fpstack [sp - 1] = fpstack [sp - 2];
2242 fpstack [sp - 2] = tmp;
2243 }
2244
2245 if (sreg2_is_fp (spec)) {
2246 g_assert (sp > 0);
2247
2248 if (fpstack [sp - 1] != ins->sreg2) {
2249 g_assert (prev);
2250
2251 i = 0;
2252 while ((i < sp) && (fpstack [i] != ins->sreg2))
2253 i ++;
2254 g_assert (i < sp);
2255
2256 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2257
2258 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2259 fxch->inst_imm = sp - 1 - i;
2260
2261 mono_bblock_insert_after_ins (bb, prev, fxch);
2262 prev = fxch;
2263
2264 tmp = fpstack [sp - 1];
2265 fpstack [sp - 1] = fpstack [i];
2266 fpstack [i] = tmp;
2267 }
2268
2269 sp --;
2270 }
2271
2272 if (sreg1_is_fp (spec)) {
2273 g_assert (sp > 0);
2274
2275 if (fpstack [sp - 1] != ins->sreg1) {
2276 g_assert (prev);
2277
2278 i = 0;
2279 while ((i < sp) && (fpstack [i] != ins->sreg1))
2280 i ++;
2281 g_assert (i < sp);
2282
2283 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2284
2285 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2286 fxch->inst_imm = sp - 1 - i;
2287
2288 mono_bblock_insert_after_ins (bb, prev, fxch);
2289 prev = fxch;
2290
2291 tmp = fpstack [sp - 1];
2292 fpstack [sp - 1] = fpstack [i];
2293 fpstack [i] = tmp;
2294 }
2295
2296 sp --;
2297 }
2298
2299 if (dreg_is_fp (spec)) {
2300 g_assert (sp < 8);
2301 fpstack [sp ++] = ins->dreg;
2302 }
2303
2304 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2305 printf ("\t[");
2306 for (i = 0; i < sp; ++i)
2307 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2308 printf ("]\n");
2309 }
2310
2311 prev = ins;
2312 }
2313
2314 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2315 /* Remove remaining items from the fp stack */
2316 /*
2317 * These can remain for example as a result of a dead fmove like in
2318 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2319 */
2320 while (sp) {
2321 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2322 mono_add_ins_to_end (bb, ins);
2323 sp --;
2324 }
2325 }
2326 }
2327 #endif
2328 }
2329
2330 CompRelation
2331 mono_opcode_to_cond (int opcode)
2332 {
2333 switch (opcode) {
2334 case OP_CEQ:
2335 case OP_IBEQ:
2336 case OP_ICEQ:
2337 case OP_LBEQ:
2338 case OP_LCEQ:
2339 case OP_FBEQ:
2340 case OP_FCEQ:
2341 case OP_RBEQ:
2342 case OP_RCEQ:
2343 case OP_COND_EXC_EQ:
2344 case OP_COND_EXC_IEQ:
2345 case OP_CMOV_IEQ:
2346 case OP_CMOV_LEQ:
2347 return CMP_EQ;
2348 case OP_FCNEQ:
2349 case OP_RCNEQ:
2350 case OP_ICNEQ:
2351 case OP_IBNE_UN:
2352 case OP_LBNE_UN:
2353 case OP_FBNE_UN:
2354 case OP_COND_EXC_NE_UN:
2355 case OP_COND_EXC_INE_UN:
2356 case OP_CMOV_INE_UN:
2357 case OP_CMOV_LNE_UN:
2358 return CMP_NE;
2359 case OP_FCLE:
2360 case OP_ICLE:
2361 case OP_IBLE:
2362 case OP_LBLE:
2363 case OP_FBLE:
2364 case OP_CMOV_ILE:
2365 case OP_CMOV_LLE:
2366 return CMP_LE;
2367 case OP_FCGE:
2368 case OP_ICGE:
2369 case OP_IBGE:
2370 case OP_LBGE:
2371 case OP_FBGE:
2372 case OP_CMOV_IGE:
2373 case OP_CMOV_LGE:
2374 return CMP_GE;
2375 case OP_CLT:
2376 case OP_IBLT:
2377 case OP_ICLT:
2378 case OP_LBLT:
2379 case OP_LCLT:
2380 case OP_FBLT:
2381 case OP_FCLT:
2382 case OP_RBLT:
2383 case OP_RCLT:
2384 case OP_COND_EXC_LT:
2385 case OP_COND_EXC_ILT:
2386 case OP_CMOV_ILT:
2387 case OP_CMOV_LLT:
2388 return CMP_LT;
2389 case OP_CGT:
2390 case OP_IBGT:
2391 case OP_ICGT:
2392 case OP_LBGT:
2393 case OP_LCGT:
2394 case OP_FBGT:
2395 case OP_FCGT:
2396 case OP_RBGT:
2397 case OP_RCGT:
2398 case OP_COND_EXC_GT:
2399 case OP_COND_EXC_IGT:
2400 case OP_CMOV_IGT:
2401 case OP_CMOV_LGT:
2402 return CMP_GT;
2403
2404 case OP_ICLE_UN:
2405 case OP_IBLE_UN:
2406 case OP_LBLE_UN:
2407 case OP_FBLE_UN:
2408 case OP_COND_EXC_LE_UN:
2409 case OP_COND_EXC_ILE_UN:
2410 case OP_CMOV_ILE_UN:
2411 case OP_CMOV_LLE_UN:
2412 return CMP_LE_UN;
2413
2414 case OP_ICGE_UN:
2415 case OP_IBGE_UN:
2416 case OP_LBGE_UN:
2417 case OP_FBGE_UN:
2418 case OP_COND_EXC_GE_UN:
2419 case OP_CMOV_IGE_UN:
2420 case OP_CMOV_LGE_UN:
2421 return CMP_GE_UN;
2422 case OP_CLT_UN:
2423 case OP_IBLT_UN:
2424 case OP_ICLT_UN:
2425 case OP_LBLT_UN:
2426 case OP_LCLT_UN:
2427 case OP_FBLT_UN:
2428 case OP_FCLT_UN:
2429 case OP_RBLT_UN:
2430 case OP_RCLT_UN:
2431 case OP_COND_EXC_LT_UN:
2432 case OP_COND_EXC_ILT_UN:
2433 case OP_CMOV_ILT_UN:
2434 case OP_CMOV_LLT_UN:
2435 return CMP_LT_UN;
2436 case OP_CGT_UN:
2437 case OP_IBGT_UN:
2438 case OP_ICGT_UN:
2439 case OP_LBGT_UN:
2440 case OP_LCGT_UN:
2441 case OP_FCGT_UN:
2442 case OP_FBGT_UN:
2443 case OP_RCGT_UN:
2444 case OP_RBGT_UN:
2445 case OP_COND_EXC_GT_UN:
2446 case OP_COND_EXC_IGT_UN:
2447 case OP_CMOV_IGT_UN:
2448 case OP_CMOV_LGT_UN:
2449 return CMP_GT_UN;
2450 default:
2451 printf ("%s\n", mono_inst_name (opcode));
2452 g_assert_not_reached ();
2453 return (CompRelation)0;
2454 }
2455 }
2456
2457 CompRelation
2458 mono_negate_cond (CompRelation cond)
2459 {
2460 switch (cond) {
2461 case CMP_EQ:
2462 return CMP_NE;
2463 case CMP_NE:
2464 return CMP_EQ;
2465 case CMP_LE:
2466 return CMP_GT;
2467 case CMP_GE:
2468 return CMP_LT;
2469 case CMP_LT:
2470 return CMP_GE;
2471 case CMP_GT:
2472 return CMP_LE;
2473 case CMP_LE_UN:
2474 return CMP_GT_UN;
2475 case CMP_GE_UN:
2476 return CMP_LT_UN;
2477 case CMP_LT_UN:
2478 return CMP_GE_UN;
2479 case CMP_GT_UN:
2480 return CMP_LE_UN;
2481 default:
2482 g_assert_not_reached ();
2483 }
2484 }
2485
2486 CompType
2487 mono_opcode_to_type (int opcode, int cmp_opcode)
2488 {
2489 if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2490 return CMP_TYPE_L;
2491 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2492 return CMP_TYPE_I;
2493 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2494 return CMP_TYPE_I;
2495 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2496 return CMP_TYPE_L;
2497 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2498 return CMP_TYPE_L;
2499 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2500 return CMP_TYPE_F;
2501 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2502 return CMP_TYPE_F;
2503 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2504 return CMP_TYPE_I;
2505 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2506 switch (cmp_opcode) {
2507 case OP_ICOMPARE:
2508 case OP_ICOMPARE_IMM:
2509 return CMP_TYPE_I;
2510 default:
2511 return CMP_TYPE_L;
2512 }
2513 } else {
2514 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2515 return (CompType)0;
2516 }
2517 }
2518
2519 /*
2520 * mono_peephole_ins:
2521 *
2522 * Perform some architecture independent peephole optimizations.
2523 */
2524 void
2525 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2526 {
2527 int filter = FILTER_IL_SEQ_POINT;
2528 MonoInst *last_ins = mono_inst_prev (ins, filter);
2529
2530 switch (ins->opcode) {
2531 case OP_MUL_IMM:
2532 /* remove unnecessary multiplication with 1 */
2533 if (ins->inst_imm == 1) {
2534 if (ins->dreg != ins->sreg1)
2535 ins->opcode = OP_MOVE;
2536 else
2537 MONO_DELETE_INS (bb, ins);
2538 }
2539 break;
2540 case OP_LOAD_MEMBASE:
2541 case OP_LOADI4_MEMBASE:
2542 /*
2543 * Note: if reg1 = reg2 the load op is removed
2544 *
2545 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2546 * OP_LOAD_MEMBASE offset(basereg), reg2
2547 * -->
2548 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2549 * OP_MOVE reg1, reg2
2550 */
2551 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2552 last_ins = mono_inst_prev (ins, filter);
2553 if (last_ins &&
2554 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2555 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2556 ins->inst_basereg == last_ins->inst_destbasereg &&
2557 ins->inst_offset == last_ins->inst_offset) {
2558 if (ins->dreg == last_ins->sreg1) {
2559 MONO_DELETE_INS (bb, ins);
2560 break;
2561 } else {
2562 ins->opcode = OP_MOVE;
2563 ins->sreg1 = last_ins->sreg1;
2564 }
2565
2566 /*
2567 * Note: reg1 must be different from the basereg in the second load
2568 * Note: if reg1 = reg2 is equal then second load is removed
2569 *
2570 * OP_LOAD_MEMBASE offset(basereg), reg1
2571 * OP_LOAD_MEMBASE offset(basereg), reg2
2572 * -->
2573 * OP_LOAD_MEMBASE offset(basereg), reg1
2574 * OP_MOVE reg1, reg2
2575 */
2576 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2577 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2578 ins->inst_basereg != last_ins->dreg &&
2579 ins->inst_basereg == last_ins->inst_basereg &&
2580 ins->inst_offset == last_ins->inst_offset) {
2581
2582 if (ins->dreg == last_ins->dreg) {
2583 MONO_DELETE_INS (bb, ins);
2584 } else {
2585 ins->opcode = OP_MOVE;
2586 ins->sreg1 = last_ins->dreg;
2587 }
2588
2589 //g_assert_not_reached ();
2590
2591 #if 0
2592 /*
2593 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2594 * OP_LOAD_MEMBASE offset(basereg), reg
2595 * -->
2596 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2597 * OP_ICONST reg, imm
2598 */
2599 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2600 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2601 ins->inst_basereg == last_ins->inst_destbasereg &&
2602 ins->inst_offset == last_ins->inst_offset) {
2603 ins->opcode = OP_ICONST;
2604 ins->inst_c0 = last_ins->inst_imm;
2605 g_assert_not_reached (); // check this rule
2606 #endif
2607 }
2608 break;
2609 case OP_LOADI1_MEMBASE:
2610 case OP_LOADU1_MEMBASE:
2611 /*
2612 * Note: if reg1 = reg2 the load op is removed
2613 *
2614 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2615 * OP_LOAD_MEMBASE offset(basereg), reg2
2616 * -->
2617 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2618 * OP_MOVE reg1, reg2
2619 */
2620 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2621 ins->inst_basereg == last_ins->inst_destbasereg &&
2622 ins->inst_offset == last_ins->inst_offset) {
2623 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2624 ins->sreg1 = last_ins->sreg1;
2625 }
2626 break;
2627 case OP_LOADI2_MEMBASE:
2628 case OP_LOADU2_MEMBASE:
2629 /*
2630 * Note: if reg1 = reg2 the load op is removed
2631 *
2632 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2633 * OP_LOAD_MEMBASE offset(basereg), reg2
2634 * -->
2635 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2636 * OP_MOVE reg1, reg2
2637 */
2638 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2639 ins->inst_basereg == last_ins->inst_destbasereg &&
2640 ins->inst_offset == last_ins->inst_offset) {
2641 #if SIZEOF_REGISTER == 8
2642 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2643 #else
2644 /* The definition of OP_PCONV_TO_U2 is wrong */
2645 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2646 #endif
2647 ins->sreg1 = last_ins->sreg1;
2648 }
2649 break;
2650 case OP_LOADX_MEMBASE:
2651 if (last_ins && last_ins->opcode == OP_STOREX_MEMBASE &&
2652 ins->inst_basereg == last_ins->inst_destbasereg &&
2653 ins->inst_offset == last_ins->inst_offset) {
2654 if (ins->dreg == last_ins->sreg1) {
2655 MONO_DELETE_INS (bb, ins);
2656 break;
2657 } else {
2658 ins->opcode = OP_XMOVE;
2659 ins->sreg1 = last_ins->sreg1;
2660 }
2661 }
2662 break;
2663 case OP_MOVE:
2664 case OP_FMOVE:
2665 /*
2666 * Removes:
2667 *
2668 * OP_MOVE reg, reg
2669 */
2670 if (ins->dreg == ins->sreg1) {
2671 MONO_DELETE_INS (bb, ins);
2672 break;
2673 }
2674 /*
2675 * Removes:
2676 *
2677 * OP_MOVE sreg, dreg
2678 * OP_MOVE dreg, sreg
2679 */
2680 if (last_ins && last_ins->opcode == ins->opcode &&
2681 ins->sreg1 == last_ins->dreg &&
2682 ins->dreg == last_ins->sreg1) {
2683 MONO_DELETE_INS (bb, ins);
2684 }
2685 break;
2686 case OP_NOP:
2687 MONO_DELETE_INS (bb, ins);
2688 break;
2689 }
2690 }
2691
2692 int
2693 mini_exception_id_by_name (const char *name)
2694 {
2695 if (strcmp (name, "NullReferenceException") == 0)
2696 return MONO_EXC_NULL_REF;
2697 if (strcmp (name, "IndexOutOfRangeException") == 0)
2698 return MONO_EXC_INDEX_OUT_OF_RANGE;
2699 if (strcmp (name, "OverflowException") == 0)
2700 return MONO_EXC_OVERFLOW;
2701 if (strcmp (name, "ArithmeticException") == 0)
2702 return MONO_EXC_ARITHMETIC;
2703 if (strcmp (name, "DivideByZeroException") == 0)
2704 return MONO_EXC_DIVIDE_BY_ZERO;
2705 if (strcmp (name, "InvalidCastException") == 0)
2706 return MONO_EXC_INVALID_CAST;
2707 if (strcmp (name, "ArrayTypeMismatchException") == 0)
2708 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2709 if (strcmp (name, "ArgumentException") == 0)
2710 return MONO_EXC_ARGUMENT;
2711 if (strcmp (name, "ArgumentOutOfRangeException") == 0)
2712 return MONO_EXC_ARGUMENT_OUT_OF_RANGE;
2713 g_error ("Unknown intrinsic exception %s\n", name);
2714 return -1;
2715 }
2716
2717 gboolean
2718 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2719 {
2720 MonoClass *klass;
2721 gpointer iter;
2722 MonoClassField *field;
2723 MonoType *ftype, *prev_ftype = NULL;
2724 int nfields = 0;
2725
2726 klass = mono_class_from_mono_type_internal (t);
2727 iter = NULL;
2728 while ((field = mono_class_get_fields_internal (klass, &iter))) {
2729 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2730 continue;
2731 ftype = mono_field_get_type_internal (field);
2732 ftype = mini_native_type_replace_type (ftype);
2733
2734 if (MONO_TYPE_ISSTRUCT (ftype)) {
2735 int nested_nfields, nested_esize;
2736
2737 if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2738 return FALSE;
2739 if (nested_esize == 4)
2740 ftype = m_class_get_byval_arg (mono_defaults.single_class);
2741 else
2742 ftype = m_class_get_byval_arg (mono_defaults.double_class);
2743 if (prev_ftype && prev_ftype->type != ftype->type)
2744 return FALSE;
2745 prev_ftype = ftype;
2746 nfields += nested_nfields;
2747 } else {
2748 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2749 return FALSE;
2750 if (prev_ftype && prev_ftype->type != ftype->type)
2751 return FALSE;
2752 prev_ftype = ftype;
2753 nfields ++;
2754 }
2755 }
2756 if (nfields == 0)
2757 return FALSE;
2758 *out_nfields = nfields;
2759 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2760 return TRUE;
2761 }
2762
2763 MonoRegState*
2764 mono_regstate_new (void)
2765 {
2766 MonoRegState* rs = g_new0 (MonoRegState, 1);
2767
2768 rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2769 #ifdef MONO_ARCH_NEED_SIMD_BANK
2770 rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2771 #endif
2772
2773 return rs;
2774 }
2775
2776 void
2777 mono_regstate_free (MonoRegState *rs) {
2778 g_free (rs->vassign);
2779 g_free (rs);
2780 }
2781
2782 #endif /* DISABLE_JIT */
2783
2784 gboolean
2785 mono_is_regsize_var (MonoType *t)
2786 {
2787 t = mini_get_underlying_type (t);
2788 switch (t->type) {
2789 case MONO_TYPE_I1:
2790 case MONO_TYPE_U1:
2791 case MONO_TYPE_I2:
2792 case MONO_TYPE_U2:
2793 case MONO_TYPE_I4:
2794 case MONO_TYPE_U4:
2795 case MONO_TYPE_I:
2796 case MONO_TYPE_U:
2797 case MONO_TYPE_PTR:
2798 case MONO_TYPE_FNPTR:
2799 #if SIZEOF_REGISTER == 8
2800 case MONO_TYPE_I8:
2801 case MONO_TYPE_U8:
2802 #endif
2803 return TRUE;
2804 case MONO_TYPE_OBJECT:
2805 case MONO_TYPE_STRING:
2806 case MONO_TYPE_CLASS:
2807 case MONO_TYPE_SZARRAY:
2808 case MONO_TYPE_ARRAY:
2809 return TRUE;
2810 case MONO_TYPE_GENERICINST:
2811 if (!mono_type_generic_inst_is_valuetype (t))
2812 return TRUE;
2813 return FALSE;
2814 case MONO_TYPE_VALUETYPE:
2815 return FALSE;
2816 default:
2817 return FALSE;
2818 }
2819 }
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