inc/timerreg.h

   1 /*      $NetBSD: timerreg.h,v 1.4 1994/10/27 04:18:17 cgd Exp $ */
   2
   3 /*
   4  * Register definitions for the Intel
   5  * 8253/8254/82C54 Programmable Interval Timer (PIT).
   6  *
   7  * This chip has three independent 16-bit down counters that can be
   8  * read on the fly.  There are three mode registers and three countdown
   9  * registers.  The countdown registers are addressed directly, via the
  10  * first three I/O ports.  The three mode registers are accessed via
  11  * the fourth I/O port, with two bits in the mode byte indicating the
  12  * register.  (Why are hardware interfaces always so braindead?).
  13  *
  14  * To write a value into the countdown register, the mode register
  15  * is first programmed with a command indicating the which byte of
  16  * the two byte register is to be modified.  The three possibilities
  17  * are load msb(TMR_MR_MSB), load lsb(TMR_MR_LSB), or load lsb then
  18  * msb(TMR_MR_BOTH).
  19  *
  20  * To read the current value("on the fly") from the countdown register,
  21  * you write a "latch" command into the mode register, then read the stable
  22  * value from the corresponding I/O port.  For example, you write
  23  * TMR_MR_LATCH into the corresponding mode register.  Presumably,
  24  * after doing this, a write operation to the I/O port would result
  25  * in undefined behavior(but hopefully not fry the chip).
  26  * Reading in this manner has no side effects.
  27  *
  28  * The outputs of the three timers are connected as follows:
  29  *
  30  *       timer 0 -> irq 0
  31  *       timer 1 -> dma chan 0 (for dram refresh)
  32  *       timer 2 -> speaker(via keyboard controller)
  33  *
  34  * Timer 0 is used to call hardclock.
  35  * Timer 2 is used to generate console beeps.
  36  */
  37
  38 /*
  39  * Frequency of all three count-down timers; (TIMER_FREQ/freq) is the
  40  * appropriate count to generate a frequency of freq hz.
  41  */
  42 #define TIMER_FREQ      1193182
  43 #define TIMER_DIV(x)    ((TIMER_FREQ+(x)/2)/(x))
  44
  45 /*
  46  * Macros for specifying values to be written into a mode register.
  47  */
  48 #define TIMER_CNTR0     (IO_TIMER1 + 0) /* timer 0 counter port */
  49 #define TIMER_CNTR1     (IO_TIMER1 + 1) /* timer 1 counter port */
  50 #define TIMER_CNTR2     (IO_TIMER1 + 2) /* timer 2 counter port */
  51 #define TIMER_MODE      (IO_TIMER1 + 3) /* timer mode port */
  52 #define         TIMER_SEL0      0x00    /* select counter 0 */
  53 #define         TIMER_SEL1      0x40    /* select counter 1 */
  54 #define         TIMER_SEL2      0x80    /* select counter 2 */
  55 #define         TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
  56 #define         TIMER_ONESHOT   0x02    /* mode 1, one shot */
  57 #define         TIMER_RATEGEN   0x04    /* mode 2, rate generator */
  58 #define         TIMER_SQWAVE    0x06    /* mode 3, square wave */
  59 #define         TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
  60 #define         TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
  61 #define         TIMER_LATCH     0x00    /* latch counter for reading */
  62 #define         TIMER_LSB       0x10    /* r/w counter LSB */
  63 #define         TIMER_MSB       0x20    /* r/w counter MSB */
  64 #define         TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
  65 #define         TIMER_BCD       0x01    /* count in BCD */
  66