inc/isareg.h

   1 /* See COPYRIGHT for copyright information. */
   2
   3 /*      $OpenBSD: isareg.h,v 1.2 1997/11/07 08:07:03 niklas Exp $       */
   4 /*      $NetBSD: isareg.h,v 1.5 1995/04/17 12:09:13 cgd Exp $   */
   5
   6 /*
   7  * ISA Bus conventions
   8  */
   9
  10 /*
  11  * Input / Output Port Assignments
  12  */
  13
  14 #ifndef IO_ISABEGIN
  15 #define IO_ISABEGIN     0x000           /* 0x000 - Beginning of I/O Registers */
  16
  17                 /* CPU Board */
  18 #define IO_DMA1         0x000           /* 8237A DMA Controller #1 */
  19 #define IO_ICU1         0x020           /* 8259A Interrupt Controller #1 */
  20 #define IO_PMP1         0x026           /* 82347 Power Management Peripheral */
  21 #define IO_TIMER1       0x040           /* 8253 Timer #1 */
  22 #define IO_TIMER2       0x048           /* 8253 Timer #2 (EISA only) */
  23 #define IO_KBD          0x060           /* 8042 Keyboard */
  24 #define IO_PPI          0x061           /* Programmable Peripheral Interface */
  25 #define IO_RTC          0x070           /* RTC */
  26 #define IO_NMI          IO_RTC          /* NMI Control */
  27 #define IO_DMAPG        0x080           /* DMA Page Registers */
  28 #define IO_ICU2         0x0A0           /* 8259A Interrupt Controller #2 */
  29 #define IO_DMA2         0x0C0           /* 8237A DMA Controller #2 */
  30 #define IO_NPX          0x0F0           /* Numeric Coprocessor */
  31
  32                 /* Cards */
  33                                         /* 0x100 - 0x16F Open */
  34
  35 #define IO_WD2          0x170           /* Secondary Fixed Disk Controller */
  36 #define IO_PMP2         0x178           /* 82347 Power Management Peripheral */
  37
  38                                         /* 0x17A - 0x1EF Open */
  39
  40 #define IO_WD1          0x1f0           /* Primary Fixed Disk Controller */
  41 #define IO_GAME         0x200           /* Game Controller */
  42
  43                                         /* 0x208 - 0x237 Open */
  44
  45 #define IO_BMS2         0x238           /* secondary InPort Bus Mouse */
  46 #define IO_BMS1         0x23c           /* primary InPort Bus Mouse */
  47
  48                                         /* 0x240 - 0x277 Open */
  49
  50 #define IO_LPT2         0x278           /* Parallel Port #2 */
  51
  52                                         /* 0x280 - 0x2E7 Open */
  53
  54 #define IO_COM4         0x2e8           /* COM4 i/o address */
  55
  56                                         /* 0x2F0 - 0x2F7 Open */
  57
  58 #define IO_COM2         0x2f8           /* COM2 i/o address */
  59
  60                                         /* 0x300 - 0x32F Open */
  61
  62 #define IO_BT0          0x330           /* bustek 742a default addr. */
  63 #define IO_AHA0         0x330           /* adaptec 1542 default addr. */
  64 #define IO_UHA0         0x330           /* ultrastore 14f default addr. */
  65 #define IO_BT1          0x334           /* bustek 742a default addr. */
  66 #define IO_AHA1         0x334           /* adaptec 1542 default addr. */
  67
  68                                         /* 0x338 - 0x34F Open */
  69
  70 #define IO_WDS          0x350           /* WD7000 scsi */
  71
  72                                         /* 0x354 - 0x36F Open */
  73
  74 #define IO_FD2          0x370           /* secondary base i/o address */
  75 #define IO_LPT1         0x378           /* Parallel Port #1 */
  76
  77                                         /* 0x380 - 0x3AF Open */
  78
  79 #define IO_MDA          0x3B0           /* Monochome Adapter */
  80 #define IO_LPT3         0x3BC           /* Monochome Adapter Printer Port */
  81 #define IO_VGA          0x3C0           /* E/VGA Ports */
  82 #define IO_CGA          0x3D0           /* CGA Ports */
  83
  84                                         /* 0x3E0 - 0x3E7 Open */
  85
  86 #define IO_COM3         0x3e8           /* COM3 i/o address */
  87 #define IO_FD1          0x3f0           /* primary base i/o address */
  88 #define IO_COM1         0x3f8           /* COM1 i/o address */
  89
  90 #define IO_ISAEND       0x3FF           /* - 0x3FF End of I/O Registers */
  91 #endif /* !IO_ISABEGIN */
  92
  93 /*
  94  * Input / Output Port Sizes - these are from several sources, and tend
  95  * to be the larger of what was found, ie COM ports can be 4, but some
  96  * boards do not fully decode the address, thus 8 ports are used.
  97  */
  98
  99 #ifndef IO_ISASIZES
 100 #define IO_ISASIZES
 101
 102 #define IO_COMSIZE      8       /* 8250, 16X50 com controllers */
 103 #define IO_CGASIZE      16      /* CGA controllers */
 104 #define IO_DMASIZE      16      /* 8237 DMA controllers */
 105 #define IO_DPGSIZE      32      /* 74LS612 DMA page reisters */
 106 #define IO_FDCSIZE      8       /* Nec765 floppy controllers */
 107 #define IO_WDCSIZE      8       /* WD compatible disk controller */
 108 #define IO_GAMSIZE      16      /* AT compatible game controller */
 109 #define IO_ICUSIZE      16      /* 8259A interrupt controllers */
 110 #define IO_KBDSIZE      16      /* 8042 Keyboard controllers */
 111 #define IO_LPTSIZE      8       /* LPT controllers, some use onl */
 112 #define IO_MDASIZE      16      /* Monochrome display controller */
 113 #define IO_RTCSIZE      16      /* CMOS real time clock, NMI con */
 114 #define IO_TMRSIZE      16      /* 8253 programmable timers */
 115 #define IO_NPXSIZE      16      /* 80387/80487 NPX registers */
 116 #define IO_VGASIZE      16      /* VGA controllers */
 117 #define IO_PMPSIZE      2       /* 82347 Power Management Peripheral */
 118 #endif /* !IO_ISASIZES */
 119
 120 /*
 121  * Input / Output Memory Physical Addresses
 122  */
 123
 124 #ifndef IOM_BEGIN
 125 #define IOM_BEGIN       0x0a0000                /* Start of I/O Memory "hole" */
 126 #define IOM_END         0x100000                /* End of I/O Memory "hole" */
 127 #define IOM_SIZE        (IOM_END - IOM_BEGIN)
 128
 129 #endif // !IOM_BEGIN