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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / sound / soc / s3c24xx / s3c2412-i2s.c
blobc4a46dd589b3b1565f6c3d2e450465a3a4c6744b
1 /* sound/soc/s3c24xx/s3c2412-i2s.c
2 *
3 * ALSA Soc Audio Layer - S3C2412 I2S driver
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/kernel.h>
25
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
31 #include <asm/hardware.h>
32
33 #include <linux/io.h>
34 #include <asm/dma.h>
35
36 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
37
38 #include <asm/arch/regs-gpio.h>
39 #include <asm/arch/audio.h>
40 #include <asm/arch/dma.h>
41
42 #include "s3c24xx-pcm.h"
43 #include "s3c2412-i2s.h"
44
45 #define S3C2412_I2S_DEBUG 0
46 #define S3C2412_I2S_DEBUG_CON 0
47
48 #if S3C2412_I2S_DEBUG
49 #define DBG(x...) printk(KERN_INFO x)
50 #else
51 #define DBG(x...) do { } while (0)
52 #endif
53
54 static struct s3c2410_dma_client s3c2412_dma_client_out = {
55 .name = "I2S PCM Stereo out"
56 };
57
58 static struct s3c2410_dma_client s3c2412_dma_client_in = {
59 .name = "I2S PCM Stereo in"
60 };
61
62 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_out = {
63 .client = &s3c2412_dma_client_out,
64 .channel = DMACH_I2S_OUT,
65 .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
66 .dma_size = 4,
67 };
68
69 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_in = {
70 .client = &s3c2412_dma_client_in,
71 .channel = DMACH_I2S_IN,
72 .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
73 .dma_size = 4,
74 };
75
76 struct s3c2412_i2s_info {
77 struct device *dev;
78 void __iomem *regs;
79 struct clk *iis_clk;
80 struct clk *iis_pclk;
81 struct clk *iis_cclk;
82
83 u32 suspend_iismod;
84 u32 suspend_iiscon;
85 u32 suspend_iispsr;
86 };
87
88 static struct s3c2412_i2s_info s3c2412_i2s;
89
90 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
91
92 #if S3C2412_I2S_DEBUG_CON
93 static void dbg_showcon(const char *fn, u32 con)
94 {
95 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
96 bit_set(con, S3C2412_IISCON_LRINDEX),
97 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
98 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
99 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
100 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
101
102 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
103 fn,
104 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
105 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
106 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
107 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
108 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
109 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
110 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
111 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
112 }
113 #else
114 static inline void dbg_showcon(const char *fn, u32 con)
115 {
116 }
117 #endif
118
119 /* Turn on or off the transmission path. */
120 static void s3c2412_snd_txctrl(int on)
121 {
122 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
123 void __iomem *regs = i2s->regs;
124 u32 fic, con, mod;
125
126 DBG("%s(%d)\n", __func__, on);
127
128 fic = readl(regs + S3C2412_IISFIC);
129 con = readl(regs + S3C2412_IISCON);
130 mod = readl(regs + S3C2412_IISMOD);
131
132 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
133
134 if (on) {
135 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
136 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
137 con &= ~S3C2412_IISCON_TXCH_PAUSE;
138
139 switch (mod & S3C2412_IISMOD_MODE_MASK) {
140 case S3C2412_IISMOD_MODE_TXONLY:
141 case S3C2412_IISMOD_MODE_TXRX:
142 /* do nothing, we are in the right mode */
143 break;
144
145 case S3C2412_IISMOD_MODE_RXONLY:
146 mod &= ~S3C2412_IISMOD_MODE_MASK;
147 mod |= S3C2412_IISMOD_MODE_TXRX;
148 break;
149
150 default:
151 dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n");
152 }
153
154 writel(con, regs + S3C2412_IISCON);
155 writel(mod, regs + S3C2412_IISMOD);
156 } else {
157 /* Note, we do not have any indication that the FIFO problems
158 * tha the S3C2410/2440 had apply here, so we should be able
159 * to disable the DMA and TX without resetting the FIFOS.
160 */
161
162 con |= S3C2412_IISCON_TXDMA_PAUSE;
163 con |= S3C2412_IISCON_TXCH_PAUSE;
164 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
165
166 switch (mod & S3C2412_IISMOD_MODE_MASK) {
167 case S3C2412_IISMOD_MODE_TXRX:
168 mod &= ~S3C2412_IISMOD_MODE_MASK;
169 mod |= S3C2412_IISMOD_MODE_RXONLY;
170 break;
171
172 case S3C2412_IISMOD_MODE_TXONLY:
173 mod &= ~S3C2412_IISMOD_MODE_MASK;
174 con &= ~S3C2412_IISCON_IIS_ACTIVE;
175 break;
176
177 default:
178 dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n");
179 }
180
181 writel(mod, regs + S3C2412_IISMOD);
182 writel(con, regs + S3C2412_IISCON);
183 }
184
185 fic = readl(regs + S3C2412_IISFIC);
186 dbg_showcon(__func__, con);
187 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
188 }
189
190 static void s3c2412_snd_rxctrl(int on)
191 {
192 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
193 void __iomem *regs = i2s->regs;
194 u32 fic, con, mod;
195
196 DBG("%s(%d)\n", __func__, on);
197
198 fic = readl(regs + S3C2412_IISFIC);
199 con = readl(regs + S3C2412_IISCON);
200 mod = readl(regs + S3C2412_IISMOD);
201
202 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
203
204 if (on) {
205 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
206 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
207 con &= ~S3C2412_IISCON_RXCH_PAUSE;
208
209 switch (mod & S3C2412_IISMOD_MODE_MASK) {
210 case S3C2412_IISMOD_MODE_TXRX:
211 case S3C2412_IISMOD_MODE_RXONLY:
212 /* do nothing, we are in the right mode */
213 break;
214
215 case S3C2412_IISMOD_MODE_TXONLY:
216 mod &= ~S3C2412_IISMOD_MODE_MASK;
217 mod |= S3C2412_IISMOD_MODE_TXRX;
218 break;
219
220 default:
221 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
222 }
223
224 writel(mod, regs + S3C2412_IISMOD);
225 writel(con, regs + S3C2412_IISCON);
226 } else {
227 /* See txctrl notes on FIFOs. */
228
229 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
230 con |= S3C2412_IISCON_RXDMA_PAUSE;
231 con |= S3C2412_IISCON_RXCH_PAUSE;
232
233 switch (mod & S3C2412_IISMOD_MODE_MASK) {
234 case S3C2412_IISMOD_MODE_RXONLY:
235 con &= ~S3C2412_IISCON_IIS_ACTIVE;
236 mod &= ~S3C2412_IISMOD_MODE_MASK;
237 break;
238
239 case S3C2412_IISMOD_MODE_TXRX:
240 mod &= ~S3C2412_IISMOD_MODE_MASK;
241 mod |= S3C2412_IISMOD_MODE_TXONLY;
242 break;
243
244 default:
245 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
246 }
247
248 writel(con, regs + S3C2412_IISCON);
249 writel(mod, regs + S3C2412_IISMOD);
250 }
251
252 fic = readl(regs + S3C2412_IISFIC);
253 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
254 }
255
256
257 /*
258 * Wait for the LR signal to allow synchronisation to the L/R clock
259 * from the codec. May only be needed for slave mode.
260 */
261 static int s3c2412_snd_lrsync(void)
262 {
263 u32 iiscon;
264 unsigned long timeout = jiffies + msecs_to_jiffies(5);
265
266 DBG("Entered %s\n", __func__);
267
268 while (1) {
269 iiscon = readl(s3c2412_i2s.regs + S3C2412_IISCON);
270 if (iiscon & S3C2412_IISCON_LRINDEX)
271 break;
272
273 if (timeout < jiffies) {
274 printk(KERN_ERR "%s: timeout\n", __func__);
275 return -ETIMEDOUT;
276 }
277 }
278
279 return 0;
280 }
281
282 /*
283 * Check whether CPU is the master or slave
284 */
285 static inline int s3c2412_snd_is_clkmaster(void)
286 {
287 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
288
289 DBG("Entered %s\n", __func__);
290
291 iismod &= S3C2412_IISMOD_MASTER_MASK;
292 return !(iismod == S3C2412_IISMOD_SLAVE);
293 }
294
295 /*
296 * Set S3C2412 I2S DAI format
297 */
298 static int s3c2412_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
299 unsigned int fmt)
300 {
301 u32 iismod;
302
303
304 DBG("Entered %s\n", __func__);
305
306 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
307 DBG("hw_params r: IISMOD: %x \n", iismod);
308
309 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
310 case SND_SOC_DAIFMT_CBM_CFM:
311 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
312 iismod |= S3C2412_IISMOD_SLAVE;
313 break;
314 case SND_SOC_DAIFMT_CBS_CFS:
315 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
316 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
317 break;
318 default:
319 DBG("unknwon master/slave format\n");
320 return -EINVAL;
321 }
322
323 iismod &= ~S3C2412_IISMOD_SDF_MASK;
324
325 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
326 case SND_SOC_DAIFMT_RIGHT_J:
327 iismod |= S3C2412_IISMOD_SDF_MSB;
328 break;
329 case SND_SOC_DAIFMT_LEFT_J:
330 iismod |= S3C2412_IISMOD_SDF_LSB;
331 break;
332 case SND_SOC_DAIFMT_I2S:
333 iismod |= S3C2412_IISMOD_SDF_IIS;
334 break;
335 default:
336 DBG("Unknown data format\n");
337 return -EINVAL;
338 }
339
340 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
341 DBG("hw_params w: IISMOD: %x \n", iismod);
342 return 0;
343 }
344
345 static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
346 struct snd_pcm_hw_params *params)
347 {
348 struct snd_soc_pcm_runtime *rtd = substream->private_data;
349 u32 iismod;
350
351 DBG("Entered %s\n", __func__);
352
353 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
354 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_out;
355 else
356 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_in;
357
358 /* Working copies of register */
359 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
360 DBG("%s: r: IISMOD: %x\n", __func__, iismod);
361
362 switch (params_format(params)) {
363 case SNDRV_PCM_FORMAT_S8:
364 iismod |= S3C2412_IISMOD_8BIT;
365 break;
366 case SNDRV_PCM_FORMAT_S16_LE:
367 iismod &= ~S3C2412_IISMOD_8BIT;
368 break;
369 }
370
371 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
372 DBG("%s: w: IISMOD: %x\n", __func__, iismod);
373 return 0;
374 }
375
376 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
377 {
378 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
379 unsigned long irqs;
380 int ret = 0;
381
382 DBG("Entered %s\n", __func__);
383
384 switch (cmd) {
385 case SNDRV_PCM_TRIGGER_START:
386 /* On start, ensure that the FIFOs are cleared and reset. */
387
388 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
389 s3c2412_i2s.regs + S3C2412_IISFIC);
390
391 /* clear again, just in case */
392 writel(0x0, s3c2412_i2s.regs + S3C2412_IISFIC);
393
394 case SNDRV_PCM_TRIGGER_RESUME:
395 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
396 if (!s3c2412_snd_is_clkmaster()) {
397 ret = s3c2412_snd_lrsync();
398 if (ret)
399 goto exit_err;
400 }
401
402 local_irq_save(irqs);
403
404 if (capture)
405 s3c2412_snd_rxctrl(1);
406 else
407 s3c2412_snd_txctrl(1);
408
409 local_irq_restore(irqs);
410 break;
411
412 case SNDRV_PCM_TRIGGER_STOP:
413 case SNDRV_PCM_TRIGGER_SUSPEND:
414 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
415 local_irq_save(irqs);
416
417 if (capture)
418 s3c2412_snd_rxctrl(0);
419 else
420 s3c2412_snd_txctrl(0);
421
422 local_irq_restore(irqs);
423 break;
424 default:
425 ret = -EINVAL;
426 break;
427 }
428
429 exit_err:
430 return ret;
431 }
432
433 /* default table of all avaialable root fs divisors */
434 static unsigned int s3c2412_iis_fs[] = { 256, 512, 384, 768, 0 };
435
436 int s3c2412_iis_calc_rate(struct s3c2412_rate_calc *info,
437 unsigned int *fstab,
438 unsigned int rate, struct clk *clk)
439 {
440 unsigned long clkrate = clk_get_rate(clk);
441 unsigned int div;
442 unsigned int fsclk;
443 unsigned int actual;
444 unsigned int fs;
445 unsigned int fsdiv;
446 signed int deviation = 0;
447 unsigned int best_fs = 0;
448 unsigned int best_div = 0;
449 unsigned int best_rate = 0;
450 unsigned int best_deviation = INT_MAX;
451
452
453 if (fstab == NULL)
454 fstab = s3c2412_iis_fs;
455
456 for (fs = 0;; fs++) {
457 fsdiv = s3c2412_iis_fs[fs];
458
459 if (fsdiv == 0)
460 break;
461
462 fsclk = clkrate / fsdiv;
463 div = fsclk / rate;
464
465 if ((fsclk % rate) > (rate / 2))
466 div++;
467
468 if (div <= 1)
469 continue;
470
471 actual = clkrate / (fsdiv * div);
472 deviation = actual - rate;
473
474 printk(KERN_DEBUG "%dfs: div %d => result %d, deviation %d\n",
475 fsdiv, div, actual, deviation);
476
477 deviation = abs(deviation);
478
479 if (deviation < best_deviation) {
480 best_fs = fsdiv;
481 best_div = div;
482 best_rate = actual;
483 best_deviation = deviation;
484 }
485
486 if (deviation == 0)
487 break;
488 }
489
490 printk(KERN_DEBUG "best: fs=%d, div=%d, rate=%d\n",
491 best_fs, best_div, best_rate);
492
493 info->fs_div = best_fs;
494 info->clk_div = best_div;
495
496 return 0;
497 }
498 EXPORT_SYMBOL_GPL(s3c2412_iis_calc_rate);
499
500 /*
501 * Set S3C2412 Clock source
502 */
503 static int s3c2412_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
504 int clk_id, unsigned int freq, int dir)
505 {
506 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
507
508 DBG("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
509 freq, dir);
510
511 switch (clk_id) {
512 case S3C2412_CLKSRC_PCLK:
513 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
514 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
515 break;
516 case S3C2412_CLKSRC_I2SCLK:
517 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
518 iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
525 return 0;
526 }
527
528 /*
529 * Set S3C2412 Clock dividers
530 */
531 static int s3c2412_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
532 int div_id, int div)
533 {
534 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
535 u32 reg;
536
537 DBG("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
538
539 switch (div_id) {
540 case S3C2412_DIV_BCLK:
541 reg = readl(i2s->regs + S3C2412_IISMOD);
542 reg &= ~S3C2412_IISMOD_BCLK_MASK;
543 writel(reg | div, i2s->regs + S3C2412_IISMOD);
544
545 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
546 break;
547
548 case S3C2412_DIV_RCLK:
549 if (div > 3) {
550 /* convert value to bit field */
551
552 switch (div) {
553 case 256:
554 div = S3C2412_IISMOD_RCLK_256FS;
555 break;
556
557 case 384:
558 div = S3C2412_IISMOD_RCLK_384FS;
559 break;
560
561 case 512:
562 div = S3C2412_IISMOD_RCLK_512FS;
563 break;
564
565 case 768:
566 div = S3C2412_IISMOD_RCLK_768FS;
567 break;
568
569 default:
570 return -EINVAL;
571 }
572 }
573
574 reg = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
575 reg &= ~S3C2412_IISMOD_RCLK_MASK;
576 writel(reg | div, i2s->regs + S3C2412_IISMOD);
577 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
578 break;
579
580 case S3C2412_DIV_PRESCALER:
581 if (div >= 0) {
582 writel((div << 8) | S3C2412_IISPSR_PSREN,
583 i2s->regs + S3C2412_IISPSR);
584 } else {
585 writel(0x0, i2s->regs + S3C2412_IISPSR);
586 }
587 DBG("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
588 break;
589
590 default:
591 return -EINVAL;
592 }
593
594 return 0;
595 }
596
597 struct clk *s3c2412_get_iisclk(void)
598 {
599 return s3c2412_i2s.iis_clk;
600 }
601 EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);
602
603
604 static int s3c2412_i2s_probe(struct platform_device *pdev)
605 {
606 DBG("Entered %s\n", __func__);
607
608 s3c2412_i2s.dev = &pdev->dev;
609
610 s3c2412_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
611 if (s3c2412_i2s.regs == NULL)
612 return -ENXIO;
613
614 s3c2412_i2s.iis_pclk = clk_get(&pdev->dev, "iis");
615 if (s3c2412_i2s.iis_pclk == NULL) {
616 DBG("failed to get iis_clock\n");
617 iounmap(s3c2412_i2s.regs);
618 return -ENODEV;
619 }
620
621 s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
622 if (s3c2412_i2s.iis_cclk == NULL) {
623 DBG("failed to get i2sclk clock\n");
624 iounmap(s3c2412_i2s.regs);
625 return -ENODEV;
626 }
627
628 clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
629
630 clk_enable(s3c2412_i2s.iis_pclk);
631 clk_enable(s3c2412_i2s.iis_cclk);
632
633 s3c2412_i2s.iis_clk = s3c2412_i2s.iis_pclk;
634
635 /* Configure the I2S pins in correct mode */
636 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
637 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
638 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
639 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
640 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
641
642 s3c2412_snd_txctrl(0);
643 s3c2412_snd_rxctrl(0);
644
645 return 0;
646 }
647
648 #ifdef CONFIG_PM
649 static int s3c2412_i2s_suspend(struct platform_device *dev,
650 struct snd_soc_cpu_dai *dai)
651 {
652 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
653 u32 iismod;
654
655 if (dai->active) {
656 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
657 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
658 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
659
660 /* some basic suspend checks */
661
662 iismod = readl(i2s->regs + S3C2412_IISMOD);
663
664 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
665 dev_warn(&dev->dev, "%s: RXDMA active?\n", __func__);
666
667 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
668 dev_warn(&dev->dev, "%s: TXDMA active?\n", __func__);
669
670 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
671 dev_warn(&dev->dev, "%s: IIS active\n", __func__);
672 }
673
674 return 0;
675 }
676
677 static int s3c2412_i2s_resume(struct platform_device *pdev,
678 struct snd_soc_cpu_dai *dai)
679 {
680 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
681
682 dev_info(&pdev->dev, "dai_active %d, IISMOD %08x, IISCON %08x\n",
683 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
684
685 if (dai->active) {
686 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
687 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
688 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
689
690 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
691 i2s->regs + S3C2412_IISFIC);
692
693 ndelay(250);
694 writel(0x0, i2s->regs + S3C2412_IISFIC);
695
696 }
697
698 return 0;
699 }
700 #else
701 #define s3c2412_i2s_suspend NULL
702 #define s3c2412_i2s_resume NULL
703 #endif /* CONFIG_PM */
704
705 #define S3C2412_I2S_RATES \
706 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
707 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
708 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
709
710 struct snd_soc_cpu_dai s3c2412_i2s_dai = {
711 .name = "s3c2412-i2s",
712 .id = 0,
713 .type = SND_SOC_DAI_I2S,
714 .probe = s3c2412_i2s_probe,
715 .suspend = s3c2412_i2s_suspend,
716 .resume = s3c2412_i2s_resume,
717 .playback = {
718 .channels_min = 2,
719 .channels_max = 2,
720 .rates = S3C2412_I2S_RATES,
721 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
722 },
723 .capture = {
724 .channels_min = 2,
725 .channels_max = 2,
726 .rates = S3C2412_I2S_RATES,
727 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
728 },
729 .ops = {
730 .trigger = s3c2412_i2s_trigger,
731 .hw_params = s3c2412_i2s_hw_params,
732 },
733 .dai_ops = {
734 .set_fmt = s3c2412_i2s_set_fmt,
735 .set_clkdiv = s3c2412_i2s_set_clkdiv,
736 .set_sysclk = s3c2412_i2s_set_sysclk,
737 },
738 };
739 EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);
740
741 /* Module information */
742 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
743 MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
744 MODULE_LICENSE("GPL");
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