sound/soc/fsl/fsl_dma.h

   1 /*
   2  * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _MPC8610_PCM_H
  10 #define _MPC8610_PCM_H
  11
  12 struct ccsr_dma {
  13         u8 res0[0x100];
  14         struct ccsr_dma_channel {
  15                 __be32 mr;      /* Mode register */
  16                 __be32 sr;      /* Status register */
  17                 __be32 eclndar; /* Current link descriptor extended addr reg */
  18                 __be32 clndar;  /* Current link descriptor address register */
  19                 __be32 satr;    /* Source attributes register */
  20                 __be32 sar;     /* Source address register */
  21                 __be32 datr;    /* Destination attributes register */
  22                 __be32 dar;     /* Destination address register */
  23                 __be32 bcr;     /* Byte count register */
  24                 __be32 enlndar; /* Next link descriptor extended address reg */
  25                 __be32 nlndar;  /* Next link descriptor address register */
  26                 u8 res1[4];
  27                 __be32 eclsdar; /* Current list descriptor extended addr reg */
  28                 __be32 clsdar;  /* Current list descriptor address register */
  29                 __be32 enlsdar; /* Next list descriptor extended address reg */
  30                 __be32 nlsdar;  /* Next list descriptor address register */
  31                 __be32 ssr;     /* Source stride register */
  32                 __be32 dsr;     /* Destination stride register */
  33                 u8 res2[0x38];
  34         } channel[4];
  35         __be32 dgsr;
  36 };
  37
  38 #define CCSR_DMA_MR_BWC_DISABLED        0x0F000000
  39 #define CCSR_DMA_MR_BWC_SHIFT           24
  40 #define CCSR_DMA_MR_BWC_MASK            0x0F000000
  41 #define CCSR_DMA_MR_BWC(x) \
  42         ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
  43 #define CCSR_DMA_MR_EMP_EN              0x00200000
  44 #define CCSR_DMA_MR_EMS_EN              0x00040000
  45 #define CCSR_DMA_MR_DAHTS_MASK          0x00030000
  46 #define CCSR_DMA_MR_DAHTS_1             0x00000000
  47 #define CCSR_DMA_MR_DAHTS_2             0x00010000
  48 #define CCSR_DMA_MR_DAHTS_4             0x00020000
  49 #define CCSR_DMA_MR_DAHTS_8             0x00030000
  50 #define CCSR_DMA_MR_SAHTS_MASK          0x0000C000
  51 #define CCSR_DMA_MR_SAHTS_1             0x00000000
  52 #define CCSR_DMA_MR_SAHTS_2             0x00004000
  53 #define CCSR_DMA_MR_SAHTS_4             0x00008000
  54 #define CCSR_DMA_MR_SAHTS_8             0x0000C000
  55 #define CCSR_DMA_MR_DAHE                0x00002000
  56 #define CCSR_DMA_MR_SAHE                0x00001000
  57 #define CCSR_DMA_MR_SRW                 0x00000400
  58 #define CCSR_DMA_MR_EOSIE               0x00000200
  59 #define CCSR_DMA_MR_EOLNIE              0x00000100
  60 #define CCSR_DMA_MR_EOLSIE              0x00000080
  61 #define CCSR_DMA_MR_EIE                 0x00000040
  62 #define CCSR_DMA_MR_XFE                 0x00000020
  63 #define CCSR_DMA_MR_CDSM_SWSM           0x00000010
  64 #define CCSR_DMA_MR_CA                  0x00000008
  65 #define CCSR_DMA_MR_CTM                 0x00000004
  66 #define CCSR_DMA_MR_CC                  0x00000002
  67 #define CCSR_DMA_MR_CS                  0x00000001
  68
  69 #define CCSR_DMA_SR_TE                  0x00000080
  70 #define CCSR_DMA_SR_CH                  0x00000020
  71 #define CCSR_DMA_SR_PE                  0x00000010
  72 #define CCSR_DMA_SR_EOLNI               0x00000008
  73 #define CCSR_DMA_SR_CB                  0x00000004
  74 #define CCSR_DMA_SR_EOSI                0x00000002
  75 #define CCSR_DMA_SR_EOLSI               0x00000001
  76
  77 /* ECLNDAR takes bits 32-36 of the CLNDAR register */
  78 static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
  79 {
  80         return (x >> 32) & 0xf;
  81 }
  82
  83 #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
  84 #define CCSR_DMA_CLNDAR_EOSIE           0x00000008
  85
  86 /* SATR and DATR, combined */
  87 #define CCSR_DMA_ATR_PBATMU             0x20000000
  88 #define CCSR_DMA_ATR_TFLOWLVL_0         0x00000000
  89 #define CCSR_DMA_ATR_TFLOWLVL_1         0x06000000
  90 #define CCSR_DMA_ATR_TFLOWLVL_2         0x08000000
  91 #define CCSR_DMA_ATR_TFLOWLVL_3         0x0C000000
  92 #define CCSR_DMA_ATR_PCIORDER           0x02000000
  93 #define CCSR_DMA_ATR_SME                0x01000000
  94 #define CCSR_DMA_ATR_NOSNOOP            0x00040000
  95 #define CCSR_DMA_ATR_SNOOP              0x00050000
  96 #define CCSR_DMA_ATR_ESAD_MASK          0x0000000F
  97
  98 /**
  99  *  List Descriptor for extended chaining mode DMA operations.
 100  *
 101  *  The CLSDAR register points to the first (in a linked-list) List
 102  *  Descriptor.  Each object must be aligned on a 32-byte boundary. Each
 103  *  list descriptor points to a linked-list of link Descriptors.
 104  */
 105 struct fsl_dma_list_descriptor {
 106         __be64 next;            /* Address of next list descriptor */
 107         __be64 first_link;      /* Address of first link descriptor */
 108         __be32 source;          /* Source stride */
 109         __be32 dest;            /* Destination stride */
 110         u8 res[8];              /* Reserved */
 111 } __attribute__ ((aligned(32), packed));
 112
 113 /**
 114  *  Link Descriptor for basic and extended chaining mode DMA operations.
 115  *
 116  *  A Link Descriptor points to a single DMA buffer.  Each link descriptor
 117  *  must be aligned on a 32-byte boundary.
 118  */
 119 struct fsl_dma_link_descriptor {
 120         __be32 source_attr;     /* Programmed into SATR register */
 121         __be32 source_addr;     /* Programmed into SAR register */
 122         __be32 dest_attr;       /* Programmed into DATR register */
 123         __be32 dest_addr;       /* Programmed into DAR register */
 124         __be64 next;    /* Address of next link descriptor */
 125         __be32 count;   /* Byte count */
 126         u8 res[4];      /* Reserved */
 127 } __attribute__ ((aligned(32), packed));
 128
 129 /* DMA information needed to create a snd_soc_cpu_dai object
 130  *
 131  * ssi_stx_phys: bus address of SSI STX register to use
 132  * ssi_srx_phys: bus address of SSI SRX register to use
 133  * dma[0]: points to the DMA channel to use for playback
 134  * dma[1]: points to the DMA channel to use for capture
 135  * dma_irq[0]: IRQ of the DMA channel to use for playback
 136  * dma_irq[1]: IRQ of the DMA channel to use for capture
 137  */
 138 struct fsl_dma_info {
 139         dma_addr_t ssi_stx_phys;
 140         dma_addr_t ssi_srx_phys;
 141         struct ccsr_dma_channel __iomem *dma_channel[2];
 142         unsigned int dma_irq[2];
 143 };
 144
 145 extern struct snd_soc_platform fsl_soc_platform;
 146
 147 int fsl_dma_configure(struct fsl_dma_info *dma_info);
 148
 149 #endif