Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / sound / pci / ice1712 / phase.h
blob13e841b554887a8c6b8ae9eac8ff3d17c762087c
1 #ifndef __SOUND_PHASE_H
2 #define __SOUND_PHASE_H
4 /*
5 * ALSA driver for ICEnsemble ICE1712 (Envy24)
7 * Lowlevel functions for Terratec PHASE 22
9 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
27 #define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\
28 "{Terratec,Phase 28},"
30 #define VT1724_SUBDEVICE_PHASE22 0x3b155011
31 #define VT1724_SUBDEVICE_PHASE28 0x3b154911
33 /* entry point */
34 extern struct snd_ice1712_card_info snd_vt1724_phase_cards[];
36 /* PHASE28 GPIO bits */
37 #define PHASE28_SPI_MISO (1 << 21)
38 #define PHASE28_WM_RESET (1 << 20)
39 #define PHASE28_SPI_CLK (1 << 19)
40 #define PHASE28_SPI_MOSI (1 << 18)
41 #define PHASE28_WM_RW (1 << 17)
42 #define PHASE28_AC97_RESET (1 << 16)
43 #define PHASE28_DIGITAL_SEL1 (1 << 15)
44 #define PHASE28_HP_SEL (1 << 14)
45 #define PHASE28_WM_CS (1 << 12)
46 #define PHASE28_AC97_COMMIT (1 << 11)
47 #define PHASE28_AC97_ADDR (1 << 10)
48 #define PHASE28_AC97_DATA_LOW (1 << 9)
49 #define PHASE28_AC97_DATA_HIGH (1 << 8)
50 #define PHASE28_AC97_DATA_MASK 0xFF
51 #endif /* __SOUND_PHASE */