Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / include / asm-sparc64 / visasm.h
blob34f2ec64933b1e25f7463e587e2070dc26d89175
1 #ifndef _SPARC64_VISASM_H
2 #define _SPARC64_VISASM_H
4 /* visasm.h: FPU saving macros for VIS routines
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
7 */
9 #include <asm/pstate.h>
10 #include <asm/ptrace.h>
12 /* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
14 #define VISEntry \
15 rd %fprs, %o5; \
16 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
17 be,pt %icc, 297f; \
18 sethi %hi(297f), %g7; \
19 sethi %hi(VISenter), %g1; \
20 jmpl %g1 + %lo(VISenter), %g0; \
21 or %g7, %lo(297f), %g7; \
22 297: wr %g0, FPRS_FEF, %fprs; \
24 #define VISExit \
25 wr %g0, 0, %fprs;
27 /* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
28 * Must preserve %o5 between VISEntryHalf and VISExitHalf */
30 #define VISEntryHalf \
31 rd %fprs, %o5; \
32 andcc %o5, FPRS_FEF, %g0; \
33 be,pt %icc, 297f; \
34 sethi %hi(298f), %g7; \
35 sethi %hi(VISenterhalf), %g1; \
36 jmpl %g1 + %lo(VISenterhalf), %g0; \
37 or %g7, %lo(298f), %g7; \
38 clr %o5; \
39 297: wr %o5, FPRS_FEF, %fprs; \
40 298:
42 #define VISExitHalf \
43 wr %o5, 0, %fprs;
45 #ifndef __ASSEMBLY__
46 static inline void save_and_clear_fpu(void) {
47 __asm__ __volatile__ (
48 " rd %%fprs, %%o5\n"
49 " andcc %%o5, %0, %%g0\n"
50 " be,pt %%icc, 299f\n"
51 " sethi %%hi(298f), %%g7\n"
52 " sethi %%hi(VISenter), %%g1\n"
53 " jmpl %%g1 + %%lo(VISenter), %%g0\n"
54 " or %%g7, %%lo(298f), %%g7\n"
55 " 298: wr %%g0, 0, %%fprs\n"
56 " 299:\n"
57 " " : : "i" (FPRS_FEF|FPRS_DU) :
58 "o5", "g1", "g2", "g3", "g7", "cc");
60 #endif
62 #endif /* _SPARC64_ASI_H */