Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / include / asm-sh / ubc.h
blob56f4e30dc49ce7f4916f86483d8777a826ab72d3
1 /*
2 * include/asm-sh/ubc.h
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
11 #ifndef __ASM_SH_UBC_H
12 #define __ASM_SH_UBC_H
13 #ifdef __KERNEL__
15 #include <asm/cpu/ubc.h>
17 /* User Break Controller */
18 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
19 #define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
20 #else
21 #define UBC_TYPE_SH7729 0
22 #endif
24 #define BAMR_ASID (1 << 2)
25 #define BAMR_NONE 0
26 #define BAMR_10 0x1
27 #define BAMR_12 0x2
28 #define BAMR_ALL 0x3
29 #define BAMR_16 0x8
30 #define BAMR_20 0x9
32 #define BBR_INST (1 << 4)
33 #define BBR_DATA (2 << 4)
34 #define BBR_READ (1 << 2)
35 #define BBR_WRITE (2 << 2)
36 #define BBR_BYTE 0x1
37 #define BBR_HALF 0x2
38 #define BBR_LONG 0x3
39 #define BBR_QUAD (1 << 6) /* SH7750 */
40 #define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
41 #define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
43 #define BRCR_CMFA (1 << 15)
44 #define BRCR_CMFB (1 << 14)
45 #define BRCR_PCTE (1 << 11)
46 #define BRCR_PCBA (1 << 10) /* 1: after execution */
47 #define BRCR_DBEB (1 << 7)
48 #define BRCR_PCBB (1 << 6)
49 #define BRCR_SEQ (1 << 3)
50 #define BRCR_UBDE (1 << 0)
52 #ifndef __ASSEMBLY__
53 /* arch/sh/kernel/cpu/ubc.S */
54 extern void ubc_sleep(void);
56 #ifdef CONFIG_UBC_WAKEUP
57 extern void ubc_wakeup(void);
58 #else
59 #define ubc_wakeup() do { } while (0)
60 #endif
61 #endif
63 #endif /* __KERNEL__ */
64 #endif /* __ASM_SH_UBC_H */