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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / include / asm-mn10300 / cpu-regs.h
blob757e9b5388ea5bec4230fad2d44f78e812e68ff6
1 /* MN10300 Core system registers
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11 #ifndef _ASM_CPU_REGS_H
12 #define _ASM_CPU_REGS_H
13
14 #ifndef __ASSEMBLY__
15 #include <linux/types.h>
16 #endif
17
18 #ifdef CONFIG_MN10300_CPU_AM33V2
19 /* we tell the compiler to pretend to be AM33 so that it doesn't try and use
20 * the FP regs, but tell the assembler that we're actually allowed AM33v2
21 * instructions */
22 #ifndef __ASSEMBLY__
23 asm(" .am33_2\n");
24 #else
25 .am33_2
26 #endif
27 #endif
28
29 #ifdef __KERNEL__
30
31 #ifndef __ASSEMBLY__
32 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
33 #define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR))
34 #else
35 #define __SYSREG(ADDR, TYPE) ADDR
36 #define __SYSREGC(ADDR, TYPE) ADDR
37 #endif
38
39 /* CPU registers */
40 #define EPSW_FLAG_Z 0x00000001 /* zero flag */
41 #define EPSW_FLAG_N 0x00000002 /* negative flag */
42 #define EPSW_FLAG_C 0x00000004 /* carry flag */
43 #define EPSW_FLAG_V 0x00000008 /* overflow flag */
44 #define EPSW_IM 0x00000700 /* interrupt mode */
45 #define EPSW_IM_0 0x00000000 /* interrupt mode 0 */
46 #define EPSW_IM_1 0x00000100 /* interrupt mode 1 */
47 #define EPSW_IM_2 0x00000200 /* interrupt mode 2 */
48 #define EPSW_IM_3 0x00000300 /* interrupt mode 3 */
49 #define EPSW_IM_4 0x00000400 /* interrupt mode 4 */
50 #define EPSW_IM_5 0x00000500 /* interrupt mode 5 */
51 #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */
52 #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */
53 #define EPSW_IE 0x00000800 /* interrupt enable */
54 #define EPSW_S 0x00003000 /* software auxilliary bits */
55 #define EPSW_T 0x00008000 /* trace enable */
56 #define EPSW_nSL 0x00010000 /* not supervisor level */
57 #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */
58 #define EPSW_nAR 0x00040000 /* register bank control */
59 #define EPSW_ML 0x00080000 /* monitor level */
60 #define EPSW_FE 0x00100000 /* FPU enable */
61
62 /* FPU registers */
63 #define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
64 #define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */
65 #define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */
66 #define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */
67 #define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */
68 #define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */
69 #define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */
70 #define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */
71 #define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */
72 #define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */
73 #define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */
74 #define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */
75 #define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */
76 #define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */
77 #define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */
78 #define FPCR_RM 0x00030000 /* rounding mode */
79 #define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */
80 #define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */
81 #define FPCR_FCC_E 0x00080000 /* FPU equal condition code */
82 #define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */
83 #define FPCR_FCC_L 0x00200000 /* FPU less than condition code */
84 #define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */
85
86 /* CPU control registers */
87 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
88 #define CPUP_DWBD 0x0020 /* write buffer disable flag */
89 #define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */
90 #define CPUP_EXM 0x0080 /* exception operation mode */
91 #define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */
92 #define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */
93
94 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
95 #define CPUM_SLEEP 0x0004 /* set to enter sleep state */
96 #define CPUM_HALT 0x0008 /* set to enter halt state */
97 #define CPUM_STOP 0x0010 /* set to enter stop state */
98
99 #define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
100 #define CPUREV_TYPE 0x0000000f /* CPU type */
101 #define CPUREV_TYPE_S 0
102 #define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */
103 #define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */
104 #define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */
105 #define CPUREV_REVISION 0x000000f0 /* CPU revision */
106 #define CPUREV_REVISION_S 4
107 #define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
108 #define CPUREV_ICWAY_S 8
109 #define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */
110 #define CPUREV_ICSIZE_S 12
111 #define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */
112 #define CPUREV_DCWAY_S 16
113 #define CPUREV_DCSIZE 0x00f00000 /* data cache way size */
114 #define CPUREV_DCSIZE_S 20
115 #define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */
116 #define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */
117 #define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */
118
119 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
120
121 /* interrupt/exception control registers */
122 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
123 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
124 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
125 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
126 #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
127 #define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
128 #define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
129
130 #define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
131 #define TBR_TB 0xff000000 /* table base address bits 31-24 */
132 #define TBR_INT_CODE 0x00ffffff /* interrupt code */
133
134 #define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
135
136 #define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
137 #define sISR_IRQICE 0x00000001 /* ICE interrupt */
138 #define sISR_ISTEP 0x00000002 /* single step interrupt */
139 #define sISR_MISSA 0x00000004 /* memory access address misalignment fault */
140 #define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */
141 #define sISR_PIEXE 0x00000010 /* program interrupt */
142 #define sISR_MEMERR 0x00000020 /* illegal memory access fault */
143 #define sISR_IBREAK 0x00000040 /* instraction break interrupt */
144 #define sISR_DBSRL 0x00000080 /* debug serial interrupt */
145 #define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */
146 #define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */
147 #define sISR_OBREAK 0x00000400 /* operand break interrupt */
148 #define sISR_PRIV 0x00000800 /* privileged instruction execution fault */
149 #define sISR_BUSERR 0x00001000 /* bus error fault */
150 #define sISR_DBLFT 0x00002000 /* double fault */
151 #define sISR_DBG 0x00008000 /* debug reserved interrupt */
152 #define sISR_ITMISS 0x00010000 /* instruction TLB miss */
153 #define sISR_DTMISS 0x00020000 /* data TLB miss */
154 #define sISR_ITEX 0x00040000 /* instruction TLB access exception */
155 #define sISR_DTEX 0x00080000 /* data TLB access exception */
156 #define sISR_ILGIA 0x00100000 /* illegal instruction access exception */
157 #define sISR_ILGDA 0x00200000 /* illegal data access exception */
158 #define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */
159 #define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */
160 #define sISR_PRIDA 0x01000000 /* privileged space data access excep */
161 #define sISR_DISA 0x02000000 /* data space instruction access excep */
162 #define sISR_SYSC 0x04000000 /* system call instruction excep */
163 #define sISR_FPUD 0x08000000 /* FPU disabled excep */
164 #define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */
165 #define sISR_FPUOP 0x20000000 /* FPU operation excep */
166 #define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */
167
168 /* cache control registers */
169 #define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
170 #define CHCTR_ICEN 0x0001 /* instruction cache enable */
171 #define CHCTR_DCEN 0x0002 /* data cache enable */
172 #define CHCTR_ICBUSY 0x0004 /* instruction cache busy */
173 #define CHCTR_DCBUSY 0x0008 /* data cache busy */
174 #define CHCTR_ICINV 0x0010 /* instruction cache invalidate */
175 #define CHCTR_DCINV 0x0020 /* data cache invalidate */
176 #define CHCTR_DCWTMD 0x0040 /* data cache writing mode */
177 #define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */
178 #define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */
179 #define CHCTR_DCALMD 0x0080 /* data cache allocation mode */
180 #define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
181 #define CHCTR_DCWMD 0xf000 /* data cache way mode */
182
183 /* MMU control registers */
184 #define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
185 #define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
186 #define MMUCTR_ITE 0x00000040 /* instruction TLB enable */
187 #define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */
188 #define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */
189 #define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */
190 #define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */
191 #define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */
192 #define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */
193 #define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */
194 #define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */
195 #define MMUCTR_CE 0x00008000 /* cacheable bit enable */
196 #define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */
197 #define MMUCTR_DTE 0x00400000 /* data TLB enable */
198 #define MMUCTR_DIV 0x00800000 /* data TLB invalidate */
199 #define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */
200 #define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */
201 #define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */
202 #define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */
203 #define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
204 #define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
205 #define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
206
207 #define PIDR __SYSREG(0xc0000094, u16) /* PID register */
208 #define PIDR_PID 0x00ff /* process identifier */
209
210 #define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
211
212 #define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
213 #define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
214 #define xPTEL_V 0x00000001 /* TLB entry valid */
215 #define xPTEL_UNUSED1 0x00000002 /* unused bit */
216 #define xPTEL_UNUSED2 0x00000004 /* unused bit */
217 #define xPTEL_C 0x00000008 /* cached if set */
218 #define xPTEL_PV 0x00000010 /* page valid */
219 #define xPTEL_D 0x00000020 /* dirty */
220 #define xPTEL_PR 0x000001c0 /* page protection */
221 #define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */
222 #define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */
223 #define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */
224 #define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */
225 #define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */
226 #define xPTEL_G 0x00000200 /* global (use PID if 0) */
227 #define xPTEL_PS 0x00000c00 /* page size */
228 #define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */
229 #define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */
230 #define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */
231 #define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
232 #define xPTEL_PPN 0xfffff006 /* physical page number */
233
234 #define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */
235 #define xPTEL_UNUSED1_BIT 1
236 #define xPTEL_UNUSED2_BIT 2
237 #define xPTEL_C_BIT 3
238 #define xPTEL_PV_BIT 4
239 #define xPTEL_D_BIT 5
240 #define xPTEL_G_BIT 9
241
242 #define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
243 #define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
244 #define xPTEU_VPN 0xfffffc00 /* virtual page number */
245 #define xPTEU_PID 0x000000ff /* process identifier to which applicable */
246
247 #define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
248 #define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */
249 #define xPTEL2_V 0x00000001 /* TLB entry valid */
250 #define xPTEL2_C 0x00000002 /* cacheable */
251 #define xPTEL2_PV 0x00000004 /* page valid */
252 #define xPTEL2_D 0x00000008 /* dirty */
253 #define xPTEL2_PR 0x00000070 /* page protection */
254 #define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */
255 #define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */
256 #define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */
257 #define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */
258 #define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */
259 #define xPTEL2_G 0x00000080 /* global (use PID if 0) */
260 #define xPTEL2_PS 0x00000300 /* page size */
261 #define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */
262 #define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
263 #define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
264 #define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
265 #define xPTEL2_PPN 0xfffffc00 /* physical page number */
266
267 #define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
268 #define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
269 #define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */
270 #define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */
271 #define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */
272 #define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */
273 #define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */
274 #define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */
275 #define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */
276 #define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */
277 #define MMUFCR_xFC_TYPE 0x0020 /* access type flag */
278 #define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */
279 #define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */
280 #define MMUFCR_xFC_PR 0x01c0 /* page protection flag */
281 #define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */
282 #define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */
283 #define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */
284 #define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */
285 #define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
286 #define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
287
288 #endif /* __KERNEL__ */
289
290 #endif /* _ASM_CPU_REGS_H */
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