include/asm-mips/mach-pb1x00/pb1200.h

   1 /*
   2  * AMD Alchemy PB1200 Referrence Board
   3  * Board Registers defines.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  *
  23  */
  24 #ifndef __ASM_PB1200_H
  25 #define __ASM_PB1200_H
  26
  27 #include <linux/types.h>
  28 #include <asm/mach-au1x00/au1xxx_psc.h>
  29
  30 // This is defined in au1000.h with bogus value
  31 #undef AU1X00_EXTERNAL_INT
  32
  33 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
  34 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
  35 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
  36 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
  37
  38 /* SPI and SMB are muxed on the Pb1200 board.
  39    Refer to board documentation.
  40  */
  41 #define SPI_PSC_BASE        PSC0_BASE_ADDR
  42 #define SMBUS_PSC_BASE      PSC0_BASE_ADDR
  43 /* AC97 and I2S are muxed on the Pb1200 board.
  44    Refer to board documentation.
  45  */
  46 #define AC97_PSC_BASE       PSC1_BASE_ADDR
  47 #define I2S_PSC_BASE            PSC1_BASE_ADDR
  48
  49 #define BCSR_KSEG1_ADDR 0xAD800000
  50
  51 typedef volatile struct
  52 {
  53         /*00*/  u16 whoami;
  54                 u16 reserved0;
  55         /*04*/  u16 status;
  56                 u16 reserved1;
  57         /*08*/  u16 switches;
  58                 u16 reserved2;
  59         /*0C*/  u16 resets;
  60                 u16 reserved3;
  61
  62         /*10*/  u16 pcmcia;
  63                 u16 reserved4;
  64         /*14*/  u16 board;
  65                 u16 reserved5;
  66         /*18*/  u16 disk_leds;
  67                 u16 reserved6;
  68         /*1C*/  u16 system;
  69                 u16 reserved7;
  70
  71         /*20*/  u16 intclr;
  72                 u16 reserved8;
  73         /*24*/  u16 intset;
  74                 u16 reserved9;
  75         /*28*/  u16 intclr_mask;
  76                 u16 reserved10;
  77         /*2C*/  u16 intset_mask;
  78                 u16 reserved11;
  79
  80         /*30*/  u16 sig_status;
  81                 u16 reserved12;
  82         /*34*/  u16 int_status;
  83                 u16 reserved13;
  84         /*38*/  u16 reserved14;
  85                 u16 reserved15;
  86         /*3C*/  u16 reserved16;
  87                 u16 reserved17;
  88
  89 } BCSR;
  90
  91 static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
  92
  93 /*
  94  * Register bit definitions for the BCSRs
  95  */
  96 #define BCSR_WHOAMI_DCID        0x000F
  97 #define BCSR_WHOAMI_CPLD        0x00F0
  98 #define BCSR_WHOAMI_BOARD       0x0F00
  99
 100 #define BCSR_STATUS_PCMCIA0VS   0x0003
 101 #define BCSR_STATUS_PCMCIA1VS   0x000C
 102 #define BCSR_STATUS_SWAPBOOT    0x0040
 103 #define BCSR_STATUS_FLASHBUSY   0x0100
 104 #define BCSR_STATUS_IDECBLID    0x0200
 105 #define BCSR_STATUS_SD0WP               0x0400
 106 #define BCSR_STATUS_SD1WP               0x0800
 107 #define BCSR_STATUS_U0RXD               0x1000
 108 #define BCSR_STATUS_U1RXD               0x2000
 109
 110 #define BCSR_SWITCHES_OCTAL     0x00FF
 111 #define BCSR_SWITCHES_DIP_1     0x0080
 112 #define BCSR_SWITCHES_DIP_2     0x0040
 113 #define BCSR_SWITCHES_DIP_3     0x0020
 114 #define BCSR_SWITCHES_DIP_4     0x0010
 115 #define BCSR_SWITCHES_DIP_5     0x0008
 116 #define BCSR_SWITCHES_DIP_6     0x0004
 117 #define BCSR_SWITCHES_DIP_7     0x0002
 118 #define BCSR_SWITCHES_DIP_8     0x0001
 119 #define BCSR_SWITCHES_ROTARY    0x0F00
 120
 121 #define BCSR_RESETS_ETH         0x0001
 122 #define BCSR_RESETS_CAMERA      0x0002
 123 #define BCSR_RESETS_DC          0x0004
 124 #define BCSR_RESETS_IDE         0x0008
 125 /* not resets but in the same register */
 126 #define BCSR_RESETS_WSCFSM  0x0800
 127 #define BCSR_RESETS_PCS0MUX     0x1000
 128 #define BCSR_RESETS_PCS1MUX     0x2000
 129 #define BCSR_RESETS_SPISEL      0x4000
 130 #define BCSR_RESETS_SD1MUX  0x8000
 131
 132 #define BCSR_PCMCIA_PC0VPP      0x0003
 133 #define BCSR_PCMCIA_PC0VCC      0x000C
 134 #define BCSR_PCMCIA_PC0DRVEN    0x0010
 135 #define BCSR_PCMCIA_PC0RST      0x0080
 136 #define BCSR_PCMCIA_PC1VPP      0x0300
 137 #define BCSR_PCMCIA_PC1VCC      0x0C00
 138 #define BCSR_PCMCIA_PC1DRVEN    0x1000
 139 #define BCSR_PCMCIA_PC1RST      0x8000
 140
 141 #define BCSR_BOARD_LCDVEE       0x0001
 142 #define BCSR_BOARD_LCDVDD       0x0002
 143 #define BCSR_BOARD_LCDBL        0x0004
 144 #define BCSR_BOARD_CAMSNAP      0x0010
 145 #define BCSR_BOARD_CAMPWR       0x0020
 146 #define BCSR_BOARD_SD0PWR       0x0040
 147 #define BCSR_BOARD_SD1PWR       0x0080
 148
 149 #define BCSR_LEDS_DECIMALS      0x00FF
 150 #define BCSR_LEDS_LED0          0x0100
 151 #define BCSR_LEDS_LED1          0x0200
 152 #define BCSR_LEDS_LED2          0x0400
 153 #define BCSR_LEDS_LED3          0x0800
 154
 155 #define BCSR_SYSTEM_VDDI        0x001F
 156 #define BCSR_SYSTEM_POWEROFF    0x4000
 157 #define BCSR_SYSTEM_RESET       0x8000
 158
 159 /* Bit positions for the different interrupt sources */
 160 #define BCSR_INT_IDE            0x0001
 161 #define BCSR_INT_ETH            0x0002
 162 #define BCSR_INT_PC0            0x0004
 163 #define BCSR_INT_PC0STSCHG      0x0008
 164 #define BCSR_INT_PC1            0x0010
 165 #define BCSR_INT_PC1STSCHG      0x0020
 166 #define BCSR_INT_DC                     0x0040
 167 #define BCSR_INT_FLASHBUSY      0x0080
 168 #define BCSR_INT_PC0INSERT      0x0100
 169 #define BCSR_INT_PC0EJECT       0x0200
 170 #define BCSR_INT_PC1INSERT      0x0400
 171 #define BCSR_INT_PC1EJECT       0x0800
 172 #define BCSR_INT_SD0INSERT      0x1000
 173 #define BCSR_INT_SD0EJECT       0x2000
 174 #define BCSR_INT_SD1INSERT      0x4000
 175 #define BCSR_INT_SD1EJECT       0x8000
 176
 177 /* PCMCIA Db1x00 specific defines */
 178 #define PCMCIA_MAX_SOCK 1
 179 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
 180
 181 /* VPP/VCC */
 182 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 183         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 184
 185 #define AU1XXX_SMC91111_PHYS_ADDR       (0x0D000300)
 186 #define AU1XXX_SMC91111_IRQ                     PB1200_ETH_INT
 187
 188 #define AU1XXX_ATA_PHYS_ADDR            (0x0C800000)
 189 #define AU1XXX_ATA_REG_OFFSET           (5)
 190 #define AU1XXX_ATA_PHYS_LEN             (16 << AU1XXX_ATA_REG_OFFSET)
 191 #define AU1XXX_ATA_INT                  PB1200_IDE_INT
 192 #define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
 193 #define AU1XXX_ATA_RQSIZE               128
 194
 195 #define NAND_PHYS_ADDR   0x1C000000
 196
 197 /* Timing values as described in databook, * ns value stripped of
 198  * lower 2 bits.
 199  * These defines are here rather than an SOC1200 generic file because
 200  * the parts chosen on another board may be different and may require
 201  * different timings.
 202  */
 203 #define NAND_T_H                        (18 >> 2)
 204 #define NAND_T_PUL                      (30 >> 2)
 205 #define NAND_T_SU                       (30 >> 2)
 206 #define NAND_T_WH                       (30 >> 2)
 207
 208 /* Bitfield shift amounts */
 209 #define NAND_T_H_SHIFT          0
 210 #define NAND_T_PUL_SHIFT        4
 211 #define NAND_T_SU_SHIFT         8
 212 #define NAND_T_WH_SHIFT         12
 213
 214 #define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
 215                         ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
 216                         ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
 217                         ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
 218
 219
 220 /*
 221  * External Interrupts for Pb1200 as of 8/6/2004.
 222  * Bit positions in the CPLD registers can be calculated by taking
 223  * the interrupt define and subtracting the PB1200_INT_BEGIN value.
 224  *
 225  *   Example: IDE bis pos is  = 64 - 64
 226  *            ETH bit pos is  = 65 - 64
 227  */
 228 enum external_pb1200_ints {
 229         PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
 230
 231         PB1200_IDE_INT          = PB1200_INT_BEGIN,
 232         PB1200_ETH_INT,
 233         PB1200_PC0_INT,
 234         PB1200_PC0_STSCHG_INT,
 235         PB1200_PC1_INT,
 236         PB1200_PC1_STSCHG_INT,
 237         PB1200_DC_INT,
 238         PB1200_FLASHBUSY_INT,
 239         PB1200_PC0_INSERT_INT,
 240         PB1200_PC0_EJECT_INT,
 241         PB1200_PC1_INSERT_INT,
 242         PB1200_PC1_EJECT_INT,
 243         PB1200_SD0_INSERT_INT,
 244         PB1200_SD0_EJECT_INT,
 245         PB1200_SD1_INSERT_INT,
 246         PB1200_SD1_EJECT_INT,
 247
 248         PB1200_INT_END          = PB1200_INT_BEGIN + 15
 249 };
 250
 251 /* For drivers/pcmcia/au1000_db1x00.c */
 252 #define BOARD_PC0_INT PB1200_PC0_INT
 253 #define BOARD_PC1_INT PB1200_PC1_INT
 254 #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
 255
 256 /* Nand chip select */
 257 #define NAND_CS 1
 258
 259 #endif /* __ASM_PB1200_H */
 260