include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h

   1 #ifndef __iop_sap_in_defs_h
   2 #define __iop_sap_in_defs_h
   3
   4 /*
   5  * This file is autogenerated from
   6  *   file:           iop_sap_in.r
   7  *
   8  *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
   9  * Any changes here will be lost.
  10  *
  11  * -*- buffer-read-only: t -*-
  12  */
  13 /* Main access macros */
  14 #ifndef REG_RD
  15 #define REG_RD( scope, inst, reg ) \
  16   REG_READ( reg_##scope##_##reg, \
  17             (inst) + REG_RD_ADDR_##scope##_##reg )
  18 #endif
  19
  20 #ifndef REG_WR
  21 #define REG_WR( scope, inst, reg, val ) \
  22   REG_WRITE( reg_##scope##_##reg, \
  23              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  24 #endif
  25
  26 #ifndef REG_RD_VECT
  27 #define REG_RD_VECT( scope, inst, reg, index ) \
  28   REG_READ( reg_##scope##_##reg, \
  29             (inst) + REG_RD_ADDR_##scope##_##reg + \
  30             (index) * STRIDE_##scope##_##reg )
  31 #endif
  32
  33 #ifndef REG_WR_VECT
  34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  35   REG_WRITE( reg_##scope##_##reg, \
  36              (inst) + REG_WR_ADDR_##scope##_##reg + \
  37              (index) * STRIDE_##scope##_##reg, (val) )
  38 #endif
  39
  40 #ifndef REG_RD_INT
  41 #define REG_RD_INT( scope, inst, reg ) \
  42   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  43 #endif
  44
  45 #ifndef REG_WR_INT
  46 #define REG_WR_INT( scope, inst, reg, val ) \
  47   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  48 #endif
  49
  50 #ifndef REG_RD_INT_VECT
  51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  52   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  53             (index) * STRIDE_##scope##_##reg )
  54 #endif
  55
  56 #ifndef REG_WR_INT_VECT
  57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  58   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  59              (index) * STRIDE_##scope##_##reg, (val) )
  60 #endif
  61
  62 #ifndef REG_TYPE_CONV
  63 #define REG_TYPE_CONV( type, orgtype, val ) \
  64   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  65 #endif
  66
  67 #ifndef reg_page_size
  68 #define reg_page_size 8192
  69 #endif
  70
  71 #ifndef REG_ADDR
  72 #define REG_ADDR( scope, inst, reg ) \
  73   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  74 #endif
  75
  76 #ifndef REG_ADDR_VECT
  77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  78   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  79     (index) * STRIDE_##scope##_##reg )
  80 #endif
  81
  82 /* C-code for register scope iop_sap_in */
  83
  84 #define STRIDE_iop_sap_in_rw_bus_byte 4
  85 /* Register rw_bus_byte, scope iop_sap_in, type rw */
  86 typedef struct {
  87   unsigned int sync_sel     : 2;
  88   unsigned int sync_ext_src : 3;
  89   unsigned int sync_edge    : 2;
  90   unsigned int delay        : 2;
  91   unsigned int dummy1       : 23;
  92 } reg_iop_sap_in_rw_bus_byte;
  93 #define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
  94 #define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
  95
  96 #define STRIDE_iop_sap_in_rw_gio 4
  97 /* Register rw_gio, scope iop_sap_in, type rw */
  98 typedef struct {
  99   unsigned int sync_sel     : 2;
 100   unsigned int sync_ext_src : 3;
 101   unsigned int sync_edge    : 2;
 102   unsigned int delay        : 2;
 103   unsigned int logic        : 2;
 104   unsigned int dummy1       : 21;
 105 } reg_iop_sap_in_rw_gio;
 106 #define REG_RD_ADDR_iop_sap_in_rw_gio 16
 107 #define REG_WR_ADDR_iop_sap_in_rw_gio 16
 108
 109
 110 /* Constants */
 111 enum {
 112   regk_iop_sap_in_and                      = 0x00000002,
 113   regk_iop_sap_in_ext_clk200               = 0x00000003,
 114   regk_iop_sap_in_gio0                     = 0x00000000,
 115   regk_iop_sap_in_gio12                    = 0x00000003,
 116   regk_iop_sap_in_gio16                    = 0x00000004,
 117   regk_iop_sap_in_gio20                    = 0x00000005,
 118   regk_iop_sap_in_gio24                    = 0x00000006,
 119   regk_iop_sap_in_gio28                    = 0x00000007,
 120   regk_iop_sap_in_gio4                     = 0x00000001,
 121   regk_iop_sap_in_gio8                     = 0x00000002,
 122   regk_iop_sap_in_inv                      = 0x00000001,
 123   regk_iop_sap_in_neg                      = 0x00000002,
 124   regk_iop_sap_in_no                       = 0x00000000,
 125   regk_iop_sap_in_no_del_ext_clk200        = 0x00000002,
 126   regk_iop_sap_in_none                     = 0x00000000,
 127   regk_iop_sap_in_one                      = 0x00000001,
 128   regk_iop_sap_in_or                       = 0x00000003,
 129   regk_iop_sap_in_pos                      = 0x00000001,
 130   regk_iop_sap_in_pos_neg                  = 0x00000003,
 131   regk_iop_sap_in_rw_bus_byte_default      = 0x00000000,
 132   regk_iop_sap_in_rw_bus_byte_size         = 0x00000004,
 133   regk_iop_sap_in_rw_gio_default           = 0x00000000,
 134   regk_iop_sap_in_rw_gio_size              = 0x00000020,
 135   regk_iop_sap_in_timer_grp0_tmr3          = 0x00000000,
 136   regk_iop_sap_in_timer_grp1_tmr3          = 0x00000001,
 137   regk_iop_sap_in_tmr_clk200               = 0x00000001,
 138   regk_iop_sap_in_two                      = 0x00000002,
 139   regk_iop_sap_in_two_clk200               = 0x00000000
 140 };
 141 #endif /* __iop_sap_in_defs_h */