include/asm-blackfin/mach-bf527/irq.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf527/irq.h
   3  * based on:    include/asm-blackfin/mach-bf537/irq.h
   4  * author:      Michael Hennerich (michael.hennerich@analog.com)
   5  *
   6  * created:
   7  * description:
   8  *      system mmr register map
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #ifndef _BF527_IRQ_H_
  33 #define _BF527_IRQ_H_
  34
  35 /*
  36  * Interrupt source definitions
  37         Event Source    Core Event Name
  38         Core        Emulation               **
  39         Events         (highest priority)  EMU         0
  40         Reset                   RST         1
  41         NMI                     NMI         2
  42         Exception               EVX         3
  43         Reserved                --          4
  44         Hardware Error          IVHW        5
  45         Core Timer              IVTMR       6 *
  46
  47         .....
  48
  49          Software Interrupt 1    IVG14       31
  50          Software Interrupt 2    --
  51          (lowest priority)  IVG15       32 *
  52 */
  53
  54 #define NR_PERI_INTS    (2 * 32)
  55
  56 /* The ABSTRACT IRQ definitions */
  57 /** the first seven of the following are fixed, the rest you change if you need to **/
  58 #define IRQ_EMU                 0       /* Emulation */
  59 #define IRQ_RST                 1       /* reset */
  60 #define IRQ_NMI                 2       /* Non Maskable */
  61 #define IRQ_EVX                 3       /* Exception */
  62 #define IRQ_UNUSED              4       /* - unused interrupt */
  63 #define IRQ_HWERR               5       /* Hardware Error */
  64 #define IRQ_CORETMR             6       /* Core timer */
  65
  66 #define BFIN_IRQ(x)             ((x) + 7)
  67
  68 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
  69 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
  70 #define IRQ_DMAR0_BLK           BFIN_IRQ(2)     /* DMAR0 Block Interrupt */
  71 #define IRQ_DMAR1_BLK           BFIN_IRQ(3)     /* DMAR1 Block Interrupt */
  72 #define IRQ_DMAR0_OVR           BFIN_IRQ(4)     /* DMAR0 Overflow Error */
  73 #define IRQ_DMAR1_OVR           BFIN_IRQ(5)     /* DMAR1 Overflow Error */
  74 #define IRQ_PPI_ERROR           BFIN_IRQ(6)     /* PPI Error */
  75 #define IRQ_MAC_ERROR           BFIN_IRQ(7)     /* MAC Status */
  76 #define IRQ_SPORT0_ERROR        BFIN_IRQ(8)     /* SPORT0 Status */
  77 #define IRQ_SPORT1_ERROR        BFIN_IRQ(9)     /* SPORT1 Status */
  78 #define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
  79 #define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
  80 #define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
  81 #define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI/NAND) */
  82 #define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
  83 #define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
  84 #define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX) */
  85 #define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
  86 #define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
  87 #define IRQ_SPI                 BFIN_IRQ(21)    /* DMA 7 Channel (SPI) */
  88 #define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
  89 #define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
  90 #define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
  91 #define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
  92 #define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
  93 #define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
  94 #define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX/HDMA) */
  95 #define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
  96 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
  97 #define IRQ_NFC                 BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
  98 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
  99 #define IRQ_TMR0                BFIN_IRQ(32)    /* Timer 0 */
 100 #define IRQ_TMR1                BFIN_IRQ(33)    /* Timer 1 */
 101 #define IRQ_TMR2                BFIN_IRQ(34)    /* Timer 2 */
 102 #define IRQ_TMR3                BFIN_IRQ(35)    /* Timer 3 */
 103 #define IRQ_TMR4                BFIN_IRQ(36)    /* Timer 4 */
 104 #define IRQ_TMR5                BFIN_IRQ(37)    /* Timer 5 */
 105 #define IRQ_TMR6                BFIN_IRQ(38)    /* Timer 6 */
 106 #define IRQ_TMR7                BFIN_IRQ(39)    /* Timer 7 */
 107 #define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
 108 #define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
 109 #define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
 110 #define IRQ_MEM_DMA1            BFIN_IRQ(43)    /* MDMA Stream 1 */
 111 #define IRQ_WATCH               BFIN_IRQ(44)    /* Software Watchdog Timer */
 112 #define IRQ_PORTF_INTA          BFIN_IRQ(45)    /* Port F Interrupt A */
 113 #define IRQ_PORTF_INTB          BFIN_IRQ(46)    /* Port F Interrupt B */
 114 #define IRQ_SPI_ERROR           BFIN_IRQ(47)    /* SPI Status */
 115 #define IRQ_NFC_ERROR           BFIN_IRQ(48)    /* NAND Error */
 116 #define IRQ_HDMA_ERROR          BFIN_IRQ(49)    /* HDMA Error */
 117 #define IRQ_HDMA                BFIN_IRQ(50)    /* HDMA (TFI) */
 118 #define IRQ_USB_EINT            BFIN_IRQ(51)    /* USB_EINT Interrupt */
 119 #define IRQ_USB_INT0            BFIN_IRQ(52)    /* USB_INT0 Interrupt */
 120 #define IRQ_USB_INT1            BFIN_IRQ(53)    /* USB_INT1 Interrupt */
 121 #define IRQ_USB_INT2            BFIN_IRQ(54)    /* USB_INT2 Interrupt */
 122 #define IRQ_USB_DMA             BFIN_IRQ(55)    /* USB_DMAINT Interrupt */
 123
 124 #define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
 125
 126 #define IRQ_PF0         71
 127 #define IRQ_PF1         72
 128 #define IRQ_PF2         73
 129 #define IRQ_PF3         74
 130 #define IRQ_PF4         75
 131 #define IRQ_PF5         76
 132 #define IRQ_PF6         77
 133 #define IRQ_PF7         78
 134 #define IRQ_PF8         79
 135 #define IRQ_PF9         80
 136 #define IRQ_PF10        81
 137 #define IRQ_PF11        82
 138 #define IRQ_PF12        83
 139 #define IRQ_PF13        84
 140 #define IRQ_PF14        85
 141 #define IRQ_PF15        86
 142
 143 #define IRQ_PG0         87
 144 #define IRQ_PG1         88
 145 #define IRQ_PG2         89
 146 #define IRQ_PG3         90
 147 #define IRQ_PG4         91
 148 #define IRQ_PG5         92
 149 #define IRQ_PG6         93
 150 #define IRQ_PG7         94
 151 #define IRQ_PG8         95
 152 #define IRQ_PG9         96
 153 #define IRQ_PG10        97
 154 #define IRQ_PG11        98
 155 #define IRQ_PG12        99
 156 #define IRQ_PG13        100
 157 #define IRQ_PG14        101
 158 #define IRQ_PG15        102
 159
 160 #define IRQ_PH0         103
 161 #define IRQ_PH1         104
 162 #define IRQ_PH2         105
 163 #define IRQ_PH3         106
 164 #define IRQ_PH4         107
 165 #define IRQ_PH5         108
 166 #define IRQ_PH6         109
 167 #define IRQ_PH7         110
 168 #define IRQ_PH8         111
 169 #define IRQ_PH9         112
 170 #define IRQ_PH10        113
 171 #define IRQ_PH11        114
 172 #define IRQ_PH12        115
 173 #define IRQ_PH13        116
 174 #define IRQ_PH14        117
 175 #define IRQ_PH15        118
 176
 177 #define GPIO_IRQ_BASE   IRQ_PF0
 178
 179 #define NR_IRQS     (IRQ_PH15+1)
 180
 181 #define IVG7            7
 182 #define IVG8            8
 183 #define IVG9            9
 184 #define IVG10           10
 185 #define IVG11           11
 186 #define IVG12           12
 187 #define IVG13           13
 188 #define IVG14           14
 189 #define IVG15           15
 190
 191 /* IAR0 BIT FIELDS */
 192 #define IRQ_PLL_WAKEUP_POS      0
 193 #define IRQ_DMA0_ERROR_POS      4
 194 #define IRQ_DMAR0_BLK_POS       8
 195 #define IRQ_DMAR1_BLK_POS       12
 196 #define IRQ_DMAR0_OVR_POS       16
 197 #define IRQ_DMAR1_OVR_POS       20
 198 #define IRQ_PPI_ERROR_POS       24
 199 #define IRQ_MAC_ERROR_POS       28
 200
 201 /* IAR1 BIT FIELDS */
 202 #define IRQ_SPORT0_ERROR_POS    0
 203 #define IRQ_SPORT1_ERROR_POS    4
 204 #define IRQ_UART0_ERROR_POS     16
 205 #define IRQ_UART1_ERROR_POS     20
 206 #define IRQ_RTC_POS             24
 207 #define IRQ_PPI_POS             28
 208
 209 /* IAR2 BIT FIELDS */
 210 #define IRQ_SPORT0_RX_POS       0
 211 #define IRQ_SPORT0_TX_POS       4
 212 #define IRQ_SPORT1_RX_POS       8
 213 #define IRQ_SPORT1_TX_POS       12
 214 #define IRQ_TWI_POS             16
 215 #define IRQ_SPI_POS             20
 216 #define IRQ_UART0_RX_POS        24
 217 #define IRQ_UART0_TX_POS        28
 218
 219 /* IAR3 BIT FIELDS */
 220 #define IRQ_UART1_RX_POS        0
 221 #define IRQ_UART1_TX_POS        4
 222 #define IRQ_OPTSEC_POS          8
 223 #define IRQ_CNT_POS             12
 224 #define IRQ_MAC_RX_POS          16
 225 #define IRQ_PORTH_INTA_POS      20
 226 #define IRQ_MAC_TX_POS          24
 227 #define IRQ_PORTH_INTB_POS      28
 228
 229 /* IAR4 BIT FIELDS */
 230 #define IRQ_TMR0_POS            0
 231 #define IRQ_TMR1_POS            4
 232 #define IRQ_TMR2_POS            8
 233 #define IRQ_TMR3_POS            12
 234 #define IRQ_TMR4_POS            16
 235 #define IRQ_TMR5_POS            20
 236 #define IRQ_TMR6_POS            24
 237 #define IRQ_TMR7_POS            28
 238
 239 /* IAR5 BIT FIELDS */
 240 #define IRQ_PORTG_INTA_POS      0
 241 #define IRQ_PORTG_INTB_POS      4
 242 #define IRQ_MEM_DMA0_POS        8
 243 #define IRQ_MEM_DMA1_POS        12
 244 #define IRQ_WATCH_POS           16
 245 #define IRQ_PORTF_INTA_POS      20
 246 #define IRQ_PORTF_INTB_POS      24
 247 #define IRQ_SPI_ERROR_POS       28
 248
 249 /* IAR6 BIT FIELDS */
 250 #define IRQ_NFC_ERROR_POS       0
 251 #define IRQ_HDMA_ERROR_POS      4
 252 #define IRQ_HDMA_POS            8
 253 #define IRQ_USB_EINT_POS        12
 254 #define IRQ_USB_INT0_POS        16
 255 #define IRQ_USB_INT1_POS        20
 256 #define IRQ_USB_INT2_POS        24
 257 #define IRQ_USB_DMA_POS         28
 258
 259 #endif                          /* _BF527_IRQ_H_ */