Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / include / asm-arm / plat-s3c / regs-watchdog.h
blob56c4193b7a46c9402a8b13530cef81658abaab6d
1 /* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2410 Watchdog timer control
14 #ifndef __ASM_ARCH_REGS_WATCHDOG_H
15 #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
17 #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
19 #define S3C2410_WTCON S3C_WDOGREG(0x00)
20 #define S3C2410_WTDAT S3C_WDOGREG(0x04)
21 #define S3C2410_WTCNT S3C_WDOGREG(0x08)
23 /* the watchdog can either generate a reset pulse, or an
24 * interrupt.
27 #define S3C2410_WTCON_RSTEN (0x01)
28 #define S3C2410_WTCON_INTEN (1<<2)
29 #define S3C2410_WTCON_ENABLE (1<<5)
31 #define S3C2410_WTCON_DIV16 (0<<3)
32 #define S3C2410_WTCON_DIV32 (1<<3)
33 #define S3C2410_WTCON_DIV64 (2<<3)
34 #define S3C2410_WTCON_DIV128 (3<<3)
36 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37 #define S3C2410_WTCON_PRESCALE_MASK (0xff00)
39 #endif /* __ASM_ARCH_REGS_WATCHDOG_H */