include/asm-arm/arch-s3c2410/regs-dsc.h

   1 /* linux/include/asm-arm/arch-s3c2410/regs-dsc.h
   2  *
   3  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2440/S3C2412 Signal Drive Strength Control
  11 */
  12
  13
  14 #ifndef __ASM_ARCH_REGS_DSC_H
  15 #define __ASM_ARCH_REGS_DSC_H "2440-dsc"
  16
  17 #if defined(CONFIG_CPU_S3C2412)
  18 #define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
  19 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
  20 #endif
  21
  22 #if defined(CONFIG_CPU_S3C244X)
  23
  24 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
  25 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
  26
  27 #define S3C2440_SELECT_DSC0 (0)
  28 #define S3C2440_SELECT_DSC1 (1<<31)
  29
  30 #define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
  31
  32 #define S3C2440_DSC0_DISABLE    (1<<31)
  33
  34 #define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
  35 #define S3C2440_DSC0_ADDR_12mA  (0<<8)
  36 #define S3C2440_DSC0_ADDR_10mA  (1<<8)
  37 #define S3C2440_DSC0_ADDR_8mA   (2<<8)
  38 #define S3C2440_DSC0_ADDR_6mA   (3<<8)
  39 #define S3C2440_DSC0_ADDR_MASK  (3<<8)
  40
  41 /* D24..D31 */
  42 #define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
  43 #define S3C2440_DSC0_DATA3_12mA (0<<6)
  44 #define S3C2440_DSC0_DATA3_10mA (1<<6)
  45 #define S3C2440_DSC0_DATA3_8mA  (2<<6)
  46 #define S3C2440_DSC0_DATA3_6mA  (3<<6)
  47 #define S3C2440_DSC0_DATA3_MASK (3<<6)
  48
  49 /* D16..D23 */
  50 #define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
  51 #define S3C2440_DSC0_DATA2_12mA (0<<4)
  52 #define S3C2440_DSC0_DATA2_10mA (1<<4)
  53 #define S3C2440_DSC0_DATA2_8mA  (2<<4)
  54 #define S3C2440_DSC0_DATA2_6mA  (3<<4)
  55 #define S3C2440_DSC0_DATA2_MASK (3<<4)
  56
  57 /* D8..D15 */
  58 #define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
  59 #define S3C2440_DSC0_DATA1_12mA (0<<2)
  60 #define S3C2440_DSC0_DATA1_10mA (1<<2)
  61 #define S3C2440_DSC0_DATA1_8mA  (2<<2)
  62 #define S3C2440_DSC0_DATA1_6mA  (3<<2)
  63 #define S3C2440_DSC0_DATA1_MASK (3<<2)
  64
  65 /* D0..D7 */
  66 #define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
  67 #define S3C2440_DSC0_DATA0_12mA (0<<0)
  68 #define S3C2440_DSC0_DATA0_10mA (1<<0)
  69 #define S3C2440_DSC0_DATA0_8mA  (2<<0)
  70 #define S3C2440_DSC0_DATA0_6mA  (3<<0)
  71 #define S3C2440_DSC0_DATA0_MASK (3<<0)
  72
  73 #define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
  74 #define S3C2440_DSC1_SCK1_12mA  (0<<28)
  75 #define S3C2440_DSC1_SCK1_10mA  (1<<28)
  76 #define S3C2440_DSC1_SCK1_8mA   (2<<28)
  77 #define S3C2440_DSC1_SCK1_6mA   (3<<28)
  78 #define S3C2440_DSC1_SCK1_MASK  (3<<28)
  79
  80 #define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
  81 #define S3C2440_DSC1_SCK0_12mA  (0<<26)
  82 #define S3C2440_DSC1_SCK0_10mA  (1<<26)
  83 #define S3C2440_DSC1_SCK0_8mA   (2<<26)
  84 #define S3C2440_DSC1_SCK0_6mA   (3<<26)
  85 #define S3C2440_DSC1_SCK0_MASK  (3<<26)
  86
  87 #define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
  88 #define S3C2440_DSC1_SCKE_10mA  (0<<24)
  89 #define S3C2440_DSC1_SCKE_8mA   (1<<24)
  90 #define S3C2440_DSC1_SCKE_6mA   (2<<24)
  91 #define S3C2440_DSC1_SCKE_4mA   (3<<24)
  92 #define S3C2440_DSC1_SCKE_MASK  (3<<24)
  93
  94 /* SDRAM nRAS/nCAS */
  95 #define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
  96 #define S3C2440_DSC1_SDR_10mA   (0<<22)
  97 #define S3C2440_DSC1_SDR_8mA    (1<<22)
  98 #define S3C2440_DSC1_SDR_6mA    (2<<22)
  99 #define S3C2440_DSC1_SDR_4mA    (3<<22)
 100 #define S3C2440_DSC1_SDR_MASK   (3<<22)
 101
 102 /* NAND Flash Controller */
 103 #define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
 104 #define S3C2440_DSC1_NFC_10mA   (0<<20)
 105 #define S3C2440_DSC1_NFC_8mA    (1<<20)
 106 #define S3C2440_DSC1_NFC_6mA    (2<<20)
 107 #define S3C2440_DSC1_NFC_4mA    (3<<20)
 108 #define S3C2440_DSC1_NFC_MASK   (3<<20)
 109
 110 /* nBE[0..3] */
 111 #define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
 112 #define S3C2440_DSC1_nBE_10mA   (0<<18)
 113 #define S3C2440_DSC1_nBE_8mA    (1<<18)
 114 #define S3C2440_DSC1_nBE_6mA    (2<<18)
 115 #define S3C2440_DSC1_nBE_4mA    (3<<18)
 116 #define S3C2440_DSC1_nBE_MASK   (3<<18)
 117
 118 #define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
 119 #define S3C2440_DSC1_WOE_10mA   (0<<16)
 120 #define S3C2440_DSC1_WOE_8mA    (1<<16)
 121 #define S3C2440_DSC1_WOE_6mA    (2<<16)
 122 #define S3C2440_DSC1_WOE_4mA    (3<<16)
 123 #define S3C2440_DSC1_WOE_MASK   (3<<16)
 124
 125 #define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
 126 #define S3C2440_DSC1_CS7_10mA   (0<<14)
 127 #define S3C2440_DSC1_CS7_8mA    (1<<14)
 128 #define S3C2440_DSC1_CS7_6mA    (2<<14)
 129 #define S3C2440_DSC1_CS7_4mA    (3<<14)
 130 #define S3C2440_DSC1_CS7_MASK   (3<<14)
 131
 132 #define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
 133 #define S3C2440_DSC1_CS6_10mA   (0<<12)
 134 #define S3C2440_DSC1_CS6_8mA    (1<<12)
 135 #define S3C2440_DSC1_CS6_6mA    (2<<12)
 136 #define S3C2440_DSC1_CS6_4mA    (3<<12)
 137 #define S3C2440_DSC1_CS6_MASK   (3<<12)
 138
 139 #define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
 140 #define S3C2440_DSC1_CS5_10mA   (0<<10)
 141 #define S3C2440_DSC1_CS5_8mA    (1<<10)
 142 #define S3C2440_DSC1_CS5_6mA    (2<<10)
 143 #define S3C2440_DSC1_CS5_4mA    (3<<10)
 144 #define S3C2440_DSC1_CS5_MASK   (3<<10)
 145
 146 #define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
 147 #define S3C2440_DSC1_CS4_10mA   (0<<8)
 148 #define S3C2440_DSC1_CS4_8mA    (1<<8)
 149 #define S3C2440_DSC1_CS4_6mA    (2<<8)
 150 #define S3C2440_DSC1_CS4_4mA    (3<<8)
 151 #define S3C2440_DSC1_CS4_MASK   (3<<8)
 152
 153 #define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
 154 #define S3C2440_DSC1_CS3_10mA   (0<<6)
 155 #define S3C2440_DSC1_CS3_8mA    (1<<6)
 156 #define S3C2440_DSC1_CS3_6mA    (2<<6)
 157 #define S3C2440_DSC1_CS3_4mA    (3<<6)
 158 #define S3C2440_DSC1_CS3_MASK   (3<<6)
 159
 160 #define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
 161 #define S3C2440_DSC1_CS2_10mA   (0<<4)
 162 #define S3C2440_DSC1_CS2_8mA    (1<<4)
 163 #define S3C2440_DSC1_CS2_6mA    (2<<4)
 164 #define S3C2440_DSC1_CS2_4mA    (3<<4)
 165 #define S3C2440_DSC1_CS2_MASK   (3<<4)
 166
 167 #define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
 168 #define S3C2440_DSC1_CS1_10mA   (0<<2)
 169 #define S3C2440_DSC1_CS1_8mA    (1<<2)
 170 #define S3C2440_DSC1_CS1_6mA    (2<<2)
 171 #define S3C2440_DSC1_CS1_4mA    (3<<2)
 172 #define S3C2440_DSC1_CS1_MASK   (3<<2)
 173
 174 #define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
 175 #define S3C2440_DSC1_CS0_10mA   (0<<0)
 176 #define S3C2440_DSC1_CS0_8mA    (1<<0)
 177 #define S3C2440_DSC1_CS0_6mA    (2<<0)
 178 #define S3C2440_DSC1_CS0_4mA    (3<<0)
 179 #define S3C2440_DSC1_CS0_MASK   (3<<0)
 180
 181 #endif /* CONFIG_CPU_S3C2440 */
 182
 183 #endif  /* __ASM_ARCH_REGS_DSC_H */
 184