Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / include / asm-arm / arch-davinci / irqs.h
blobf4c5ca6da9f452af04bd8a5df8fcdf7ef9328e28
1 /*
2 * DaVinci interrupt controller definitions
4 * Copyright (C) 2006 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 #ifndef __ASM_ARCH_IRQS_H
28 #define __ASM_ARCH_IRQS_H
30 /* Base address */
31 #define DAVINCI_ARM_INTC_BASE 0x01C48000
33 /* Interrupt lines */
34 #define IRQ_VDINT0 0
35 #define IRQ_VDINT1 1
36 #define IRQ_VDINT2 2
37 #define IRQ_HISTINT 3
38 #define IRQ_H3AINT 4
39 #define IRQ_PRVUINT 5
40 #define IRQ_RSZINT 6
41 #define IRQ_VFOCINT 7
42 #define IRQ_VENCINT 8
43 #define IRQ_ASQINT 9
44 #define IRQ_IMXINT 10
45 #define IRQ_VLCDINT 11
46 #define IRQ_USBINT 12
47 #define IRQ_EMACINT 13
49 #define IRQ_CCINT0 16
50 #define IRQ_CCERRINT 17
51 #define IRQ_TCERRINT0 18
52 #define IRQ_TCERRINT 19
53 #define IRQ_PSCIN 20
55 #define IRQ_IDE 22
56 #define IRQ_HPIINT 23
57 #define IRQ_MBXINT 24
58 #define IRQ_MBRINT 25
59 #define IRQ_MMCINT 26
60 #define IRQ_SDIOINT 27
61 #define IRQ_MSINT 28
62 #define IRQ_DDRINT 29
63 #define IRQ_AEMIFINT 30
64 #define IRQ_VLQINT 31
65 #define IRQ_TINT0_TINT12 32
66 #define IRQ_TINT0_TINT34 33
67 #define IRQ_TINT1_TINT12 34
68 #define IRQ_TINT1_TINT34 35
69 #define IRQ_PWMINT0 36
70 #define IRQ_PWMINT1 37
71 #define IRQ_PWMINT2 38
72 #define IRQ_I2C 39
73 #define IRQ_UARTINT0 40
74 #define IRQ_UARTINT1 41
75 #define IRQ_UARTINT2 42
76 #define IRQ_SPINT0 43
77 #define IRQ_SPINT1 44
79 #define IRQ_DSP2ARM0 46
80 #define IRQ_DSP2ARM1 47
81 #define IRQ_GPIO0 48
82 #define IRQ_GPIO1 49
83 #define IRQ_GPIO2 50
84 #define IRQ_GPIO3 51
85 #define IRQ_GPIO4 52
86 #define IRQ_GPIO5 53
87 #define IRQ_GPIO6 54
88 #define IRQ_GPIO7 55
89 #define IRQ_GPIOBNK0 56
90 #define IRQ_GPIOBNK1 57
91 #define IRQ_GPIOBNK2 58
92 #define IRQ_GPIOBNK3 59
93 #define IRQ_GPIOBNK4 60
94 #define IRQ_COMMTX 61
95 #define IRQ_COMMRX 62
96 #define IRQ_EMUINT 63
98 #define DAVINCI_N_AINTC_IRQ 64
99 #define DAVINCI_N_GPIO 71
101 #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
103 #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
105 #endif /* __ASM_ARCH_IRQS_H */