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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / watchdog / iTCO_wdt.c
bloba0e6809e369ff997f3cdb03b92c98394c3d81d8a
1 /*
2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
3 *
4 * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
38 * 82801HB (ICH8) : document number 313056-003, 313057-009,
39 * 82801HR (ICH8R) : document number 313056-003, 313057-009,
40 * 82801HBM (ICH8M) : document number 313056-003, 313057-009,
41 * 82801HH (ICH8DH) : document number 313056-003, 313057-009,
42 * 82801HO (ICH8DO) : document number 313056-003, 313057-009,
43 * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009,
44 * 82801IB (ICH9) : document number 316972-001, 316973-001,
45 * 82801IR (ICH9R) : document number 316972-001, 316973-001,
46 * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
47 * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
48 * 631xESB (631xESB) : document number 313082-001, 313075-005,
49 * 632xESB (632xESB) : document number 313082-001, 313075-005
50 */
51
52 /*
53 * Includes, defines, variables, module parameters, ...
54 */
55
56 /* Module and version information */
57 #define DRV_NAME "iTCO_wdt"
58 #define DRV_VERSION "1.02"
59 #define DRV_RELDATE "26-Jul-2007"
60 #define PFX DRV_NAME ": "
61
62 /* Includes */
63 #include <linux/module.h> /* For module specific items */
64 #include <linux/moduleparam.h> /* For new moduleparam's */
65 #include <linux/types.h> /* For standard types (like size_t) */
66 #include <linux/errno.h> /* For the -ENODEV/... values */
67 #include <linux/kernel.h> /* For printk/panic/... */
68 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
69 #include <linux/watchdog.h> /* For the watchdog specific items */
70 #include <linux/init.h> /* For __init/__exit/... */
71 #include <linux/fs.h> /* For file operations */
72 #include <linux/platform_device.h> /* For platform_driver framework */
73 #include <linux/pci.h> /* For pci functions */
74 #include <linux/ioport.h> /* For io-port access */
75 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
76
77 #include <asm/uaccess.h> /* For copy_to_user/put_user/... */
78 #include <asm/io.h> /* For inb/outb/... */
79
80 /* TCO related info */
81 enum iTCO_chipsets {
82 TCO_ICH = 0, /* ICH */
83 TCO_ICH0, /* ICH0 */
84 TCO_ICH2, /* ICH2 */
85 TCO_ICH2M, /* ICH2-M */
86 TCO_ICH3, /* ICH3-S */
87 TCO_ICH3M, /* ICH3-M */
88 TCO_ICH4, /* ICH4 */
89 TCO_ICH4M, /* ICH4-M */
90 TCO_CICH, /* C-ICH */
91 TCO_ICH5, /* ICH5 & ICH5R */
92 TCO_6300ESB, /* 6300ESB */
93 TCO_ICH6, /* ICH6 & ICH6R */
94 TCO_ICH6M, /* ICH6-M */
95 TCO_ICH6W, /* ICH6W & ICH6RW */
96 TCO_ICH7, /* ICH7 & ICH7R */
97 TCO_ICH7M, /* ICH7-M */
98 TCO_ICH7MDH, /* ICH7-M DH */
99 TCO_ICH8, /* ICH8 & ICH8R */
100 TCO_ICH8ME, /* ICH8M-E */
101 TCO_ICH8DH, /* ICH8DH */
102 TCO_ICH8DO, /* ICH8DO */
103 TCO_ICH8M, /* ICH8M */
104 TCO_ICH9, /* ICH9 */
105 TCO_ICH9R, /* ICH9R */
106 TCO_ICH9DH, /* ICH9DH */
107 TCO_631XESB, /* 631xESB/632xESB */
108 };
109
110 static struct {
111 char *name;
112 unsigned int iTCO_version;
113 } iTCO_chipset_info[] __devinitdata = {
114 {"ICH", 1},
115 {"ICH0", 1},
116 {"ICH2", 1},
117 {"ICH2-M", 1},
118 {"ICH3-S", 1},
119 {"ICH3-M", 1},
120 {"ICH4", 1},
121 {"ICH4-M", 1},
122 {"C-ICH", 1},
123 {"ICH5 or ICH5R", 1},
124 {"6300ESB", 1},
125 {"ICH6 or ICH6R", 2},
126 {"ICH6-M", 2},
127 {"ICH6W or ICH6RW", 2},
128 {"ICH7 or ICH7R", 2},
129 {"ICH7-M", 2},
130 {"ICH7-M DH", 2},
131 {"ICH8 or ICH8R", 2},
132 {"ICH8M-E", 2},
133 {"ICH8DH", 2},
134 {"ICH8DO", 2},
135 {"ICH8M", 2},
136 {"ICH9", 2},
137 {"ICH9R", 2},
138 {"ICH9DH", 2},
139 {"631xESB/632xESB", 2},
140 {NULL,0}
141 };
142
143 #define ITCO_PCI_DEVICE(dev, data) \
144 .vendor = PCI_VENDOR_ID_INTEL, \
145 .device = dev, \
146 .subvendor = PCI_ANY_ID, \
147 .subdevice = PCI_ANY_ID, \
148 .class = 0, \
149 .class_mask = 0, \
150 .driver_data = data
151
152 /*
153 * This data only exists for exporting the supported PCI ids
154 * via MODULE_DEVICE_TABLE. We do not actually register a
155 * pci_driver, because the I/O Controller Hub has also other
156 * functions that probably will be registered by other drivers.
157 */
158 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
159 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )},
160 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )},
161 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )},
162 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )},
163 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )},
164 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )},
165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )},
166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )},
167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )},
168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )},
169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )},
171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )},
172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )},
173 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )},
174 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )},
175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )},
177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME )},
178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )},
179 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )},
180 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M )},
181 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )},
182 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )},
183 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )},
184 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
185 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
186 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
187 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
188 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
189 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
190 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
191 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
192 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
193 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
194 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
195 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
196 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
197 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
198 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
199 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
200 { 0, }, /* End of list */
201 };
202 MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
203
204 /* Address definitions for the TCO */
205 #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
206 #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
207
208 #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
209 #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
210 #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
211 #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
212 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
213 #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
214 #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
215 #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
216 #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
217
218 /* internal variables */
219 static unsigned long is_active;
220 static char expect_release;
221 static struct { /* this is private data for the iTCO_wdt device */
222 unsigned int iTCO_version; /* TCO version/generation */
223 unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
224 unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
225 spinlock_t io_lock; /* the lock for io operations */
226 struct pci_dev *pdev; /* the PCI-device */
227 } iTCO_wdt_private;
228
229 static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
230
231 /* module parameters */
232 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
233 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
234 module_param(heartbeat, int, 0);
235 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
236
237 static int nowayout = WATCHDOG_NOWAYOUT;
238 module_param(nowayout, int, 0);
239 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
240
241 /* iTCO Vendor Specific Support hooks */
242 #ifdef CONFIG_ITCO_VENDOR_SUPPORT
243 extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
244 extern void iTCO_vendor_pre_stop(unsigned long);
245 extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
246 extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
247 extern int iTCO_vendor_check_noreboot_on(void);
248 #else
249 #define iTCO_vendor_pre_start(acpibase, heartbeat) {}
250 #define iTCO_vendor_pre_stop(acpibase) {}
251 #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
252 #define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
253 #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
254 #endif
255
256 /*
257 * Some TCO specific functions
258 */
259
260 static inline unsigned int seconds_to_ticks(int seconds)
261 {
262 /* the internal timer is stored as ticks which decrement
263 * every 0.6 seconds */
264 return (seconds * 10) / 6;
265 }
266
267 static void iTCO_wdt_set_NO_REBOOT_bit(void)
268 {
269 u32 val32;
270
271 /* Set the NO_REBOOT bit: this disables reboots */
272 if (iTCO_wdt_private.iTCO_version == 2) {
273 val32 = readl(iTCO_wdt_private.gcs);
274 val32 |= 0x00000020;
275 writel(val32, iTCO_wdt_private.gcs);
276 } else if (iTCO_wdt_private.iTCO_version == 1) {
277 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
278 val32 |= 0x00000002;
279 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
280 }
281 }
282
283 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
284 {
285 int ret = 0;
286 u32 val32;
287
288 /* Unset the NO_REBOOT bit: this enables reboots */
289 if (iTCO_wdt_private.iTCO_version == 2) {
290 val32 = readl(iTCO_wdt_private.gcs);
291 val32 &= 0xffffffdf;
292 writel(val32, iTCO_wdt_private.gcs);
293
294 val32 = readl(iTCO_wdt_private.gcs);
295 if (val32 & 0x00000020)
296 ret = -EIO;
297 } else if (iTCO_wdt_private.iTCO_version == 1) {
298 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
299 val32 &= 0xfffffffd;
300 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
301
302 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
303 if (val32 & 0x00000002)
304 ret = -EIO;
305 }
306
307 return ret; /* returns: 0 = OK, -EIO = Error */
308 }
309
310 static int iTCO_wdt_start(void)
311 {
312 unsigned int val;
313
314 spin_lock(&iTCO_wdt_private.io_lock);
315
316 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
317
318 /* disable chipset's NO_REBOOT bit */
319 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
320 spin_unlock(&iTCO_wdt_private.io_lock);
321 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
322 return -EIO;
323 }
324
325 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
326 val = inw(TCO1_CNT);
327 val &= 0xf7ff;
328 outw(val, TCO1_CNT);
329 val = inw(TCO1_CNT);
330 spin_unlock(&iTCO_wdt_private.io_lock);
331
332 if (val & 0x0800)
333 return -1;
334 return 0;
335 }
336
337 static int iTCO_wdt_stop(void)
338 {
339 unsigned int val;
340
341 spin_lock(&iTCO_wdt_private.io_lock);
342
343 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
344
345 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
346 val = inw(TCO1_CNT);
347 val |= 0x0800;
348 outw(val, TCO1_CNT);
349 val = inw(TCO1_CNT);
350
351 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
352 iTCO_wdt_set_NO_REBOOT_bit();
353
354 spin_unlock(&iTCO_wdt_private.io_lock);
355
356 if ((val & 0x0800) == 0)
357 return -1;
358 return 0;
359 }
360
361 static int iTCO_wdt_keepalive(void)
362 {
363 spin_lock(&iTCO_wdt_private.io_lock);
364
365 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
366
367 /* Reload the timer by writing to the TCO Timer Counter register */
368 if (iTCO_wdt_private.iTCO_version == 2) {
369 outw(0x01, TCO_RLD);
370 } else if (iTCO_wdt_private.iTCO_version == 1) {
371 outb(0x01, TCO_RLD);
372 }
373
374 spin_unlock(&iTCO_wdt_private.io_lock);
375 return 0;
376 }
377
378 static int iTCO_wdt_set_heartbeat(int t)
379 {
380 unsigned int val16;
381 unsigned char val8;
382 unsigned int tmrval;
383
384 tmrval = seconds_to_ticks(t);
385 /* from the specs: */
386 /* "Values of 0h-3h are ignored and should not be attempted" */
387 if (tmrval < 0x04)
388 return -EINVAL;
389 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
390 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
391 return -EINVAL;
392
393 iTCO_vendor_pre_set_heartbeat(tmrval);
394
395 /* Write new heartbeat to watchdog */
396 if (iTCO_wdt_private.iTCO_version == 2) {
397 spin_lock(&iTCO_wdt_private.io_lock);
398 val16 = inw(TCOv2_TMR);
399 val16 &= 0xfc00;
400 val16 |= tmrval;
401 outw(val16, TCOv2_TMR);
402 val16 = inw(TCOv2_TMR);
403 spin_unlock(&iTCO_wdt_private.io_lock);
404
405 if ((val16 & 0x3ff) != tmrval)
406 return -EINVAL;
407 } else if (iTCO_wdt_private.iTCO_version == 1) {
408 spin_lock(&iTCO_wdt_private.io_lock);
409 val8 = inb(TCOv1_TMR);
410 val8 &= 0xc0;
411 val8 |= (tmrval & 0xff);
412 outb(val8, TCOv1_TMR);
413 val8 = inb(TCOv1_TMR);
414 spin_unlock(&iTCO_wdt_private.io_lock);
415
416 if ((val8 & 0x3f) != tmrval)
417 return -EINVAL;
418 }
419
420 heartbeat = t;
421 return 0;
422 }
423
424 static int iTCO_wdt_get_timeleft (int *time_left)
425 {
426 unsigned int val16;
427 unsigned char val8;
428
429 /* read the TCO Timer */
430 if (iTCO_wdt_private.iTCO_version == 2) {
431 spin_lock(&iTCO_wdt_private.io_lock);
432 val16 = inw(TCO_RLD);
433 val16 &= 0x3ff;
434 spin_unlock(&iTCO_wdt_private.io_lock);
435
436 *time_left = (val16 * 6) / 10;
437 } else if (iTCO_wdt_private.iTCO_version == 1) {
438 spin_lock(&iTCO_wdt_private.io_lock);
439 val8 = inb(TCO_RLD);
440 val8 &= 0x3f;
441 spin_unlock(&iTCO_wdt_private.io_lock);
442
443 *time_left = (val8 * 6) / 10;
444 } else
445 return -EINVAL;
446 return 0;
447 }
448
449 /*
450 * /dev/watchdog handling
451 */
452
453 static int iTCO_wdt_open (struct inode *inode, struct file *file)
454 {
455 /* /dev/watchdog can only be opened once */
456 if (test_and_set_bit(0, &is_active))
457 return -EBUSY;
458
459 /*
460 * Reload and activate timer
461 */
462 iTCO_wdt_keepalive();
463 iTCO_wdt_start();
464 return nonseekable_open(inode, file);
465 }
466
467 static int iTCO_wdt_release (struct inode *inode, struct file *file)
468 {
469 /*
470 * Shut off the timer.
471 */
472 if (expect_release == 42) {
473 iTCO_wdt_stop();
474 } else {
475 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
476 iTCO_wdt_keepalive();
477 }
478 clear_bit(0, &is_active);
479 expect_release = 0;
480 return 0;
481 }
482
483 static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
484 size_t len, loff_t * ppos)
485 {
486 /* See if we got the magic character 'V' and reload the timer */
487 if (len) {
488 if (!nowayout) {
489 size_t i;
490
491 /* note: just in case someone wrote the magic character
492 * five months ago... */
493 expect_release = 0;
494
495 /* scan to see whether or not we got the magic character */
496 for (i = 0; i != len; i++) {
497 char c;
498 if (get_user(c, data+i))
499 return -EFAULT;
500 if (c == 'V')
501 expect_release = 42;
502 }
503 }
504
505 /* someone wrote to us, we should reload the timer */
506 iTCO_wdt_keepalive();
507 }
508 return len;
509 }
510
511 static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
512 unsigned int cmd, unsigned long arg)
513 {
514 int new_options, retval = -EINVAL;
515 int new_heartbeat;
516 void __user *argp = (void __user *)arg;
517 int __user *p = argp;
518 static struct watchdog_info ident = {
519 .options = WDIOF_SETTIMEOUT |
520 WDIOF_KEEPALIVEPING |
521 WDIOF_MAGICCLOSE,
522 .firmware_version = 0,
523 .identity = DRV_NAME,
524 };
525
526 switch (cmd) {
527 case WDIOC_GETSUPPORT:
528 return copy_to_user(argp, &ident,
529 sizeof (ident)) ? -EFAULT : 0;
530
531 case WDIOC_GETSTATUS:
532 case WDIOC_GETBOOTSTATUS:
533 return put_user(0, p);
534
535 case WDIOC_KEEPALIVE:
536 iTCO_wdt_keepalive();
537 return 0;
538
539 case WDIOC_SETOPTIONS:
540 {
541 if (get_user(new_options, p))
542 return -EFAULT;
543
544 if (new_options & WDIOS_DISABLECARD) {
545 iTCO_wdt_stop();
546 retval = 0;
547 }
548
549 if (new_options & WDIOS_ENABLECARD) {
550 iTCO_wdt_keepalive();
551 iTCO_wdt_start();
552 retval = 0;
553 }
554
555 return retval;
556 }
557
558 case WDIOC_SETTIMEOUT:
559 {
560 if (get_user(new_heartbeat, p))
561 return -EFAULT;
562
563 if (iTCO_wdt_set_heartbeat(new_heartbeat))
564 return -EINVAL;
565
566 iTCO_wdt_keepalive();
567 /* Fall */
568 }
569
570 case WDIOC_GETTIMEOUT:
571 return put_user(heartbeat, p);
572
573 case WDIOC_GETTIMELEFT:
574 {
575 int time_left;
576
577 if (iTCO_wdt_get_timeleft(&time_left))
578 return -EINVAL;
579
580 return put_user(time_left, p);
581 }
582
583 default:
584 return -ENOTTY;
585 }
586 }
587
588 /*
589 * Kernel Interfaces
590 */
591
592 static const struct file_operations iTCO_wdt_fops = {
593 .owner = THIS_MODULE,
594 .llseek = no_llseek,
595 .write = iTCO_wdt_write,
596 .ioctl = iTCO_wdt_ioctl,
597 .open = iTCO_wdt_open,
598 .release = iTCO_wdt_release,
599 };
600
601 static struct miscdevice iTCO_wdt_miscdev = {
602 .minor = WATCHDOG_MINOR,
603 .name = "watchdog",
604 .fops = &iTCO_wdt_fops,
605 };
606
607 /*
608 * Init & exit routines
609 */
610
611 static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
612 {
613 int ret;
614 u32 base_address;
615 unsigned long RCBA;
616 unsigned long val32;
617
618 /*
619 * Find the ACPI/PM base I/O address which is the base
620 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
621 * ACPIBASE is bits [15:7] from 0x40-0x43
622 */
623 pci_read_config_dword(pdev, 0x40, &base_address);
624 base_address &= 0x0000ff80;
625 if (base_address == 0x00000000) {
626 /* Something's wrong here, ACPIBASE has to be set */
627 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
628 pci_dev_put(pdev);
629 return -ENODEV;
630 }
631 iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
632 iTCO_wdt_private.ACPIBASE = base_address;
633 iTCO_wdt_private.pdev = pdev;
634
635 /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
636 /* To get access to it you have to read RCBA from PCI Config space 0xf0
637 and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
638 if (iTCO_wdt_private.iTCO_version == 2) {
639 pci_read_config_dword(pdev, 0xf0, &base_address);
640 RCBA = base_address & 0xffffc000;
641 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
642 }
643
644 /* Check chipset's NO_REBOOT bit */
645 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
646 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
647 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
648 goto out;
649 }
650
651 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
652 iTCO_wdt_set_NO_REBOOT_bit();
653
654 /* Set the TCO_EN bit in SMI_EN register */
655 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
656 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
657 SMI_EN );
658 ret = -EIO;
659 goto out;
660 }
661 val32 = inl(SMI_EN);
662 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
663 outl(val32, SMI_EN);
664 release_region(SMI_EN, 4);
665
666 /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
667 if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
668 printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
669 TCOBASE);
670 ret = -EIO;
671 goto out;
672 }
673
674 printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
675 iTCO_chipset_info[ent->driver_data].name,
676 iTCO_chipset_info[ent->driver_data].iTCO_version,
677 TCOBASE);
678
679 /* Clear out the (probably old) status */
680 outb(0, TCO1_STS);
681 outb(3, TCO2_STS);
682
683 /* Make sure the watchdog is not running */
684 iTCO_wdt_stop();
685
686 /* Check that the heartbeat value is within it's range ; if not reset to the default */
687 if (iTCO_wdt_set_heartbeat(heartbeat)) {
688 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
689 printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
690 heartbeat);
691 }
692
693 ret = misc_register(&iTCO_wdt_miscdev);
694 if (ret != 0) {
695 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
696 WATCHDOG_MINOR, ret);
697 goto unreg_region;
698 }
699
700 printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
701 heartbeat, nowayout);
702
703 return 0;
704
705 unreg_region:
706 release_region (TCOBASE, 0x20);
707 out:
708 if (iTCO_wdt_private.iTCO_version == 2)
709 iounmap(iTCO_wdt_private.gcs);
710 pci_dev_put(iTCO_wdt_private.pdev);
711 iTCO_wdt_private.ACPIBASE = 0;
712 return ret;
713 }
714
715 static void __devexit iTCO_wdt_cleanup(void)
716 {
717 /* Stop the timer before we leave */
718 if (!nowayout)
719 iTCO_wdt_stop();
720
721 /* Deregister */
722 misc_deregister(&iTCO_wdt_miscdev);
723 release_region(TCOBASE, 0x20);
724 if (iTCO_wdt_private.iTCO_version == 2)
725 iounmap(iTCO_wdt_private.gcs);
726 pci_dev_put(iTCO_wdt_private.pdev);
727 iTCO_wdt_private.ACPIBASE = 0;
728 }
729
730 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
731 {
732 int found = 0;
733 struct pci_dev *pdev = NULL;
734 const struct pci_device_id *ent;
735
736 spin_lock_init(&iTCO_wdt_private.io_lock);
737
738 for_each_pci_dev(pdev) {
739 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
740 if (ent) {
741 if (!(iTCO_wdt_init(pdev, ent, dev))) {
742 found++;
743 break;
744 }
745 }
746 }
747
748 if (!found) {
749 printk(KERN_INFO PFX "No card detected\n");
750 return -ENODEV;
751 }
752
753 return 0;
754 }
755
756 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
757 {
758 if (iTCO_wdt_private.ACPIBASE)
759 iTCO_wdt_cleanup();
760
761 return 0;
762 }
763
764 static void iTCO_wdt_shutdown(struct platform_device *dev)
765 {
766 iTCO_wdt_stop();
767 }
768
769 #define iTCO_wdt_suspend NULL
770 #define iTCO_wdt_resume NULL
771
772 static struct platform_driver iTCO_wdt_driver = {
773 .probe = iTCO_wdt_probe,
774 .remove = __devexit_p(iTCO_wdt_remove),
775 .shutdown = iTCO_wdt_shutdown,
776 .suspend = iTCO_wdt_suspend,
777 .resume = iTCO_wdt_resume,
778 .driver = {
779 .owner = THIS_MODULE,
780 .name = DRV_NAME,
781 },
782 };
783
784 static int __init iTCO_wdt_init_module(void)
785 {
786 int err;
787
788 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
789 DRV_VERSION, DRV_RELDATE);
790
791 err = platform_driver_register(&iTCO_wdt_driver);
792 if (err)
793 return err;
794
795 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
796 if (IS_ERR(iTCO_wdt_platform_device)) {
797 err = PTR_ERR(iTCO_wdt_platform_device);
798 goto unreg_platform_driver;
799 }
800
801 return 0;
802
803 unreg_platform_driver:
804 platform_driver_unregister(&iTCO_wdt_driver);
805 return err;
806 }
807
808 static void __exit iTCO_wdt_cleanup_module(void)
809 {
810 platform_device_unregister(iTCO_wdt_platform_device);
811 platform_driver_unregister(&iTCO_wdt_driver);
812 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
813 }
814
815 module_init(iTCO_wdt_init_module);
816 module_exit(iTCO_wdt_cleanup_module);
817
818 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
819 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
820 MODULE_VERSION(DRV_VERSION);
821 MODULE_LICENSE("GPL");
822 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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