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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / video / intelfb / intelfbhw.c
blobfa1fff5535654e4f6bbce1c294efd9031d16d1a2
1 /*
2 * intelfb
3 *
4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5 *
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7 * 2004 Sylvain Meyer
8 *
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
15 *
16 * Author: David Dawes
17 *
18 */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
26 #include <linux/mm.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/pci.h>
33 #include <linux/vmalloc.h>
34 #include <linux/pagemap.h>
35 #include <linux/interrupt.h>
36
37 #include <asm/io.h>
38
39 #include "intelfb.h"
40 #include "intelfbhw.h"
41
42 struct pll_min_max {
43 int min_m, max_m, min_m1, max_m1;
44 int min_m2, max_m2, min_n, max_n;
45 int min_p, max_p, min_p1, max_p1;
46 int min_vco, max_vco, p_transition_clk, ref_clk;
47 int p_inc_lo, p_inc_hi;
48 };
49
50 #define PLLS_I8xx 0
51 #define PLLS_I9xx 1
52 #define PLLS_MAX 2
53
54 static struct pll_min_max plls[PLLS_MAX] = {
55 { 108, 140, 18, 26,
56 6, 16, 3, 16,
57 4, 128, 0, 31,
58 930000, 1400000, 165000, 48000,
59 4, 2 }, /* I8xx */
60
61 { 75, 120, 10, 20,
62 5, 9, 4, 7,
63 5, 80, 1, 8,
64 1400000, 2800000, 200000, 96000,
65 10, 5 } /* I9xx */
66 };
67
68 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
69 {
70 u32 tmp;
71 if (!pdev || !dinfo)
72 return 1;
73
74 switch (pdev->device) {
75 case PCI_DEVICE_ID_INTEL_830M:
76 dinfo->name = "Intel(R) 830M";
77 dinfo->chipset = INTEL_830M;
78 dinfo->mobile = 1;
79 dinfo->pll_index = PLLS_I8xx;
80 return 0;
81 case PCI_DEVICE_ID_INTEL_845G:
82 dinfo->name = "Intel(R) 845G";
83 dinfo->chipset = INTEL_845G;
84 dinfo->mobile = 0;
85 dinfo->pll_index = PLLS_I8xx;
86 return 0;
87 case PCI_DEVICE_ID_INTEL_85XGM:
88 tmp = 0;
89 dinfo->mobile = 1;
90 dinfo->pll_index = PLLS_I8xx;
91 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
92 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
93 INTEL_85X_VARIANT_MASK) {
94 case INTEL_VAR_855GME:
95 dinfo->name = "Intel(R) 855GME";
96 dinfo->chipset = INTEL_855GME;
97 return 0;
98 case INTEL_VAR_855GM:
99 dinfo->name = "Intel(R) 855GM";
100 dinfo->chipset = INTEL_855GM;
101 return 0;
102 case INTEL_VAR_852GME:
103 dinfo->name = "Intel(R) 852GME";
104 dinfo->chipset = INTEL_852GME;
105 return 0;
106 case INTEL_VAR_852GM:
107 dinfo->name = "Intel(R) 852GM";
108 dinfo->chipset = INTEL_852GM;
109 return 0;
110 default:
111 dinfo->name = "Intel(R) 852GM/855GM";
112 dinfo->chipset = INTEL_85XGM;
113 return 0;
114 }
115 break;
116 case PCI_DEVICE_ID_INTEL_865G:
117 dinfo->name = "Intel(R) 865G";
118 dinfo->chipset = INTEL_865G;
119 dinfo->mobile = 0;
120 dinfo->pll_index = PLLS_I8xx;
121 return 0;
122 case PCI_DEVICE_ID_INTEL_915G:
123 dinfo->name = "Intel(R) 915G";
124 dinfo->chipset = INTEL_915G;
125 dinfo->mobile = 0;
126 dinfo->pll_index = PLLS_I9xx;
127 return 0;
128 case PCI_DEVICE_ID_INTEL_915GM:
129 dinfo->name = "Intel(R) 915GM";
130 dinfo->chipset = INTEL_915GM;
131 dinfo->mobile = 1;
132 dinfo->pll_index = PLLS_I9xx;
133 return 0;
134 case PCI_DEVICE_ID_INTEL_945G:
135 dinfo->name = "Intel(R) 945G";
136 dinfo->chipset = INTEL_945G;
137 dinfo->mobile = 0;
138 dinfo->pll_index = PLLS_I9xx;
139 return 0;
140 case PCI_DEVICE_ID_INTEL_945GM:
141 dinfo->name = "Intel(R) 945GM";
142 dinfo->chipset = INTEL_945GM;
143 dinfo->mobile = 1;
144 dinfo->pll_index = PLLS_I9xx;
145 return 0;
146 default:
147 return 1;
148 }
149 }
150
151 int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
152 int *stolen_size)
153 {
154 struct pci_dev *bridge_dev;
155 u16 tmp;
156 int stolen_overhead;
157
158 if (!pdev || !aperture_size || !stolen_size)
159 return 1;
160
161 /* Find the bridge device. It is always 0:0.0 */
162 if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
163 ERR_MSG("cannot find bridge device\n");
164 return 1;
165 }
166
167 /* Get the fb aperture size and "stolen" memory amount. */
168 tmp = 0;
169 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
170 pci_dev_put(bridge_dev);
171
172 switch (pdev->device) {
173 case PCI_DEVICE_ID_INTEL_915G:
174 case PCI_DEVICE_ID_INTEL_915GM:
175 case PCI_DEVICE_ID_INTEL_945G:
176 case PCI_DEVICE_ID_INTEL_945GM:
177 /* 915 and 945 chipsets support a 256MB aperture.
178 Aperture size is determined by inspected the
179 base address of the aperture. */
180 if (pci_resource_start(pdev, 2) & 0x08000000)
181 *aperture_size = MB(128);
182 else
183 *aperture_size = MB(256);
184 break;
185 default:
186 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
187 *aperture_size = MB(64);
188 else
189 *aperture_size = MB(128);
190 break;
191 }
192
193 /* Stolen memory size is reduced by the GTT and the popup.
194 GTT is 1K per MB of aperture size, and popup is 4K. */
195 stolen_overhead = (*aperture_size / MB(1)) + 4;
196 switch(pdev->device) {
197 case PCI_DEVICE_ID_INTEL_830M:
198 case PCI_DEVICE_ID_INTEL_845G:
199 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
200 case INTEL_830_GMCH_GMS_STOLEN_512:
201 *stolen_size = KB(512) - KB(stolen_overhead);
202 return 0;
203 case INTEL_830_GMCH_GMS_STOLEN_1024:
204 *stolen_size = MB(1) - KB(stolen_overhead);
205 return 0;
206 case INTEL_830_GMCH_GMS_STOLEN_8192:
207 *stolen_size = MB(8) - KB(stolen_overhead);
208 return 0;
209 case INTEL_830_GMCH_GMS_LOCAL:
210 ERR_MSG("only local memory found\n");
211 return 1;
212 case INTEL_830_GMCH_GMS_DISABLED:
213 ERR_MSG("video memory is disabled\n");
214 return 1;
215 default:
216 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
217 tmp & INTEL_830_GMCH_GMS_MASK);
218 return 1;
219 }
220 break;
221 default:
222 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
223 case INTEL_855_GMCH_GMS_STOLEN_1M:
224 *stolen_size = MB(1) - KB(stolen_overhead);
225 return 0;
226 case INTEL_855_GMCH_GMS_STOLEN_4M:
227 *stolen_size = MB(4) - KB(stolen_overhead);
228 return 0;
229 case INTEL_855_GMCH_GMS_STOLEN_8M:
230 *stolen_size = MB(8) - KB(stolen_overhead);
231 return 0;
232 case INTEL_855_GMCH_GMS_STOLEN_16M:
233 *stolen_size = MB(16) - KB(stolen_overhead);
234 return 0;
235 case INTEL_855_GMCH_GMS_STOLEN_32M:
236 *stolen_size = MB(32) - KB(stolen_overhead);
237 return 0;
238 case INTEL_915G_GMCH_GMS_STOLEN_48M:
239 *stolen_size = MB(48) - KB(stolen_overhead);
240 return 0;
241 case INTEL_915G_GMCH_GMS_STOLEN_64M:
242 *stolen_size = MB(64) - KB(stolen_overhead);
243 return 0;
244 case INTEL_855_GMCH_GMS_DISABLED:
245 ERR_MSG("video memory is disabled\n");
246 return 0;
247 default:
248 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
249 tmp & INTEL_855_GMCH_GMS_MASK);
250 return 1;
251 }
252 }
253 }
254
255 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
256 {
257 int dvo = 0;
258
259 if (INREG(LVDS) & PORT_ENABLE)
260 dvo |= LVDS_PORT;
261 if (INREG(DVOA) & PORT_ENABLE)
262 dvo |= DVOA_PORT;
263 if (INREG(DVOB) & PORT_ENABLE)
264 dvo |= DVOB_PORT;
265 if (INREG(DVOC) & PORT_ENABLE)
266 dvo |= DVOC_PORT;
267
268 return dvo;
269 }
270
271 const char * intelfbhw_dvo_to_string(int dvo)
272 {
273 if (dvo & DVOA_PORT)
274 return "DVO port A";
275 else if (dvo & DVOB_PORT)
276 return "DVO port B";
277 else if (dvo & DVOC_PORT)
278 return "DVO port C";
279 else if (dvo & LVDS_PORT)
280 return "LVDS port";
281 else
282 return NULL;
283 }
284
285
286 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
287 struct fb_var_screeninfo *var)
288 {
289 int bytes_per_pixel;
290 int tmp;
291
292 #if VERBOSE > 0
293 DBG_MSG("intelfbhw_validate_mode\n");
294 #endif
295
296 bytes_per_pixel = var->bits_per_pixel / 8;
297 if (bytes_per_pixel == 3)
298 bytes_per_pixel = 4;
299
300 /* Check if enough video memory. */
301 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
302 if (tmp > dinfo->fb.size) {
303 WRN_MSG("Not enough video ram for mode "
304 "(%d KByte vs %d KByte).\n",
305 BtoKB(tmp), BtoKB(dinfo->fb.size));
306 return 1;
307 }
308
309 /* Check if x/y limits are OK. */
310 if (var->xres - 1 > HACTIVE_MASK) {
311 WRN_MSG("X resolution too large (%d vs %d).\n",
312 var->xres, HACTIVE_MASK + 1);
313 return 1;
314 }
315 if (var->yres - 1 > VACTIVE_MASK) {
316 WRN_MSG("Y resolution too large (%d vs %d).\n",
317 var->yres, VACTIVE_MASK + 1);
318 return 1;
319 }
320 if (var->xres < 4) {
321 WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);
322 return 1;
323 }
324 if (var->yres < 4) {
325 WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);
326 return 1;
327 }
328
329 /* Check for doublescan modes. */
330 if (var->vmode & FB_VMODE_DOUBLE) {
331 WRN_MSG("Mode is double-scan.\n");
332 return 1;
333 }
334
335 if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {
336 WRN_MSG("Odd number of lines in interlaced mode\n");
337 return 1;
338 }
339
340 /* Check if clock is OK. */
341 tmp = 1000000000 / var->pixclock;
342 if (tmp < MIN_CLOCK) {
343 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
344 (tmp + 500) / 1000, MIN_CLOCK / 1000);
345 return 1;
346 }
347 if (tmp > MAX_CLOCK) {
348 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
349 (tmp + 500) / 1000, MAX_CLOCK / 1000);
350 return 1;
351 }
352
353 return 0;
354 }
355
356 int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
357 {
358 struct intelfb_info *dinfo = GET_DINFO(info);
359 u32 offset, xoffset, yoffset;
360
361 #if VERBOSE > 0
362 DBG_MSG("intelfbhw_pan_display\n");
363 #endif
364
365 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
366 yoffset = var->yoffset;
367
368 if ((xoffset + var->xres > var->xres_virtual) ||
369 (yoffset + var->yres > var->yres_virtual))
370 return -EINVAL;
371
372 offset = (yoffset * dinfo->pitch) +
373 (xoffset * var->bits_per_pixel) / 8;
374
375 offset += dinfo->fb.offset << 12;
376
377 dinfo->vsync.pan_offset = offset;
378 if ((var->activate & FB_ACTIVATE_VBL) &&
379 !intelfbhw_enable_irq(dinfo))
380 dinfo->vsync.pan_display = 1;
381 else {
382 dinfo->vsync.pan_display = 0;
383 OUTREG(DSPABASE, offset);
384 }
385
386 return 0;
387 }
388
389 /* Blank the screen. */
390 void intelfbhw_do_blank(int blank, struct fb_info *info)
391 {
392 struct intelfb_info *dinfo = GET_DINFO(info);
393 u32 tmp;
394
395 #if VERBOSE > 0
396 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
397 #endif
398
399 /* Turn plane A on or off */
400 tmp = INREG(DSPACNTR);
401 if (blank)
402 tmp &= ~DISPPLANE_PLANE_ENABLE;
403 else
404 tmp |= DISPPLANE_PLANE_ENABLE;
405 OUTREG(DSPACNTR, tmp);
406 /* Flush */
407 tmp = INREG(DSPABASE);
408 OUTREG(DSPABASE, tmp);
409
410 /* Turn off/on the HW cursor */
411 #if VERBOSE > 0
412 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
413 #endif
414 if (dinfo->cursor_on) {
415 if (blank)
416 intelfbhw_cursor_hide(dinfo);
417 else
418 intelfbhw_cursor_show(dinfo);
419 dinfo->cursor_on = 1;
420 }
421 dinfo->cursor_blanked = blank;
422
423 /* Set DPMS level */
424 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
425 switch (blank) {
426 case FB_BLANK_UNBLANK:
427 case FB_BLANK_NORMAL:
428 tmp |= ADPA_DPMS_D0;
429 break;
430 case FB_BLANK_VSYNC_SUSPEND:
431 tmp |= ADPA_DPMS_D1;
432 break;
433 case FB_BLANK_HSYNC_SUSPEND:
434 tmp |= ADPA_DPMS_D2;
435 break;
436 case FB_BLANK_POWERDOWN:
437 tmp |= ADPA_DPMS_D3;
438 break;
439 }
440 OUTREG(ADPA, tmp);
441
442 return;
443 }
444
445
446 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
447 unsigned red, unsigned green, unsigned blue,
448 unsigned transp)
449 {
450 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
451 PALETTE_A : PALETTE_B;
452
453 #if VERBOSE > 0
454 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
455 regno, red, green, blue);
456 #endif
457
458 OUTREG(palette_reg + (regno << 2),
459 (red << PALETTE_8_RED_SHIFT) |
460 (green << PALETTE_8_GREEN_SHIFT) |
461 (blue << PALETTE_8_BLUE_SHIFT));
462 }
463
464
465 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
466 struct intelfb_hwstate *hw, int flag)
467 {
468 int i;
469
470 #if VERBOSE > 0
471 DBG_MSG("intelfbhw_read_hw_state\n");
472 #endif
473
474 if (!hw || !dinfo)
475 return -1;
476
477 /* Read in as much of the HW state as possible. */
478 hw->vga0_divisor = INREG(VGA0_DIVISOR);
479 hw->vga1_divisor = INREG(VGA1_DIVISOR);
480 hw->vga_pd = INREG(VGAPD);
481 hw->dpll_a = INREG(DPLL_A);
482 hw->dpll_b = INREG(DPLL_B);
483 hw->fpa0 = INREG(FPA0);
484 hw->fpa1 = INREG(FPA1);
485 hw->fpb0 = INREG(FPB0);
486 hw->fpb1 = INREG(FPB1);
487
488 if (flag == 1)
489 return flag;
490
491 #if 0
492 /* This seems to be a problem with the 852GM/855GM */
493 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
494 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
495 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
496 }
497 #endif
498
499 if (flag == 2)
500 return flag;
501
502 hw->htotal_a = INREG(HTOTAL_A);
503 hw->hblank_a = INREG(HBLANK_A);
504 hw->hsync_a = INREG(HSYNC_A);
505 hw->vtotal_a = INREG(VTOTAL_A);
506 hw->vblank_a = INREG(VBLANK_A);
507 hw->vsync_a = INREG(VSYNC_A);
508 hw->src_size_a = INREG(SRC_SIZE_A);
509 hw->bclrpat_a = INREG(BCLRPAT_A);
510 hw->htotal_b = INREG(HTOTAL_B);
511 hw->hblank_b = INREG(HBLANK_B);
512 hw->hsync_b = INREG(HSYNC_B);
513 hw->vtotal_b = INREG(VTOTAL_B);
514 hw->vblank_b = INREG(VBLANK_B);
515 hw->vsync_b = INREG(VSYNC_B);
516 hw->src_size_b = INREG(SRC_SIZE_B);
517 hw->bclrpat_b = INREG(BCLRPAT_B);
518
519 if (flag == 3)
520 return flag;
521
522 hw->adpa = INREG(ADPA);
523 hw->dvoa = INREG(DVOA);
524 hw->dvob = INREG(DVOB);
525 hw->dvoc = INREG(DVOC);
526 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
527 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
528 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
529 hw->lvds = INREG(LVDS);
530
531 if (flag == 4)
532 return flag;
533
534 hw->pipe_a_conf = INREG(PIPEACONF);
535 hw->pipe_b_conf = INREG(PIPEBCONF);
536 hw->disp_arb = INREG(DISPARB);
537
538 if (flag == 5)
539 return flag;
540
541 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
542 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
543 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
544 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
545
546 if (flag == 6)
547 return flag;
548
549 for (i = 0; i < 4; i++) {
550 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
551 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
552 }
553
554 if (flag == 7)
555 return flag;
556
557 hw->cursor_size = INREG(CURSOR_SIZE);
558
559 if (flag == 8)
560 return flag;
561
562 hw->disp_a_ctrl = INREG(DSPACNTR);
563 hw->disp_b_ctrl = INREG(DSPBCNTR);
564 hw->disp_a_base = INREG(DSPABASE);
565 hw->disp_b_base = INREG(DSPBBASE);
566 hw->disp_a_stride = INREG(DSPASTRIDE);
567 hw->disp_b_stride = INREG(DSPBSTRIDE);
568
569 if (flag == 9)
570 return flag;
571
572 hw->vgacntrl = INREG(VGACNTRL);
573
574 if (flag == 10)
575 return flag;
576
577 hw->add_id = INREG(ADD_ID);
578
579 if (flag == 11)
580 return flag;
581
582 for (i = 0; i < 7; i++) {
583 hw->swf0x[i] = INREG(SWF00 + (i << 2));
584 hw->swf1x[i] = INREG(SWF10 + (i << 2));
585 if (i < 3)
586 hw->swf3x[i] = INREG(SWF30 + (i << 2));
587 }
588
589 for (i = 0; i < 8; i++)
590 hw->fence[i] = INREG(FENCE + (i << 2));
591
592 hw->instpm = INREG(INSTPM);
593 hw->mem_mode = INREG(MEM_MODE);
594 hw->fw_blc_0 = INREG(FW_BLC_0);
595 hw->fw_blc_1 = INREG(FW_BLC_1);
596
597 hw->hwstam = INREG16(HWSTAM);
598 hw->ier = INREG16(IER);
599 hw->iir = INREG16(IIR);
600 hw->imr = INREG16(IMR);
601
602 return 0;
603 }
604
605
606 static int calc_vclock3(int index, int m, int n, int p)
607 {
608 if (p == 0 || n == 0)
609 return 0;
610 return plls[index].ref_clk * m / n / p;
611 }
612
613 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
614 int lvds)
615 {
616 struct pll_min_max *pll = &plls[index];
617 u32 m, vco, p;
618
619 m = (5 * (m1 + 2)) + (m2 + 2);
620 n += 2;
621 vco = pll->ref_clk * m / n;
622
623 if (index == PLLS_I8xx)
624 p = ((p1 + 2) * (1 << (p2 + 1)));
625 else
626 p = ((p1) * (p2 ? 5 : 10));
627 return vco / p;
628 }
629
630 #if REGDUMP
631 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
632 int *o_p1, int *o_p2)
633 {
634 int p1, p2;
635
636 if (IS_I9XX(dinfo)) {
637 if (dpll & DPLL_P1_FORCE_DIV2)
638 p1 = 1;
639 else
640 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
641
642 p1 = ffs(p1);
643
644 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
645 } else {
646 if (dpll & DPLL_P1_FORCE_DIV2)
647 p1 = 0;
648 else
649 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
650 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
651 }
652
653 *o_p1 = p1;
654 *o_p2 = p2;
655 }
656 #endif
657
658
659 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
660 struct intelfb_hwstate *hw)
661 {
662 #if REGDUMP
663 int i, m1, m2, n, p1, p2;
664 int index = dinfo->pll_index;
665 DBG_MSG("intelfbhw_print_hw_state\n");
666
667 if (!hw)
668 return;
669 /* Read in as much of the HW state as possible. */
670 printk("hw state dump start\n");
671 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
672 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
673 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
674 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
675 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
676 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
677
678 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
679
680 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
681 m1, m2, n, p1, p2);
682 printk(" VGA0: clock is %d\n",
683 calc_vclock(index, m1, m2, n, p1, p2, 0));
684
685 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
686 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
687 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
688
689 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
690 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
691 m1, m2, n, p1, p2);
692 printk(" VGA1: clock is %d\n",
693 calc_vclock(index, m1, m2, n, p1, p2, 0));
694
695 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
696 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
697 printk(" FPA0: 0x%08x\n", hw->fpa0);
698 printk(" FPA1: 0x%08x\n", hw->fpa1);
699 printk(" FPB0: 0x%08x\n", hw->fpb0);
700 printk(" FPB1: 0x%08x\n", hw->fpb1);
701
702 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
703 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
704 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
705
706 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
707
708 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
709 m1, m2, n, p1, p2);
710 printk(" PLLA0: clock is %d\n",
711 calc_vclock(index, m1, m2, n, p1, p2, 0));
712
713 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
714 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
715 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
716
717 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
718
719 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
720 m1, m2, n, p1, p2);
721 printk(" PLLA1: clock is %d\n",
722 calc_vclock(index, m1, m2, n, p1, p2, 0));
723
724 #if 0
725 printk(" PALETTE_A:\n");
726 for (i = 0; i < PALETTE_8_ENTRIES)
727 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
728 printk(" PALETTE_B:\n");
729 for (i = 0; i < PALETTE_8_ENTRIES)
730 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
731 #endif
732
733 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
734 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
735 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
736 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
737 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
738 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
739 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
740 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
741 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
742 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
743 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
744 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
745 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
746 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
747 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
748 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
749
750 printk(" ADPA: 0x%08x\n", hw->adpa);
751 printk(" DVOA: 0x%08x\n", hw->dvoa);
752 printk(" DVOB: 0x%08x\n", hw->dvob);
753 printk(" DVOC: 0x%08x\n", hw->dvoc);
754 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
755 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
756 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
757 printk(" LVDS: 0x%08x\n", hw->lvds);
758
759 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
760 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
761 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
762
763 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
764 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
765 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
766 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
767
768 printk(" CURSOR_A_PALETTE: ");
769 for (i = 0; i < 4; i++) {
770 printk("0x%08x", hw->cursor_a_palette[i]);
771 if (i < 3)
772 printk(", ");
773 }
774 printk("\n");
775 printk(" CURSOR_B_PALETTE: ");
776 for (i = 0; i < 4; i++) {
777 printk("0x%08x", hw->cursor_b_palette[i]);
778 if (i < 3)
779 printk(", ");
780 }
781 printk("\n");
782
783 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
784
785 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
786 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
787 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
788 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
789 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
790 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
791
792 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
793 printk(" ADD_ID: 0x%08x\n", hw->add_id);
794
795 for (i = 0; i < 7; i++) {
796 printk(" SWF0%d 0x%08x\n", i,
797 hw->swf0x[i]);
798 }
799 for (i = 0; i < 7; i++) {
800 printk(" SWF1%d 0x%08x\n", i,
801 hw->swf1x[i]);
802 }
803 for (i = 0; i < 3; i++) {
804 printk(" SWF3%d 0x%08x\n", i,
805 hw->swf3x[i]);
806 }
807 for (i = 0; i < 8; i++)
808 printk(" FENCE%d 0x%08x\n", i,
809 hw->fence[i]);
810
811 printk(" INSTPM 0x%08x\n", hw->instpm);
812 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
813 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
814 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
815
816 printk(" HWSTAM 0x%04x\n", hw->hwstam);
817 printk(" IER 0x%04x\n", hw->ier);
818 printk(" IIR 0x%04x\n", hw->iir);
819 printk(" IMR 0x%04x\n", hw->imr);
820 printk("hw state dump end\n");
821 #endif
822 }
823
824
825
826 /* Split the M parameter into M1 and M2. */
827 static int splitm(int index, unsigned int m, unsigned int *retm1,
828 unsigned int *retm2)
829 {
830 int m1, m2;
831 int testm;
832 struct pll_min_max *pll = &plls[index];
833
834 /* no point optimising too much - brute force m */
835 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
836 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
837 testm = (5 * (m1 + 2)) + (m2 + 2);
838 if (testm == m) {
839 *retm1 = (unsigned int)m1;
840 *retm2 = (unsigned int)m2;
841 return 0;
842 }
843 }
844 }
845 return 1;
846 }
847
848 /* Split the P parameter into P1 and P2. */
849 static int splitp(int index, unsigned int p, unsigned int *retp1,
850 unsigned int *retp2)
851 {
852 int p1, p2;
853 struct pll_min_max *pll = &plls[index];
854
855 if (index == PLLS_I9xx) {
856 p2 = (p % 10) ? 1 : 0;
857
858 p1 = p / (p2 ? 5 : 10);
859
860 *retp1 = (unsigned int)p1;
861 *retp2 = (unsigned int)p2;
862 return 0;
863 }
864
865 if (p % 4 == 0)
866 p2 = 1;
867 else
868 p2 = 0;
869 p1 = (p / (1 << (p2 + 1))) - 2;
870 if (p % 4 == 0 && p1 < pll->min_p1) {
871 p2 = 0;
872 p1 = (p / (1 << (p2 + 1))) - 2;
873 }
874 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
875 (p1 + 2) * (1 << (p2 + 1)) != p) {
876 return 1;
877 } else {
878 *retp1 = (unsigned int)p1;
879 *retp2 = (unsigned int)p2;
880 return 0;
881 }
882 }
883
884 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
885 u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
886 {
887 u32 m1, m2, n, p1, p2, n1, testm;
888 u32 f_vco, p, p_best = 0, m, f_out = 0;
889 u32 err_max, err_target, err_best = 10000000;
890 u32 n_best = 0, m_best = 0, f_best, f_err;
891 u32 p_min, p_max, p_inc, div_max;
892 struct pll_min_max *pll = &plls[index];
893
894 /* Accept 0.5% difference, but aim for 0.1% */
895 err_max = 5 * clock / 1000;
896 err_target = clock / 1000;
897
898 DBG_MSG("Clock is %d\n", clock);
899
900 div_max = pll->max_vco / clock;
901
902 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
903 p_min = p_inc;
904 p_max = ROUND_DOWN_TO(div_max, p_inc);
905 if (p_min < pll->min_p)
906 p_min = pll->min_p;
907 if (p_max > pll->max_p)
908 p_max = pll->max_p;
909
910 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
911
912 p = p_min;
913 do {
914 if (splitp(index, p, &p1, &p2)) {
915 WRN_MSG("cannot split p = %d\n", p);
916 p += p_inc;
917 continue;
918 }
919 n = pll->min_n;
920 f_vco = clock * p;
921
922 do {
923 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
924 if (m < pll->min_m)
925 m = pll->min_m + 1;
926 if (m > pll->max_m)
927 m = pll->max_m - 1;
928 for (testm = m - 1; testm <= m; testm++) {
929 f_out = calc_vclock3(index, testm, n, p);
930 if (splitm(index, testm, &m1, &m2)) {
931 WRN_MSG("cannot split m = %d\n",
932 testm);
933 continue;
934 }
935 if (clock > f_out)
936 f_err = clock - f_out;
937 else/* slightly bias the error for bigger clocks */
938 f_err = f_out - clock + 1;
939
940 if (f_err < err_best) {
941 m_best = testm;
942 n_best = n;
943 p_best = p;
944 f_best = f_out;
945 err_best = f_err;
946 }
947 }
948 n++;
949 } while ((n <= pll->max_n) && (f_out >= clock));
950 p += p_inc;
951 } while ((p <= p_max));
952
953 if (!m_best) {
954 WRN_MSG("cannot find parameters for clock %d\n", clock);
955 return 1;
956 }
957 m = m_best;
958 n = n_best;
959 p = p_best;
960 splitm(index, m, &m1, &m2);
961 splitp(index, p, &p1, &p2);
962 n1 = n - 2;
963
964 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
965 "f: %d (%d), VCO: %d\n",
966 m, m1, m2, n, n1, p, p1, p2,
967 calc_vclock3(index, m, n, p),
968 calc_vclock(index, m1, m2, n1, p1, p2, 0),
969 calc_vclock3(index, m, n, p) * p);
970 *retm1 = m1;
971 *retm2 = m2;
972 *retn = n1;
973 *retp1 = p1;
974 *retp2 = p2;
975 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
976
977 return 0;
978 }
979
980 static __inline__ int check_overflow(u32 value, u32 limit,
981 const char *description)
982 {
983 if (value > limit) {
984 WRN_MSG("%s value %d exceeds limit %d\n",
985 description, value, limit);
986 return 1;
987 }
988 return 0;
989 }
990
991 /* It is assumed that hw is filled in with the initial state information. */
992 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
993 struct intelfb_hwstate *hw,
994 struct fb_var_screeninfo *var)
995 {
996 int pipe = PIPE_A;
997 u32 *dpll, *fp0, *fp1;
998 u32 m1, m2, n, p1, p2, clock_target, clock;
999 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1000 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1001 u32 vsync_pol, hsync_pol;
1002 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1003 u32 stride_alignment;
1004
1005 DBG_MSG("intelfbhw_mode_to_hw\n");
1006
1007 /* Disable VGA */
1008 hw->vgacntrl |= VGA_DISABLE;
1009
1010 /* Check whether pipe A or pipe B is enabled. */
1011 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1012 pipe = PIPE_A;
1013 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1014 pipe = PIPE_B;
1015
1016 /* Set which pipe's registers will be set. */
1017 if (pipe == PIPE_B) {
1018 dpll = &hw->dpll_b;
1019 fp0 = &hw->fpb0;
1020 fp1 = &hw->fpb1;
1021 hs = &hw->hsync_b;
1022 hb = &hw->hblank_b;
1023 ht = &hw->htotal_b;
1024 vs = &hw->vsync_b;
1025 vb = &hw->vblank_b;
1026 vt = &hw->vtotal_b;
1027 ss = &hw->src_size_b;
1028 pipe_conf = &hw->pipe_b_conf;
1029 } else {
1030 dpll = &hw->dpll_a;
1031 fp0 = &hw->fpa0;
1032 fp1 = &hw->fpa1;
1033 hs = &hw->hsync_a;
1034 hb = &hw->hblank_a;
1035 ht = &hw->htotal_a;
1036 vs = &hw->vsync_a;
1037 vb = &hw->vblank_a;
1038 vt = &hw->vtotal_a;
1039 ss = &hw->src_size_a;
1040 pipe_conf = &hw->pipe_a_conf;
1041 }
1042
1043 /* Use ADPA register for sync control. */
1044 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1045
1046 /* sync polarity */
1047 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1048 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1049 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1050 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1051 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1052 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1053 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1054 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1055
1056 /* Connect correct pipe to the analog port DAC */
1057 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1058 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1059
1060 /* Set DPMS state to D0 (on) */
1061 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1062 hw->adpa |= ADPA_DPMS_D0;
1063
1064 hw->adpa |= ADPA_DAC_ENABLE;
1065
1066 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1067 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1068 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1069
1070 /* Desired clock in kHz */
1071 clock_target = 1000000000 / var->pixclock;
1072
1073 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1074 &n, &p1, &p2, &clock)) {
1075 WRN_MSG("calc_pll_params failed\n");
1076 return 1;
1077 }
1078
1079 /* Check for overflow. */
1080 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1081 return 1;
1082 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1083 return 1;
1084 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1085 return 1;
1086 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1087 return 1;
1088 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1089 return 1;
1090
1091 *dpll &= ~DPLL_P1_FORCE_DIV2;
1092 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1093 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1094
1095 if (IS_I9XX(dinfo)) {
1096 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1097 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1098 } else
1099 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1100
1101 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1102 (m1 << FP_M1_DIVISOR_SHIFT) |
1103 (m2 << FP_M2_DIVISOR_SHIFT);
1104 *fp1 = *fp0;
1105
1106 hw->dvob &= ~PORT_ENABLE;
1107 hw->dvoc &= ~PORT_ENABLE;
1108
1109 /* Use display plane A. */
1110 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1111 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1112 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1113 switch (intelfb_var_to_depth(var)) {
1114 case 8:
1115 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1116 break;
1117 case 15:
1118 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1119 break;
1120 case 16:
1121 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1122 break;
1123 case 24:
1124 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1125 break;
1126 }
1127 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1128 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1129
1130 /* Set CRTC registers. */
1131 hactive = var->xres;
1132 hsync_start = hactive + var->right_margin;
1133 hsync_end = hsync_start + var->hsync_len;
1134 htotal = hsync_end + var->left_margin;
1135 hblank_start = hactive;
1136 hblank_end = htotal;
1137
1138 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1139 hactive, hsync_start, hsync_end, htotal, hblank_start,
1140 hblank_end);
1141
1142 vactive = var->yres;
1143 if (var->vmode & FB_VMODE_INTERLACED)
1144 vactive--; /* the chip adds 2 halflines automatically */
1145 vsync_start = vactive + var->lower_margin;
1146 vsync_end = vsync_start + var->vsync_len;
1147 vtotal = vsync_end + var->upper_margin;
1148 vblank_start = vactive;
1149 vblank_end = vtotal;
1150 vblank_end = vsync_end + 1;
1151
1152 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1153 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1154 vblank_end);
1155
1156 /* Adjust for register values, and check for overflow. */
1157 hactive--;
1158 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1159 return 1;
1160 hsync_start--;
1161 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1162 return 1;
1163 hsync_end--;
1164 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1165 return 1;
1166 htotal--;
1167 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1168 return 1;
1169 hblank_start--;
1170 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1171 return 1;
1172 hblank_end--;
1173 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1174 return 1;
1175
1176 vactive--;
1177 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1178 return 1;
1179 vsync_start--;
1180 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1181 return 1;
1182 vsync_end--;
1183 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1184 return 1;
1185 vtotal--;
1186 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1187 return 1;
1188 vblank_start--;
1189 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1190 return 1;
1191 vblank_end--;
1192 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1193 return 1;
1194
1195 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1196 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1197 (hblank_end << HSYNCEND_SHIFT);
1198 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1199
1200 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1201 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1202 (vblank_end << VSYNCEND_SHIFT);
1203 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1204 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1205 (vactive << SRC_SIZE_VERT_SHIFT);
1206
1207 hw->disp_a_stride = dinfo->pitch;
1208 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1209
1210 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1211 var->xoffset * var->bits_per_pixel / 8;
1212
1213 hw->disp_a_base += dinfo->fb.offset << 12;
1214
1215 /* Check stride alignment. */
1216 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1217 STRIDE_ALIGNMENT;
1218 if (hw->disp_a_stride % stride_alignment != 0) {
1219 WRN_MSG("display stride %d has bad alignment %d\n",
1220 hw->disp_a_stride, stride_alignment);
1221 return 1;
1222 }
1223
1224 /* Set the palette to 8-bit mode. */
1225 *pipe_conf &= ~PIPECONF_GAMMA;
1226
1227 if (var->vmode & FB_VMODE_INTERLACED)
1228 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1229 else
1230 *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1231
1232 return 0;
1233 }
1234
1235 /* Program a (non-VGA) video mode. */
1236 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1237 const struct intelfb_hwstate *hw, int blank)
1238 {
1239 int pipe = PIPE_A;
1240 u32 tmp;
1241 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1242 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1243 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
1244 u32 hsync_reg, htotal_reg, hblank_reg;
1245 u32 vsync_reg, vtotal_reg, vblank_reg;
1246 u32 src_size_reg;
1247 u32 count, tmp_val[3];
1248
1249 /* Assume single pipe, display plane A, analog CRT. */
1250
1251 #if VERBOSE > 0
1252 DBG_MSG("intelfbhw_program_mode\n");
1253 #endif
1254
1255 /* Disable VGA */
1256 tmp = INREG(VGACNTRL);
1257 tmp |= VGA_DISABLE;
1258 OUTREG(VGACNTRL, tmp);
1259
1260 /* Check whether pipe A or pipe B is enabled. */
1261 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1262 pipe = PIPE_A;
1263 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1264 pipe = PIPE_B;
1265
1266 dinfo->pipe = pipe;
1267
1268 if (pipe == PIPE_B) {
1269 dpll = &hw->dpll_b;
1270 fp0 = &hw->fpb0;
1271 fp1 = &hw->fpb1;
1272 pipe_conf = &hw->pipe_b_conf;
1273 hs = &hw->hsync_b;
1274 hb = &hw->hblank_b;
1275 ht = &hw->htotal_b;
1276 vs = &hw->vsync_b;
1277 vb = &hw->vblank_b;
1278 vt = &hw->vtotal_b;
1279 ss = &hw->src_size_b;
1280 dpll_reg = DPLL_B;
1281 fp0_reg = FPB0;
1282 fp1_reg = FPB1;
1283 pipe_conf_reg = PIPEBCONF;
1284 pipe_stat_reg = PIPEBSTAT;
1285 hsync_reg = HSYNC_B;
1286 htotal_reg = HTOTAL_B;
1287 hblank_reg = HBLANK_B;
1288 vsync_reg = VSYNC_B;
1289 vtotal_reg = VTOTAL_B;
1290 vblank_reg = VBLANK_B;
1291 src_size_reg = SRC_SIZE_B;
1292 } else {
1293 dpll = &hw->dpll_a;
1294 fp0 = &hw->fpa0;
1295 fp1 = &hw->fpa1;
1296 pipe_conf = &hw->pipe_a_conf;
1297 hs = &hw->hsync_a;
1298 hb = &hw->hblank_a;
1299 ht = &hw->htotal_a;
1300 vs = &hw->vsync_a;
1301 vb = &hw->vblank_a;
1302 vt = &hw->vtotal_a;
1303 ss = &hw->src_size_a;
1304 dpll_reg = DPLL_A;
1305 fp0_reg = FPA0;
1306 fp1_reg = FPA1;
1307 pipe_conf_reg = PIPEACONF;
1308 pipe_stat_reg = PIPEASTAT;
1309 hsync_reg = HSYNC_A;
1310 htotal_reg = HTOTAL_A;
1311 hblank_reg = HBLANK_A;
1312 vsync_reg = VSYNC_A;
1313 vtotal_reg = VTOTAL_A;
1314 vblank_reg = VBLANK_A;
1315 src_size_reg = SRC_SIZE_A;
1316 }
1317
1318 /* turn off pipe */
1319 tmp = INREG(pipe_conf_reg);
1320 tmp &= ~PIPECONF_ENABLE;
1321 OUTREG(pipe_conf_reg, tmp);
1322
1323 count = 0;
1324 do {
1325 tmp_val[count % 3] = INREG(PIPEA_DSL);
1326 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1327 break;
1328 count++;
1329 udelay(1);
1330 if (count % 200 == 0) {
1331 tmp = INREG(pipe_conf_reg);
1332 tmp &= ~PIPECONF_ENABLE;
1333 OUTREG(pipe_conf_reg, tmp);
1334 }
1335 } while (count < 2000);
1336
1337 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1338
1339 /* Disable planes A and B. */
1340 tmp = INREG(DSPACNTR);
1341 tmp &= ~DISPPLANE_PLANE_ENABLE;
1342 OUTREG(DSPACNTR, tmp);
1343 tmp = INREG(DSPBCNTR);
1344 tmp &= ~DISPPLANE_PLANE_ENABLE;
1345 OUTREG(DSPBCNTR, tmp);
1346
1347 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1348 mdelay(20);
1349
1350 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1351 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1352 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1353
1354 /* Disable Sync */
1355 tmp = INREG(ADPA);
1356 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1357 tmp |= ADPA_DPMS_D3;
1358 OUTREG(ADPA, tmp);
1359
1360 /* do some funky magic - xyzzy */
1361 OUTREG(0x61204, 0xabcd0000);
1362
1363 /* turn off PLL */
1364 tmp = INREG(dpll_reg);
1365 tmp &= ~DPLL_VCO_ENABLE;
1366 OUTREG(dpll_reg, tmp);
1367
1368 /* Set PLL parameters */
1369 OUTREG(fp0_reg, *fp0);
1370 OUTREG(fp1_reg, *fp1);
1371
1372 /* Enable PLL */
1373 OUTREG(dpll_reg, *dpll);
1374
1375 /* Set DVOs B/C */
1376 OUTREG(DVOB, hw->dvob);
1377 OUTREG(DVOC, hw->dvoc);
1378
1379 /* undo funky magic */
1380 OUTREG(0x61204, 0x00000000);
1381
1382 /* Set ADPA */
1383 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1384 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1385
1386 /* Set pipe parameters */
1387 OUTREG(hsync_reg, *hs);
1388 OUTREG(hblank_reg, *hb);
1389 OUTREG(htotal_reg, *ht);
1390 OUTREG(vsync_reg, *vs);
1391 OUTREG(vblank_reg, *vb);
1392 OUTREG(vtotal_reg, *vt);
1393 OUTREG(src_size_reg, *ss);
1394
1395 switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1396 FB_VMODE_ODD_FLD_FIRST)) {
1397 case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
1398 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
1399 break;
1400 case FB_VMODE_INTERLACED: /* even lines first */
1401 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
1402 break;
1403 default: /* non-interlaced */
1404 OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
1405 }
1406 /* Enable pipe */
1407 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1408
1409 /* Enable sync */
1410 tmp = INREG(ADPA);
1411 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1412 tmp |= ADPA_DPMS_D0;
1413 OUTREG(ADPA, tmp);
1414
1415 /* setup display plane */
1416 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1417 /*
1418 * i830M errata: the display plane must be enabled
1419 * to allow writes to the other bits in the plane
1420 * control register.
1421 */
1422 tmp = INREG(DSPACNTR);
1423 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1424 tmp |= DISPPLANE_PLANE_ENABLE;
1425 OUTREG(DSPACNTR, tmp);
1426 OUTREG(DSPACNTR,
1427 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1428 mdelay(1);
1429 }
1430 }
1431
1432 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1433 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1434 OUTREG(DSPABASE, hw->disp_a_base);
1435
1436 /* Enable plane */
1437 if (!blank) {
1438 tmp = INREG(DSPACNTR);
1439 tmp |= DISPPLANE_PLANE_ENABLE;
1440 OUTREG(DSPACNTR, tmp);
1441 OUTREG(DSPABASE, hw->disp_a_base);
1442 }
1443
1444 return 0;
1445 }
1446
1447 /* forward declarations */
1448 static void refresh_ring(struct intelfb_info *dinfo);
1449 static void reset_state(struct intelfb_info *dinfo);
1450 static void do_flush(struct intelfb_info *dinfo);
1451
1452 static u32 get_ring_space(struct intelfb_info *dinfo)
1453 {
1454 u32 ring_space;
1455
1456 if (dinfo->ring_tail >= dinfo->ring_head)
1457 ring_space = dinfo->ring.size -
1458 (dinfo->ring_tail - dinfo->ring_head);
1459 else
1460 ring_space = dinfo->ring_head - dinfo->ring_tail;
1461
1462 if (ring_space > RING_MIN_FREE)
1463 ring_space -= RING_MIN_FREE;
1464 else
1465 ring_space = 0;
1466
1467 return ring_space;
1468 }
1469
1470 static int wait_ring(struct intelfb_info *dinfo, int n)
1471 {
1472 int i = 0;
1473 unsigned long end;
1474 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1475
1476 #if VERBOSE > 0
1477 DBG_MSG("wait_ring: %d\n", n);
1478 #endif
1479
1480 end = jiffies + (HZ * 3);
1481 while (dinfo->ring_space < n) {
1482 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1483 dinfo->ring_space = get_ring_space(dinfo);
1484
1485 if (dinfo->ring_head != last_head) {
1486 end = jiffies + (HZ * 3);
1487 last_head = dinfo->ring_head;
1488 }
1489 i++;
1490 if (time_before(end, jiffies)) {
1491 if (!i) {
1492 /* Try again */
1493 reset_state(dinfo);
1494 refresh_ring(dinfo);
1495 do_flush(dinfo);
1496 end = jiffies + (HZ * 3);
1497 i = 1;
1498 } else {
1499 WRN_MSG("ring buffer : space: %d wanted %d\n",
1500 dinfo->ring_space, n);
1501 WRN_MSG("lockup - turning off hardware "
1502 "acceleration\n");
1503 dinfo->ring_lockup = 1;
1504 break;
1505 }
1506 }
1507 udelay(1);
1508 }
1509 return i;
1510 }
1511
1512 static void do_flush(struct intelfb_info *dinfo)
1513 {
1514 START_RING(2);
1515 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1516 OUT_RING(MI_NOOP);
1517 ADVANCE_RING();
1518 }
1519
1520 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1521 {
1522 #if VERBOSE > 0
1523 DBG_MSG("intelfbhw_do_sync\n");
1524 #endif
1525
1526 if (!dinfo->accel)
1527 return;
1528
1529 /*
1530 * Send a flush, then wait until the ring is empty. This is what
1531 * the XFree86 driver does, and actually it doesn't seem a lot worse
1532 * than the recommended method (both have problems).
1533 */
1534 do_flush(dinfo);
1535 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1536 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1537 }
1538
1539 static void refresh_ring(struct intelfb_info *dinfo)
1540 {
1541 #if VERBOSE > 0
1542 DBG_MSG("refresh_ring\n");
1543 #endif
1544
1545 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1546 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1547 dinfo->ring_space = get_ring_space(dinfo);
1548 }
1549
1550 static void reset_state(struct intelfb_info *dinfo)
1551 {
1552 int i;
1553 u32 tmp;
1554
1555 #if VERBOSE > 0
1556 DBG_MSG("reset_state\n");
1557 #endif
1558
1559 for (i = 0; i < FENCE_NUM; i++)
1560 OUTREG(FENCE + (i << 2), 0);
1561
1562 /* Flush the ring buffer if it's enabled. */
1563 tmp = INREG(PRI_RING_LENGTH);
1564 if (tmp & RING_ENABLE) {
1565 #if VERBOSE > 0
1566 DBG_MSG("reset_state: ring was enabled\n");
1567 #endif
1568 refresh_ring(dinfo);
1569 intelfbhw_do_sync(dinfo);
1570 DO_RING_IDLE();
1571 }
1572
1573 OUTREG(PRI_RING_LENGTH, 0);
1574 OUTREG(PRI_RING_HEAD, 0);
1575 OUTREG(PRI_RING_TAIL, 0);
1576 OUTREG(PRI_RING_START, 0);
1577 }
1578
1579 /* Stop the 2D engine, and turn off the ring buffer. */
1580 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1581 {
1582 #if VERBOSE > 0
1583 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1584 dinfo->accel, dinfo->ring_active);
1585 #endif
1586
1587 if (!dinfo->accel)
1588 return;
1589
1590 dinfo->ring_active = 0;
1591 reset_state(dinfo);
1592 }
1593
1594 /*
1595 * Enable the ring buffer, and initialise the 2D engine.
1596 * It is assumed that the graphics engine has been stopped by previously
1597 * calling intelfb_2d_stop().
1598 */
1599 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1600 {
1601 #if VERBOSE > 0
1602 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1603 dinfo->accel, dinfo->ring_active);
1604 #endif
1605
1606 if (!dinfo->accel)
1607 return;
1608
1609 /* Initialise the primary ring buffer. */
1610 OUTREG(PRI_RING_LENGTH, 0);
1611 OUTREG(PRI_RING_TAIL, 0);
1612 OUTREG(PRI_RING_HEAD, 0);
1613
1614 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1615 OUTREG(PRI_RING_LENGTH,
1616 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1617 RING_NO_REPORT | RING_ENABLE);
1618 refresh_ring(dinfo);
1619 dinfo->ring_active = 1;
1620 }
1621
1622 /* 2D fillrect (solid fill or invert) */
1623 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1624 u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
1625 {
1626 u32 br00, br09, br13, br14, br16;
1627
1628 #if VERBOSE > 0
1629 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1630 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1631 #endif
1632
1633 br00 = COLOR_BLT_CMD;
1634 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1635 br13 = (rop << ROP_SHIFT) | pitch;
1636 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1637 br16 = color;
1638
1639 switch (bpp) {
1640 case 8:
1641 br13 |= COLOR_DEPTH_8;
1642 break;
1643 case 16:
1644 br13 |= COLOR_DEPTH_16;
1645 break;
1646 case 32:
1647 br13 |= COLOR_DEPTH_32;
1648 br00 |= WRITE_ALPHA | WRITE_RGB;
1649 break;
1650 }
1651
1652 START_RING(6);
1653 OUT_RING(br00);
1654 OUT_RING(br13);
1655 OUT_RING(br14);
1656 OUT_RING(br09);
1657 OUT_RING(br16);
1658 OUT_RING(MI_NOOP);
1659 ADVANCE_RING();
1660
1661 #if VERBOSE > 0
1662 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1663 dinfo->ring_tail, dinfo->ring_space);
1664 #endif
1665 }
1666
1667 void
1668 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1669 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1670 {
1671 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1672
1673 #if VERBOSE > 0
1674 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1675 curx, cury, dstx, dsty, w, h, pitch, bpp);
1676 #endif
1677
1678 br00 = XY_SRC_COPY_BLT_CMD;
1679 br09 = dinfo->fb_start;
1680 br11 = (pitch << PITCH_SHIFT);
1681 br12 = dinfo->fb_start;
1682 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1683 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1684 br23 = ((dstx + w) << WIDTH_SHIFT) |
1685 ((dsty + h) << HEIGHT_SHIFT);
1686 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1687
1688 switch (bpp) {
1689 case 8:
1690 br13 |= COLOR_DEPTH_8;
1691 break;
1692 case 16:
1693 br13 |= COLOR_DEPTH_16;
1694 break;
1695 case 32:
1696 br13 |= COLOR_DEPTH_32;
1697 br00 |= WRITE_ALPHA | WRITE_RGB;
1698 break;
1699 }
1700
1701 START_RING(8);
1702 OUT_RING(br00);
1703 OUT_RING(br13);
1704 OUT_RING(br22);
1705 OUT_RING(br23);
1706 OUT_RING(br09);
1707 OUT_RING(br26);
1708 OUT_RING(br11);
1709 OUT_RING(br12);
1710 ADVANCE_RING();
1711 }
1712
1713 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1714 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
1715 u32 bpp)
1716 {
1717 int nbytes, ndwords, pad, tmp;
1718 u32 br00, br09, br13, br18, br19, br22, br23;
1719 int dat, ix, iy, iw;
1720 int i, j;
1721
1722 #if VERBOSE > 0
1723 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1724 #endif
1725
1726 /* size in bytes of a padded scanline */
1727 nbytes = ROUND_UP_TO(w, 16) / 8;
1728
1729 /* Total bytes of padded scanline data to write out. */
1730 nbytes = nbytes * h;
1731
1732 /*
1733 * Check if the glyph data exceeds the immediate mode limit.
1734 * It would take a large font (1K pixels) to hit this limit.
1735 */
1736 if (nbytes > MAX_MONO_IMM_SIZE)
1737 return 0;
1738
1739 /* Src data is packaged a dword (32-bit) at a time. */
1740 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1741
1742 /*
1743 * Ring has to be padded to a quad word. But because the command starts
1744 with 7 bytes, pad only if there is an even number of ndwords
1745 */
1746 pad = !(ndwords % 2);
1747
1748 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1749 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1750 br09 = dinfo->fb_start;
1751 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1752 br18 = bg;
1753 br19 = fg;
1754 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1755 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1756
1757 switch (bpp) {
1758 case 8:
1759 br13 |= COLOR_DEPTH_8;
1760 break;
1761 case 16:
1762 br13 |= COLOR_DEPTH_16;
1763 break;
1764 case 32:
1765 br13 |= COLOR_DEPTH_32;
1766 br00 |= WRITE_ALPHA | WRITE_RGB;
1767 break;
1768 }
1769
1770 START_RING(8 + ndwords);
1771 OUT_RING(br00);
1772 OUT_RING(br13);
1773 OUT_RING(br22);
1774 OUT_RING(br23);
1775 OUT_RING(br09);
1776 OUT_RING(br18);
1777 OUT_RING(br19);
1778 ix = iy = 0;
1779 iw = ROUND_UP_TO(w, 8) / 8;
1780 while (ndwords--) {
1781 dat = 0;
1782 for (j = 0; j < 2; ++j) {
1783 for (i = 0; i < 2; ++i) {
1784 if (ix != iw || i == 0)
1785 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1786 }
1787 if (ix == iw && iy != (h-1)) {
1788 ix = 0;
1789 ++iy;
1790 }
1791 }
1792 OUT_RING(dat);
1793 }
1794 if (pad)
1795 OUT_RING(MI_NOOP);
1796 ADVANCE_RING();
1797
1798 return 1;
1799 }
1800
1801 /* HW cursor functions. */
1802 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1803 {
1804 u32 tmp;
1805
1806 #if VERBOSE > 0
1807 DBG_MSG("intelfbhw_cursor_init\n");
1808 #endif
1809
1810 if (dinfo->mobile || IS_I9XX(dinfo)) {
1811 if (!dinfo->cursor.physical)
1812 return;
1813 tmp = INREG(CURSOR_A_CONTROL);
1814 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1815 CURSOR_MEM_TYPE_LOCAL |
1816 (1 << CURSOR_PIPE_SELECT_SHIFT));
1817 tmp |= CURSOR_MODE_DISABLE;
1818 OUTREG(CURSOR_A_CONTROL, tmp);
1819 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1820 } else {
1821 tmp = INREG(CURSOR_CONTROL);
1822 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1823 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1824 tmp = CURSOR_FORMAT_3C;
1825 OUTREG(CURSOR_CONTROL, tmp);
1826 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1827 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1828 (64 << CURSOR_SIZE_V_SHIFT);
1829 OUTREG(CURSOR_SIZE, tmp);
1830 }
1831 }
1832
1833 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1834 {
1835 u32 tmp;
1836
1837 #if VERBOSE > 0
1838 DBG_MSG("intelfbhw_cursor_hide\n");
1839 #endif
1840
1841 dinfo->cursor_on = 0;
1842 if (dinfo->mobile || IS_I9XX(dinfo)) {
1843 if (!dinfo->cursor.physical)
1844 return;
1845 tmp = INREG(CURSOR_A_CONTROL);
1846 tmp &= ~CURSOR_MODE_MASK;
1847 tmp |= CURSOR_MODE_DISABLE;
1848 OUTREG(CURSOR_A_CONTROL, tmp);
1849 /* Flush changes */
1850 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1851 } else {
1852 tmp = INREG(CURSOR_CONTROL);
1853 tmp &= ~CURSOR_ENABLE;
1854 OUTREG(CURSOR_CONTROL, tmp);
1855 }
1856 }
1857
1858 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1859 {
1860 u32 tmp;
1861
1862 #if VERBOSE > 0
1863 DBG_MSG("intelfbhw_cursor_show\n");
1864 #endif
1865
1866 dinfo->cursor_on = 1;
1867
1868 if (dinfo->cursor_blanked)
1869 return;
1870
1871 if (dinfo->mobile || IS_I9XX(dinfo)) {
1872 if (!dinfo->cursor.physical)
1873 return;
1874 tmp = INREG(CURSOR_A_CONTROL);
1875 tmp &= ~CURSOR_MODE_MASK;
1876 tmp |= CURSOR_MODE_64_4C_AX;
1877 OUTREG(CURSOR_A_CONTROL, tmp);
1878 /* Flush changes */
1879 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1880 } else {
1881 tmp = INREG(CURSOR_CONTROL);
1882 tmp |= CURSOR_ENABLE;
1883 OUTREG(CURSOR_CONTROL, tmp);
1884 }
1885 }
1886
1887 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1888 {
1889 u32 tmp;
1890
1891 #if VERBOSE > 0
1892 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1893 #endif
1894
1895 /*
1896 * Sets the position. The coordinates are assumed to already
1897 * have any offset adjusted. Assume that the cursor is never
1898 * completely off-screen, and that x, y are always >= 0.
1899 */
1900
1901 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1902 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1903 OUTREG(CURSOR_A_POSITION, tmp);
1904
1905 if (IS_I9XX(dinfo))
1906 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1907 }
1908
1909 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1910 {
1911 #if VERBOSE > 0
1912 DBG_MSG("intelfbhw_cursor_setcolor\n");
1913 #endif
1914
1915 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1916 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1917 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1918 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1919 }
1920
1921 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1922 u8 *data)
1923 {
1924 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1925 int i, j, w = width / 8;
1926 int mod = width % 8, t_mask, d_mask;
1927
1928 #if VERBOSE > 0
1929 DBG_MSG("intelfbhw_cursor_load\n");
1930 #endif
1931
1932 if (!dinfo->cursor.virtual)
1933 return;
1934
1935 t_mask = 0xff >> mod;
1936 d_mask = ~(0xff >> mod);
1937 for (i = height; i--; ) {
1938 for (j = 0; j < w; j++) {
1939 writeb(0x00, addr + j);
1940 writeb(*(data++), addr + j+8);
1941 }
1942 if (mod) {
1943 writeb(t_mask, addr + j);
1944 writeb(*(data++) & d_mask, addr + j+8);
1945 }
1946 addr += 16;
1947 }
1948 }
1949
1950 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1951 {
1952 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1953 int i, j;
1954
1955 #if VERBOSE > 0
1956 DBG_MSG("intelfbhw_cursor_reset\n");
1957 #endif
1958
1959 if (!dinfo->cursor.virtual)
1960 return;
1961
1962 for (i = 64; i--; ) {
1963 for (j = 0; j < 8; j++) {
1964 writeb(0xff, addr + j+0);
1965 writeb(0x00, addr + j+8);
1966 }
1967 addr += 16;
1968 }
1969 }
1970
1971 static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
1972 {
1973 u16 tmp;
1974 struct intelfb_info *dinfo = dev_id;
1975
1976 spin_lock(&dinfo->int_lock);
1977
1978 tmp = INREG16(IIR);
1979 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
1980 tmp &= PIPE_A_EVENT_INTERRUPT;
1981 else
1982 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
1983
1984 if (tmp == 0) {
1985 spin_unlock(&dinfo->int_lock);
1986 return IRQ_RETVAL(0); /* not us */
1987 }
1988
1989 /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
1990 OUTREG(PIPEASTAT, INREG(PIPEASTAT));
1991
1992 OUTREG16(IIR, tmp);
1993 if (dinfo->vsync.pan_display) {
1994 dinfo->vsync.pan_display = 0;
1995 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1996 }
1997
1998 dinfo->vsync.count++;
1999 wake_up_interruptible(&dinfo->vsync.wait);
2000
2001 spin_unlock(&dinfo->int_lock);
2002
2003 return IRQ_RETVAL(1);
2004 }
2005
2006 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2007 {
2008 u16 tmp;
2009 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2010 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2011 "intelfb", dinfo)) {
2012 clear_bit(0, &dinfo->irq_flags);
2013 return -EINVAL;
2014 }
2015
2016 spin_lock_irq(&dinfo->int_lock);
2017 OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
2018 OUTREG16(IMR, 0);
2019 } else
2020 spin_lock_irq(&dinfo->int_lock);
2021
2022 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2023 tmp = PIPE_A_EVENT_INTERRUPT;
2024 else
2025 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2026 if (tmp != INREG16(IER)) {
2027 DBG_MSG("changing IER to 0x%X\n", tmp);
2028 OUTREG16(IER, tmp);
2029 }
2030
2031 spin_unlock_irq(&dinfo->int_lock);
2032 return 0;
2033 }
2034
2035 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2036 {
2037 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2038 if (dinfo->vsync.pan_display) {
2039 dinfo->vsync.pan_display = 0;
2040 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2041 }
2042 spin_lock_irq(&dinfo->int_lock);
2043 OUTREG16(HWSTAM, 0xffff);
2044 OUTREG16(IMR, 0xffff);
2045 OUTREG16(IER, 0x0);
2046
2047 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2048 spin_unlock_irq(&dinfo->int_lock);
2049
2050 free_irq(dinfo->pdev->irq, dinfo);
2051 }
2052 }
2053
2054 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2055 {
2056 struct intelfb_vsync *vsync;
2057 unsigned int count;
2058 int ret;
2059
2060 switch (pipe) {
2061 case 0:
2062 vsync = &dinfo->vsync;
2063 break;
2064 default:
2065 return -ENODEV;
2066 }
2067
2068 ret = intelfbhw_enable_irq(dinfo);
2069 if (ret)
2070 return ret;
2071
2072 count = vsync->count;
2073 ret = wait_event_interruptible_timeout(vsync->wait,
2074 count != vsync->count, HZ / 10);
2075 if (ret < 0)
2076 return ret;
2077 if (ret == 0) {
2078 DBG_MSG("wait_for_vsync timed out!\n");
2079 return -ETIMEDOUT;
2080 }
2081
2082 return 0;
2083 }
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