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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / serial / cpm_uart / cpm_uart_cpm2.c
blobd9af06a791ba51b77bbb9af8bb93d35299fc9d7d
1 /*
2 * linux/drivers/serial/cpm_uart_cpm2.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/tty.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/serial.h>
35 #include <linux/console.h>
36 #include <linux/sysrq.h>
37 #include <linux/device.h>
38 #include <linux/bootmem.h>
39 #include <linux/dma-mapping.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/fs_pd.h>
44
45 #include <linux/serial_core.h>
46 #include <linux/kernel.h>
47
48 #include "cpm_uart.h"
49
50 /**************************************************************/
51
52 #ifdef CONFIG_PPC_CPM_NEW_BINDING
53 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
54 {
55 cpm_command(port->command, cmd);
56 }
57 #else
58 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
59 {
60 ulong val;
61 int line = port - cpm_uart_ports;
62 volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
63
64
65 switch (line) {
66 case UART_SMC1:
67 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
68 cmd) | CPM_CR_FLG;
69 break;
70 case UART_SMC2:
71 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
72 cmd) | CPM_CR_FLG;
73 break;
74 case UART_SCC1:
75 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
76 cmd) | CPM_CR_FLG;
77 break;
78 case UART_SCC2:
79 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
80 cmd) | CPM_CR_FLG;
81 break;
82 case UART_SCC3:
83 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
84 cmd) | CPM_CR_FLG;
85 break;
86 case UART_SCC4:
87 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
88 cmd) | CPM_CR_FLG;
89 break;
90 default:
91 return;
92
93 }
94 cp->cp_cpcr = val;
95 while (cp->cp_cpcr & CPM_CR_FLG) ;
96
97 cpm2_unmap(cp);
98 }
99
100 void smc1_lineif(struct uart_cpm_port *pinfo)
101 {
102 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
103 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
104
105 /* SMC1 is only on port D */
106 io->iop_ppard |= 0x00c00000;
107 io->iop_pdird |= 0x00400000;
108 io->iop_pdird &= ~0x00800000;
109 io->iop_psord &= ~0x00c00000;
110
111 /* Wire BRG1 to SMC1 */
112 cpmux->cmx_smr &= 0x0f;
113 pinfo->brg = 1;
114
115 cpm2_unmap(cpmux);
116 cpm2_unmap(io);
117 }
118
119 void smc2_lineif(struct uart_cpm_port *pinfo)
120 {
121 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
122 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
123
124 /* SMC2 is only on port A */
125 io->iop_ppara |= 0x00c00000;
126 io->iop_pdira |= 0x00400000;
127 io->iop_pdira &= ~0x00800000;
128 io->iop_psora &= ~0x00c00000;
129
130 /* Wire BRG2 to SMC2 */
131 cpmux->cmx_smr &= 0xf0;
132 pinfo->brg = 2;
133
134 cpm2_unmap(cpmux);
135 cpm2_unmap(io);
136 }
137
138 void scc1_lineif(struct uart_cpm_port *pinfo)
139 {
140 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
141 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
142
143 /* Use Port D for SCC1 instead of other functions. */
144 io->iop_ppard |= 0x00000003;
145 io->iop_psord &= ~0x00000001; /* Rx */
146 io->iop_psord |= 0x00000002; /* Tx */
147 io->iop_pdird &= ~0x00000001; /* Rx */
148 io->iop_pdird |= 0x00000002; /* Tx */
149
150 /* Wire BRG1 to SCC1 */
151 cpmux->cmx_scr &= 0x00ffffff;
152 cpmux->cmx_scr |= 0x00000000;
153 pinfo->brg = 1;
154
155 cpm2_unmap(cpmux);
156 cpm2_unmap(io);
157 }
158
159 void scc2_lineif(struct uart_cpm_port *pinfo)
160 {
161 /*
162 * STx GP3 uses the SCC2 secondary option pin assignment
163 * which this driver doesn't account for in the static
164 * pin assignments. This kind of board specific info
165 * really has to get out of the driver so boards can
166 * be supported in a sane fashion.
167 */
168 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
169 #ifndef CONFIG_STX_GP3
170 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
171
172 io->iop_pparb |= 0x008b0000;
173 io->iop_pdirb |= 0x00880000;
174 io->iop_psorb |= 0x00880000;
175 io->iop_pdirb &= ~0x00030000;
176 io->iop_psorb &= ~0x00030000;
177 #endif
178 cpmux->cmx_scr &= 0xff00ffff;
179 cpmux->cmx_scr |= 0x00090000;
180 pinfo->brg = 2;
181
182 cpm2_unmap(cpmux);
183 cpm2_unmap(io);
184 }
185
186 void scc3_lineif(struct uart_cpm_port *pinfo)
187 {
188 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
189 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
190
191 io->iop_pparb |= 0x008b0000;
192 io->iop_pdirb |= 0x00880000;
193 io->iop_psorb |= 0x00880000;
194 io->iop_pdirb &= ~0x00030000;
195 io->iop_psorb &= ~0x00030000;
196 cpmux->cmx_scr &= 0xffff00ff;
197 cpmux->cmx_scr |= 0x00001200;
198 pinfo->brg = 3;
199
200 cpm2_unmap(cpmux);
201 cpm2_unmap(io);
202 }
203
204 void scc4_lineif(struct uart_cpm_port *pinfo)
205 {
206 volatile iop_cpm2_t *io = cpm2_map(im_ioport);
207 volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
208
209 io->iop_ppard |= 0x00000600;
210 io->iop_psord &= ~0x00000600; /* Tx/Rx */
211 io->iop_pdird &= ~0x00000200; /* Rx */
212 io->iop_pdird |= 0x00000400; /* Tx */
213
214 cpmux->cmx_scr &= 0xffffff00;
215 cpmux->cmx_scr |= 0x0000001b;
216 pinfo->brg = 4;
217
218 cpm2_unmap(cpmux);
219 cpm2_unmap(io);
220 }
221 #endif
222
223 /*
224 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
225 * receive buffer descriptors from dual port ram, and a character
226 * buffer area from host mem. If we are allocating for the console we need
227 * to do it from bootmem
228 */
229 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
230 {
231 int dpmemsz, memsz;
232 u8 __iomem *dp_mem;
233 unsigned long dp_offset;
234 u8 *mem_addr;
235 dma_addr_t dma_addr = 0;
236
237 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
238
239 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
240 dp_offset = cpm_dpalloc(dpmemsz, 8);
241 if (IS_ERR_VALUE(dp_offset)) {
242 printk(KERN_ERR
243 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
244 return -ENOMEM;
245 }
246
247 dp_mem = cpm_dpram_addr(dp_offset);
248
249 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
250 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
251 if (is_con) {
252 mem_addr = alloc_bootmem(memsz);
253 dma_addr = virt_to_bus(mem_addr);
254 }
255 else
256 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
257 GFP_KERNEL);
258
259 if (mem_addr == NULL) {
260 cpm_dpfree(dp_offset);
261 printk(KERN_ERR
262 "cpm_uart_cpm.c: could not allocate coherent memory\n");
263 return -ENOMEM;
264 }
265
266 pinfo->dp_addr = dp_offset;
267 pinfo->mem_addr = mem_addr;
268 pinfo->dma_addr = dma_addr;
269 pinfo->mem_size = memsz;
270
271 pinfo->rx_buf = mem_addr;
272 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
273 * pinfo->rx_fifosize);
274
275 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem;
276 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
277
278 return 0;
279 }
280
281 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
282 {
283 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
284 pinfo->rx_fifosize) +
285 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
286 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
287 pinfo->dma_addr);
288
289 cpm_dpfree(pinfo->dp_addr);
290 }
291
292 #ifndef CONFIG_PPC_CPM_NEW_BINDING
293 /* Setup any dynamic params in the uart desc */
294 int cpm_uart_init_portdesc(void)
295 {
296 #if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
297 u16 *addr;
298 #endif
299 pr_debug("CPM uart[-]:init portdesc\n");
300
301 cpm_uart_nr = 0;
302 #ifdef CONFIG_SERIAL_CPM_SMC1
303 cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
304 cpm_uart_ports[UART_SMC1].port.mapbase =
305 (unsigned long)cpm_uart_ports[UART_SMC1].smcp;
306
307 cpm_uart_ports[UART_SMC1].smcup =
308 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
309 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
310 *addr = PROFF_SMC1;
311 cpm2_unmap(addr);
312
313 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
314 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
315 cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
316 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
317 #endif
318
319 #ifdef CONFIG_SERIAL_CPM_SMC2
320 cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
321 cpm_uart_ports[UART_SMC2].port.mapbase =
322 (unsigned long)cpm_uart_ports[UART_SMC2].smcp;
323
324 cpm_uart_ports[UART_SMC2].smcup =
325 (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
326 addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
327 *addr = PROFF_SMC2;
328 cpm2_unmap(addr);
329
330 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
331 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
332 cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
333 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
334 #endif
335
336 #ifdef CONFIG_SERIAL_CPM_SCC1
337 cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
338 cpm_uart_ports[UART_SCC1].port.mapbase =
339 (unsigned long)cpm_uart_ports[UART_SCC1].sccp;
340 cpm_uart_ports[UART_SCC1].sccup =
341 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
342
343 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
344 ~(UART_SCCM_TX | UART_SCCM_RX);
345 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
346 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
347 cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
348 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
349 #endif
350
351 #ifdef CONFIG_SERIAL_CPM_SCC2
352 cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
353 cpm_uart_ports[UART_SCC2].port.mapbase =
354 (unsigned long)cpm_uart_ports[UART_SCC2].sccp;
355 cpm_uart_ports[UART_SCC2].sccup =
356 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
357
358 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
359 ~(UART_SCCM_TX | UART_SCCM_RX);
360 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
361 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
362 cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
363 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
364 #endif
365
366 #ifdef CONFIG_SERIAL_CPM_SCC3
367 cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
368 cpm_uart_ports[UART_SCC3].port.mapbase =
369 (unsigned long)cpm_uart_ports[UART_SCC3].sccp;
370 cpm_uart_ports[UART_SCC3].sccup =
371 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
372
373 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
374 ~(UART_SCCM_TX | UART_SCCM_RX);
375 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
376 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
377 cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
378 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
379 #endif
380
381 #ifdef CONFIG_SERIAL_CPM_SCC4
382 cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
383 cpm_uart_ports[UART_SCC4].port.mapbase =
384 (unsigned long)cpm_uart_ports[UART_SCC4].sccp;
385 cpm_uart_ports[UART_SCC4].sccup =
386 (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
387
388 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
389 ~(UART_SCCM_TX | UART_SCCM_RX);
390 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
391 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
392 cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
393 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
394 #endif
395
396 return 0;
397 }
398 #endif
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