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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / scsi / aic7xxx / aic7xxx_pci.c
blob56848f41e4f961f7a70d66964a8d770671ff0663
1 /*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $
43 */
44
45 #ifdef __linux__
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aic7xxx_93cx6.h"
49 #else
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aic7xxx_93cx6.h>
53 #endif
54
55 #include "aic7xxx_pci.h"
56
57 static __inline uint64_t
58 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
59 {
60 uint64_t id;
61
62 id = subvendor
63 | (subdevice << 16)
64 | ((uint64_t)vendor << 32)
65 | ((uint64_t)device << 48);
66
67 return (id);
68 }
69
70 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
71 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
72
73 #define DEVID_9005_TYPE(id) ((id) & 0xF)
74 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
75 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
76 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
77 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
78
79 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
80 #define DEVID_9005_MAXRATE_U160 0x0
81 #define DEVID_9005_MAXRATE_ULTRA2 0x1
82 #define DEVID_9005_MAXRATE_ULTRA 0x2
83 #define DEVID_9005_MAXRATE_FAST 0x3
84
85 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
86
87 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
88 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
89
90 #define SUBID_9005_TYPE(id) ((id) & 0xF)
91 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
92 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
93 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
94 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
95
96 #define SUBID_9005_TYPE_KNOWN(id) \
97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
101
102 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
103 #define SUBID_9005_MAXRATE_ULTRA2 0x0
104 #define SUBID_9005_MAXRATE_ULTRA 0x1
105 #define SUBID_9005_MAXRATE_U160 0x2
106 #define SUBID_9005_MAXRATE_RESERVED 0x3
107
108 #define SUBID_9005_SEEPTYPE(id) \
109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
110 ? ((id) & 0xC0) >> 6 \
111 : ((id) & 0x300) >> 8)
112 #define SUBID_9005_SEEPTYPE_NONE 0x0
113 #define SUBID_9005_SEEPTYPE_1K 0x1
114 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
115 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
116 #define SUBID_9005_AUTOTERM(id) \
117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
118 ? (((id) & 0x400) >> 10) == 0 \
119 : (((id) & 0x40) >> 6) == 0)
120
121 #define SUBID_9005_NUMCHAN(id) \
122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
123 ? ((id) & 0x300) >> 8 \
124 : ((id) & 0xC00) >> 10)
125
126 #define SUBID_9005_LEGACYCONN(id) \
127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
128 ? 0 \
129 : ((id) & 0x80) >> 7)
130
131 #define SUBID_9005_MFUNCENB(id) \
132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
133 ? ((id) & 0x800) >> 11 \
134 : ((id) & 0x1000) >> 12)
135 /*
136 * Informational only. Should use chip register to be
137 * certain, but may be use in identification strings.
138 */
139 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
140 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
141 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
142
143 static ahc_device_setup_t ahc_aic785X_setup;
144 static ahc_device_setup_t ahc_aic7860_setup;
145 static ahc_device_setup_t ahc_apa1480_setup;
146 static ahc_device_setup_t ahc_aic7870_setup;
147 static ahc_device_setup_t ahc_aic7870h_setup;
148 static ahc_device_setup_t ahc_aha394X_setup;
149 static ahc_device_setup_t ahc_aha394Xh_setup;
150 static ahc_device_setup_t ahc_aha494X_setup;
151 static ahc_device_setup_t ahc_aha494Xh_setup;
152 static ahc_device_setup_t ahc_aha398X_setup;
153 static ahc_device_setup_t ahc_aic7880_setup;
154 static ahc_device_setup_t ahc_aic7880h_setup;
155 static ahc_device_setup_t ahc_aha2940Pro_setup;
156 static ahc_device_setup_t ahc_aha394XU_setup;
157 static ahc_device_setup_t ahc_aha394XUh_setup;
158 static ahc_device_setup_t ahc_aha398XU_setup;
159 static ahc_device_setup_t ahc_aic7890_setup;
160 static ahc_device_setup_t ahc_aic7892_setup;
161 static ahc_device_setup_t ahc_aic7895_setup;
162 static ahc_device_setup_t ahc_aic7895h_setup;
163 static ahc_device_setup_t ahc_aic7896_setup;
164 static ahc_device_setup_t ahc_aic7899_setup;
165 static ahc_device_setup_t ahc_aha29160C_setup;
166 static ahc_device_setup_t ahc_raid_setup;
167 static ahc_device_setup_t ahc_aha394XX_setup;
168 static ahc_device_setup_t ahc_aha494XX_setup;
169 static ahc_device_setup_t ahc_aha398XX_setup;
170
171 static struct ahc_pci_identity ahc_pci_ident_table [] =
172 {
173 /* aic7850 based controllers */
174 {
175 ID_AHA_2902_04_10_15_20C_30C,
176 ID_ALL_MASK,
177 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
178 ahc_aic785X_setup
179 },
180 /* aic7860 based controllers */
181 {
182 ID_AHA_2930CU,
183 ID_ALL_MASK,
184 "Adaptec 2930CU SCSI adapter",
185 ahc_aic7860_setup
186 },
187 {
188 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
189 ID_DEV_VENDOR_MASK,
190 "Adaptec 1480A Ultra SCSI adapter",
191 ahc_apa1480_setup
192 },
193 {
194 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
195 ID_DEV_VENDOR_MASK,
196 "Adaptec 2940A Ultra SCSI adapter",
197 ahc_aic7860_setup
198 },
199 {
200 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
201 ID_DEV_VENDOR_MASK,
202 "Adaptec 2940A/CN Ultra SCSI adapter",
203 ahc_aic7860_setup
204 },
205 {
206 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
207 ID_DEV_VENDOR_MASK,
208 "Adaptec 2930C Ultra SCSI adapter (VAR)",
209 ahc_aic7860_setup
210 },
211 /* aic7870 based controllers */
212 {
213 ID_AHA_2940,
214 ID_ALL_MASK,
215 "Adaptec 2940 SCSI adapter",
216 ahc_aic7870_setup
217 },
218 {
219 ID_AHA_3940,
220 ID_ALL_MASK,
221 "Adaptec 3940 SCSI adapter",
222 ahc_aha394X_setup
223 },
224 {
225 ID_AHA_398X,
226 ID_ALL_MASK,
227 "Adaptec 398X SCSI RAID adapter",
228 ahc_aha398X_setup
229 },
230 {
231 ID_AHA_2944,
232 ID_ALL_MASK,
233 "Adaptec 2944 SCSI adapter",
234 ahc_aic7870h_setup
235 },
236 {
237 ID_AHA_3944,
238 ID_ALL_MASK,
239 "Adaptec 3944 SCSI adapter",
240 ahc_aha394Xh_setup
241 },
242 {
243 ID_AHA_4944,
244 ID_ALL_MASK,
245 "Adaptec 4944 SCSI adapter",
246 ahc_aha494Xh_setup
247 },
248 /* aic7880 based controllers */
249 {
250 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
251 ID_DEV_VENDOR_MASK,
252 "Adaptec 2940 Ultra SCSI adapter",
253 ahc_aic7880_setup
254 },
255 {
256 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
257 ID_DEV_VENDOR_MASK,
258 "Adaptec 3940 Ultra SCSI adapter",
259 ahc_aha394XU_setup
260 },
261 {
262 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
263 ID_DEV_VENDOR_MASK,
264 "Adaptec 2944 Ultra SCSI adapter",
265 ahc_aic7880h_setup
266 },
267 {
268 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
269 ID_DEV_VENDOR_MASK,
270 "Adaptec 3944 Ultra SCSI adapter",
271 ahc_aha394XUh_setup
272 },
273 {
274 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
275 ID_DEV_VENDOR_MASK,
276 "Adaptec 398X Ultra SCSI RAID adapter",
277 ahc_aha398XU_setup
278 },
279 {
280 /*
281 * XXX Don't know the slot numbers
282 * so we can't identify channels
283 */
284 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
285 ID_DEV_VENDOR_MASK,
286 "Adaptec 4944 Ultra SCSI adapter",
287 ahc_aic7880h_setup
288 },
289 {
290 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
291 ID_DEV_VENDOR_MASK,
292 "Adaptec 2930 Ultra SCSI adapter",
293 ahc_aic7880_setup
294 },
295 {
296 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
297 ID_DEV_VENDOR_MASK,
298 "Adaptec 2940 Pro Ultra SCSI adapter",
299 ahc_aha2940Pro_setup
300 },
301 {
302 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
303 ID_DEV_VENDOR_MASK,
304 "Adaptec 2940/CN Ultra SCSI adapter",
305 ahc_aic7880_setup
306 },
307 /* Ignore all SISL (AAC on MB) based controllers. */
308 {
309 ID_9005_SISL_ID,
310 ID_9005_SISL_MASK,
311 NULL,
312 NULL
313 },
314 /* aic7890 based controllers */
315 {
316 ID_AHA_2930U2,
317 ID_ALL_MASK,
318 "Adaptec 2930 Ultra2 SCSI adapter",
319 ahc_aic7890_setup
320 },
321 {
322 ID_AHA_2940U2B,
323 ID_ALL_MASK,
324 "Adaptec 2940B Ultra2 SCSI adapter",
325 ahc_aic7890_setup
326 },
327 {
328 ID_AHA_2940U2_OEM,
329 ID_ALL_MASK,
330 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
331 ahc_aic7890_setup
332 },
333 {
334 ID_AHA_2940U2,
335 ID_ALL_MASK,
336 "Adaptec 2940 Ultra2 SCSI adapter",
337 ahc_aic7890_setup
338 },
339 {
340 ID_AHA_2950U2B,
341 ID_ALL_MASK,
342 "Adaptec 2950 Ultra2 SCSI adapter",
343 ahc_aic7890_setup
344 },
345 {
346 ID_AIC7890_ARO,
347 ID_ALL_MASK,
348 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
349 ahc_aic7890_setup
350 },
351 {
352 ID_AAA_131U2,
353 ID_ALL_MASK,
354 "Adaptec AAA-131 Ultra2 RAID adapter",
355 ahc_aic7890_setup
356 },
357 /* aic7892 based controllers */
358 {
359 ID_AHA_29160,
360 ID_ALL_MASK,
361 "Adaptec 29160 Ultra160 SCSI adapter",
362 ahc_aic7892_setup
363 },
364 {
365 ID_AHA_29160_CPQ,
366 ID_ALL_MASK,
367 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
368 ahc_aic7892_setup
369 },
370 {
371 ID_AHA_29160N,
372 ID_ALL_MASK,
373 "Adaptec 29160N Ultra160 SCSI adapter",
374 ahc_aic7892_setup
375 },
376 {
377 ID_AHA_29160C,
378 ID_ALL_MASK,
379 "Adaptec 29160C Ultra160 SCSI adapter",
380 ahc_aha29160C_setup
381 },
382 {
383 ID_AHA_29160B,
384 ID_ALL_MASK,
385 "Adaptec 29160B Ultra160 SCSI adapter",
386 ahc_aic7892_setup
387 },
388 {
389 ID_AHA_19160B,
390 ID_ALL_MASK,
391 "Adaptec 19160B Ultra160 SCSI adapter",
392 ahc_aic7892_setup
393 },
394 {
395 ID_AIC7892_ARO,
396 ID_ALL_MASK,
397 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
398 ahc_aic7892_setup
399 },
400 {
401 ID_AHA_2915_30LP,
402 ID_ALL_MASK,
403 "Adaptec 2915/30LP Ultra160 SCSI adapter",
404 ahc_aic7892_setup
405 },
406 /* aic7895 based controllers */
407 {
408 ID_AHA_2940U_DUAL,
409 ID_ALL_MASK,
410 "Adaptec 2940/DUAL Ultra SCSI adapter",
411 ahc_aic7895_setup
412 },
413 {
414 ID_AHA_3940AU,
415 ID_ALL_MASK,
416 "Adaptec 3940A Ultra SCSI adapter",
417 ahc_aic7895_setup
418 },
419 {
420 ID_AHA_3944AU,
421 ID_ALL_MASK,
422 "Adaptec 3944A Ultra SCSI adapter",
423 ahc_aic7895h_setup
424 },
425 {
426 ID_AIC7895_ARO,
427 ID_AIC7895_ARO_MASK,
428 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
429 ahc_aic7895_setup
430 },
431 /* aic7896/97 based controllers */
432 {
433 ID_AHA_3950U2B_0,
434 ID_ALL_MASK,
435 "Adaptec 3950B Ultra2 SCSI adapter",
436 ahc_aic7896_setup
437 },
438 {
439 ID_AHA_3950U2B_1,
440 ID_ALL_MASK,
441 "Adaptec 3950B Ultra2 SCSI adapter",
442 ahc_aic7896_setup
443 },
444 {
445 ID_AHA_3950U2D_0,
446 ID_ALL_MASK,
447 "Adaptec 3950D Ultra2 SCSI adapter",
448 ahc_aic7896_setup
449 },
450 {
451 ID_AHA_3950U2D_1,
452 ID_ALL_MASK,
453 "Adaptec 3950D Ultra2 SCSI adapter",
454 ahc_aic7896_setup
455 },
456 {
457 ID_AIC7896_ARO,
458 ID_ALL_MASK,
459 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
460 ahc_aic7896_setup
461 },
462 /* aic7899 based controllers */
463 {
464 ID_AHA_3960D,
465 ID_ALL_MASK,
466 "Adaptec 3960D Ultra160 SCSI adapter",
467 ahc_aic7899_setup
468 },
469 {
470 ID_AHA_3960D_CPQ,
471 ID_ALL_MASK,
472 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
473 ahc_aic7899_setup
474 },
475 {
476 ID_AIC7899_ARO,
477 ID_ALL_MASK,
478 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
479 ahc_aic7899_setup
480 },
481 /* Generic chip probes for devices we don't know 'exactly' */
482 {
483 ID_AIC7850 & ID_DEV_VENDOR_MASK,
484 ID_DEV_VENDOR_MASK,
485 "Adaptec aic7850 SCSI adapter",
486 ahc_aic785X_setup
487 },
488 {
489 ID_AIC7855 & ID_DEV_VENDOR_MASK,
490 ID_DEV_VENDOR_MASK,
491 "Adaptec aic7855 SCSI adapter",
492 ahc_aic785X_setup
493 },
494 {
495 ID_AIC7859 & ID_DEV_VENDOR_MASK,
496 ID_DEV_VENDOR_MASK,
497 "Adaptec aic7859 SCSI adapter",
498 ahc_aic7860_setup
499 },
500 {
501 ID_AIC7860 & ID_DEV_VENDOR_MASK,
502 ID_DEV_VENDOR_MASK,
503 "Adaptec aic7860 Ultra SCSI adapter",
504 ahc_aic7860_setup
505 },
506 {
507 ID_AIC7870 & ID_DEV_VENDOR_MASK,
508 ID_DEV_VENDOR_MASK,
509 "Adaptec aic7870 SCSI adapter",
510 ahc_aic7870_setup
511 },
512 {
513 ID_AIC7880 & ID_DEV_VENDOR_MASK,
514 ID_DEV_VENDOR_MASK,
515 "Adaptec aic7880 Ultra SCSI adapter",
516 ahc_aic7880_setup
517 },
518 {
519 ID_AIC7890 & ID_9005_GENERIC_MASK,
520 ID_9005_GENERIC_MASK,
521 "Adaptec aic7890/91 Ultra2 SCSI adapter",
522 ahc_aic7890_setup
523 },
524 {
525 ID_AIC7892 & ID_9005_GENERIC_MASK,
526 ID_9005_GENERIC_MASK,
527 "Adaptec aic7892 Ultra160 SCSI adapter",
528 ahc_aic7892_setup
529 },
530 {
531 ID_AIC7895 & ID_DEV_VENDOR_MASK,
532 ID_DEV_VENDOR_MASK,
533 "Adaptec aic7895 Ultra SCSI adapter",
534 ahc_aic7895_setup
535 },
536 {
537 ID_AIC7896 & ID_9005_GENERIC_MASK,
538 ID_9005_GENERIC_MASK,
539 "Adaptec aic7896/97 Ultra2 SCSI adapter",
540 ahc_aic7896_setup
541 },
542 {
543 ID_AIC7899 & ID_9005_GENERIC_MASK,
544 ID_9005_GENERIC_MASK,
545 "Adaptec aic7899 Ultra160 SCSI adapter",
546 ahc_aic7899_setup
547 },
548 {
549 ID_AIC7810 & ID_DEV_VENDOR_MASK,
550 ID_DEV_VENDOR_MASK,
551 "Adaptec aic7810 RAID memory controller",
552 ahc_raid_setup
553 },
554 {
555 ID_AIC7815 & ID_DEV_VENDOR_MASK,
556 ID_DEV_VENDOR_MASK,
557 "Adaptec aic7815 RAID memory controller",
558 ahc_raid_setup
559 }
560 };
561
562 static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table);
563
564 #define AHC_394X_SLOT_CHANNEL_A 4
565 #define AHC_394X_SLOT_CHANNEL_B 5
566
567 #define AHC_398X_SLOT_CHANNEL_A 4
568 #define AHC_398X_SLOT_CHANNEL_B 8
569 #define AHC_398X_SLOT_CHANNEL_C 12
570
571 #define AHC_494X_SLOT_CHANNEL_A 4
572 #define AHC_494X_SLOT_CHANNEL_B 5
573 #define AHC_494X_SLOT_CHANNEL_C 6
574 #define AHC_494X_SLOT_CHANNEL_D 7
575
576 #define DEVCONFIG 0x40
577 #define PCIERRGENDIS 0x80000000ul
578 #define SCBSIZE32 0x00010000ul /* aic789X only */
579 #define REXTVALID 0x00001000ul /* ultra cards only */
580 #define MPORTMODE 0x00000400ul /* aic7870+ only */
581 #define RAMPSM 0x00000200ul /* aic7870+ only */
582 #define VOLSENSE 0x00000100ul
583 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
584 #define SCBRAMSEL 0x00000080ul
585 #define MRDCEN 0x00000040ul
586 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
587 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
588 #define BERREN 0x00000008ul
589 #define DACEN 0x00000004ul
590 #define STPWLEVEL 0x00000002ul
591 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
592
593 #define CSIZE_LATTIME 0x0c
594 #define CACHESIZE 0x0000003ful /* only 5 bits */
595 #define LATTIME 0x0000ff00ul
596
597 /* PCI STATUS definitions */
598 #define DPE 0x80
599 #define SSE 0x40
600 #define RMA 0x20
601 #define RTA 0x10
602 #define STA 0x08
603 #define DPR 0x01
604
605 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
606 uint16_t subvendor, uint16_t subdevice);
607 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
608 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
609 int pcheck, int fast, int large);
610 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
611 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
612 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
613 struct seeprom_config *sc);
614 static void configure_termination(struct ahc_softc *ahc,
615 struct seeprom_descriptor *sd,
616 u_int adapter_control,
617 u_int *sxfrctl1);
618
619 static void ahc_new_term_detect(struct ahc_softc *ahc,
620 int *enableSEC_low,
621 int *enableSEC_high,
622 int *enablePRI_low,
623 int *enablePRI_high,
624 int *eeprom_present);
625 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
626 int *internal68_present,
627 int *externalcable_present,
628 int *eeprom_present);
629 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
630 int *externalcable_present,
631 int *eeprom_present);
632 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
633 static uint8_t read_brdctl(struct ahc_softc *ahc);
634 static void ahc_pci_intr(struct ahc_softc *ahc);
635 static int ahc_pci_chip_init(struct ahc_softc *ahc);
636
637 static int
638 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
639 uint16_t subdevice, uint16_t subvendor)
640 {
641 int result;
642
643 /* Default to invalid. */
644 result = 0;
645 if (vendor == 0x9005
646 && subvendor == 0x9005
647 && subdevice != device
648 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
649
650 switch (SUBID_9005_TYPE(subdevice)) {
651 case SUBID_9005_TYPE_MB:
652 break;
653 case SUBID_9005_TYPE_CARD:
654 case SUBID_9005_TYPE_LCCARD:
655 /*
656 * Currently only trust Adaptec cards to
657 * get the sub device info correct.
658 */
659 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
660 result = 1;
661 break;
662 case SUBID_9005_TYPE_RAID:
663 break;
664 default:
665 break;
666 }
667 }
668 return (result);
669 }
670
671 struct ahc_pci_identity *
672 ahc_find_pci_device(ahc_dev_softc_t pci)
673 {
674 uint64_t full_id;
675 uint16_t device;
676 uint16_t vendor;
677 uint16_t subdevice;
678 uint16_t subvendor;
679 struct ahc_pci_identity *entry;
680 u_int i;
681
682 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
683 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
684 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
685 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
686 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
687
688 /*
689 * If the second function is not hooked up, ignore it.
690 * Unfortunately, not all MB vendors implement the
691 * subdevice ID as per the Adaptec spec, so do our best
692 * to sanity check it prior to accepting the subdevice
693 * ID as valid.
694 */
695 if (ahc_get_pci_function(pci) > 0
696 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
697 && SUBID_9005_MFUNCENB(subdevice) == 0)
698 return (NULL);
699
700 for (i = 0; i < ahc_num_pci_devs; i++) {
701 entry = &ahc_pci_ident_table[i];
702 if (entry->full_id == (full_id & entry->id_mask)) {
703 /* Honor exclusion entries. */
704 if (entry->name == NULL)
705 return (NULL);
706 return (entry);
707 }
708 }
709 return (NULL);
710 }
711
712 int
713 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
714 {
715 u_int command;
716 u_int our_id;
717 u_int sxfrctl1;
718 u_int scsiseq;
719 u_int dscommand0;
720 uint32_t devconfig;
721 int error;
722 uint8_t sblkctl;
723
724 our_id = 0;
725 error = entry->setup(ahc);
726 if (error != 0)
727 return (error);
728 ahc->chip |= AHC_PCI;
729 ahc->description = entry->name;
730
731 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
732
733 error = ahc_pci_map_registers(ahc);
734 if (error != 0)
735 return (error);
736
737 /*
738 * Before we continue probing the card, ensure that
739 * its interrupts are *disabled*. We don't want
740 * a misstep to hang the machine in an interrupt
741 * storm.
742 */
743 ahc_intr_enable(ahc, FALSE);
744
745 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
746
747 /*
748 * If we need to support high memory, enable dual
749 * address cycles. This bit must be set to enable
750 * high address bit generation even if we are on a
751 * 64bit bus (PCI64BIT set in devconfig).
752 */
753 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
754
755 if (bootverbose)
756 printf("%s: Enabling 39Bit Addressing\n",
757 ahc_name(ahc));
758 devconfig |= DACEN;
759 }
760
761 /* Ensure that pci error generation, a test feature, is disabled. */
762 devconfig |= PCIERRGENDIS;
763
764 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
765
766 /* Ensure busmastering is enabled */
767 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
768 command |= PCIM_CMD_BUSMASTEREN;
769
770 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
771
772 /* On all PCI adapters, we allow SCB paging */
773 ahc->flags |= AHC_PAGESCBS;
774
775 error = ahc_softc_init(ahc);
776 if (error != 0)
777 return (error);
778
779 /*
780 * Disable PCI parity error checking. Users typically
781 * do this to work around broken PCI chipsets that get
782 * the parity timing wrong and thus generate lots of spurious
783 * errors. The chip only allows us to disable *all* parity
784 * error reporting when doing this, so CIO bus, scb ram, and
785 * scratch ram parity errors will be ignored too.
786 */
787 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
788 ahc->seqctl |= FAILDIS;
789
790 ahc->bus_intr = ahc_pci_intr;
791 ahc->bus_chip_init = ahc_pci_chip_init;
792
793 /* Remeber how the card was setup in case there is no SEEPROM */
794 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
795 ahc_pause(ahc);
796 if ((ahc->features & AHC_ULTRA2) != 0)
797 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
798 else
799 our_id = ahc_inb(ahc, SCSIID) & OID;
800 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
801 scsiseq = ahc_inb(ahc, SCSISEQ);
802 } else {
803 sxfrctl1 = STPWEN;
804 our_id = 7;
805 scsiseq = 0;
806 }
807
808 error = ahc_reset(ahc, /*reinit*/FALSE);
809 if (error != 0)
810 return (ENXIO);
811
812 if ((ahc->features & AHC_DT) != 0) {
813 u_int sfunct;
814
815 /* Perform ALT-Mode Setup */
816 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
817 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
818 ahc_outb(ahc, OPTIONMODE,
819 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
820 ahc_outb(ahc, SFUNCT, sfunct);
821
822 /* Normal mode setup */
823 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
824 |TARGCRCENDEN);
825 }
826
827 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
828 dscommand0 |= MPARCKEN|CACHETHEN;
829 if ((ahc->features & AHC_ULTRA2) != 0) {
830
831 /*
832 * DPARCKEN doesn't work correctly on
833 * some MBs so don't use it.
834 */
835 dscommand0 &= ~DPARCKEN;
836 }
837
838 /*
839 * Handle chips that must have cache line
840 * streaming (dis/en)abled.
841 */
842 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
843 dscommand0 |= CACHETHEN;
844
845 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
846 dscommand0 &= ~CACHETHEN;
847
848 ahc_outb(ahc, DSCOMMAND0, dscommand0);
849
850 ahc->pci_cachesize =
851 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
852 /*bytes*/1) & CACHESIZE;
853 ahc->pci_cachesize *= 4;
854
855 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
856 && ahc->pci_cachesize == 4) {
857
858 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
859 0, /*bytes*/1);
860 ahc->pci_cachesize = 0;
861 }
862
863 /*
864 * We cannot perform ULTRA speeds without the presense
865 * of the external precision resistor.
866 */
867 if ((ahc->features & AHC_ULTRA) != 0) {
868 uint32_t devconfig;
869
870 devconfig = ahc_pci_read_config(ahc->dev_softc,
871 DEVCONFIG, /*bytes*/4);
872 if ((devconfig & REXTVALID) == 0)
873 ahc->features &= ~AHC_ULTRA;
874 }
875
876 /* See if we have a SEEPROM and perform auto-term */
877 check_extport(ahc, &sxfrctl1);
878
879 /*
880 * Take the LED out of diagnostic mode
881 */
882 sblkctl = ahc_inb(ahc, SBLKCTL);
883 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
884
885 if ((ahc->features & AHC_ULTRA2) != 0) {
886 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
887 } else {
888 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
889 }
890
891 if (ahc->flags & AHC_USEDEFAULTS) {
892 /*
893 * PCI Adapter default setup
894 * Should only be used if the adapter does not have
895 * a SEEPROM.
896 */
897 /* See if someone else set us up already */
898 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
899 && scsiseq != 0) {
900 printf("%s: Using left over BIOS settings\n",
901 ahc_name(ahc));
902 ahc->flags &= ~AHC_USEDEFAULTS;
903 ahc->flags |= AHC_BIOS_ENABLED;
904 } else {
905 /*
906 * Assume only one connector and always turn
907 * on termination.
908 */
909 our_id = 0x07;
910 sxfrctl1 = STPWEN;
911 }
912 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
913
914 ahc->our_id = our_id;
915 }
916
917 /*
918 * Take a look to see if we have external SRAM.
919 * We currently do not attempt to use SRAM that is
920 * shared among multiple controllers.
921 */
922 ahc_probe_ext_scbram(ahc);
923
924 /*
925 * Record our termination setting for the
926 * generic initialization routine.
927 */
928 if ((sxfrctl1 & STPWEN) != 0)
929 ahc->flags |= AHC_TERM_ENB_A;
930
931 /*
932 * Save chip register configuration data for chip resets
933 * that occur during runtime and resume events.
934 */
935 ahc->bus_softc.pci_softc.devconfig =
936 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
937 ahc->bus_softc.pci_softc.command =
938 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
939 ahc->bus_softc.pci_softc.csize_lattime =
940 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
941 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
942 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
943 if ((ahc->features & AHC_DT) != 0) {
944 u_int sfunct;
945
946 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
947 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
948 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
949 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
950 ahc_outb(ahc, SFUNCT, sfunct);
951 ahc->bus_softc.pci_softc.crccontrol1 =
952 ahc_inb(ahc, CRCCONTROL1);
953 }
954 if ((ahc->features & AHC_MULTI_FUNC) != 0)
955 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
956
957 if ((ahc->features & AHC_ULTRA2) != 0)
958 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
959
960 /* Core initialization */
961 error = ahc_init(ahc);
962 if (error != 0)
963 return (error);
964
965 /*
966 * Allow interrupts now that we are completely setup.
967 */
968 error = ahc_pci_map_int(ahc);
969 if (error != 0)
970 return (error);
971
972 ahc->init_level++;
973 return (0);
974 }
975
976 /*
977 * Test for the presense of external sram in an
978 * "unshared" configuration.
979 */
980 static int
981 ahc_ext_scbram_present(struct ahc_softc *ahc)
982 {
983 u_int chip;
984 int ramps;
985 int single_user;
986 uint32_t devconfig;
987
988 chip = ahc->chip & AHC_CHIPID_MASK;
989 devconfig = ahc_pci_read_config(ahc->dev_softc,
990 DEVCONFIG, /*bytes*/4);
991 single_user = (devconfig & MPORTMODE) != 0;
992
993 if ((ahc->features & AHC_ULTRA2) != 0)
994 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
995 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
996 /*
997 * External SCBRAM arbitration is flakey
998 * on these chips. Unfortunately this means
999 * we don't use the extra SCB ram space on the
1000 * 3940AUW.
1001 */
1002 ramps = 0;
1003 else if (chip >= AHC_AIC7870)
1004 ramps = (devconfig & RAMPSM) != 0;
1005 else
1006 ramps = 0;
1007
1008 if (ramps && single_user)
1009 return (1);
1010 return (0);
1011 }
1012
1013 /*
1014 * Enable external scbram.
1015 */
1016 static void
1017 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1018 int fast, int large)
1019 {
1020 uint32_t devconfig;
1021
1022 if (ahc->features & AHC_MULTI_FUNC) {
1023 /*
1024 * Set the SCB Base addr (highest address bit)
1025 * depending on which channel we are.
1026 */
1027 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1028 }
1029
1030 ahc->flags &= ~AHC_LSCBS_ENABLED;
1031 if (large)
1032 ahc->flags |= AHC_LSCBS_ENABLED;
1033 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1034 if ((ahc->features & AHC_ULTRA2) != 0) {
1035 u_int dscommand0;
1036
1037 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1038 if (enable)
1039 dscommand0 &= ~INTSCBRAMSEL;
1040 else
1041 dscommand0 |= INTSCBRAMSEL;
1042 if (large)
1043 dscommand0 &= ~USCBSIZE32;
1044 else
1045 dscommand0 |= USCBSIZE32;
1046 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1047 } else {
1048 if (fast)
1049 devconfig &= ~EXTSCBTIME;
1050 else
1051 devconfig |= EXTSCBTIME;
1052 if (enable)
1053 devconfig &= ~SCBRAMSEL;
1054 else
1055 devconfig |= SCBRAMSEL;
1056 if (large)
1057 devconfig &= ~SCBSIZE32;
1058 else
1059 devconfig |= SCBSIZE32;
1060 }
1061 if (pcheck)
1062 devconfig |= EXTSCBPEN;
1063 else
1064 devconfig &= ~EXTSCBPEN;
1065
1066 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1067 }
1068
1069 /*
1070 * Take a look to see if we have external SRAM.
1071 * We currently do not attempt to use SRAM that is
1072 * shared among multiple controllers.
1073 */
1074 static void
1075 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1076 {
1077 int num_scbs;
1078 int test_num_scbs;
1079 int enable;
1080 int pcheck;
1081 int fast;
1082 int large;
1083
1084 enable = FALSE;
1085 pcheck = FALSE;
1086 fast = FALSE;
1087 large = FALSE;
1088 num_scbs = 0;
1089
1090 if (ahc_ext_scbram_present(ahc) == 0)
1091 goto done;
1092
1093 /*
1094 * Probe for the best parameters to use.
1095 */
1096 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1097 num_scbs = ahc_probe_scbs(ahc);
1098 if (num_scbs == 0) {
1099 /* The SRAM wasn't really present. */
1100 goto done;
1101 }
1102 enable = TRUE;
1103
1104 /*
1105 * Clear any outstanding parity error
1106 * and ensure that parity error reporting
1107 * is enabled.
1108 */
1109 ahc_outb(ahc, SEQCTL, 0);
1110 ahc_outb(ahc, CLRINT, CLRPARERR);
1111 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1112
1113 /* Now see if we can do parity */
1114 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1115 num_scbs = ahc_probe_scbs(ahc);
1116 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1117 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1118 pcheck = TRUE;
1119
1120 /* Clear any resulting parity error */
1121 ahc_outb(ahc, CLRINT, CLRPARERR);
1122 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1123
1124 /* Now see if we can do fast timing */
1125 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1126 test_num_scbs = ahc_probe_scbs(ahc);
1127 if (test_num_scbs == num_scbs
1128 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1129 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1130 fast = TRUE;
1131
1132 /*
1133 * See if we can use large SCBs and still maintain
1134 * the same overall count of SCBs.
1135 */
1136 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1137 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1138 test_num_scbs = ahc_probe_scbs(ahc);
1139 if (test_num_scbs >= num_scbs) {
1140 large = TRUE;
1141 num_scbs = test_num_scbs;
1142 if (num_scbs >= 64) {
1143 /*
1144 * We have enough space to move the
1145 * "busy targets table" into SCB space
1146 * and make it qualify all the way to the
1147 * lun level.
1148 */
1149 ahc->flags |= AHC_SCB_BTT;
1150 }
1151 }
1152 }
1153 done:
1154 /*
1155 * Disable parity error reporting until we
1156 * can load instruction ram.
1157 */
1158 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1159 /* Clear any latched parity error */
1160 ahc_outb(ahc, CLRINT, CLRPARERR);
1161 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1162 if (bootverbose && enable) {
1163 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1164 ahc_name(ahc), fast ? "fast" : "slow",
1165 pcheck ? ", parity checking enabled" : "",
1166 large ? 64 : 32);
1167 }
1168 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1169 }
1170
1171 /*
1172 * Perform some simple tests that should catch situations where
1173 * our registers are invalidly mapped.
1174 */
1175 int
1176 ahc_pci_test_register_access(struct ahc_softc *ahc)
1177 {
1178 int error;
1179 u_int status1;
1180 uint32_t cmd;
1181 uint8_t hcntrl;
1182
1183 error = EIO;
1184
1185 /*
1186 * Enable PCI error interrupt status, but suppress NMIs
1187 * generated by SERR raised due to target aborts.
1188 */
1189 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1190 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1191 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1192
1193 /*
1194 * First a simple test to see if any
1195 * registers can be read. Reading
1196 * HCNTRL has no side effects and has
1197 * at least one bit that is guaranteed to
1198 * be zero so it is a good register to
1199 * use for this test.
1200 */
1201 hcntrl = ahc_inb(ahc, HCNTRL);
1202
1203 if (hcntrl == 0xFF)
1204 goto fail;
1205
1206 if ((hcntrl & CHIPRST) != 0) {
1207 /*
1208 * The chip has not been initialized since
1209 * PCI/EISA/VLB bus reset. Don't trust
1210 * "left over BIOS data".
1211 */
1212 ahc->flags |= AHC_NO_BIOS_INIT;
1213 }
1214
1215 /*
1216 * Next create a situation where write combining
1217 * or read prefetching could be initiated by the
1218 * CPU or host bridge. Our device does not support
1219 * either, so look for data corruption and/or flagged
1220 * PCI errors. First pause without causing another
1221 * chip reset.
1222 */
1223 hcntrl &= ~CHIPRST;
1224 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1225 while (ahc_is_paused(ahc) == 0)
1226 ;
1227
1228 /* Clear any PCI errors that occurred before our driver attached. */
1229 status1 = ahc_pci_read_config(ahc->dev_softc,
1230 PCIR_STATUS + 1, /*bytes*/1);
1231 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1232 status1, /*bytes*/1);
1233 ahc_outb(ahc, CLRINT, CLRPARERR);
1234
1235 ahc_outb(ahc, SEQCTL, PERRORDIS);
1236 ahc_outb(ahc, SCBPTR, 0);
1237 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1238 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1239 goto fail;
1240
1241 status1 = ahc_pci_read_config(ahc->dev_softc,
1242 PCIR_STATUS + 1, /*bytes*/1);
1243 if ((status1 & STA) != 0)
1244 goto fail;
1245
1246 error = 0;
1247
1248 fail:
1249 /* Silently clear any latched errors. */
1250 status1 = ahc_pci_read_config(ahc->dev_softc,
1251 PCIR_STATUS + 1, /*bytes*/1);
1252 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1253 status1, /*bytes*/1);
1254 ahc_outb(ahc, CLRINT, CLRPARERR);
1255 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1256 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1257 return (error);
1258 }
1259
1260 /*
1261 * Check the external port logic for a serial eeprom
1262 * and termination/cable detection contrls.
1263 */
1264 static void
1265 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1266 {
1267 struct seeprom_descriptor sd;
1268 struct seeprom_config *sc;
1269 int have_seeprom;
1270 int have_autoterm;
1271
1272 sd.sd_ahc = ahc;
1273 sd.sd_control_offset = SEECTL;
1274 sd.sd_status_offset = SEECTL;
1275 sd.sd_dataout_offset = SEECTL;
1276 sc = ahc->seep_config;
1277
1278 /*
1279 * For some multi-channel devices, the c46 is simply too
1280 * small to work. For the other controller types, we can
1281 * get our information from either SEEPROM type. Set the
1282 * type to start our probe with accordingly.
1283 */
1284 if (ahc->flags & AHC_LARGE_SEEPROM)
1285 sd.sd_chip = C56_66;
1286 else
1287 sd.sd_chip = C46;
1288
1289 sd.sd_MS = SEEMS;
1290 sd.sd_RDY = SEERDY;
1291 sd.sd_CS = SEECS;
1292 sd.sd_CK = SEECK;
1293 sd.sd_DO = SEEDO;
1294 sd.sd_DI = SEEDI;
1295
1296 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1297 if (have_seeprom) {
1298
1299 if (bootverbose)
1300 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1301
1302 for (;;) {
1303 u_int start_addr;
1304
1305 start_addr = 32 * (ahc->channel - 'A');
1306
1307 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1308 start_addr,
1309 sizeof(*sc)/2);
1310
1311 if (have_seeprom)
1312 have_seeprom = ahc_verify_cksum(sc);
1313
1314 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1315 if (bootverbose) {
1316 if (have_seeprom == 0)
1317 printf ("checksum error\n");
1318 else
1319 printf ("done.\n");
1320 }
1321 break;
1322 }
1323 sd.sd_chip = C56_66;
1324 }
1325 ahc_release_seeprom(&sd);
1326
1327 /* Remember the SEEPROM type for later */
1328 if (sd.sd_chip == C56_66)
1329 ahc->flags |= AHC_LARGE_SEEPROM;
1330 }
1331
1332 if (!have_seeprom) {
1333 /*
1334 * Pull scratch ram settings and treat them as
1335 * if they are the contents of an seeprom if
1336 * the 'ADPT' signature is found in SCB2.
1337 * We manually compose the data as 16bit values
1338 * to avoid endian issues.
1339 */
1340 ahc_outb(ahc, SCBPTR, 2);
1341 if (ahc_inb(ahc, SCB_BASE) == 'A'
1342 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1343 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1344 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1345 uint16_t *sc_data;
1346 int i;
1347
1348 sc_data = (uint16_t *)sc;
1349 for (i = 0; i < 32; i++, sc_data++) {
1350 int j;
1351
1352 j = i * 2;
1353 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1354 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1355 }
1356 have_seeprom = ahc_verify_cksum(sc);
1357 if (have_seeprom)
1358 ahc->flags |= AHC_SCB_CONFIG_USED;
1359 }
1360 /*
1361 * Clear any SCB parity errors in case this data and
1362 * its associated parity was not initialized by the BIOS
1363 */
1364 ahc_outb(ahc, CLRINT, CLRPARERR);
1365 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1366 }
1367
1368 if (!have_seeprom) {
1369 if (bootverbose)
1370 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1371 ahc->flags |= AHC_USEDEFAULTS;
1372 free(ahc->seep_config, M_DEVBUF);
1373 ahc->seep_config = NULL;
1374 sc = NULL;
1375 } else {
1376 ahc_parse_pci_eeprom(ahc, sc);
1377 }
1378
1379 /*
1380 * Cards that have the external logic necessary to talk to
1381 * a SEEPROM, are almost certain to have the remaining logic
1382 * necessary for auto-termination control. This assumption
1383 * hasn't failed yet...
1384 */
1385 have_autoterm = have_seeprom;
1386
1387 /*
1388 * Some low-cost chips have SEEPROM and auto-term control built
1389 * in, instead of using a GAL. They can tell us directly
1390 * if the termination logic is enabled.
1391 */
1392 if ((ahc->features & AHC_SPIOCAP) != 0) {
1393 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1394 have_autoterm = FALSE;
1395 }
1396
1397 if (have_autoterm) {
1398 ahc->flags |= AHC_HAS_TERM_LOGIC;
1399 ahc_acquire_seeprom(ahc, &sd);
1400 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1401 ahc_release_seeprom(&sd);
1402 } else if (have_seeprom) {
1403 *sxfrctl1 &= ~STPWEN;
1404 if ((sc->adapter_control & CFSTERM) != 0)
1405 *sxfrctl1 |= STPWEN;
1406 if (bootverbose)
1407 printf("%s: Low byte termination %sabled\n",
1408 ahc_name(ahc),
1409 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1410 }
1411 }
1412
1413 static void
1414 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1415 {
1416 /*
1417 * Put the data we've collected down into SRAM
1418 * where ahc_init will find it.
1419 */
1420 int i;
1421 int max_targ = sc->max_targets & CFMAXTARG;
1422 u_int scsi_conf;
1423 uint16_t discenable;
1424 uint16_t ultraenb;
1425
1426 discenable = 0;
1427 ultraenb = 0;
1428 if ((sc->adapter_control & CFULTRAEN) != 0) {
1429 /*
1430 * Determine if this adapter has a "newstyle"
1431 * SEEPROM format.
1432 */
1433 for (i = 0; i < max_targ; i++) {
1434 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1435 ahc->flags |= AHC_NEWEEPROM_FMT;
1436 break;
1437 }
1438 }
1439 }
1440
1441 for (i = 0; i < max_targ; i++) {
1442 u_int scsirate;
1443 uint16_t target_mask;
1444
1445 target_mask = 0x01 << i;
1446 if (sc->device_flags[i] & CFDISC)
1447 discenable |= target_mask;
1448 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1449 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1450 ultraenb |= target_mask;
1451 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1452 ultraenb |= target_mask;
1453 }
1454 if ((sc->device_flags[i] & CFXFER) == 0x04
1455 && (ultraenb & target_mask) != 0) {
1456 /* Treat 10MHz as a non-ultra speed */
1457 sc->device_flags[i] &= ~CFXFER;
1458 ultraenb &= ~target_mask;
1459 }
1460 if ((ahc->features & AHC_ULTRA2) != 0) {
1461 u_int offset;
1462
1463 if (sc->device_flags[i] & CFSYNCH)
1464 offset = MAX_OFFSET_ULTRA2;
1465 else
1466 offset = 0;
1467 ahc_outb(ahc, TARG_OFFSET + i, offset);
1468
1469 /*
1470 * The ultra enable bits contain the
1471 * high bit of the ultra2 sync rate
1472 * field.
1473 */
1474 scsirate = (sc->device_flags[i] & CFXFER)
1475 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1476 if (sc->device_flags[i] & CFWIDEB)
1477 scsirate |= WIDEXFER;
1478 } else {
1479 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1480 if (sc->device_flags[i] & CFSYNCH)
1481 scsirate |= SOFS;
1482 if (sc->device_flags[i] & CFWIDEB)
1483 scsirate |= WIDEXFER;
1484 }
1485 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1486 }
1487 ahc->our_id = sc->brtime_id & CFSCSIID;
1488
1489 scsi_conf = (ahc->our_id & 0x7);
1490 if (sc->adapter_control & CFSPARITY)
1491 scsi_conf |= ENSPCHK;
1492 if (sc->adapter_control & CFRESETB)
1493 scsi_conf |= RESET_SCSI;
1494
1495 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1496
1497 if (sc->bios_control & CFEXTEND)
1498 ahc->flags |= AHC_EXTENDED_TRANS_A;
1499
1500 if (sc->bios_control & CFBIOSEN)
1501 ahc->flags |= AHC_BIOS_ENABLED;
1502 if (ahc->features & AHC_ULTRA
1503 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1504 /* Should we enable Ultra mode? */
1505 if (!(sc->adapter_control & CFULTRAEN))
1506 /* Treat us as a non-ultra card */
1507 ultraenb = 0;
1508 }
1509
1510 if (sc->signature == CFSIGNATURE
1511 || sc->signature == CFSIGNATURE2) {
1512 uint32_t devconfig;
1513
1514 /* Honor the STPWLEVEL settings */
1515 devconfig = ahc_pci_read_config(ahc->dev_softc,
1516 DEVCONFIG, /*bytes*/4);
1517 devconfig &= ~STPWLEVEL;
1518 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1519 devconfig |= STPWLEVEL;
1520 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1521 devconfig, /*bytes*/4);
1522 }
1523 /* Set SCSICONF info */
1524 ahc_outb(ahc, SCSICONF, scsi_conf);
1525 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1526 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1527 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1528 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1529 }
1530
1531 static void
1532 configure_termination(struct ahc_softc *ahc,
1533 struct seeprom_descriptor *sd,
1534 u_int adapter_control,
1535 u_int *sxfrctl1)
1536 {
1537 uint8_t brddat;
1538
1539 brddat = 0;
1540
1541 /*
1542 * Update the settings in sxfrctl1 to match the
1543 * termination settings
1544 */
1545 *sxfrctl1 = 0;
1546
1547 /*
1548 * SEECS must be on for the GALS to latch
1549 * the data properly. Be sure to leave MS
1550 * on or we will release the seeprom.
1551 */
1552 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1553 if ((adapter_control & CFAUTOTERM) != 0
1554 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1555 int internal50_present;
1556 int internal68_present;
1557 int externalcable_present;
1558 int eeprom_present;
1559 int enableSEC_low;
1560 int enableSEC_high;
1561 int enablePRI_low;
1562 int enablePRI_high;
1563 int sum;
1564
1565 enableSEC_low = 0;
1566 enableSEC_high = 0;
1567 enablePRI_low = 0;
1568 enablePRI_high = 0;
1569 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1570 ahc_new_term_detect(ahc, &enableSEC_low,
1571 &enableSEC_high,
1572 &enablePRI_low,
1573 &enablePRI_high,
1574 &eeprom_present);
1575 if ((adapter_control & CFSEAUTOTERM) == 0) {
1576 if (bootverbose)
1577 printf("%s: Manual SE Termination\n",
1578 ahc_name(ahc));
1579 enableSEC_low = (adapter_control & CFSELOWTERM);
1580 enableSEC_high =
1581 (adapter_control & CFSEHIGHTERM);
1582 }
1583 if ((adapter_control & CFAUTOTERM) == 0) {
1584 if (bootverbose)
1585 printf("%s: Manual LVD Termination\n",
1586 ahc_name(ahc));
1587 enablePRI_low = (adapter_control & CFSTERM);
1588 enablePRI_high = (adapter_control & CFWSTERM);
1589 }
1590 /* Make the table calculations below happy */
1591 internal50_present = 0;
1592 internal68_present = 1;
1593 externalcable_present = 1;
1594 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1595 aic785X_cable_detect(ahc, &internal50_present,
1596 &externalcable_present,
1597 &eeprom_present);
1598 /* Can never support a wide connector. */
1599 internal68_present = 0;
1600 } else {
1601 aic787X_cable_detect(ahc, &internal50_present,
1602 &internal68_present,
1603 &externalcable_present,
1604 &eeprom_present);
1605 }
1606
1607 if ((ahc->features & AHC_WIDE) == 0)
1608 internal68_present = 0;
1609
1610 if (bootverbose
1611 && (ahc->features & AHC_ULTRA2) == 0) {
1612 printf("%s: internal 50 cable %s present",
1613 ahc_name(ahc),
1614 internal50_present ? "is":"not");
1615
1616 if ((ahc->features & AHC_WIDE) != 0)
1617 printf(", internal 68 cable %s present",
1618 internal68_present ? "is":"not");
1619 printf("\n%s: external cable %s present\n",
1620 ahc_name(ahc),
1621 externalcable_present ? "is":"not");
1622 }
1623 if (bootverbose)
1624 printf("%s: BIOS eeprom %s present\n",
1625 ahc_name(ahc), eeprom_present ? "is" : "not");
1626
1627 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1628 /*
1629 * The 50 pin connector is a separate bus,
1630 * so force it to always be terminated.
1631 * In the future, perform current sensing
1632 * to determine if we are in the middle of
1633 * a properly terminated bus.
1634 */
1635 internal50_present = 0;
1636 }
1637
1638 /*
1639 * Now set the termination based on what
1640 * we found.
1641 * Flash Enable = BRDDAT7
1642 * Secondary High Term Enable = BRDDAT6
1643 * Secondary Low Term Enable = BRDDAT5 (7890)
1644 * Primary High Term Enable = BRDDAT4 (7890)
1645 */
1646 if ((ahc->features & AHC_ULTRA2) == 0
1647 && (internal50_present != 0)
1648 && (internal68_present != 0)
1649 && (externalcable_present != 0)) {
1650 printf("%s: Illegal cable configuration!!. "
1651 "Only two connectors on the "
1652 "adapter may be used at a "
1653 "time!\n", ahc_name(ahc));
1654
1655 /*
1656 * Pretend there are no cables in the hope
1657 * that having all of the termination on
1658 * gives us a more stable bus.
1659 */
1660 internal50_present = 0;
1661 internal68_present = 0;
1662 externalcable_present = 0;
1663 }
1664
1665 if ((ahc->features & AHC_WIDE) != 0
1666 && ((externalcable_present == 0)
1667 || (internal68_present == 0)
1668 || (enableSEC_high != 0))) {
1669 brddat |= BRDDAT6;
1670 if (bootverbose) {
1671 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1672 printf("%s: 68 pin termination "
1673 "Enabled\n", ahc_name(ahc));
1674 else
1675 printf("%s: %sHigh byte termination "
1676 "Enabled\n", ahc_name(ahc),
1677 enableSEC_high ? "Secondary "
1678 : "");
1679 }
1680 }
1681
1682 sum = internal50_present + internal68_present
1683 + externalcable_present;
1684 if (sum < 2 || (enableSEC_low != 0)) {
1685 if ((ahc->features & AHC_ULTRA2) != 0)
1686 brddat |= BRDDAT5;
1687 else
1688 *sxfrctl1 |= STPWEN;
1689 if (bootverbose) {
1690 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1691 printf("%s: 50 pin termination "
1692 "Enabled\n", ahc_name(ahc));
1693 else
1694 printf("%s: %sLow byte termination "
1695 "Enabled\n", ahc_name(ahc),
1696 enableSEC_low ? "Secondary "
1697 : "");
1698 }
1699 }
1700
1701 if (enablePRI_low != 0) {
1702 *sxfrctl1 |= STPWEN;
1703 if (bootverbose)
1704 printf("%s: Primary Low Byte termination "
1705 "Enabled\n", ahc_name(ahc));
1706 }
1707
1708 /*
1709 * Setup STPWEN before setting up the rest of
1710 * the termination per the tech note on the U160 cards.
1711 */
1712 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1713
1714 if (enablePRI_high != 0) {
1715 brddat |= BRDDAT4;
1716 if (bootverbose)
1717 printf("%s: Primary High Byte "
1718 "termination Enabled\n",
1719 ahc_name(ahc));
1720 }
1721
1722 write_brdctl(ahc, brddat);
1723
1724 } else {
1725 if ((adapter_control & CFSTERM) != 0) {
1726 *sxfrctl1 |= STPWEN;
1727
1728 if (bootverbose)
1729 printf("%s: %sLow byte termination Enabled\n",
1730 ahc_name(ahc),
1731 (ahc->features & AHC_ULTRA2) ? "Primary "
1732 : "");
1733 }
1734
1735 if ((adapter_control & CFWSTERM) != 0
1736 && (ahc->features & AHC_WIDE) != 0) {
1737 brddat |= BRDDAT6;
1738 if (bootverbose)
1739 printf("%s: %sHigh byte termination Enabled\n",
1740 ahc_name(ahc),
1741 (ahc->features & AHC_ULTRA2)
1742 ? "Secondary " : "");
1743 }
1744
1745 /*
1746 * Setup STPWEN before setting up the rest of
1747 * the termination per the tech note on the U160 cards.
1748 */
1749 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1750
1751 if ((ahc->features & AHC_WIDE) != 0)
1752 write_brdctl(ahc, brddat);
1753 }
1754 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1755 }
1756
1757 static void
1758 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1759 int *enableSEC_high, int *enablePRI_low,
1760 int *enablePRI_high, int *eeprom_present)
1761 {
1762 uint8_t brdctl;
1763
1764 /*
1765 * BRDDAT7 = Eeprom
1766 * BRDDAT6 = Enable Secondary High Byte termination
1767 * BRDDAT5 = Enable Secondary Low Byte termination
1768 * BRDDAT4 = Enable Primary high byte termination
1769 * BRDDAT3 = Enable Primary low byte termination
1770 */
1771 brdctl = read_brdctl(ahc);
1772 *eeprom_present = brdctl & BRDDAT7;
1773 *enableSEC_high = (brdctl & BRDDAT6);
1774 *enableSEC_low = (brdctl & BRDDAT5);
1775 *enablePRI_high = (brdctl & BRDDAT4);
1776 *enablePRI_low = (brdctl & BRDDAT3);
1777 }
1778
1779 static void
1780 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1781 int *internal68_present, int *externalcable_present,
1782 int *eeprom_present)
1783 {
1784 uint8_t brdctl;
1785
1786 /*
1787 * First read the status of our cables.
1788 * Set the rom bank to 0 since the
1789 * bank setting serves as a multiplexor
1790 * for the cable detection logic.
1791 * BRDDAT5 controls the bank switch.
1792 */
1793 write_brdctl(ahc, 0);
1794
1795 /*
1796 * Now read the state of the internal
1797 * connectors. BRDDAT6 is INT50 and
1798 * BRDDAT7 is INT68.
1799 */
1800 brdctl = read_brdctl(ahc);
1801 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1802 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1803
1804 /*
1805 * Set the rom bank to 1 and determine
1806 * the other signals.
1807 */
1808 write_brdctl(ahc, BRDDAT5);
1809
1810 /*
1811 * Now read the state of the external
1812 * connectors. BRDDAT6 is EXT68 and
1813 * BRDDAT7 is EPROMPS.
1814 */
1815 brdctl = read_brdctl(ahc);
1816 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1817 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1818 }
1819
1820 static void
1821 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1822 int *externalcable_present, int *eeprom_present)
1823 {
1824 uint8_t brdctl;
1825 uint8_t spiocap;
1826
1827 spiocap = ahc_inb(ahc, SPIOCAP);
1828 spiocap &= ~SOFTCMDEN;
1829 spiocap |= EXT_BRDCTL;
1830 ahc_outb(ahc, SPIOCAP, spiocap);
1831 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1832 ahc_flush_device_writes(ahc);
1833 ahc_delay(500);
1834 ahc_outb(ahc, BRDCTL, 0);
1835 ahc_flush_device_writes(ahc);
1836 ahc_delay(500);
1837 brdctl = ahc_inb(ahc, BRDCTL);
1838 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1839 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1840 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1841 }
1842
1843 int
1844 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1845 {
1846 int wait;
1847
1848 if ((ahc->features & AHC_SPIOCAP) != 0
1849 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1850 return (0);
1851
1852 /*
1853 * Request access of the memory port. When access is
1854 * granted, SEERDY will go high. We use a 1 second
1855 * timeout which should be near 1 second more than
1856 * is needed. Reason: after the chip reset, there
1857 * should be no contention.
1858 */
1859 SEEPROM_OUTB(sd, sd->sd_MS);
1860 wait = 1000; /* 1 second timeout in msec */
1861 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1862 ahc_delay(1000); /* delay 1 msec */
1863 }
1864 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1865 SEEPROM_OUTB(sd, 0);
1866 return (0);
1867 }
1868 return(1);
1869 }
1870
1871 void
1872 ahc_release_seeprom(struct seeprom_descriptor *sd)
1873 {
1874 /* Release access to the memory port and the serial EEPROM. */
1875 SEEPROM_OUTB(sd, 0);
1876 }
1877
1878 static void
1879 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1880 {
1881 uint8_t brdctl;
1882
1883 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1884 brdctl = BRDSTB;
1885 if (ahc->channel == 'B')
1886 brdctl |= BRDCS;
1887 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1888 brdctl = 0;
1889 } else {
1890 brdctl = BRDSTB|BRDCS;
1891 }
1892 ahc_outb(ahc, BRDCTL, brdctl);
1893 ahc_flush_device_writes(ahc);
1894 brdctl |= value;
1895 ahc_outb(ahc, BRDCTL, brdctl);
1896 ahc_flush_device_writes(ahc);
1897 if ((ahc->features & AHC_ULTRA2) != 0)
1898 brdctl |= BRDSTB_ULTRA2;
1899 else
1900 brdctl &= ~BRDSTB;
1901 ahc_outb(ahc, BRDCTL, brdctl);
1902 ahc_flush_device_writes(ahc);
1903 if ((ahc->features & AHC_ULTRA2) != 0)
1904 brdctl = 0;
1905 else
1906 brdctl &= ~BRDCS;
1907 ahc_outb(ahc, BRDCTL, brdctl);
1908 }
1909
1910 static uint8_t
1911 read_brdctl(struct ahc_softc *ahc)
1912 {
1913 uint8_t brdctl;
1914 uint8_t value;
1915
1916 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1917 brdctl = BRDRW;
1918 if (ahc->channel == 'B')
1919 brdctl |= BRDCS;
1920 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1921 brdctl = BRDRW_ULTRA2;
1922 } else {
1923 brdctl = BRDRW|BRDCS;
1924 }
1925 ahc_outb(ahc, BRDCTL, brdctl);
1926 ahc_flush_device_writes(ahc);
1927 value = ahc_inb(ahc, BRDCTL);
1928 ahc_outb(ahc, BRDCTL, 0);
1929 return (value);
1930 }
1931
1932 static void
1933 ahc_pci_intr(struct ahc_softc *ahc)
1934 {
1935 u_int error;
1936 u_int status1;
1937
1938 error = ahc_inb(ahc, ERROR);
1939 if ((error & PCIERRSTAT) == 0)
1940 return;
1941
1942 status1 = ahc_pci_read_config(ahc->dev_softc,
1943 PCIR_STATUS + 1, /*bytes*/1);
1944
1945 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1946 ahc_name(ahc),
1947 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1948
1949 if (status1 & DPE) {
1950 ahc->pci_target_perr_count++;
1951 printf("%s: Data Parity Error Detected during address "
1952 "or write data phase\n", ahc_name(ahc));
1953 }
1954 if (status1 & SSE) {
1955 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1956 }
1957 if (status1 & RMA) {
1958 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1959 }
1960 if (status1 & RTA) {
1961 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1962 }
1963 if (status1 & STA) {
1964 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1965 }
1966 if (status1 & DPR) {
1967 printf("%s: Data Parity Error has been reported via PERR#\n",
1968 ahc_name(ahc));
1969 }
1970
1971 /* Clear latched errors. */
1972 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1973 status1, /*bytes*/1);
1974
1975 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1976 printf("%s: Latched PCIERR interrupt with "
1977 "no status bits set\n", ahc_name(ahc));
1978 } else {
1979 ahc_outb(ahc, CLRINT, CLRPARERR);
1980 }
1981
1982 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
1983 printf(
1984 "%s: WARNING WARNING WARNING WARNING\n"
1985 "%s: Too many PCI parity errors observed as a target.\n"
1986 "%s: Some device on this bus is generating bad parity.\n"
1987 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
1988 "%s: PCI parity error checking has been disabled.\n"
1989 "%s: WARNING WARNING WARNING WARNING\n",
1990 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
1991 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
1992 ahc->seqctl |= FAILDIS;
1993 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1994 }
1995 ahc_unpause(ahc);
1996 }
1997
1998 static int
1999 ahc_pci_chip_init(struct ahc_softc *ahc)
2000 {
2001 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2002 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2003 if ((ahc->features & AHC_DT) != 0) {
2004 u_int sfunct;
2005
2006 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2007 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2008 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2009 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2010 ahc_outb(ahc, SFUNCT, sfunct);
2011 ahc_outb(ahc, CRCCONTROL1,
2012 ahc->bus_softc.pci_softc.crccontrol1);
2013 }
2014 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2015 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2016
2017 if ((ahc->features & AHC_ULTRA2) != 0)
2018 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2019
2020 return (ahc_chip_init(ahc));
2021 }
2022
2023 #ifdef CONFIG_PM
2024 void
2025 ahc_pci_resume(struct ahc_softc *ahc)
2026 {
2027 /*
2028 * We assume that the OS has restored our register
2029 * mappings, etc. Just update the config space registers
2030 * that the OS doesn't know about and rely on our chip
2031 * reset handler to handle the rest.
2032 */
2033 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
2034 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2035 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2036 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2037 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2038 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1);
2039 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2040 struct seeprom_descriptor sd;
2041 u_int sxfrctl1;
2042
2043 sd.sd_ahc = ahc;
2044 sd.sd_control_offset = SEECTL;
2045 sd.sd_status_offset = SEECTL;
2046 sd.sd_dataout_offset = SEECTL;
2047
2048 ahc_acquire_seeprom(ahc, &sd);
2049 configure_termination(ahc, &sd,
2050 ahc->seep_config->adapter_control,
2051 &sxfrctl1);
2052 ahc_release_seeprom(&sd);
2053 }
2054 }
2055 #endif
2056
2057 static int
2058 ahc_aic785X_setup(struct ahc_softc *ahc)
2059 {
2060 ahc_dev_softc_t pci;
2061 uint8_t rev;
2062
2063 pci = ahc->dev_softc;
2064 ahc->channel = 'A';
2065 ahc->chip = AHC_AIC7850;
2066 ahc->features = AHC_AIC7850_FE;
2067 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2068 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2069 if (rev >= 1)
2070 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2071 ahc->instruction_ram_size = 512;
2072 return (0);
2073 }
2074
2075 static int
2076 ahc_aic7860_setup(struct ahc_softc *ahc)
2077 {
2078 ahc_dev_softc_t pci;
2079 uint8_t rev;
2080
2081 pci = ahc->dev_softc;
2082 ahc->channel = 'A';
2083 ahc->chip = AHC_AIC7860;
2084 ahc->features = AHC_AIC7860_FE;
2085 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2086 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2087 if (rev >= 1)
2088 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2089 ahc->instruction_ram_size = 512;
2090 return (0);
2091 }
2092
2093 static int
2094 ahc_apa1480_setup(struct ahc_softc *ahc)
2095 {
2096 int error;
2097
2098 error = ahc_aic7860_setup(ahc);
2099 if (error != 0)
2100 return (error);
2101 ahc->features |= AHC_REMOVABLE;
2102 return (0);
2103 }
2104
2105 static int
2106 ahc_aic7870_setup(struct ahc_softc *ahc)
2107 {
2108
2109 ahc->channel = 'A';
2110 ahc->chip = AHC_AIC7870;
2111 ahc->features = AHC_AIC7870_FE;
2112 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2113 ahc->instruction_ram_size = 512;
2114 return (0);
2115 }
2116
2117 static int
2118 ahc_aic7870h_setup(struct ahc_softc *ahc)
2119 {
2120 int error = ahc_aic7870_setup(ahc);
2121
2122 ahc->features |= AHC_HVD;
2123
2124 return error;
2125 }
2126
2127 static int
2128 ahc_aha394X_setup(struct ahc_softc *ahc)
2129 {
2130 int error;
2131
2132 error = ahc_aic7870_setup(ahc);
2133 if (error == 0)
2134 error = ahc_aha394XX_setup(ahc);
2135 return (error);
2136 }
2137
2138 static int
2139 ahc_aha394Xh_setup(struct ahc_softc *ahc)
2140 {
2141 int error = ahc_aha394X_setup(ahc);
2142
2143 ahc->features |= AHC_HVD;
2144
2145 return error;
2146 }
2147
2148 static int
2149 ahc_aha398X_setup(struct ahc_softc *ahc)
2150 {
2151 int error;
2152
2153 error = ahc_aic7870_setup(ahc);
2154 if (error == 0)
2155 error = ahc_aha398XX_setup(ahc);
2156 return (error);
2157 }
2158
2159 static int
2160 ahc_aha494X_setup(struct ahc_softc *ahc)
2161 {
2162 int error;
2163
2164 error = ahc_aic7870_setup(ahc);
2165 if (error == 0)
2166 error = ahc_aha494XX_setup(ahc);
2167 return (error);
2168 }
2169
2170 static int
2171 ahc_aha494Xh_setup(struct ahc_softc *ahc)
2172 {
2173 int error = ahc_aha494X_setup(ahc);
2174
2175 ahc->features |= AHC_HVD;
2176
2177 return error;
2178 }
2179
2180 static int
2181 ahc_aic7880_setup(struct ahc_softc *ahc)
2182 {
2183 ahc_dev_softc_t pci;
2184 uint8_t rev;
2185
2186 pci = ahc->dev_softc;
2187 ahc->channel = 'A';
2188 ahc->chip = AHC_AIC7880;
2189 ahc->features = AHC_AIC7880_FE;
2190 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2191 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2192 if (rev >= 1) {
2193 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2194 } else {
2195 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2196 }
2197 ahc->instruction_ram_size = 512;
2198 return (0);
2199 }
2200
2201 static int
2202 ahc_aic7880h_setup(struct ahc_softc *ahc)
2203 {
2204 int error = ahc_aic7880_setup(ahc);
2205
2206 ahc->features |= AHC_HVD;
2207
2208 return error;
2209 }
2210
2211
2212 static int
2213 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2214 {
2215
2216 ahc->flags |= AHC_INT50_SPEEDFLEX;
2217 return (ahc_aic7880_setup(ahc));
2218 }
2219
2220 static int
2221 ahc_aha394XU_setup(struct ahc_softc *ahc)
2222 {
2223 int error;
2224
2225 error = ahc_aic7880_setup(ahc);
2226 if (error == 0)
2227 error = ahc_aha394XX_setup(ahc);
2228 return (error);
2229 }
2230
2231 static int
2232 ahc_aha394XUh_setup(struct ahc_softc *ahc)
2233 {
2234 int error = ahc_aha394XU_setup(ahc);
2235
2236 ahc->features |= AHC_HVD;
2237
2238 return error;
2239 }
2240
2241 static int
2242 ahc_aha398XU_setup(struct ahc_softc *ahc)
2243 {
2244 int error;
2245
2246 error = ahc_aic7880_setup(ahc);
2247 if (error == 0)
2248 error = ahc_aha398XX_setup(ahc);
2249 return (error);
2250 }
2251
2252 static int
2253 ahc_aic7890_setup(struct ahc_softc *ahc)
2254 {
2255 ahc_dev_softc_t pci;
2256 uint8_t rev;
2257
2258 pci = ahc->dev_softc;
2259 ahc->channel = 'A';
2260 ahc->chip = AHC_AIC7890;
2261 ahc->features = AHC_AIC7890_FE;
2262 ahc->flags |= AHC_NEWEEPROM_FMT;
2263 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2264 if (rev == 0)
2265 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2266 ahc->instruction_ram_size = 768;
2267 return (0);
2268 }
2269
2270 static int
2271 ahc_aic7892_setup(struct ahc_softc *ahc)
2272 {
2273
2274 ahc->channel = 'A';
2275 ahc->chip = AHC_AIC7892;
2276 ahc->features = AHC_AIC7892_FE;
2277 ahc->flags |= AHC_NEWEEPROM_FMT;
2278 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2279 ahc->instruction_ram_size = 1024;
2280 return (0);
2281 }
2282
2283 static int
2284 ahc_aic7895_setup(struct ahc_softc *ahc)
2285 {
2286 ahc_dev_softc_t pci;
2287 uint8_t rev;
2288
2289 pci = ahc->dev_softc;
2290 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2291 /*
2292 * The 'C' revision of the aic7895 has a few additional features.
2293 */
2294 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2295 if (rev >= 4) {
2296 ahc->chip = AHC_AIC7895C;
2297 ahc->features = AHC_AIC7895C_FE;
2298 } else {
2299 u_int command;
2300
2301 ahc->chip = AHC_AIC7895;
2302 ahc->features = AHC_AIC7895_FE;
2303
2304 /*
2305 * The BIOS disables the use of MWI transactions
2306 * since it does not have the MWI bug work around
2307 * we have. Disabling MWI reduces performance, so
2308 * turn it on again.
2309 */
2310 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2311 command |= PCIM_CMD_MWRICEN;
2312 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2313 ahc->bugs |= AHC_PCI_MWI_BUG;
2314 }
2315 /*
2316 * XXX Does CACHETHEN really not work??? What about PCI retry?
2317 * on C level chips. Need to test, but for now, play it safe.
2318 */
2319 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2320 | AHC_CACHETHEN_BUG;
2321
2322 #if 0
2323 uint32_t devconfig;
2324
2325 /*
2326 * Cachesize must also be zero due to stray DAC
2327 * problem when sitting behind some bridges.
2328 */
2329 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2330 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2331 devconfig |= MRDCEN;
2332 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2333 #endif
2334 ahc->flags |= AHC_NEWEEPROM_FMT;
2335 ahc->instruction_ram_size = 512;
2336 return (0);
2337 }
2338
2339 static int
2340 ahc_aic7895h_setup(struct ahc_softc *ahc)
2341 {
2342 int error = ahc_aic7895_setup(ahc);
2343
2344 ahc->features |= AHC_HVD;
2345
2346 return error;
2347 }
2348
2349 static int
2350 ahc_aic7896_setup(struct ahc_softc *ahc)
2351 {
2352 ahc_dev_softc_t pci;
2353
2354 pci = ahc->dev_softc;
2355 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2356 ahc->chip = AHC_AIC7896;
2357 ahc->features = AHC_AIC7896_FE;
2358 ahc->flags |= AHC_NEWEEPROM_FMT;
2359 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2360 ahc->instruction_ram_size = 768;
2361 return (0);
2362 }
2363
2364 static int
2365 ahc_aic7899_setup(struct ahc_softc *ahc)
2366 {
2367 ahc_dev_softc_t pci;
2368
2369 pci = ahc->dev_softc;
2370 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2371 ahc->chip = AHC_AIC7899;
2372 ahc->features = AHC_AIC7899_FE;
2373 ahc->flags |= AHC_NEWEEPROM_FMT;
2374 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2375 ahc->instruction_ram_size = 1024;
2376 return (0);
2377 }
2378
2379 static int
2380 ahc_aha29160C_setup(struct ahc_softc *ahc)
2381 {
2382 int error;
2383
2384 error = ahc_aic7899_setup(ahc);
2385 if (error != 0)
2386 return (error);
2387 ahc->features |= AHC_REMOVABLE;
2388 return (0);
2389 }
2390
2391 static int
2392 ahc_raid_setup(struct ahc_softc *ahc)
2393 {
2394 printf("RAID functionality unsupported\n");
2395 return (ENXIO);
2396 }
2397
2398 static int
2399 ahc_aha394XX_setup(struct ahc_softc *ahc)
2400 {
2401 ahc_dev_softc_t pci;
2402
2403 pci = ahc->dev_softc;
2404 switch (ahc_get_pci_slot(pci)) {
2405 case AHC_394X_SLOT_CHANNEL_A:
2406 ahc->channel = 'A';
2407 break;
2408 case AHC_394X_SLOT_CHANNEL_B:
2409 ahc->channel = 'B';
2410 break;
2411 default:
2412 printf("adapter at unexpected slot %d\n"
2413 "unable to map to a channel\n",
2414 ahc_get_pci_slot(pci));
2415 ahc->channel = 'A';
2416 }
2417 return (0);
2418 }
2419
2420 static int
2421 ahc_aha398XX_setup(struct ahc_softc *ahc)
2422 {
2423 ahc_dev_softc_t pci;
2424
2425 pci = ahc->dev_softc;
2426 switch (ahc_get_pci_slot(pci)) {
2427 case AHC_398X_SLOT_CHANNEL_A:
2428 ahc->channel = 'A';
2429 break;
2430 case AHC_398X_SLOT_CHANNEL_B:
2431 ahc->channel = 'B';
2432 break;
2433 case AHC_398X_SLOT_CHANNEL_C:
2434 ahc->channel = 'C';
2435 break;
2436 default:
2437 printf("adapter at unexpected slot %d\n"
2438 "unable to map to a channel\n",
2439 ahc_get_pci_slot(pci));
2440 ahc->channel = 'A';
2441 break;
2442 }
2443 ahc->flags |= AHC_LARGE_SEEPROM;
2444 return (0);
2445 }
2446
2447 static int
2448 ahc_aha494XX_setup(struct ahc_softc *ahc)
2449 {
2450 ahc_dev_softc_t pci;
2451
2452 pci = ahc->dev_softc;
2453 switch (ahc_get_pci_slot(pci)) {
2454 case AHC_494X_SLOT_CHANNEL_A:
2455 ahc->channel = 'A';
2456 break;
2457 case AHC_494X_SLOT_CHANNEL_B:
2458 ahc->channel = 'B';
2459 break;
2460 case AHC_494X_SLOT_CHANNEL_C:
2461 ahc->channel = 'C';
2462 break;
2463 case AHC_494X_SLOT_CHANNEL_D:
2464 ahc->channel = 'D';
2465 break;
2466 default:
2467 printf("adapter at unexpected slot %d\n"
2468 "unable to map to a channel\n",
2469 ahc_get_pci_slot(pci));
2470 ahc->channel = 'A';
2471 }
2472 ahc->flags |= AHC_LARGE_SEEPROM;
2473 return (0);
2474 }
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