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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / pci / hotplug / pciehp_hpc.c
blob698975a6a21c712b46654cba06b71b641612a143
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61 } __attribute__ ((packed));
62
63 /* offsets to the controller registers based on the above structure layout */
64 enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79 };
80
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82 {
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85 }
86
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88 {
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91 }
92
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94 {
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97 }
98
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100 {
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103 }
104
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
110
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
119
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
124
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128
129 /* Link Width Encoding */
130 #define LNK_X1 0x01
131 #define LNK_X2 0x02
132 #define LNK_X4 0x04
133 #define LNK_X8 0x08
134 #define LNK_X12 0x0C
135 #define LNK_X16 0x10
136 #define LNK_X32 0x20
137
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
144
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
156
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
168
169 /* Attention indicator and Power indicator states */
170 #define LED_ON 0x01
171 #define LED_BLINK 0x10
172 #define LED_OFF 0x11
173
174 /* Power Control Command */
175 #define POWER_ON 0
176 #define POWER_OFF 0x0400
177
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
181
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
192
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
195
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
198 {
199 struct controller *ctrl = (struct controller *)data;
200
201 /* Poll for interrupt events. regs == NULL => polling */
202 pcie_isr(0, ctrl);
203
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
207
208 start_int_poll_timer(ctrl, pciehp_poll_time);
209 }
210
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
213 {
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
216 sec = 2;
217
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
222 }
223
224 static inline int pcie_wait_cmd(struct controller *ctrl)
225 {
226 int retval = 0;
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
229 int rc;
230
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
233 if (!rc)
234 dbg("Command not completed in 1000 msec\n");
235 else if (rc < 0) {
236 retval = -EINTR;
237 info("Command was interrupted by a signal\n");
238 }
239
240 return retval;
241 }
242
243 /**
244 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
248 */
249 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
250 {
251 struct controller *ctrl = slot->ctrl;
252 int retval = 0;
253 u16 slot_status;
254 u16 slot_ctrl;
255 unsigned long flags;
256
257 mutex_lock(&ctrl->ctrl_lock);
258
259 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
260 if (retval) {
261 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
262 goto out;
263 }
264
265 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
266 /* After 1 sec and CMD_COMPLETED still not set, just
267 proceed forward to issue the next command according
268 to spec. Just print out the error message */
269 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
270 __FUNCTION__);
271 }
272
273 spin_lock_irqsave(&ctrl->lock, flags);
274 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
275 if (retval) {
276 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
277 goto out_spin_unlock;
278 }
279
280 slot_ctrl &= ~mask;
281 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
282
283 ctrl->cmd_busy = 1;
284 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
285 if (retval)
286 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
287
288 out_spin_unlock:
289 spin_unlock_irqrestore(&ctrl->lock, flags);
290
291 /*
292 * Wait for command completion.
293 */
294 if (!retval)
295 retval = pcie_wait_cmd(ctrl);
296 out:
297 mutex_unlock(&ctrl->ctrl_lock);
298 return retval;
299 }
300
301 static int hpc_check_lnk_status(struct controller *ctrl)
302 {
303 u16 lnk_status;
304 int retval = 0;
305
306 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
307 if (retval) {
308 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
309 return retval;
310 }
311
312 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
313 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
314 !(lnk_status & NEG_LINK_WD)) {
315 err("%s : Link Training Error occurs \n", __FUNCTION__);
316 retval = -1;
317 return retval;
318 }
319
320 return retval;
321 }
322
323 static int hpc_get_attention_status(struct slot *slot, u8 *status)
324 {
325 struct controller *ctrl = slot->ctrl;
326 u16 slot_ctrl;
327 u8 atten_led_state;
328 int retval = 0;
329
330 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
331 if (retval) {
332 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
333 return retval;
334 }
335
336 dbg("%s: SLOTCTRL %x, value read %x\n",
337 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
338
339 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
340
341 switch (atten_led_state) {
342 case 0:
343 *status = 0xFF; /* Reserved */
344 break;
345 case 1:
346 *status = 1; /* On */
347 break;
348 case 2:
349 *status = 2; /* Blink */
350 break;
351 case 3:
352 *status = 0; /* Off */
353 break;
354 default:
355 *status = 0xFF;
356 break;
357 }
358
359 return 0;
360 }
361
362 static int hpc_get_power_status(struct slot *slot, u8 *status)
363 {
364 struct controller *ctrl = slot->ctrl;
365 u16 slot_ctrl;
366 u8 pwr_state;
367 int retval = 0;
368
369 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
370 if (retval) {
371 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
372 return retval;
373 }
374 dbg("%s: SLOTCTRL %x value read %x\n",
375 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
376
377 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
378
379 switch (pwr_state) {
380 case 0:
381 *status = 1;
382 break;
383 case 1:
384 *status = 0;
385 break;
386 default:
387 *status = 0xFF;
388 break;
389 }
390
391 return retval;
392 }
393
394 static int hpc_get_latch_status(struct slot *slot, u8 *status)
395 {
396 struct controller *ctrl = slot->ctrl;
397 u16 slot_status;
398 int retval = 0;
399
400 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
401 if (retval) {
402 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
403 return retval;
404 }
405
406 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
407
408 return 0;
409 }
410
411 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
412 {
413 struct controller *ctrl = slot->ctrl;
414 u16 slot_status;
415 u8 card_state;
416 int retval = 0;
417
418 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
419 if (retval) {
420 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
421 return retval;
422 }
423 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
424 *status = (card_state == 1) ? 1 : 0;
425
426 return 0;
427 }
428
429 static int hpc_query_power_fault(struct slot *slot)
430 {
431 struct controller *ctrl = slot->ctrl;
432 u16 slot_status;
433 u8 pwr_fault;
434 int retval = 0;
435
436 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
437 if (retval) {
438 err("%s: Cannot check for power fault\n", __FUNCTION__);
439 return retval;
440 }
441 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
442
443 return pwr_fault;
444 }
445
446 static int hpc_get_emi_status(struct slot *slot, u8 *status)
447 {
448 struct controller *ctrl = slot->ctrl;
449 u16 slot_status;
450 int retval = 0;
451
452 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
453 if (retval) {
454 err("%s : Cannot check EMI status\n", __FUNCTION__);
455 return retval;
456 }
457 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
458
459 return retval;
460 }
461
462 static int hpc_toggle_emi(struct slot *slot)
463 {
464 u16 slot_cmd;
465 u16 cmd_mask;
466 int rc;
467
468 slot_cmd = EMI_CTRL;
469 cmd_mask = EMI_CTRL;
470 if (!pciehp_poll_mode) {
471 slot_cmd = slot_cmd | HP_INTR_ENABLE;
472 cmd_mask = cmd_mask | HP_INTR_ENABLE;
473 }
474
475 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
476 slot->last_emi_toggle = get_seconds();
477
478 return rc;
479 }
480
481 static int hpc_set_attention_status(struct slot *slot, u8 value)
482 {
483 struct controller *ctrl = slot->ctrl;
484 u16 slot_cmd;
485 u16 cmd_mask;
486 int rc;
487
488 cmd_mask = ATTN_LED_CTRL;
489 switch (value) {
490 case 0 : /* turn off */
491 slot_cmd = 0x00C0;
492 break;
493 case 1: /* turn on */
494 slot_cmd = 0x0040;
495 break;
496 case 2: /* turn blink */
497 slot_cmd = 0x0080;
498 break;
499 default:
500 return -1;
501 }
502 if (!pciehp_poll_mode) {
503 slot_cmd = slot_cmd | HP_INTR_ENABLE;
504 cmd_mask = cmd_mask | HP_INTR_ENABLE;
505 }
506
507 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
508 dbg("%s: SLOTCTRL %x write cmd %x\n",
509 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
510
511 return rc;
512 }
513
514 static void hpc_set_green_led_on(struct slot *slot)
515 {
516 struct controller *ctrl = slot->ctrl;
517 u16 slot_cmd;
518 u16 cmd_mask;
519
520 slot_cmd = 0x0100;
521 cmd_mask = PWR_LED_CTRL;
522 if (!pciehp_poll_mode) {
523 slot_cmd = slot_cmd | HP_INTR_ENABLE;
524 cmd_mask = cmd_mask | HP_INTR_ENABLE;
525 }
526
527 pcie_write_cmd(slot, slot_cmd, cmd_mask);
528
529 dbg("%s: SLOTCTRL %x write cmd %x\n",
530 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
531 }
532
533 static void hpc_set_green_led_off(struct slot *slot)
534 {
535 struct controller *ctrl = slot->ctrl;
536 u16 slot_cmd;
537 u16 cmd_mask;
538
539 slot_cmd = 0x0300;
540 cmd_mask = PWR_LED_CTRL;
541 if (!pciehp_poll_mode) {
542 slot_cmd = slot_cmd | HP_INTR_ENABLE;
543 cmd_mask = cmd_mask | HP_INTR_ENABLE;
544 }
545
546 pcie_write_cmd(slot, slot_cmd, cmd_mask);
547 dbg("%s: SLOTCTRL %x write cmd %x\n",
548 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
549 }
550
551 static void hpc_set_green_led_blink(struct slot *slot)
552 {
553 struct controller *ctrl = slot->ctrl;
554 u16 slot_cmd;
555 u16 cmd_mask;
556
557 slot_cmd = 0x0200;
558 cmd_mask = PWR_LED_CTRL;
559 if (!pciehp_poll_mode) {
560 slot_cmd = slot_cmd | HP_INTR_ENABLE;
561 cmd_mask = cmd_mask | HP_INTR_ENABLE;
562 }
563
564 pcie_write_cmd(slot, slot_cmd, cmd_mask);
565
566 dbg("%s: SLOTCTRL %x write cmd %x\n",
567 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
568 }
569
570 static void hpc_release_ctlr(struct controller *ctrl)
571 {
572 if (pciehp_poll_mode)
573 del_timer(&ctrl->poll_timer);
574 else
575 free_irq(ctrl->pci_dev->irq, ctrl);
576
577 /*
578 * If this is the last controller to be released, destroy the
579 * pciehp work queue
580 */
581 if (atomic_dec_and_test(&pciehp_num_controllers))
582 destroy_workqueue(pciehp_wq);
583 }
584
585 static int hpc_power_on_slot(struct slot * slot)
586 {
587 struct controller *ctrl = slot->ctrl;
588 u16 slot_cmd;
589 u16 cmd_mask;
590 u16 slot_status;
591 int retval = 0;
592
593 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
594
595 /* Clear sticky power-fault bit from previous power failures */
596 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
597 if (retval) {
598 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
599 return retval;
600 }
601 slot_status &= PWR_FAULT_DETECTED;
602 if (slot_status) {
603 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
604 if (retval) {
605 err("%s: Cannot write to SLOTSTATUS register\n",
606 __FUNCTION__);
607 return retval;
608 }
609 }
610
611 slot_cmd = POWER_ON;
612 cmd_mask = PWR_CTRL;
613 /* Enable detection that we turned off at slot power-off time */
614 if (!pciehp_poll_mode) {
615 slot_cmd = slot_cmd |
616 PWR_FAULT_DETECT_ENABLE |
617 MRL_DETECT_ENABLE |
618 PRSN_DETECT_ENABLE |
619 HP_INTR_ENABLE;
620 cmd_mask = cmd_mask |
621 PWR_FAULT_DETECT_ENABLE |
622 MRL_DETECT_ENABLE |
623 PRSN_DETECT_ENABLE |
624 HP_INTR_ENABLE;
625 }
626
627 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
628
629 if (retval) {
630 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
631 return -1;
632 }
633 dbg("%s: SLOTCTRL %x write cmd %x\n",
634 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
635
636 return retval;
637 }
638
639 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
640 {
641 struct pci_dev *dev = ctrl->pci_dev;
642 int pos;
643 u32 reg;
644
645 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
646 if (!pos)
647 return 0;
648 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
649 if (reg & PCI_ERR_COR_BAD_DLLP)
650 return 0;
651 reg |= PCI_ERR_COR_BAD_DLLP;
652 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
653 return 1;
654 }
655
656 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
657 {
658 struct pci_dev *dev = ctrl->pci_dev;
659 u32 reg;
660 int pos;
661
662 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
663 if (!pos)
664 return;
665 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
666 if (!(reg & PCI_ERR_COR_BAD_DLLP))
667 return;
668 reg &= ~PCI_ERR_COR_BAD_DLLP;
669 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
670 }
671
672 static int hpc_power_off_slot(struct slot * slot)
673 {
674 struct controller *ctrl = slot->ctrl;
675 u16 slot_cmd;
676 u16 cmd_mask;
677 int retval = 0;
678 int changed;
679
680 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
681
682 /*
683 * Set Bad DLLP Mask bit in Correctable Error Mask
684 * Register. This is the workaround against Bad DLLP error
685 * that sometimes happens during turning power off the slot
686 * which conforms to PCI Express 1.0a spec.
687 */
688 changed = pcie_mask_bad_dllp(ctrl);
689
690 slot_cmd = POWER_OFF;
691 cmd_mask = PWR_CTRL;
692 /*
693 * If we get MRL or presence detect interrupts now, the isr
694 * will notice the sticky power-fault bit too and issue power
695 * indicator change commands. This will lead to an endless loop
696 * of command completions, since the power-fault bit remains on
697 * till the slot is powered on again.
698 */
699 if (!pciehp_poll_mode) {
700 slot_cmd = (slot_cmd &
701 ~PWR_FAULT_DETECT_ENABLE &
702 ~MRL_DETECT_ENABLE &
703 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
704 cmd_mask = cmd_mask |
705 PWR_FAULT_DETECT_ENABLE |
706 MRL_DETECT_ENABLE |
707 PRSN_DETECT_ENABLE |
708 HP_INTR_ENABLE;
709 }
710
711 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
712 if (retval) {
713 err("%s: Write command failed!\n", __FUNCTION__);
714 retval = -1;
715 goto out;
716 }
717 dbg("%s: SLOTCTRL %x write cmd %x\n",
718 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
719
720 /*
721 * After turning power off, we must wait for at least 1 second
722 * before taking any action that relies on power having been
723 * removed from the slot/adapter.
724 */
725 msleep(1000);
726 out:
727 if (changed)
728 pcie_unmask_bad_dllp(ctrl);
729
730 return retval;
731 }
732
733 static irqreturn_t pcie_isr(int irq, void *dev_id)
734 {
735 struct controller *ctrl = (struct controller *)dev_id;
736 u16 slot_status, intr_detect, intr_loc;
737 u16 temp_word;
738 int hp_slot = 0; /* only 1 slot per PCI Express port */
739 int rc = 0;
740 unsigned long flags;
741
742 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
743 if (rc) {
744 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
745 return IRQ_NONE;
746 }
747
748 intr_detect = (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
749 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | CMD_COMPLETED);
750
751 intr_loc = slot_status & intr_detect;
752
753 /* Check to see if it was our interrupt */
754 if ( !intr_loc )
755 return IRQ_NONE;
756
757 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
758 /* Mask Hot-plug Interrupt Enable */
759 if (!pciehp_poll_mode) {
760 spin_lock_irqsave(&ctrl->lock, flags);
761 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
762 if (rc) {
763 err("%s: Cannot read SLOT_CTRL register\n",
764 __FUNCTION__);
765 spin_unlock_irqrestore(&ctrl->lock, flags);
766 return IRQ_NONE;
767 }
768
769 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
770 __FUNCTION__, temp_word);
771 temp_word = (temp_word & ~HP_INTR_ENABLE &
772 ~CMD_CMPL_INTR_ENABLE) | 0x00;
773 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
774 if (rc) {
775 err("%s: Cannot write to SLOTCTRL register\n",
776 __FUNCTION__);
777 spin_unlock_irqrestore(&ctrl->lock, flags);
778 return IRQ_NONE;
779 }
780 spin_unlock_irqrestore(&ctrl->lock, flags);
781
782 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
783 if (rc) {
784 err("%s: Cannot read SLOT_STATUS register\n",
785 __FUNCTION__);
786 return IRQ_NONE;
787 }
788 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
789 __FUNCTION__, slot_status);
790
791 /* Clear command complete interrupt caused by this write */
792 temp_word = 0x1f;
793 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
794 if (rc) {
795 err("%s: Cannot write to SLOTSTATUS register\n",
796 __FUNCTION__);
797 return IRQ_NONE;
798 }
799 }
800
801 if (intr_loc & CMD_COMPLETED) {
802 /*
803 * Command Complete Interrupt Pending
804 */
805 ctrl->cmd_busy = 0;
806 wake_up_interruptible(&ctrl->queue);
807 }
808
809 if (intr_loc & MRL_SENS_CHANGED)
810 pciehp_handle_switch_change(hp_slot, ctrl);
811
812 if (intr_loc & ATTN_BUTTN_PRESSED)
813 pciehp_handle_attention_button(hp_slot, ctrl);
814
815 if (intr_loc & PRSN_DETECT_CHANGED)
816 pciehp_handle_presence_change(hp_slot, ctrl);
817
818 if (intr_loc & PWR_FAULT_DETECTED)
819 pciehp_handle_power_fault(hp_slot, ctrl);
820
821 /* Clear all events after serving them */
822 temp_word = 0x1F;
823 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
824 if (rc) {
825 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
826 return IRQ_NONE;
827 }
828 /* Unmask Hot-plug Interrupt Enable */
829 if (!pciehp_poll_mode) {
830 spin_lock_irqsave(&ctrl->lock, flags);
831 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
832 if (rc) {
833 err("%s: Cannot read SLOTCTRL register\n",
834 __FUNCTION__);
835 spin_unlock_irqrestore(&ctrl->lock, flags);
836 return IRQ_NONE;
837 }
838
839 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
840 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
841
842 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
843 if (rc) {
844 err("%s: Cannot write to SLOTCTRL register\n",
845 __FUNCTION__);
846 spin_unlock_irqrestore(&ctrl->lock, flags);
847 return IRQ_NONE;
848 }
849 spin_unlock_irqrestore(&ctrl->lock, flags);
850
851 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
852 if (rc) {
853 err("%s: Cannot read SLOT_STATUS register\n",
854 __FUNCTION__);
855 return IRQ_NONE;
856 }
857
858 /* Clear command complete interrupt caused by this write */
859 temp_word = 0x1F;
860 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
861 if (rc) {
862 err("%s: Cannot write to SLOTSTATUS failed\n",
863 __FUNCTION__);
864 return IRQ_NONE;
865 }
866 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
867 __FUNCTION__, temp_word);
868 }
869
870 return IRQ_HANDLED;
871 }
872
873 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
874 {
875 struct controller *ctrl = slot->ctrl;
876 enum pcie_link_speed lnk_speed;
877 u32 lnk_cap;
878 int retval = 0;
879
880 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
881 if (retval) {
882 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
883 return retval;
884 }
885
886 switch (lnk_cap & 0x000F) {
887 case 1:
888 lnk_speed = PCIE_2PT5GB;
889 break;
890 default:
891 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
892 break;
893 }
894
895 *value = lnk_speed;
896 dbg("Max link speed = %d\n", lnk_speed);
897
898 return retval;
899 }
900
901 static int hpc_get_max_lnk_width(struct slot *slot,
902 enum pcie_link_width *value)
903 {
904 struct controller *ctrl = slot->ctrl;
905 enum pcie_link_width lnk_wdth;
906 u32 lnk_cap;
907 int retval = 0;
908
909 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
910 if (retval) {
911 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
912 return retval;
913 }
914
915 switch ((lnk_cap & 0x03F0) >> 4){
916 case 0:
917 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
918 break;
919 case 1:
920 lnk_wdth = PCIE_LNK_X1;
921 break;
922 case 2:
923 lnk_wdth = PCIE_LNK_X2;
924 break;
925 case 4:
926 lnk_wdth = PCIE_LNK_X4;
927 break;
928 case 8:
929 lnk_wdth = PCIE_LNK_X8;
930 break;
931 case 12:
932 lnk_wdth = PCIE_LNK_X12;
933 break;
934 case 16:
935 lnk_wdth = PCIE_LNK_X16;
936 break;
937 case 32:
938 lnk_wdth = PCIE_LNK_X32;
939 break;
940 default:
941 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
942 break;
943 }
944
945 *value = lnk_wdth;
946 dbg("Max link width = %d\n", lnk_wdth);
947
948 return retval;
949 }
950
951 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
952 {
953 struct controller *ctrl = slot->ctrl;
954 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
955 int retval = 0;
956 u16 lnk_status;
957
958 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
959 if (retval) {
960 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
961 return retval;
962 }
963
964 switch (lnk_status & 0x0F) {
965 case 1:
966 lnk_speed = PCIE_2PT5GB;
967 break;
968 default:
969 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
970 break;
971 }
972
973 *value = lnk_speed;
974 dbg("Current link speed = %d\n", lnk_speed);
975
976 return retval;
977 }
978
979 static int hpc_get_cur_lnk_width(struct slot *slot,
980 enum pcie_link_width *value)
981 {
982 struct controller *ctrl = slot->ctrl;
983 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
984 int retval = 0;
985 u16 lnk_status;
986
987 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
988 if (retval) {
989 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
990 return retval;
991 }
992
993 switch ((lnk_status & 0x03F0) >> 4){
994 case 0:
995 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
996 break;
997 case 1:
998 lnk_wdth = PCIE_LNK_X1;
999 break;
1000 case 2:
1001 lnk_wdth = PCIE_LNK_X2;
1002 break;
1003 case 4:
1004 lnk_wdth = PCIE_LNK_X4;
1005 break;
1006 case 8:
1007 lnk_wdth = PCIE_LNK_X8;
1008 break;
1009 case 12:
1010 lnk_wdth = PCIE_LNK_X12;
1011 break;
1012 case 16:
1013 lnk_wdth = PCIE_LNK_X16;
1014 break;
1015 case 32:
1016 lnk_wdth = PCIE_LNK_X32;
1017 break;
1018 default:
1019 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1020 break;
1021 }
1022
1023 *value = lnk_wdth;
1024 dbg("Current link width = %d\n", lnk_wdth);
1025
1026 return retval;
1027 }
1028
1029 static struct hpc_ops pciehp_hpc_ops = {
1030 .power_on_slot = hpc_power_on_slot,
1031 .power_off_slot = hpc_power_off_slot,
1032 .set_attention_status = hpc_set_attention_status,
1033 .get_power_status = hpc_get_power_status,
1034 .get_attention_status = hpc_get_attention_status,
1035 .get_latch_status = hpc_get_latch_status,
1036 .get_adapter_status = hpc_get_adapter_status,
1037 .get_emi_status = hpc_get_emi_status,
1038 .toggle_emi = hpc_toggle_emi,
1039
1040 .get_max_bus_speed = hpc_get_max_lnk_speed,
1041 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1042 .get_max_lnk_width = hpc_get_max_lnk_width,
1043 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1044
1045 .query_power_fault = hpc_query_power_fault,
1046 .green_led_on = hpc_set_green_led_on,
1047 .green_led_off = hpc_set_green_led_off,
1048 .green_led_blink = hpc_set_green_led_blink,
1049
1050 .release_ctlr = hpc_release_ctlr,
1051 .check_lnk_status = hpc_check_lnk_status,
1052 };
1053
1054 #ifdef CONFIG_ACPI
1055 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1056 {
1057 acpi_status status;
1058 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1059 struct pci_dev *pdev = dev;
1060 struct pci_bus *parent;
1061 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1062
1063 /*
1064 * Per PCI firmware specification, we should run the ACPI _OSC
1065 * method to get control of hotplug hardware before using it.
1066 * If an _OSC is missing, we look for an OSHP to do the same thing.
1067 * To handle different BIOS behavior, we look for _OSC and OSHP
1068 * within the scope of the hotplug controller and its parents, upto
1069 * the host bridge under which this controller exists.
1070 */
1071 while (!handle) {
1072 /*
1073 * This hotplug controller was not listed in the ACPI name
1074 * space at all. Try to get acpi handle of parent pci bus.
1075 */
1076 if (!pdev || !pdev->bus->parent)
1077 break;
1078 parent = pdev->bus->parent;
1079 dbg("Could not find %s in acpi namespace, trying parent\n",
1080 pci_name(pdev));
1081 if (!parent->self)
1082 /* Parent must be a host bridge */
1083 handle = acpi_get_pci_rootbridge_handle(
1084 pci_domain_nr(parent),
1085 parent->number);
1086 else
1087 handle = DEVICE_ACPI_HANDLE(
1088 &(parent->self->dev));
1089 pdev = parent->self;
1090 }
1091
1092 while (handle) {
1093 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1094 dbg("Trying to get hotplug control for %s \n",
1095 (char *)string.pointer);
1096 status = pci_osc_control_set(handle,
1097 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1098 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1099 if (status == AE_NOT_FOUND)
1100 status = acpi_run_oshp(handle);
1101 if (ACPI_SUCCESS(status)) {
1102 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1103 pci_name(dev), (char *)string.pointer);
1104 kfree(string.pointer);
1105 return 0;
1106 }
1107 if (acpi_root_bridge(handle))
1108 break;
1109 chandle = handle;
1110 status = acpi_get_parent(chandle, &handle);
1111 if (ACPI_FAILURE(status))
1112 break;
1113 }
1114
1115 err("Cannot get control of hotplug hardware for pci %s\n",
1116 pci_name(dev));
1117
1118 kfree(string.pointer);
1119 return -1;
1120 }
1121 #endif
1122
1123 static int pcie_init_hardware_part1(struct controller *ctrl,
1124 struct pcie_device *dev)
1125 {
1126 int rc;
1127 u16 temp_word;
1128 u32 slot_cap;
1129 u16 slot_status;
1130
1131 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1132 if (rc) {
1133 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1134 return -1;
1135 }
1136
1137 /* Mask Hot-plug Interrupt Enable */
1138 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1139 if (rc) {
1140 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1141 return -1;
1142 }
1143
1144 dbg("%s: SLOTCTRL %x value read %x\n",
1145 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1146 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1147 0x00;
1148
1149 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1150 if (rc) {
1151 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1152 return -1;
1153 }
1154
1155 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1156 if (rc) {
1157 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1158 return -1;
1159 }
1160
1161 temp_word = 0x1F; /* Clear all events */
1162 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1163 if (rc) {
1164 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1165 return -1;
1166 }
1167 return 0;
1168 }
1169
1170 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1171 {
1172 int rc;
1173 u16 temp_word;
1174 u16 intr_enable = 0;
1175 u32 slot_cap;
1176 u16 slot_status;
1177
1178 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1179 if (rc) {
1180 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1181 goto abort;
1182 }
1183
1184 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1185
1186 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1187 if (rc) {
1188 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1189 goto abort;
1190 }
1191
1192 if (ATTN_BUTTN(slot_cap))
1193 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1194
1195 if (POWER_CTRL(slot_cap))
1196 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1197
1198 if (MRL_SENS(slot_cap))
1199 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1200
1201 temp_word = (temp_word & ~intr_enable) | intr_enable;
1202
1203 if (pciehp_poll_mode) {
1204 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1205 } else {
1206 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1207 }
1208
1209 /*
1210 * Unmask Hot-plug Interrupt Enable for the interrupt
1211 * notification mechanism case.
1212 */
1213 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1214 if (rc) {
1215 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1216 goto abort;
1217 }
1218 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1219 if (rc) {
1220 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1221 goto abort_disable_intr;
1222 }
1223
1224 temp_word = 0x1F; /* Clear all events */
1225 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1226 if (rc) {
1227 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1228 goto abort_disable_intr;
1229 }
1230
1231 if (pciehp_force) {
1232 dbg("Bypassing BIOS check for pciehp use on %s\n",
1233 pci_name(ctrl->pci_dev));
1234 } else {
1235 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1236 if (rc)
1237 goto abort_disable_intr;
1238 }
1239
1240 return 0;
1241
1242 /* We end up here for the many possible ways to fail this API. */
1243 abort_disable_intr:
1244 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1245 if (!rc) {
1246 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1247 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1248 }
1249 if (rc)
1250 err("%s : disabling interrupts failed\n", __FUNCTION__);
1251 abort:
1252 return -1;
1253 }
1254
1255 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1256 {
1257 int rc;
1258 u16 cap_reg;
1259 u32 slot_cap;
1260 int cap_base;
1261 u16 slot_status, slot_ctrl;
1262 struct pci_dev *pdev;
1263
1264 pdev = dev->port;
1265 ctrl->pci_dev = pdev; /* save pci_dev in context */
1266
1267 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1268 __FUNCTION__, pdev->vendor, pdev->device);
1269
1270 cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1271 if (cap_base == 0) {
1272 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1273 goto abort;
1274 }
1275
1276 ctrl->cap_base = cap_base;
1277
1278 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1279
1280 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1281 if (rc) {
1282 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1283 goto abort;
1284 }
1285 dbg("%s: CAPREG offset %x cap_reg %x\n",
1286 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1287
1288 if (((cap_reg & SLOT_IMPL) == 0) ||
1289 (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1290 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1291 dbg("%s : This is not a root port or the port is not "
1292 "connected to a slot\n", __FUNCTION__);
1293 goto abort;
1294 }
1295
1296 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1297 if (rc) {
1298 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1299 goto abort;
1300 }
1301 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1302 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1303
1304 if (!(slot_cap & HP_CAP)) {
1305 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1306 goto abort;
1307 }
1308 /* For debugging purpose */
1309 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1310 if (rc) {
1311 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1312 goto abort;
1313 }
1314 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1315 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1316
1317 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1318 if (rc) {
1319 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1320 goto abort;
1321 }
1322 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1323 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1324
1325 for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1326 if (pci_resource_len(pdev, rc) > 0)
1327 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1328 (unsigned long long)pci_resource_start(pdev, rc),
1329 (unsigned long long)pci_resource_len(pdev, rc));
1330
1331 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1332 pdev->vendor, pdev->device,
1333 pdev->subsystem_vendor, pdev->subsystem_device);
1334
1335 mutex_init(&ctrl->crit_sect);
1336 mutex_init(&ctrl->ctrl_lock);
1337 spin_lock_init(&ctrl->lock);
1338
1339 /* setup wait queue */
1340 init_waitqueue_head(&ctrl->queue);
1341
1342 /* return PCI Controller Info */
1343 ctrl->slot_device_offset = 0;
1344 ctrl->num_slots = 1;
1345 ctrl->first_slot = slot_cap >> 19;
1346 ctrl->ctrlcap = slot_cap & 0x0000007f;
1347
1348 rc = pcie_init_hardware_part1(ctrl, dev);
1349 if (rc)
1350 goto abort;
1351
1352 if (pciehp_poll_mode) {
1353 /* Install interrupt polling timer. Start with 10 sec delay */
1354 init_timer(&ctrl->poll_timer);
1355 start_int_poll_timer(ctrl, 10);
1356 } else {
1357 /* Installs the interrupt handler */
1358 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1359 MY_NAME, (void *)ctrl);
1360 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1361 __FUNCTION__, ctrl->pci_dev->irq,
1362 atomic_read(&pciehp_num_controllers), rc);
1363 if (rc) {
1364 err("Can't get irq %d for the hotplug controller\n",
1365 ctrl->pci_dev->irq);
1366 goto abort;
1367 }
1368 }
1369 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1370 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1371
1372 /*
1373 * If this is the first controller to be initialized,
1374 * initialize the pciehp work queue
1375 */
1376 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1377 pciehp_wq = create_singlethread_workqueue("pciehpd");
1378 if (!pciehp_wq) {
1379 rc = -ENOMEM;
1380 goto abort_free_irq;
1381 }
1382 }
1383
1384 rc = pcie_init_hardware_part2(ctrl, dev);
1385 if (rc == 0) {
1386 ctrl->hpc_ops = &pciehp_hpc_ops;
1387 return 0;
1388 }
1389 abort_free_irq:
1390 if (pciehp_poll_mode)
1391 del_timer_sync(&ctrl->poll_timer);
1392 else
1393 free_irq(ctrl->pci_dev->irq, ctrl);
1394 abort:
1395 return -1;
1396 }
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