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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / wireless / rt2x00 / rt73usb.h
blobd49dcaaceceec65066b7a816412969adb7063201
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #ifndef RT73USB_H
28 #define RT73USB_H
29
30 /*
31 * RF chip defines.
32 */
33 #define RF5226 0x0001
34 #define RF2528 0x0002
35 #define RF5225 0x0003
36 #define RF2527 0x0004
37
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define MAX_SIGNAL 100
43 #define MAX_RX_SSI -1
44 #define DEFAULT_RSSI_OFFSET 120
45
46 /*
47 * Register layout information.
48 */
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
55
56 /*
57 * USB registers.
58 */
59
60 /*
61 * MCU_LEDCS: LED control for MCU Mailbox.
62 */
63 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
64 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
65 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
66 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
67 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
68 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
69 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
70 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
71 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
72 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
73 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
74 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
75
76 /*
77 * 8051 firmware image.
78 */
79 #define FIRMWARE_RT2571 "rt73.bin"
80 #define FIRMWARE_IMAGE_BASE 0x0800
81
82 /*
83 * Security key table memory.
84 * 16 entries 32-byte for shared key table
85 * 64 entries 32-byte for pairwise key table
86 * 64 entries 8-byte for pairwise ta key table
87 */
88 #define SHARED_KEY_TABLE_BASE 0x1000
89 #define PAIRWISE_KEY_TABLE_BASE 0x1200
90 #define PAIRWISE_TA_TABLE_BASE 0x1a00
91
92 struct hw_key_entry {
93 u8 key[16];
94 u8 tx_mic[8];
95 u8 rx_mic[8];
96 } __attribute__ ((packed));
97
98 struct hw_pairwise_ta_entry {
99 u8 address[6];
100 u8 reserved[2];
101 } __attribute__ ((packed));
102
103 /*
104 * Since NULL frame won't be that long (256 byte),
105 * We steal 16 tail bytes to save debugging settings.
106 */
107 #define HW_DEBUG_SETTING_BASE 0x2bf0
108
109 /*
110 * On-chip BEACON frame space.
111 */
112 #define HW_BEACON_BASE0 0x2400
113 #define HW_BEACON_BASE1 0x2500
114 #define HW_BEACON_BASE2 0x2600
115 #define HW_BEACON_BASE3 0x2700
116
117 /*
118 * MAC Control/Status Registers(CSR).
119 * Some values are set in TU, whereas 1 TU == 1024 us.
120 */
121
122 /*
123 * MAC_CSR0: ASIC revision number.
124 */
125 #define MAC_CSR0 0x3000
126
127 /*
128 * MAC_CSR1: System control register.
129 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
130 * BBP_RESET: Hardware reset BBP.
131 * HOST_READY: Host is ready after initialization, 1: ready.
132 */
133 #define MAC_CSR1 0x3004
134 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
135 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
136 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
137
138 /*
139 * MAC_CSR2: STA MAC register 0.
140 */
141 #define MAC_CSR2 0x3008
142 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
143 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
144 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
145 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
146
147 /*
148 * MAC_CSR3: STA MAC register 1.
149 */
150 #define MAC_CSR3 0x300c
151 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
152 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
153 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
154
155 /*
156 * MAC_CSR4: BSSID register 0.
157 */
158 #define MAC_CSR4 0x3010
159 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
160 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
161 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
162 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
163
164 /*
165 * MAC_CSR5: BSSID register 1.
166 * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
167 */
168 #define MAC_CSR5 0x3014
169 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
170 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
171 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
172
173 /*
174 * MAC_CSR6: Maximum frame length register.
175 */
176 #define MAC_CSR6 0x3018
177 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
178
179 /*
180 * MAC_CSR7: Reserved
181 */
182 #define MAC_CSR7 0x301c
183
184 /*
185 * MAC_CSR8: SIFS/EIFS register.
186 * All units are in US.
187 */
188 #define MAC_CSR8 0x3020
189 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
190 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
191 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
192
193 /*
194 * MAC_CSR9: Back-Off control register.
195 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
196 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
197 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
198 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
199 */
200 #define MAC_CSR9 0x3024
201 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
202 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
203 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
204 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
205
206 /*
207 * MAC_CSR10: Power state configuration.
208 */
209 #define MAC_CSR10 0x3028
210
211 /*
212 * MAC_CSR11: Power saving transition time register.
213 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
214 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
215 * WAKEUP_LATENCY: In unit of TU.
216 */
217 #define MAC_CSR11 0x302c
218 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
219 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
220 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
221 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
222
223 /*
224 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
225 * CURRENT_STATE: 0:sleep, 1:awake.
226 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
227 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
228 */
229 #define MAC_CSR12 0x3030
230 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
231 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
232 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
233 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
234
235 /*
236 * MAC_CSR13: GPIO.
237 */
238 #define MAC_CSR13 0x3034
239
240 /*
241 * MAC_CSR14: LED control register.
242 * ON_PERIOD: On period, default 70ms.
243 * OFF_PERIOD: Off period, default 30ms.
244 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
245 * SW_LED: s/w LED, 1: ON, 0: OFF.
246 * HW_LED_POLARITY: 0: active low, 1: active high.
247 */
248 #define MAC_CSR14 0x3038
249 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
250 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
251 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
252 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
253 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
254 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
255
256 /*
257 * MAC_CSR15: NAV control.
258 */
259 #define MAC_CSR15 0x303c
260
261 /*
262 * TXRX control registers.
263 * Some values are set in TU, whereas 1 TU == 1024 us.
264 */
265
266 /*
267 * TXRX_CSR0: TX/RX configuration register.
268 * TSF_OFFSET: Default is 24.
269 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
270 * DISABLE_RX: Disable Rx engine.
271 * DROP_CRC: Drop CRC error.
272 * DROP_PHYSICAL: Drop physical error.
273 * DROP_CONTROL: Drop control frame.
274 * DROP_NOT_TO_ME: Drop not to me unicast frame.
275 * DROP_TO_DS: Drop fram ToDs bit is true.
276 * DROP_VERSION_ERROR: Drop version error frame.
277 * DROP_MULTICAST: Drop multicast frames.
278 * DROP_BORADCAST: Drop broadcast frames.
279 * ROP_ACK_CTS: Drop received ACK and CTS.
280 */
281 #define TXRX_CSR0 0x3040
282 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
283 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
284 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
285 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
286 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
287 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
288 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
289 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
290 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
291 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
292 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
293 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
294 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
295 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
296
297 /*
298 * TXRX_CSR1
299 */
300 #define TXRX_CSR1 0x3044
301 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
302 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
303 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
304 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
305 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
306 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
307 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
308 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
309
310 /*
311 * TXRX_CSR2
312 */
313 #define TXRX_CSR2 0x3048
314 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
315 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
316 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
317 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
318 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
319 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
320 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
321 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
322
323 /*
324 * TXRX_CSR3
325 */
326 #define TXRX_CSR3 0x304c
327 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
328 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
329 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
330 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
331 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
332 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
333 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
334 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
335
336 /*
337 * TXRX_CSR4: Auto-Responder/Tx-retry register.
338 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
339 * OFDM_TX_RATE_DOWN: 1:enable.
340 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
341 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
342 */
343 #define TXRX_CSR4 0x3050
344 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
345 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
346 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
347 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
348 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
349 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
350 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
351 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
352 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
353 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
354
355 /*
356 * TXRX_CSR5
357 */
358 #define TXRX_CSR5 0x3054
359
360 /*
361 * TXRX_CSR6: ACK/CTS payload consumed time
362 */
363 #define TXRX_CSR6 0x3058
364
365 /*
366 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
367 */
368 #define TXRX_CSR7 0x305c
369 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
370 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
371 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
372 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
373
374 /*
375 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
376 */
377 #define TXRX_CSR8 0x3060
378 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
379 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
380 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
381 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
382
383 /*
384 * TXRX_CSR9: Synchronization control register.
385 * BEACON_INTERVAL: In unit of 1/16 TU.
386 * TSF_TICKING: Enable TSF auto counting.
387 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
388 * BEACON_GEN: Enable beacon generator.
389 */
390 #define TXRX_CSR9 0x3064
391 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
392 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
393 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
394 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
395 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
396 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
397
398 /*
399 * TXRX_CSR10: BEACON alignment.
400 */
401 #define TXRX_CSR10 0x3068
402
403 /*
404 * TXRX_CSR11: AES mask.
405 */
406 #define TXRX_CSR11 0x306c
407
408 /*
409 * TXRX_CSR12: TSF low 32.
410 */
411 #define TXRX_CSR12 0x3070
412 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
413
414 /*
415 * TXRX_CSR13: TSF high 32.
416 */
417 #define TXRX_CSR13 0x3074
418 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
419
420 /*
421 * TXRX_CSR14: TBTT timer.
422 */
423 #define TXRX_CSR14 0x3078
424
425 /*
426 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
427 */
428 #define TXRX_CSR15 0x307c
429
430 /*
431 * PHY control registers.
432 * Some values are set in TU, whereas 1 TU == 1024 us.
433 */
434
435 /*
436 * PHY_CSR0: RF/PS control.
437 */
438 #define PHY_CSR0 0x3080
439 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
440 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
441
442 /*
443 * PHY_CSR1
444 */
445 #define PHY_CSR1 0x3084
446 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
447
448 /*
449 * PHY_CSR2: Pre-TX BBP control.
450 */
451 #define PHY_CSR2 0x3088
452
453 /*
454 * PHY_CSR3: BBP serial control register.
455 * VALUE: Register value to program into BBP.
456 * REG_NUM: Selected BBP register.
457 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
458 * BUSY: 1: ASIC is busy execute BBP programming.
459 */
460 #define PHY_CSR3 0x308c
461 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
462 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
463 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
464 #define PHY_CSR3_BUSY FIELD32(0x00010000)
465
466 /*
467 * PHY_CSR4: RF serial control register
468 * VALUE: Register value (include register id) serial out to RF/IF chip.
469 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
470 * IF_SELECT: 1: select IF to program, 0: select RF to program.
471 * PLL_LD: RF PLL_LD status.
472 * BUSY: 1: ASIC is busy execute RF programming.
473 */
474 #define PHY_CSR4 0x3090
475 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
476 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
477 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
478 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
479 #define PHY_CSR4_BUSY FIELD32(0x80000000)
480
481 /*
482 * PHY_CSR5: RX to TX signal switch timing control.
483 */
484 #define PHY_CSR5 0x3094
485 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
486
487 /*
488 * PHY_CSR6: TX to RX signal timing control.
489 */
490 #define PHY_CSR6 0x3098
491 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
492
493 /*
494 * PHY_CSR7: TX DAC switching timing control.
495 */
496 #define PHY_CSR7 0x309c
497
498 /*
499 * Security control register.
500 */
501
502 /*
503 * SEC_CSR0: Shared key table control.
504 */
505 #define SEC_CSR0 0x30a0
506 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
507 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
508 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
509 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
510 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
511 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
512 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
513 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
514 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
515 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
516 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
517 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
518 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
519 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
520 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
521 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
522
523 /*
524 * SEC_CSR1: Shared key table security mode register.
525 */
526 #define SEC_CSR1 0x30a4
527 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
528 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
529 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
530 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
531 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
532 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
533 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
534 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
535
536 /*
537 * Pairwise key table valid bitmap registers.
538 * SEC_CSR2: pairwise key table valid bitmap 0.
539 * SEC_CSR3: pairwise key table valid bitmap 1.
540 */
541 #define SEC_CSR2 0x30a8
542 #define SEC_CSR3 0x30ac
543
544 /*
545 * SEC_CSR4: Pairwise key table lookup control.
546 */
547 #define SEC_CSR4 0x30b0
548
549 /*
550 * SEC_CSR5: shared key table security mode register.
551 */
552 #define SEC_CSR5 0x30b4
553 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
554 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
555 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
556 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
557 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
558 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
559 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
560 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
561
562 /*
563 * STA control registers.
564 */
565
566 /*
567 * STA_CSR0: RX PLCP error count & RX FCS error count.
568 */
569 #define STA_CSR0 0x30c0
570 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
571 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
572
573 /*
574 * STA_CSR1: RX False CCA count & RX LONG frame count.
575 */
576 #define STA_CSR1 0x30c4
577 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
578 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
579
580 /*
581 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
582 */
583 #define STA_CSR2 0x30c8
584 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
585 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
586
587 /*
588 * STA_CSR3: TX Beacon count.
589 */
590 #define STA_CSR3 0x30cc
591 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
592
593 /*
594 * STA_CSR4: TX Retry count.
595 */
596 #define STA_CSR4 0x30d0
597 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
598 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
599
600 /*
601 * STA_CSR5: TX Retry count.
602 */
603 #define STA_CSR5 0x30d4
604 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
605 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
606
607 /*
608 * QOS control registers.
609 */
610
611 /*
612 * QOS_CSR1: TXOP holder MAC address register.
613 */
614 #define QOS_CSR1 0x30e4
615 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
616 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
617
618 /*
619 * QOS_CSR2: TXOP holder timeout register.
620 */
621 #define QOS_CSR2 0x30e8
622
623 /*
624 * RX QOS-CFPOLL MAC address register.
625 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
626 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
627 */
628 #define QOS_CSR3 0x30ec
629 #define QOS_CSR4 0x30f0
630
631 /*
632 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
633 */
634 #define QOS_CSR5 0x30f4
635
636 /*
637 * WMM Scheduler Register
638 */
639
640 /*
641 * AIFSN_CSR: AIFSN for each EDCA AC.
642 * AIFSN0: For AC_BK.
643 * AIFSN1: For AC_BE.
644 * AIFSN2: For AC_VI.
645 * AIFSN3: For AC_VO.
646 */
647 #define AIFSN_CSR 0x0400
648 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
649 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
650 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
651 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
652
653 /*
654 * CWMIN_CSR: CWmin for each EDCA AC.
655 * CWMIN0: For AC_BK.
656 * CWMIN1: For AC_BE.
657 * CWMIN2: For AC_VI.
658 * CWMIN3: For AC_VO.
659 */
660 #define CWMIN_CSR 0x0404
661 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
662 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
663 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
664 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
665
666 /*
667 * CWMAX_CSR: CWmax for each EDCA AC.
668 * CWMAX0: For AC_BK.
669 * CWMAX1: For AC_BE.
670 * CWMAX2: For AC_VI.
671 * CWMAX3: For AC_VO.
672 */
673 #define CWMAX_CSR 0x0408
674 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
675 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
676 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
677 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
678
679 /*
680 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
681 * AC0_TX_OP: For AC_BK, in unit of 32us.
682 * AC1_TX_OP: For AC_BE, in unit of 32us.
683 */
684 #define AC_TXOP_CSR0 0x040c
685 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
686 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
687
688 /*
689 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
690 * AC2_TX_OP: For AC_VI, in unit of 32us.
691 * AC3_TX_OP: For AC_VO, in unit of 32us.
692 */
693 #define AC_TXOP_CSR1 0x0410
694 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
695 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
696
697 /*
698 * BBP registers.
699 * The wordsize of the BBP is 8 bits.
700 */
701
702 /*
703 * R2
704 */
705 #define BBP_R2_BG_MODE FIELD8(0x20)
706
707 /*
708 * R3
709 */
710 #define BBP_R3_SMART_MODE FIELD8(0x01)
711
712 /*
713 * R4: RX antenna control
714 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
715 */
716
717 /*
718 * ANTENNA_CONTROL semantics (guessed):
719 * 0x1: Software controlled antenna switching (fixed or SW diversity)
720 * 0x2: Hardware diversity.
721 */
722 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
723 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
724
725 /*
726 * R77
727 */
728 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
729
730 /*
731 * RF registers
732 */
733
734 /*
735 * RF 3
736 */
737 #define RF3_TXPOWER FIELD32(0x00003e00)
738
739 /*
740 * RF 4
741 */
742 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
743
744 /*
745 * EEPROM content.
746 * The wordsize of the EEPROM is 16 bits.
747 */
748
749 /*
750 * HW MAC address.
751 */
752 #define EEPROM_MAC_ADDR_0 0x0002
753 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
754 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
755 #define EEPROM_MAC_ADDR1 0x0003
756 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
757 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
758 #define EEPROM_MAC_ADDR_2 0x0004
759 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
760 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
761
762 /*
763 * EEPROM antenna.
764 * ANTENNA_NUM: Number of antenna's.
765 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
766 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
767 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
768 * DYN_TXAGC: Dynamic TX AGC control.
769 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
770 * RF_TYPE: Rf_type of this adapter.
771 */
772 #define EEPROM_ANTENNA 0x0010
773 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
774 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
775 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
776 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
777 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
778 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
779 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
780
781 /*
782 * EEPROM NIC config.
783 * EXTERNAL_LNA: External LNA.
784 */
785 #define EEPROM_NIC 0x0011
786 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
787
788 /*
789 * EEPROM geography.
790 * GEO_A: Default geographical setting for 5GHz band
791 * GEO: Default geographical setting.
792 */
793 #define EEPROM_GEOGRAPHY 0x0012
794 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
795 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
796
797 /*
798 * EEPROM BBP.
799 */
800 #define EEPROM_BBP_START 0x0013
801 #define EEPROM_BBP_SIZE 16
802 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
803 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
804
805 /*
806 * EEPROM TXPOWER 802.11G
807 */
808 #define EEPROM_TXPOWER_G_START 0x0023
809 #define EEPROM_TXPOWER_G_SIZE 7
810 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
811 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
812
813 /*
814 * EEPROM Frequency
815 */
816 #define EEPROM_FREQ 0x002f
817 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
818 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
819 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
820
821 /*
822 * EEPROM LED.
823 * POLARITY_RDY_G: Polarity RDY_G setting.
824 * POLARITY_RDY_A: Polarity RDY_A setting.
825 * POLARITY_ACT: Polarity ACT setting.
826 * POLARITY_GPIO_0: Polarity GPIO0 setting.
827 * POLARITY_GPIO_1: Polarity GPIO1 setting.
828 * POLARITY_GPIO_2: Polarity GPIO2 setting.
829 * POLARITY_GPIO_3: Polarity GPIO3 setting.
830 * POLARITY_GPIO_4: Polarity GPIO4 setting.
831 * LED_MODE: Led mode.
832 */
833 #define EEPROM_LED 0x0030
834 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
835 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
836 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
837 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
838 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
839 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
840 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
841 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
842 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
843
844 /*
845 * EEPROM TXPOWER 802.11A
846 */
847 #define EEPROM_TXPOWER_A_START 0x0031
848 #define EEPROM_TXPOWER_A_SIZE 12
849 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
850 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
851
852 /*
853 * EEPROM RSSI offset 802.11BG
854 */
855 #define EEPROM_RSSI_OFFSET_BG 0x004d
856 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
857 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
858
859 /*
860 * EEPROM RSSI offset 802.11A
861 */
862 #define EEPROM_RSSI_OFFSET_A 0x004e
863 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
864 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
865
866 /*
867 * DMA descriptor defines.
868 */
869 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
870 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
871
872 /*
873 * TX descriptor format for TX, PRIO and Beacon Ring.
874 */
875
876 /*
877 * Word0
878 * BURST: Next frame belongs to same "burst" event.
879 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
880 * KEY_TABLE: Use per-client pairwise KEY table.
881 * KEY_INDEX:
882 * Key index (0~31) to the pairwise KEY table.
883 * 0~3 to shared KEY table 0 (BSS0).
884 * 4~7 to shared KEY table 1 (BSS1).
885 * 8~11 to shared KEY table 2 (BSS2).
886 * 12~15 to shared KEY table 3 (BSS3).
887 * BURST2: For backward compatibility, set to same value as BURST.
888 */
889 #define TXD_W0_BURST FIELD32(0x00000001)
890 #define TXD_W0_VALID FIELD32(0x00000002)
891 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
892 #define TXD_W0_ACK FIELD32(0x00000008)
893 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
894 #define TXD_W0_OFDM FIELD32(0x00000020)
895 #define TXD_W0_IFS FIELD32(0x00000040)
896 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
897 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
898 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
899 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
900 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
901 #define TXD_W0_BURST2 FIELD32(0x10000000)
902 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
903
904 /*
905 * Word1
906 * HOST_Q_ID: EDCA/HCCA queue ID.
907 * HW_SEQUENCE: MAC overwrites the frame sequence number.
908 * BUFFER_COUNT: Number of buffers in this TXD.
909 */
910 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
911 #define TXD_W1_AIFSN FIELD32(0x000000f0)
912 #define TXD_W1_CWMIN FIELD32(0x00000f00)
913 #define TXD_W1_CWMAX FIELD32(0x0000f000)
914 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
915 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
916 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
917
918 /*
919 * Word2: PLCP information
920 */
921 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
922 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
923 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
924 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
925
926 /*
927 * Word3
928 */
929 #define TXD_W3_IV FIELD32(0xffffffff)
930
931 /*
932 * Word4
933 */
934 #define TXD_W4_EIV FIELD32(0xffffffff)
935
936 /*
937 * Word5
938 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
939 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
940 * WAITING_DMA_DONE_INT: TXD been filled with data
941 * and waiting for TxDoneISR housekeeping.
942 */
943 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
944 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
945 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
946 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
947
948 /*
949 * RX descriptor format for RX Ring.
950 */
951
952 /*
953 * Word0
954 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
955 * KEY_INDEX: Decryption key actually used.
956 */
957 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
958 #define RXD_W0_DROP FIELD32(0x00000002)
959 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
960 #define RXD_W0_MULTICAST FIELD32(0x00000008)
961 #define RXD_W0_BROADCAST FIELD32(0x00000010)
962 #define RXD_W0_MY_BSS FIELD32(0x00000020)
963 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
964 #define RXD_W0_OFDM FIELD32(0x00000080)
965 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
966 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
967 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
968 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
969
970 /*
971 * WORD1
972 * SIGNAL: RX raw data rate reported by BBP.
973 * RSSI: RSSI reported by BBP.
974 */
975 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
976 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
977 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
978 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
979
980 /*
981 * Word2
982 * IV: Received IV of originally encrypted.
983 */
984 #define RXD_W2_IV FIELD32(0xffffffff)
985
986 /*
987 * Word3
988 * EIV: Received EIV of originally encrypted.
989 */
990 #define RXD_W3_EIV FIELD32(0xffffffff)
991
992 /*
993 * Word4
994 */
995 #define RXD_W4_RESERVED FIELD32(0xffffffff)
996
997 /*
998 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
999 * and passed to the HOST driver.
1000 * The following fields are for DMA block and HOST usage only.
1001 * Can't be touched by ASIC MAC block.
1002 */
1003
1004 /*
1005 * Word5
1006 */
1007 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1008
1009 /*
1010 * Macro's for converting txpower from EEPROM to dscape value
1011 * and from dscape value to register value.
1012 */
1013 #define MIN_TXPOWER 0
1014 #define MAX_TXPOWER 31
1015 #define DEFAULT_TXPOWER 24
1016
1017 #define TXPOWER_FROM_DEV(__txpower) \
1018 ({ \
1019 ((__txpower) > MAX_TXPOWER) ? \
1020 DEFAULT_TXPOWER : (__txpower); \
1021 })
1022
1023 #define TXPOWER_TO_DEV(__txpower) \
1024 ({ \
1025 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1026 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1027 (__txpower)); \
1028 })
1029
1030 #endif /* RT73USB_H */
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