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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / wireless / rt2x00 / rt61pci.h
blob4c6524eedad0d219ca6ed3bb8e1f7267cb6b1520
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #ifndef RT61PCI_H
28 #define RT61PCI_H
29
30 /*
31 * RF chip defines.
32 */
33 #define RF5225 0x0001
34 #define RF5325 0x0002
35 #define RF2527 0x0003
36 #define RF2529 0x0004
37
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define MAX_SIGNAL 100
43 #define MAX_RX_SSI -1
44 #define DEFAULT_RSSI_OFFSET 120
45
46 /*
47 * Register layout information.
48 */
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
55
56 /*
57 * PCI registers.
58 */
59
60 /*
61 * PCI Configuration Header
62 */
63 #define PCI_CONFIG_HEADER_VENDOR 0x0000
64 #define PCI_CONFIG_HEADER_DEVICE 0x0002
65
66 /*
67 * HOST_CMD_CSR: For HOST to interrupt embedded processor
68 */
69 #define HOST_CMD_CSR 0x0008
70 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
71 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
72
73 /*
74 * MCU_CNTL_CSR
75 * SELECT_BANK: Select 8051 program bank.
76 * RESET: Enable 8051 reset state.
77 * READY: Ready state for 8051.
78 */
79 #define MCU_CNTL_CSR 0x000c
80 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
81 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
82 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
83
84 /*
85 * SOFT_RESET_CSR
86 */
87 #define SOFT_RESET_CSR 0x0010
88
89 /*
90 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
91 */
92 #define MCU_INT_SOURCE_CSR 0x0014
93 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
94 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
95 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
96 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
97 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
98 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
99 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
100 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
101 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
102 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
103
104 /*
105 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
106 */
107 #define MCU_INT_MASK_CSR 0x0018
108 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
109 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
110 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
111 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
112 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
113 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
114 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
115 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
116 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
117 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
118
119 /*
120 * PCI_USEC_CSR
121 */
122 #define PCI_USEC_CSR 0x001c
123
124 /*
125 * Security key table memory.
126 * 16 entries 32-byte for shared key table
127 * 64 entries 32-byte for pairwise key table
128 * 64 entries 8-byte for pairwise ta key table
129 */
130 #define SHARED_KEY_TABLE_BASE 0x1000
131 #define PAIRWISE_KEY_TABLE_BASE 0x1200
132 #define PAIRWISE_TA_TABLE_BASE 0x1a00
133
134 struct hw_key_entry {
135 u8 key[16];
136 u8 tx_mic[8];
137 u8 rx_mic[8];
138 } __attribute__ ((packed));
139
140 struct hw_pairwise_ta_entry {
141 u8 address[6];
142 u8 reserved[2];
143 } __attribute__ ((packed));
144
145 /*
146 * Other on-chip shared memory space.
147 */
148 #define HW_CIS_BASE 0x2000
149 #define HW_NULL_BASE 0x2b00
150
151 /*
152 * Since NULL frame won't be that long (256 byte),
153 * We steal 16 tail bytes to save debugging settings.
154 */
155 #define HW_DEBUG_SETTING_BASE 0x2bf0
156
157 /*
158 * On-chip BEACON frame space.
159 */
160 #define HW_BEACON_BASE0 0x2c00
161 #define HW_BEACON_BASE1 0x2d00
162 #define HW_BEACON_BASE2 0x2e00
163 #define HW_BEACON_BASE3 0x2f00
164 #define HW_BEACON_OFFSET 0x0100
165
166 /*
167 * HOST-MCU shared memory.
168 */
169
170 /*
171 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
172 */
173 #define H2M_MAILBOX_CSR 0x2100
174 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
175 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
176 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
177 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
178
179 /*
180 * MCU_LEDCS: LED control for MCU Mailbox.
181 */
182 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
183 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
184 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
185 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
186 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
187 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
188 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
189 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
190 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
191 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
192 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
193 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
194
195 /*
196 * M2H_CMD_DONE_CSR.
197 */
198 #define M2H_CMD_DONE_CSR 0x2104
199
200 /*
201 * MCU_TXOP_ARRAY_BASE.
202 */
203 #define MCU_TXOP_ARRAY_BASE 0x2110
204
205 /*
206 * MAC Control/Status Registers(CSR).
207 * Some values are set in TU, whereas 1 TU == 1024 us.
208 */
209
210 /*
211 * MAC_CSR0: ASIC revision number.
212 */
213 #define MAC_CSR0 0x3000
214
215 /*
216 * MAC_CSR1: System control register.
217 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
218 * BBP_RESET: Hardware reset BBP.
219 * HOST_READY: Host is ready after initialization, 1: ready.
220 */
221 #define MAC_CSR1 0x3004
222 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
223 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
224 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
225
226 /*
227 * MAC_CSR2: STA MAC register 0.
228 */
229 #define MAC_CSR2 0x3008
230 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
231 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
232 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
233 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
234
235 /*
236 * MAC_CSR3: STA MAC register 1.
237 */
238 #define MAC_CSR3 0x300c
239 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
240 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
241 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
242
243 /*
244 * MAC_CSR4: BSSID register 0.
245 */
246 #define MAC_CSR4 0x3010
247 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
248 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
249 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
250 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
251
252 /*
253 * MAC_CSR5: BSSID register 1.
254 * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
255 */
256 #define MAC_CSR5 0x3014
257 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
258 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
259 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
260
261 /*
262 * MAC_CSR6: Maximum frame length register.
263 */
264 #define MAC_CSR6 0x3018
265 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
266
267 /*
268 * MAC_CSR7: Reserved
269 */
270 #define MAC_CSR7 0x301c
271
272 /*
273 * MAC_CSR8: SIFS/EIFS register.
274 * All units are in US.
275 */
276 #define MAC_CSR8 0x3020
277 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
278 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
279 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
280
281 /*
282 * MAC_CSR9: Back-Off control register.
283 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
284 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
285 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
286 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
287 */
288 #define MAC_CSR9 0x3024
289 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
290 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
291 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
292 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
293
294 /*
295 * MAC_CSR10: Power state configuration.
296 */
297 #define MAC_CSR10 0x3028
298
299 /*
300 * MAC_CSR11: Power saving transition time register.
301 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
302 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
303 * WAKEUP_LATENCY: In unit of TU.
304 */
305 #define MAC_CSR11 0x302c
306 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
307 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
308 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
309 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
310
311 /*
312 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
313 * CURRENT_STATE: 0:sleep, 1:awake.
314 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
315 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
316 */
317 #define MAC_CSR12 0x3030
318 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
319 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
320 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
321 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
322
323 /*
324 * MAC_CSR13: GPIO.
325 */
326 #define MAC_CSR13 0x3034
327 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
328 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
329 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
330 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
331 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
332 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
333 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
334 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
335 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
336 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
337 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
338 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
339 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
340
341 /*
342 * MAC_CSR14: LED control register.
343 * ON_PERIOD: On period, default 70ms.
344 * OFF_PERIOD: Off period, default 30ms.
345 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
346 * SW_LED: s/w LED, 1: ON, 0: OFF.
347 * HW_LED_POLARITY: 0: active low, 1: active high.
348 */
349 #define MAC_CSR14 0x3038
350 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
351 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
352 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
353 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
354 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
355 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
356
357 /*
358 * MAC_CSR15: NAV control.
359 */
360 #define MAC_CSR15 0x303c
361
362 /*
363 * TXRX control registers.
364 * Some values are set in TU, whereas 1 TU == 1024 us.
365 */
366
367 /*
368 * TXRX_CSR0: TX/RX configuration register.
369 * TSF_OFFSET: Default is 24.
370 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
371 * DISABLE_RX: Disable Rx engine.
372 * DROP_CRC: Drop CRC error.
373 * DROP_PHYSICAL: Drop physical error.
374 * DROP_CONTROL: Drop control frame.
375 * DROP_NOT_TO_ME: Drop not to me unicast frame.
376 * DROP_TO_DS: Drop fram ToDs bit is true.
377 * DROP_VERSION_ERROR: Drop version error frame.
378 * DROP_MULTICAST: Drop multicast frames.
379 * DROP_BORADCAST: Drop broadcast frames.
380 * ROP_ACK_CTS: Drop received ACK and CTS.
381 */
382 #define TXRX_CSR0 0x3040
383 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
384 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
385 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
386 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
387 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
388 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
389 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
390 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
391 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
392 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
393 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
394 #define TXRX_CSR0_DROP_BORADCAST FIELD32(0x01000000)
395 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
396 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
397
398 /*
399 * TXRX_CSR1
400 */
401 #define TXRX_CSR1 0x3044
402 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
403 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
404 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
405 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
406 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
407 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
408 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
409 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
410
411 /*
412 * TXRX_CSR2
413 */
414 #define TXRX_CSR2 0x3048
415 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
416 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
417 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
418 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
419 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
420 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
421 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
422 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
423
424 /*
425 * TXRX_CSR3
426 */
427 #define TXRX_CSR3 0x304c
428 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
429 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
430 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
431 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
432 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
433 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
434 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
435 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
436
437 /*
438 * TXRX_CSR4: Auto-Responder/Tx-retry register.
439 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
440 * OFDM_TX_RATE_DOWN: 1:enable.
441 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
442 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
443 */
444 #define TXRX_CSR4 0x3050
445 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
446 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
447 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
448 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
449 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
450 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
451 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
452 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
453 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
454 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
455
456 /*
457 * TXRX_CSR5
458 */
459 #define TXRX_CSR5 0x3054
460
461 /*
462 * TXRX_CSR6: ACK/CTS payload consumed time
463 */
464 #define TXRX_CSR6 0x3058
465
466 /*
467 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
468 */
469 #define TXRX_CSR7 0x305c
470 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
471 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
472 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
473 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
474
475 /*
476 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
477 */
478 #define TXRX_CSR8 0x3060
479 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
480 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
481 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
482 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
483
484 /*
485 * TXRX_CSR9: Synchronization control register.
486 * BEACON_INTERVAL: In unit of 1/16 TU.
487 * TSF_TICKING: Enable TSF auto counting.
488 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
489 * BEACON_GEN: Enable beacon generator.
490 */
491 #define TXRX_CSR9 0x3064
492 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
493 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
494 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
495 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
496 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
497 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
498
499 /*
500 * TXRX_CSR10: BEACON alignment.
501 */
502 #define TXRX_CSR10 0x3068
503
504 /*
505 * TXRX_CSR11: AES mask.
506 */
507 #define TXRX_CSR11 0x306c
508
509 /*
510 * TXRX_CSR12: TSF low 32.
511 */
512 #define TXRX_CSR12 0x3070
513 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
514
515 /*
516 * TXRX_CSR13: TSF high 32.
517 */
518 #define TXRX_CSR13 0x3074
519 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
520
521 /*
522 * TXRX_CSR14: TBTT timer.
523 */
524 #define TXRX_CSR14 0x3078
525
526 /*
527 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
528 */
529 #define TXRX_CSR15 0x307c
530
531 /*
532 * PHY control registers.
533 * Some values are set in TU, whereas 1 TU == 1024 us.
534 */
535
536 /*
537 * PHY_CSR0: RF/PS control.
538 */
539 #define PHY_CSR0 0x3080
540 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
541 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
542
543 /*
544 * PHY_CSR1
545 */
546 #define PHY_CSR1 0x3084
547
548 /*
549 * PHY_CSR2: Pre-TX BBP control.
550 */
551 #define PHY_CSR2 0x3088
552
553 /*
554 * PHY_CSR3: BBP serial control register.
555 * VALUE: Register value to program into BBP.
556 * REG_NUM: Selected BBP register.
557 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
558 * BUSY: 1: ASIC is busy execute BBP programming.
559 */
560 #define PHY_CSR3 0x308c
561 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
562 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
563 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
564 #define PHY_CSR3_BUSY FIELD32(0x00010000)
565
566 /*
567 * PHY_CSR4: RF serial control register
568 * VALUE: Register value (include register id) serial out to RF/IF chip.
569 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
570 * IF_SELECT: 1: select IF to program, 0: select RF to program.
571 * PLL_LD: RF PLL_LD status.
572 * BUSY: 1: ASIC is busy execute RF programming.
573 */
574 #define PHY_CSR4 0x3090
575 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
576 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
577 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
578 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
579 #define PHY_CSR4_BUSY FIELD32(0x80000000)
580
581 /*
582 * PHY_CSR5: RX to TX signal switch timing control.
583 */
584 #define PHY_CSR5 0x3094
585 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
586
587 /*
588 * PHY_CSR6: TX to RX signal timing control.
589 */
590 #define PHY_CSR6 0x3098
591 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
592
593 /*
594 * PHY_CSR7: TX DAC switching timing control.
595 */
596 #define PHY_CSR7 0x309c
597
598 /*
599 * Security control register.
600 */
601
602 /*
603 * SEC_CSR0: Shared key table control.
604 */
605 #define SEC_CSR0 0x30a0
606 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
607 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
608 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
609 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
610 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
611 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
612 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
613 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
614 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
615 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
616 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
617 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
618 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
619 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
620 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
621 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
622
623 /*
624 * SEC_CSR1: Shared key table security mode register.
625 */
626 #define SEC_CSR1 0x30a4
627 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
628 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
629 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
630 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
631 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
632 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
633 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
634 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
635
636 /*
637 * Pairwise key table valid bitmap registers.
638 * SEC_CSR2: pairwise key table valid bitmap 0.
639 * SEC_CSR3: pairwise key table valid bitmap 1.
640 */
641 #define SEC_CSR2 0x30a8
642 #define SEC_CSR3 0x30ac
643
644 /*
645 * SEC_CSR4: Pairwise key table lookup control.
646 */
647 #define SEC_CSR4 0x30b0
648
649 /*
650 * SEC_CSR5: shared key table security mode register.
651 */
652 #define SEC_CSR5 0x30b4
653 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
654 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
655 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
656 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
657 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
658 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
659 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
660 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
661
662 /*
663 * STA control registers.
664 */
665
666 /*
667 * STA_CSR0: RX PLCP error count & RX FCS error count.
668 */
669 #define STA_CSR0 0x30c0
670 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
671 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
672
673 /*
674 * STA_CSR1: RX False CCA count & RX LONG frame count.
675 */
676 #define STA_CSR1 0x30c4
677 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
678 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
679
680 /*
681 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
682 */
683 #define STA_CSR2 0x30c8
684 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
685 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
686
687 /*
688 * STA_CSR3: TX Beacon count.
689 */
690 #define STA_CSR3 0x30cc
691 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
692
693 /*
694 * STA_CSR4: TX Result status register.
695 * VALID: 1:This register contains a valid TX result.
696 */
697 #define STA_CSR4 0x30d0
698 #define STA_CSR4_VALID FIELD32(0x00000001)
699 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
700 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
701 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
702 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
703 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
704
705 /*
706 * QOS control registers.
707 */
708
709 /*
710 * QOS_CSR0: TXOP holder MAC address register.
711 */
712 #define QOS_CSR0 0x30e0
713 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
714 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
715 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
716 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
717
718 /*
719 * QOS_CSR1: TXOP holder MAC address register.
720 */
721 #define QOS_CSR1 0x30e4
722 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
723 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
724
725 /*
726 * QOS_CSR2: TXOP holder timeout register.
727 */
728 #define QOS_CSR2 0x30e8
729
730 /*
731 * RX QOS-CFPOLL MAC address register.
732 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
733 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
734 */
735 #define QOS_CSR3 0x30ec
736 #define QOS_CSR4 0x30f0
737
738 /*
739 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
740 */
741 #define QOS_CSR5 0x30f4
742
743 /*
744 * Host DMA registers.
745 */
746
747 /*
748 * AC0_BASE_CSR: AC_BK base address.
749 */
750 #define AC0_BASE_CSR 0x3400
751 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
752
753 /*
754 * AC1_BASE_CSR: AC_BE base address.
755 */
756 #define AC1_BASE_CSR 0x3404
757 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
758
759 /*
760 * AC2_BASE_CSR: AC_VI base address.
761 */
762 #define AC2_BASE_CSR 0x3408
763 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
764
765 /*
766 * AC3_BASE_CSR: AC_VO base address.
767 */
768 #define AC3_BASE_CSR 0x340c
769 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
770
771 /*
772 * MGMT_BASE_CSR: MGMT ring base address.
773 */
774 #define MGMT_BASE_CSR 0x3410
775 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
776
777 /*
778 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
779 */
780 #define TX_RING_CSR0 0x3418
781 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
782 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
783 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
784 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
785
786 /*
787 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
788 * TXD_SIZE: In unit of 32-bit.
789 */
790 #define TX_RING_CSR1 0x341c
791 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
792 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
793 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
794
795 /*
796 * AIFSN_CSR: AIFSN for each EDCA AC.
797 * AIFSN0: For AC_BK.
798 * AIFSN1: For AC_BE.
799 * AIFSN2: For AC_VI.
800 * AIFSN3: For AC_VO.
801 */
802 #define AIFSN_CSR 0x3420
803 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
804 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
805 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
806 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
807
808 /*
809 * CWMIN_CSR: CWmin for each EDCA AC.
810 * CWMIN0: For AC_BK.
811 * CWMIN1: For AC_BE.
812 * CWMIN2: For AC_VI.
813 * CWMIN3: For AC_VO.
814 */
815 #define CWMIN_CSR 0x3424
816 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
817 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
818 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
819 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
820
821 /*
822 * CWMAX_CSR: CWmax for each EDCA AC.
823 * CWMAX0: For AC_BK.
824 * CWMAX1: For AC_BE.
825 * CWMAX2: For AC_VI.
826 * CWMAX3: For AC_VO.
827 */
828 #define CWMAX_CSR 0x3428
829 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
830 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
831 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
832 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
833
834 /*
835 * TX_DMA_DST_CSR: TX DMA destination
836 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
837 */
838 #define TX_DMA_DST_CSR 0x342c
839 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
840 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
841 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
842 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
843 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
844
845 /*
846 * TX_CNTL_CSR: KICK/Abort TX.
847 * KICK_TX_AC0: For AC_BK.
848 * KICK_TX_AC1: For AC_BE.
849 * KICK_TX_AC2: For AC_VI.
850 * KICK_TX_AC3: For AC_VO.
851 * ABORT_TX_AC0: For AC_BK.
852 * ABORT_TX_AC1: For AC_BE.
853 * ABORT_TX_AC2: For AC_VI.
854 * ABORT_TX_AC3: For AC_VO.
855 */
856 #define TX_CNTL_CSR 0x3430
857 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
858 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
859 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
860 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
861 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
862 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
863 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
864 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
865 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
866 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
867
868 /*
869 * LOAD_TX_RING_CSR: Load RX de
870 */
871 #define LOAD_TX_RING_CSR 0x3434
872 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
873 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
874 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
875 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
876 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
877
878 /*
879 * Several read-only registers, for debugging.
880 */
881 #define AC0_TXPTR_CSR 0x3438
882 #define AC1_TXPTR_CSR 0x343c
883 #define AC2_TXPTR_CSR 0x3440
884 #define AC3_TXPTR_CSR 0x3444
885 #define MGMT_TXPTR_CSR 0x3448
886
887 /*
888 * RX_BASE_CSR
889 */
890 #define RX_BASE_CSR 0x3450
891 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
892
893 /*
894 * RX_RING_CSR.
895 * RXD_SIZE: In unit of 32-bit.
896 */
897 #define RX_RING_CSR 0x3454
898 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
899 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
900 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
901
902 /*
903 * RX_CNTL_CSR
904 */
905 #define RX_CNTL_CSR 0x3458
906 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
907 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
908
909 /*
910 * RXPTR_CSR: Read-only, for debugging.
911 */
912 #define RXPTR_CSR 0x345c
913
914 /*
915 * PCI_CFG_CSR
916 */
917 #define PCI_CFG_CSR 0x3460
918
919 /*
920 * BUF_FORMAT_CSR
921 */
922 #define BUF_FORMAT_CSR 0x3464
923
924 /*
925 * INT_SOURCE_CSR: Interrupt source register.
926 * Write one to clear corresponding bit.
927 */
928 #define INT_SOURCE_CSR 0x3468
929 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
930 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
931 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
932 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
933 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
934 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
935 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
936 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
937 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
938 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
939
940 /*
941 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
942 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
943 */
944 #define INT_MASK_CSR 0x346c
945 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
946 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
947 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
948 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
949 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
950 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
951 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
952 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
953 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
954 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
955 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
956 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
957
958 /*
959 * E2PROM_CSR: EEPROM control register.
960 * RELOAD: Write 1 to reload eeprom content.
961 * TYPE_93C46: 1: 93c46, 0:93c66.
962 * LOAD_STATUS: 1:loading, 0:done.
963 */
964 #define E2PROM_CSR 0x3470
965 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
966 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
967 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
968 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
969 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
970 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
971 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
972
973 /*
974 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
975 * AC0_TX_OP: For AC_BK, in unit of 32us.
976 * AC1_TX_OP: For AC_BE, in unit of 32us.
977 */
978 #define AC_TXOP_CSR0 0x3474
979 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
980 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
981
982 /*
983 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
984 * AC2_TX_OP: For AC_VI, in unit of 32us.
985 * AC3_TX_OP: For AC_VO, in unit of 32us.
986 */
987 #define AC_TXOP_CSR1 0x3478
988 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
989 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
990
991 /*
992 * DMA_STATUS_CSR
993 */
994 #define DMA_STATUS_CSR 0x3480
995
996 /*
997 * TEST_MODE_CSR
998 */
999 #define TEST_MODE_CSR 0x3484
1000
1001 /*
1002 * UART0_TX_CSR
1003 */
1004 #define UART0_TX_CSR 0x3488
1005
1006 /*
1007 * UART0_RX_CSR
1008 */
1009 #define UART0_RX_CSR 0x348c
1010
1011 /*
1012 * UART0_FRAME_CSR
1013 */
1014 #define UART0_FRAME_CSR 0x3490
1015
1016 /*
1017 * UART0_BUFFER_CSR
1018 */
1019 #define UART0_BUFFER_CSR 0x3494
1020
1021 /*
1022 * IO_CNTL_CSR
1023 */
1024 #define IO_CNTL_CSR 0x3498
1025
1026 /*
1027 * UART_INT_SOURCE_CSR
1028 */
1029 #define UART_INT_SOURCE_CSR 0x34a8
1030
1031 /*
1032 * UART_INT_MASK_CSR
1033 */
1034 #define UART_INT_MASK_CSR 0x34ac
1035
1036 /*
1037 * PBF_QUEUE_CSR
1038 */
1039 #define PBF_QUEUE_CSR 0x34b0
1040
1041 /*
1042 * Firmware DMA registers.
1043 * Firmware DMA registers are dedicated for MCU usage
1044 * and should not be touched by host driver.
1045 * Therefore we skip the definition of these registers.
1046 */
1047 #define FW_TX_BASE_CSR 0x34c0
1048 #define FW_TX_START_CSR 0x34c4
1049 #define FW_TX_LAST_CSR 0x34c8
1050 #define FW_MODE_CNTL_CSR 0x34cc
1051 #define FW_TXPTR_CSR 0x34d0
1052
1053 /*
1054 * 8051 firmware image.
1055 */
1056 #define FIRMWARE_RT2561 "rt2561.bin"
1057 #define FIRMWARE_RT2561s "rt2561s.bin"
1058 #define FIRMWARE_RT2661 "rt2661.bin"
1059 #define FIRMWARE_IMAGE_BASE 0x4000
1060
1061 /*
1062 * BBP registers.
1063 * The wordsize of the BBP is 8 bits.
1064 */
1065
1066 /*
1067 * R2
1068 */
1069 #define BBP_R2_BG_MODE FIELD8(0x20)
1070
1071 /*
1072 * R3
1073 */
1074 #define BBP_R3_SMART_MODE FIELD8(0x01)
1075
1076 /*
1077 * R4: RX antenna control
1078 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1079 */
1080
1081 /*
1082 * ANTENNA_CONTROL semantics (guessed):
1083 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1084 * 0x2: Hardware diversity.
1085 */
1086 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
1087 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
1088
1089 /*
1090 * R77
1091 */
1092 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
1093
1094 /*
1095 * RF registers
1096 */
1097
1098 /*
1099 * RF 3
1100 */
1101 #define RF3_TXPOWER FIELD32(0x00003e00)
1102
1103 /*
1104 * RF 4
1105 */
1106 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1107
1108 /*
1109 * EEPROM content.
1110 * The wordsize of the EEPROM is 16 bits.
1111 */
1112
1113 /*
1114 * HW MAC address.
1115 */
1116 #define EEPROM_MAC_ADDR_0 0x0002
1117 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1118 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1119 #define EEPROM_MAC_ADDR1 0x0004
1120 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1121 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1122 #define EEPROM_MAC_ADDR_2 0x0006
1123 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1124 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1125
1126 /*
1127 * EEPROM antenna.
1128 * ANTENNA_NUM: Number of antenna's.
1129 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1130 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1131 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1132 * DYN_TXAGC: Dynamic TX AGC control.
1133 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1134 * RF_TYPE: Rf_type of this adapter.
1135 */
1136 #define EEPROM_ANTENNA 0x0010
1137 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1138 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1139 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1140 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1141 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1142 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1143 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1144
1145 /*
1146 * EEPROM NIC config.
1147 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1148 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1149 * CARDBUS_ACCEL: 0:enable, 1:disable.
1150 * EXTERNAL_LNA_A: External LNA enable for 5G.
1151 */
1152 #define EEPROM_NIC 0x0011
1153 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1154 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1155 #define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1156 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1157 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1158 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1159
1160 /*
1161 * EEPROM geography.
1162 * GEO_A: Default geographical setting for 5GHz band
1163 * GEO: Default geographical setting.
1164 */
1165 #define EEPROM_GEOGRAPHY 0x0012
1166 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1167 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1168
1169 /*
1170 * EEPROM BBP.
1171 */
1172 #define EEPROM_BBP_START 0x0013
1173 #define EEPROM_BBP_SIZE 16
1174 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1175 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1176
1177 /*
1178 * EEPROM TXPOWER 802.11G
1179 */
1180 #define EEPROM_TXPOWER_G_START 0x0023
1181 #define EEPROM_TXPOWER_G_SIZE 7
1182 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1183 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1184
1185 /*
1186 * EEPROM Frequency
1187 */
1188 #define EEPROM_FREQ 0x002f
1189 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1190 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1191 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1192
1193 /*
1194 * EEPROM LED.
1195 * POLARITY_RDY_G: Polarity RDY_G setting.
1196 * POLARITY_RDY_A: Polarity RDY_A setting.
1197 * POLARITY_ACT: Polarity ACT setting.
1198 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1199 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1200 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1201 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1202 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1203 * LED_MODE: Led mode.
1204 */
1205 #define EEPROM_LED 0x0030
1206 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1207 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1208 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1209 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1210 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1211 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1212 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1213 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1214 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1215
1216 /*
1217 * EEPROM TXPOWER 802.11A
1218 */
1219 #define EEPROM_TXPOWER_A_START 0x0031
1220 #define EEPROM_TXPOWER_A_SIZE 12
1221 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1222 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1223
1224 /*
1225 * EEPROM RSSI offset 802.11BG
1226 */
1227 #define EEPROM_RSSI_OFFSET_BG 0x004d
1228 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1229 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1230
1231 /*
1232 * EEPROM RSSI offset 802.11A
1233 */
1234 #define EEPROM_RSSI_OFFSET_A 0x004e
1235 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1236 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1237
1238 /*
1239 * MCU mailbox commands.
1240 */
1241 #define MCU_SLEEP 0x30
1242 #define MCU_WAKEUP 0x31
1243 #define MCU_LED 0x50
1244 #define MCU_LED_STRENGTH 0x52
1245
1246 /*
1247 * DMA descriptor defines.
1248 */
1249 #define TXD_DESC_SIZE ( 16 * sizeof(__le32) )
1250 #define RXD_DESC_SIZE ( 16 * sizeof(__le32) )
1251
1252 /*
1253 * TX descriptor format for TX, PRIO and Beacon Ring.
1254 */
1255
1256 /*
1257 * Word0
1258 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1259 * KEY_TABLE: Use per-client pairwise KEY table.
1260 * KEY_INDEX:
1261 * Key index (0~31) to the pairwise KEY table.
1262 * 0~3 to shared KEY table 0 (BSS0).
1263 * 4~7 to shared KEY table 1 (BSS1).
1264 * 8~11 to shared KEY table 2 (BSS2).
1265 * 12~15 to shared KEY table 3 (BSS3).
1266 * BURST: Next frame belongs to same "burst" event.
1267 */
1268 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1269 #define TXD_W0_VALID FIELD32(0x00000002)
1270 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1271 #define TXD_W0_ACK FIELD32(0x00000008)
1272 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1273 #define TXD_W0_OFDM FIELD32(0x00000020)
1274 #define TXD_W0_IFS FIELD32(0x00000040)
1275 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1276 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1277 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1278 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1279 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1280 #define TXD_W0_BURST FIELD32(0x10000000)
1281 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1282
1283 /*
1284 * Word1
1285 * HOST_Q_ID: EDCA/HCCA queue ID.
1286 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1287 * BUFFER_COUNT: Number of buffers in this TXD.
1288 */
1289 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1290 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1291 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1292 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1293 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1294 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1295 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1296 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1297
1298 /*
1299 * Word2: PLCP information
1300 */
1301 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1302 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1303 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1304 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1305
1306 /*
1307 * Word3
1308 */
1309 #define TXD_W3_IV FIELD32(0xffffffff)
1310
1311 /*
1312 * Word4
1313 */
1314 #define TXD_W4_EIV FIELD32(0xffffffff)
1315
1316 /*
1317 * Word5
1318 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1319 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1320 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1321 * WAITING_DMA_DONE_INT: TXD been filled with data
1322 * and waiting for TxDoneISR housekeeping.
1323 */
1324 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1325 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1326 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1327 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1328 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1329
1330 /*
1331 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1332 * through TXFIFO. MAC block use this TXINFO to control the transmission
1333 * behavior of this frame.
1334 * The following fields are not used by MAC block.
1335 * They are used by DMA block and HOST driver only.
1336 * Once a frame has been DMA to ASIC, all the following fields are useless
1337 * to ASIC.
1338 */
1339
1340 /*
1341 * Word6-10: Buffer physical address
1342 */
1343 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1344 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1345 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1346 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1347 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1348
1349 /*
1350 * Word11-13: Buffer length
1351 */
1352 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1353 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1354 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1355 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1356 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1357
1358 /*
1359 * Word14
1360 */
1361 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1362
1363 /*
1364 * Word15
1365 */
1366 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1367
1368 /*
1369 * RX descriptor format for RX Ring.
1370 */
1371
1372 /*
1373 * Word0
1374 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1375 * KEY_INDEX: Decryption key actually used.
1376 */
1377 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1378 #define RXD_W0_DROP FIELD32(0x00000002)
1379 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1380 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1381 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1382 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1383 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1384 #define RXD_W0_OFDM FIELD32(0x00000080)
1385 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1386 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1387 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1388 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1389
1390 /*
1391 * Word1
1392 * SIGNAL: RX raw data rate reported by BBP.
1393 */
1394 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1395 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1396 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1397 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1398
1399 /*
1400 * Word2
1401 * IV: Received IV of originally encrypted.
1402 */
1403 #define RXD_W2_IV FIELD32(0xffffffff)
1404
1405 /*
1406 * Word3
1407 * EIV: Received EIV of originally encrypted.
1408 */
1409 #define RXD_W3_EIV FIELD32(0xffffffff)
1410
1411 /*
1412 * Word4
1413 */
1414 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1415
1416 /*
1417 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1418 * and passed to the HOST driver.
1419 * The following fields are for DMA block and HOST usage only.
1420 * Can't be touched by ASIC MAC block.
1421 */
1422
1423 /*
1424 * Word5
1425 */
1426 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1427
1428 /*
1429 * Word6-15: Reserved
1430 */
1431 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1432 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1433 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1434 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1435 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1436 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1437 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1438 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1439 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1440 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1441
1442 /*
1443 * Macro's for converting txpower from EEPROM to dscape value
1444 * and from dscape value to register value.
1445 */
1446 #define MIN_TXPOWER 0
1447 #define MAX_TXPOWER 31
1448 #define DEFAULT_TXPOWER 24
1449
1450 #define TXPOWER_FROM_DEV(__txpower) \
1451 ({ \
1452 ((__txpower) > MAX_TXPOWER) ? \
1453 DEFAULT_TXPOWER : (__txpower); \
1454 })
1455
1456 #define TXPOWER_TO_DEV(__txpower) \
1457 ({ \
1458 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1459 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1460 (__txpower)); \
1461 })
1462
1463 #endif /* RT61PCI_H */
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