| blob | 92ba0902d107254725cbb0b6c230b2e1acbc57f4 |
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt2500pci
23 Abstract: Data structures and registers for the rt2500pci module.
24 Supported chipsets: RT2560.
25 */
27 #ifndef RT2500PCI_H
28 #define RT2500PCI_H
30 /*
31 * RF chip defines.
32 */
33 #define RF2522 0x0000
34 #define RF2523 0x0001
35 #define RF2524 0x0002
36 #define RF2525 0x0003
37 #define RF2525E 0x0004
38 #define RF5222 0x0010
40 /*
41 * RT2560 version
42 */
43 #define RT2560_VERSION_B 2
44 #define RT2560_VERSION_C 3
45 #define RT2560_VERSION_D 4
47 /*
48 * Signal information.
49 * Defaul offset is required for RSSI <-> dBm conversion.
50 */
51 #define MAX_SIGNAL 100
52 #define MAX_RX_SSI -1
53 #define DEFAULT_RSSI_OFFSET 121
55 /*
56 * Register layout information.
57 */
58 #define CSR_REG_BASE 0x0000
59 #define CSR_REG_SIZE 0x0174
60 #define EEPROM_BASE 0x0000
61 #define EEPROM_SIZE 0x0200
62 #define BBP_SIZE 0x0040
63 #define RF_SIZE 0x0014
65 /*
66 * Control/Status Registers(CSR).
67 * Some values are set in TU, whereas 1 TU == 1024 us.
68 */
70 /*
71 * CSR0: ASIC revision number.
72 */
73 #define CSR0 0x0000
75 /*
76 * CSR1: System control register.
77 * SOFT_RESET: Software reset, 1: reset, 0: normal.
78 * BBP_RESET: Hardware reset, 1: reset, 0, release.
79 * HOST_READY: Host ready after initialization.
80 */
81 #define CSR1 0x0004
82 #define CSR1_SOFT_RESET FIELD32(0x00000001)
83 #define CSR1_BBP_RESET FIELD32(0x00000002)
84 #define CSR1_HOST_READY FIELD32(0x00000004)
86 /*
87 * CSR2: System admin status register (invalid).
88 */
89 #define CSR2 0x0008
91 /*
92 * CSR3: STA MAC address register 0.
93 */
94 #define CSR3 0x000c
95 #define CSR3_BYTE0 FIELD32(0x000000ff)
96 #define CSR3_BYTE1 FIELD32(0x0000ff00)
97 #define CSR3_BYTE2 FIELD32(0x00ff0000)
98 #define CSR3_BYTE3 FIELD32(0xff000000)
100 /*
101 * CSR4: STA MAC address register 1.
102 */
103 #define CSR4 0x0010
104 #define CSR4_BYTE4 FIELD32(0x000000ff)
105 #define CSR4_BYTE5 FIELD32(0x0000ff00)
107 /*
108 * CSR5: BSSID register 0.
109 */
110 #define CSR5 0x0014
111 #define CSR5_BYTE0 FIELD32(0x000000ff)
112 #define CSR5_BYTE1 FIELD32(0x0000ff00)
113 #define CSR5_BYTE2 FIELD32(0x00ff0000)
114 #define CSR5_BYTE3 FIELD32(0xff000000)
116 /*
117 * CSR6: BSSID register 1.
118 */
119 #define CSR6 0x0018
120 #define CSR6_BYTE4 FIELD32(0x000000ff)
121 #define CSR6_BYTE5 FIELD32(0x0000ff00)
123 /*
124 * CSR7: Interrupt source register.
125 * Write 1 to clear.
126 * TBCN_EXPIRE: Beacon timer expired interrupt.
127 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
128 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
129 * TXDONE_TXRING: Tx ring transmit done interrupt.
130 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
131 * TXDONE_PRIORING: Priority ring transmit done interrupt.
132 * RXDONE: Receive done interrupt.
133 * DECRYPTION_DONE: Decryption done interrupt.
134 * ENCRYPTION_DONE: Encryption done interrupt.
135 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
136 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
137 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
138 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
139 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
140 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
141 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
142 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
143 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
144 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
145 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
147 */
148 #define CSR7 0x001c
149 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
150 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
151 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
152 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
153 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
154 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
155 #define CSR7_RXDONE FIELD32(0x00000040)
156 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
157 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
158 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
159 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
160 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
161 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
162 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
163 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
164 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
165 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
166 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
167 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
168 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
170 /*
171 * CSR8: Interrupt mask register.
172 * Write 1 to mask interrupt.
173 * TBCN_EXPIRE: Beacon timer expired interrupt.
174 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
175 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
176 * TXDONE_TXRING: Tx ring transmit done interrupt.
177 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
178 * TXDONE_PRIORING: Priority ring transmit done interrupt.
179 * RXDONE: Receive done interrupt.
180 * DECRYPTION_DONE: Decryption done interrupt.
181 * ENCRYPTION_DONE: Encryption done interrupt.
182 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
183 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
184 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
185 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
186 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
187 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
188 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
189 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
190 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
191 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
192 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
193 */
194 #define CSR8 0x0020
195 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
196 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
197 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
198 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
199 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
200 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
201 #define CSR8_RXDONE FIELD32(0x00000040)
202 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
203 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
204 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
205 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
206 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
207 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
208 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
209 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
210 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
211 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
212 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
213 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
214 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
216 /*
217 * CSR9: Maximum frame length register.
218 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
219 */
220 #define CSR9 0x0024
221 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
223 /*
224 * SECCSR0: WEP control register.
225 * KICK_DECRYPT: Kick decryption engine, self-clear.
226 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
227 * DESC_ADDRESS: Descriptor physical address of frame.
228 */
229 #define SECCSR0 0x0028
230 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
231 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
232 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
234 /*
235 * CSR11: Back-off control register.
236 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
237 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
238 * SLOT_TIME: Slot time, default is 20us for 802.11b
239 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
240 * LONG_RETRY: Long retry count.
241 * SHORT_RETRY: Short retry count.
242 */
243 #define CSR11 0x002c
244 #define CSR11_CWMIN FIELD32(0x0000000f)
245 #define CSR11_CWMAX FIELD32(0x000000f0)
246 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
247 #define CSR11_CW_SELECT FIELD32(0x00002000)
248 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
249 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
251 /*
252 * CSR12: Synchronization configuration register 0.
253 * All units in 1/16 TU.
254 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
255 * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
256 */
257 #define CSR12 0x0030
258 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
259 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
261 /*
262 * CSR13: Synchronization configuration register 1.
263 * All units in 1/16 TU.
264 * ATIMW_DURATION: Atim window duration.
265 * CFP_PERIOD: Cfp period, default is 0 TU.
266 */
267 #define CSR13 0x0034
268 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
269 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
271 /*
272 * CSR14: Synchronization control register.
273 * TSF_COUNT: Enable tsf auto counting.
274 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
275 * TBCN: Enable tbcn with reload value.
276 * TCFP: Enable tcfp & cfp / cp switching.
277 * TATIMW: Enable tatimw & atim window switching.
278 * BEACON_GEN: Enable beacon generator.
279 * CFP_COUNT_PRELOAD: Cfp count preload value.
280 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
281 */
282 #define CSR14 0x0038
283 #define CSR14_TSF_COUNT FIELD32(0x00000001)
284 #define CSR14_TSF_SYNC FIELD32(0x00000006)
285 #define CSR14_TBCN FIELD32(0x00000008)
286 #define CSR14_TCFP FIELD32(0x00000010)
287 #define CSR14_TATIMW FIELD32(0x00000020)
288 #define CSR14_BEACON_GEN FIELD32(0x00000040)
289 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
290 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
292 /*
293 * CSR15: Synchronization status register.
294 * CFP: ASIC is in contention-free period.
295 * ATIMW: ASIC is in ATIM window.
296 * BEACON_SENT: Beacon is send.
297 */
298 #define CSR15 0x003c
299 #define CSR15_CFP FIELD32(0x00000001)
300 #define CSR15_ATIMW FIELD32(0x00000002)
301 #define CSR15_BEACON_SENT FIELD32(0x00000004)
303 /*
304 * CSR16: TSF timer register 0.
305 */
306 #define CSR16 0x0040
307 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
309 /*
310 * CSR17: TSF timer register 1.
311 */
312 #define CSR17 0x0044
313 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
315 /*
316 * CSR18: IFS timer register 0.
317 * SIFS: Sifs, default is 10 us.
318 * PIFS: Pifs, default is 30 us.
319 */
320 #define CSR18 0x0048
321 #define CSR18_SIFS FIELD32(0x000001ff)
322 #define CSR18_PIFS FIELD32(0x001f0000)
324 /*
325 * CSR19: IFS timer register 1.
326 * DIFS: Difs, default is 50 us.
327 * EIFS: Eifs, default is 364 us.
328 */
329 #define CSR19 0x004c
330 #define CSR19_DIFS FIELD32(0x0000ffff)
331 #define CSR19_EIFS FIELD32(0xffff0000)
333 /*
334 * CSR20: Wakeup timer register.
335 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
336 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
337 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
338 */
339 #define CSR20 0x0050
340 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
341 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
342 #define CSR20_AUTOWAKE FIELD32(0x01000000)
344 /*
345 * CSR21: EEPROM control register.
346 * RELOAD: Write 1 to reload eeprom content.
347 * TYPE_93C46: 1: 93c46, 0:93c66.
348 */
349 #define CSR21 0x0054
350 #define CSR21_RELOAD FIELD32(0x00000001)
351 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
352 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
353 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
354 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
355 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
357 /*
358 * CSR22: CFP control register.
359 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
360 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
361 */
362 #define CSR22 0x0058
363 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
364 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
366 /*
367 * Transmit related CSRs.
368 * Some values are set in TU, whereas 1 TU == 1024 us.
369 */
371 /*
372 * TXCSR0: TX Control Register.
373 * KICK_TX: Kick tx ring.
374 * KICK_ATIM: Kick atim ring.
375 * KICK_PRIO: Kick priority ring.
376 * ABORT: Abort all transmit related ring operation.
377 */
378 #define TXCSR0 0x0060
379 #define TXCSR0_KICK_TX FIELD32(0x00000001)
380 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
381 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
382 #define TXCSR0_ABORT FIELD32(0x00000008)
384 /*
385 * TXCSR1: TX Configuration Register.
386 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
387 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
388 * TSF_OFFSET: Insert tsf offset.
389 * AUTORESPONDER: Enable auto responder which include ack & cts.
390 */
391 #define TXCSR1 0x0064
392 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
393 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
394 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
395 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
397 /*
398 * TXCSR2: Tx descriptor configuration register.
399 * TXD_SIZE: Tx descriptor size, default is 48.
400 * NUM_TXD: Number of tx entries in ring.
401 * NUM_ATIM: Number of atim entries in ring.
402 * NUM_PRIO: Number of priority entries in ring.
403 */
404 #define TXCSR2 0x0068
405 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
406 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
407 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
408 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
410 /*
411 * TXCSR3: TX Ring Base address register.
412 */
413 #define TXCSR3 0x006c
414 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
416 /*
417 * TXCSR4: TX Atim Ring Base address register.
418 */
419 #define TXCSR4 0x0070
420 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
422 /*
423 * TXCSR5: TX Prio Ring Base address register.
424 */
425 #define TXCSR5 0x0074
426 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
428 /*
429 * TXCSR6: Beacon Base address register.
430 */
431 #define TXCSR6 0x0078
432 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
434 /*
435 * TXCSR7: Auto responder control register.
436 * AR_POWERMANAGEMENT: Auto responder power management bit.
437 */
438 #define TXCSR7 0x007c
439 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
441 /*
442 * TXCSR8: CCK Tx BBP register.
443 */
444 #define TXCSR8 0x0098
445 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
446 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
447 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
448 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
449 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
450 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
451 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
452 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
454 /*
455 * TXCSR9: OFDM TX BBP registers
456 * OFDM_SIGNAL: BBP rate field address for OFDM.
457 * OFDM_SERVICE: BBP service field address for OFDM.
458 * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
459 * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
460 */
461 #define TXCSR9 0x0094
462 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
463 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
464 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
465 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
467 /*
468 * Receive related CSRs.
469 * Some values are set in TU, whereas 1 TU == 1024 us.
470 */
472 /*
473 * RXCSR0: RX Control Register.
474 * DISABLE_RX: Disable rx engine.
475 * DROP_CRC: Drop crc error.
476 * DROP_PHYSICAL: Drop physical error.
477 * DROP_CONTROL: Drop control frame.
478 * DROP_NOT_TO_ME: Drop not to me unicast frame.
479 * DROP_TODS: Drop frame tods bit is true.
480 * DROP_VERSION_ERROR: Drop version error frame.
481 * PASS_CRC: Pass all packets with crc attached.
482 * PASS_CRC: Pass all packets with crc attached.
483 * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
484 * DROP_MCAST: Drop multicast frames.
485 * DROP_BCAST: Drop broadcast frames.
486 * ENABLE_QOS: Accept QOS data frame and parse QOS field.
487 */
488 #define RXCSR0 0x0080
489 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
490 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
491 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
492 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
493 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
494 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
495 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
496 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
497 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
498 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
499 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
500 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
502 /*
503 * RXCSR1: RX descriptor configuration register.
504 * RXD_SIZE: Rx descriptor size, default is 32b.
505 * NUM_RXD: Number of rx entries in ring.
506 */
507 #define RXCSR1 0x0084
508 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
509 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
511 /*
512 * RXCSR2: RX Ring base address register.
513 */
514 #define RXCSR2 0x0088
515 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
517 /*
518 * RXCSR3: BBP ID register for Rx operation.
519 * BBP_ID#: BBP register # id.
520 * BBP_ID#_VALID: BBP register # id is valid or not.
521 */
522 #define RXCSR3 0x0090
523 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
524 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
525 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
526 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
527 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
528 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
529 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
530 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
532 /*
533 * ARCSR1: Auto Responder PLCP config register 1.
534 * AR_BBP_DATA#: Auto responder BBP register # data.
535 * AR_BBP_ID#: Auto responder BBP register # Id.
536 */
537 #define ARCSR1 0x009c
538 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
539 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
540 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
541 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
543 /*
544 * Miscellaneous Registers.
545 * Some values are set in TU, whereas 1 TU == 1024 us.
547 */
549 /*
550 * PCICSR: PCI control register.
551 * BIG_ENDIAN: 1: big endian, 0: little endian.
552 * RX_TRESHOLD: Rx threshold in dw to start pci access
553 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
554 * TX_TRESHOLD: Tx threshold in dw to start pci access
555 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
556 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
557 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
558 * READ_MULTIPLE: Enable memory read multiple.
559 * WRITE_INVALID: Enable memory write & invalid.
560 */
561 #define PCICSR 0x008c
562 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
563 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
564 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
565 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
566 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
567 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
568 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
570 /*
571 * CNT0: FCS error count.
572 * FCS_ERROR: FCS error count, cleared when read.
573 */
574 #define CNT0 0x00a0
575 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
577 /*
578 * Statistic Register.
579 * CNT1: PLCP error count.
580 * CNT2: Long error count.
581 */
582 #define TIMECSR2 0x00a8
583 #define CNT1 0x00ac
584 #define CNT2 0x00b0
585 #define TIMECSR3 0x00b4
587 /*
588 * CNT3: CCA false alarm count.
589 */
590 #define CNT3 0x00b8
591 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
593 /*
594 * Statistic Register.
595 * CNT4: Rx FIFO overflow count.
596 * CNT5: Tx FIFO underrun count.
597 */
598 #define CNT4 0x00bc
599 #define CNT5 0x00c0
601 /*
602 * Baseband Control Register.
603 */
605 /*
606 * PWRCSR0: Power mode configuration register.
607 */
608 #define PWRCSR0 0x00c4
610 /*
611 * Power state transition time registers.
612 */
613 #define PSCSR0 0x00c8
614 #define PSCSR1 0x00cc
615 #define PSCSR2 0x00d0
616 #define PSCSR3 0x00d4
618 /*
619 * PWRCSR1: Manual power control / status register.
620 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
621 * SET_STATE: Set state. Write 1 to trigger, self cleared.
622 * BBP_DESIRE_STATE: BBP desired state.
623 * RF_DESIRE_STATE: RF desired state.
624 * BBP_CURR_STATE: BBP current state.
625 * RF_CURR_STATE: RF current state.
626 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
627 */
628 #define PWRCSR1 0x00d8
629 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
630 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
631 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
632 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
633 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
634 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
636 /*
637 * TIMECSR: Timer control register.
638 * US_COUNT: 1 us timer count in units of clock cycles.
639 * US_64_COUNT: 64 us timer count in units of 1 us timer.
640 * BEACON_EXPECT: Beacon expect window.
641 */
642 #define TIMECSR 0x00dc
643 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
644 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
645 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
647 /*
648 * MACCSR0: MAC configuration register 0.
649 */
650 #define MACCSR0 0x00e0
652 /*
653 * MACCSR1: MAC configuration register 1.
654 * KICK_RX: Kick one-shot rx in one-shot rx mode.
655 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
656 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
657 * AUTO_TXBBP: Auto tx logic access bbp control register.
658 * AUTO_RXBBP: Auto rx logic access bbp control register.
659 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
660 * INTERSIL_IF: Intersil if calibration pin.
661 */
662 #define MACCSR1 0x00e4
663 #define MACCSR1_KICK_RX FIELD32(0x00000001)
664 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
665 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
666 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
667 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
668 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
669 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
671 /*
672 * RALINKCSR: Ralink Rx auto-reset BBCR.
673 * AR_BBP_DATA#: Auto reset BBP register # data.
674 * AR_BBP_ID#: Auto reset BBP register # id.
675 */
676 #define RALINKCSR 0x00e8
677 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
678 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
679 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
680 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
681 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
682 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
684 /*
685 * BCNCSR: Beacon interval control register.
686 * CHANGE: Write one to change beacon interval.
687 * DELTATIME: The delta time value.
688 * NUM_BEACON: Number of beacon according to mode.
689 * MODE: Please refer to asic specs.
690 * PLUS: Plus or minus delta time value.
691 */
692 #define BCNCSR 0x00ec
693 #define BCNCSR_CHANGE FIELD32(0x00000001)
694 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
695 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
696 #define BCNCSR_MODE FIELD32(0x00006000)
697 #define BCNCSR_PLUS FIELD32(0x00008000)
699 /*
700 * BBP / RF / IF Control Register.
701 */
703 /*
704 * BBPCSR: BBP serial control register.
705 * VALUE: Register value to program into BBP.
706 * REGNUM: Selected BBP register.
707 * BUSY: 1: asic is busy execute BBP programming.
708 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
709 */
710 #define BBPCSR 0x00f0
711 #define BBPCSR_VALUE FIELD32(0x000000ff)
712 #define BBPCSR_REGNUM FIELD32(0x00007f00)
713 #define BBPCSR_BUSY FIELD32(0x00008000)
714 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
716 /*
717 * RFCSR: RF serial control register.
718 * VALUE: Register value + id to program into rf/if.
719 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
720 * IF_SELECT: Chip to program: 0: rf, 1: if.
721 * PLL_LD: Rf pll_ld status.
722 * BUSY: 1: asic is busy execute rf programming.
723 */
724 #define RFCSR 0x00f4
725 #define RFCSR_VALUE FIELD32(0x00ffffff)
726 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
727 #define RFCSR_IF_SELECT FIELD32(0x20000000)
728 #define RFCSR_PLL_LD FIELD32(0x40000000)
729 #define RFCSR_BUSY FIELD32(0x80000000)
731 /*
732 * LEDCSR: LED control register.
733 * ON_PERIOD: On period, default 70ms.
734 * OFF_PERIOD: Off period, default 30ms.
735 * LINK: 0: linkoff, 1: linkup.
736 * ACTIVITY: 0: idle, 1: active.
737 * LINK_POLARITY: 0: active low, 1: active high.
738 * ACTIVITY_POLARITY: 0: active low, 1: active high.
739 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
740 */
741 #define LEDCSR 0x00f8
742 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
743 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
744 #define LEDCSR_LINK FIELD32(0x00010000)
745 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
746 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
747 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
748 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
750 /*
751 * AES control register.
752 */
753 #define SECCSR3 0x00fc
755 /*
756 * ASIC pointer information.
757 * RXPTR: Current RX ring address.
758 * TXPTR: Current Tx ring address.
759 * PRIPTR: Current Priority ring address.
760 * ATIMPTR: Current ATIM ring address.
761 */
762 #define RXPTR 0x0100
763 #define TXPTR 0x0104
764 #define PRIPTR 0x0108
765 #define ATIMPTR 0x010c
767 /*
768 * TXACKCSR0: TX ACK timeout.
769 */
770 #define TXACKCSR0 0x0110
772 /*
773 * ACK timeout count registers.
774 * ACKCNT0: TX ACK timeout count.
775 * ACKCNT1: RX ACK timeout count.
776 */
777 #define ACKCNT0 0x0114
778 #define ACKCNT1 0x0118
780 /*
781 * GPIO and others.
782 */
784 /*
785 * GPIOCSR: GPIO control register.
786 */
787 #define GPIOCSR 0x0120
788 #define GPIOCSR_BIT0 FIELD32(0x00000001)
789 #define GPIOCSR_BIT1 FIELD32(0x00000002)
790 #define GPIOCSR_BIT2 FIELD32(0x00000004)
791 #define GPIOCSR_BIT3 FIELD32(0x00000008)
792 #define GPIOCSR_BIT4 FIELD32(0x00000010)
793 #define GPIOCSR_BIT5 FIELD32(0x00000020)
794 #define GPIOCSR_BIT6 FIELD32(0x00000040)
795 #define GPIOCSR_BIT7 FIELD32(0x00000080)
796 #define GPIOCSR_DIR0 FIELD32(0x00000100)
797 #define GPIOCSR_DIR1 FIELD32(0x00000200)
798 #define GPIOCSR_DIR2 FIELD32(0x00000400)
799 #define GPIOCSR_DIR3 FIELD32(0x00000800)
800 #define GPIOCSR_DIR4 FIELD32(0x00001000)
801 #define GPIOCSR_DIR5 FIELD32(0x00002000)
802 #define GPIOCSR_DIR6 FIELD32(0x00004000)
803 #define GPIOCSR_DIR7 FIELD32(0x00008000)
805 /*
806 * FIFO pointer registers.
807 * FIFOCSR0: TX FIFO pointer.
808 * FIFOCSR1: RX FIFO pointer.
809 */
810 #define FIFOCSR0 0x0128
811 #define FIFOCSR1 0x012c
813 /*
814 * BCNCSR1: Tx BEACON offset time control register.
815 * PRELOAD: Beacon timer offset in units of usec.
816 * BEACON_CWMIN: 2^CwMin.
817 */
818 #define BCNCSR1 0x0130
819 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
820 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
822 /*
823 * MACCSR2: TX_PE to RX_PE turn-around time control register
824 * DELAY: RX_PE low width, in units of pci clock cycle.
825 */
826 #define MACCSR2 0x0134
827 #define MACCSR2_DELAY FIELD32(0x000000ff)
829 /*
830 * TESTCSR: TEST mode selection register.
831 */
832 #define TESTCSR 0x0138
834 /*
835 * ARCSR2: 1 Mbps ACK/CTS PLCP.
836 */
837 #define ARCSR2 0x013c
838 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
839 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
840 #define ARCSR2_LENGTH FIELD32(0xffff0000)
842 /*
843 * ARCSR3: 2 Mbps ACK/CTS PLCP.
844 */
845 #define ARCSR3 0x0140
846 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
847 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
848 #define ARCSR3_LENGTH FIELD32(0xffff0000)
850 /*
851 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
852 */
853 #define ARCSR4 0x0144
854 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
855 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
856 #define ARCSR4_LENGTH FIELD32(0xffff0000)
858 /*
859 * ARCSR5: 11 Mbps ACK/CTS PLCP.
860 */
861 #define ARCSR5 0x0148
862 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
863 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
864 #define ARCSR5_LENGTH FIELD32(0xffff0000)
866 /*
867 * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
868 */
869 #define ARTCSR0 0x014c
870 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
871 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
872 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
873 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
876 /*
877 * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
878 */
879 #define ARTCSR1 0x0150
880 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
881 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
882 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
883 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
885 /*
886 * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
887 */
888 #define ARTCSR2 0x0154
889 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
890 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
891 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
892 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
894 /*
895 * SECCSR1_RT2509: WEP control register.
896 * KICK_ENCRYPT: Kick encryption engine, self-clear.
897 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
898 * DESC_ADDRESS: Descriptor physical address of frame.
899 */
900 #define SECCSR1 0x0158
901 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
902 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
903 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
905 /*
906 * BBPCSR1: BBP TX configuration.
907 */
908 #define BBPCSR1 0x015c
909 #define BBPCSR1_CCK FIELD32(0x00000003)
910 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
911 #define BBPCSR1_OFDM FIELD32(0x00030000)
912 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
914 /*
915 * Dual band configuration registers.
916 * DBANDCSR0: Dual band configuration register 0.
917 * DBANDCSR1: Dual band configuration register 1.
918 */
919 #define DBANDCSR0 0x0160
920 #define DBANDCSR1 0x0164
922 /*
923 * BBPPCSR: BBP Pin control register.
924 */
925 #define BBPPCSR 0x0168
927 /*
928 * MAC special debug mode selection registers.
929 * DBGSEL0: MAC special debug mode selection register 0.
930 * DBGSEL1: MAC special debug mode selection register 1.
931 */
932 #define DBGSEL0 0x016c
933 #define DBGSEL1 0x0170
935 /*
936 * BISTCSR: BBP BIST register.
937 */
938 #define BISTCSR 0x0174
940 /*
941 * Multicast filter registers.
942 * MCAST0: Multicast filter register 0.
943 * MCAST1: Multicast filter register 1.
944 */
945 #define MCAST0 0x0178
946 #define MCAST1 0x017c
948 /*
949 * UART registers.
950 * UARTCSR0: UART1 TX register.
951 * UARTCSR1: UART1 RX register.
952 * UARTCSR3: UART1 frame control register.
953 * UARTCSR4: UART1 buffer control register.
954 * UART2CSR0: UART2 TX register.
955 * UART2CSR1: UART2 RX register.
956 * UART2CSR3: UART2 frame control register.
957 * UART2CSR4: UART2 buffer control register.
958 */
959 #define UARTCSR0 0x0180
960 #define UARTCSR1 0x0184
961 #define UARTCSR3 0x0188
962 #define UARTCSR4 0x018c
963 #define UART2CSR0 0x0190
964 #define UART2CSR1 0x0194
965 #define UART2CSR3 0x0198
966 #define UART2CSR4 0x019c
968 /*
969 * BBP registers.
970 * The wordsize of the BBP is 8 bits.
971 */
973 /*
974 * R2: TX antenna control
975 */
976 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
977 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
979 /*
980 * R14: RX antenna control
981 */
982 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
983 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
985 /*
986 * BBP_R70
987 */
988 #define BBP_R70_JAPAN_FILTER FIELD8(0x08)
990 /*
991 * RF registers
992 */
994 /*
995 * RF 1
996 */
997 #define RF1_TUNER FIELD32(0x00020000)
999 /*
1000 * RF 3
1001 */
1002 #define RF3_TUNER FIELD32(0x00000100)
1003 #define RF3_TXPOWER FIELD32(0x00003e00)
1005 /*
1006 * EEPROM content.
1007 * The wordsize of the EEPROM is 16 bits.
1008 */
1010 /*
1011 * HW MAC address.
1012 */
1013 #define EEPROM_MAC_ADDR_0 0x0002
1014 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1015 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1016 #define EEPROM_MAC_ADDR1 0x0003
1017 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1018 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1019 #define EEPROM_MAC_ADDR_2 0x0004
1020 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1021 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1023 /*
1024 * EEPROM antenna.
1025 * ANTENNA_NUM: Number of antenna's.
1026 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1027 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1028 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
1029 * DYN_TXAGC: Dynamic TX AGC control.
1030 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1031 * RF_TYPE: Rf_type of this adapter.
1032 */
1033 #define EEPROM_ANTENNA 0x10
1034 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1035 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1036 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1037 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
1038 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1039 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1040 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1042 /*
1043 * EEPROM NIC config.
1044 * CARDBUS_ACCEL: 0: enable, 1: disable.
1045 * DYN_BBP_TUNE: 0: enable, 1: disable.
1046 * CCK_TX_POWER: CCK TX power compensation.
1047 */
1048 #define EEPROM_NIC 0x11
1049 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
1050 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
1051 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
1053 /*
1054 * EEPROM geography.
1055 * GEO: Default geography setting for device.
1056 */
1057 #define EEPROM_GEOGRAPHY 0x12
1058 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
1060 /*
1061 * EEPROM BBP.
1062 */
1063 #define EEPROM_BBP_START 0x13
1064 #define EEPROM_BBP_SIZE 16
1065 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1066 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1068 /*
1069 * EEPROM TXPOWER
1070 */
1071 #define EEPROM_TXPOWER_START 0x23
1072 #define EEPROM_TXPOWER_SIZE 7
1073 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
1074 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
1076 /*
1077 * RSSI <-> dBm offset calibration
1078 */
1079 #define EEPROM_CALIBRATE_OFFSET 0x3e
1080 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
1082 /*
1083 * DMA descriptor defines.
1084 */
1085 #define TXD_DESC_SIZE ( 11 * sizeof(__le32) )
1086 #define RXD_DESC_SIZE ( 11 * sizeof(__le32) )
1088 /*
1089 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1090 */
1092 /*
1093 * Word0
1094 */
1095 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1096 #define TXD_W0_VALID FIELD32(0x00000002)
1097 #define TXD_W0_RESULT FIELD32(0x0000001c)
1098 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1099 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1100 #define TXD_W0_ACK FIELD32(0x00000200)
1101 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1102 #define TXD_W0_OFDM FIELD32(0x00000800)
1103 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1104 #define TXD_W0_IFS FIELD32(0x00006000)
1105 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1106 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1107 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1109 /*
1110 * Word1
1111 */
1112 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1114 /*
1115 * Word2
1116 */
1117 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1118 #define TXD_W2_AIFS FIELD32(0x000000c0)
1119 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1120 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1122 /*
1123 * Word3: PLCP information
1124 */
1125 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1126 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1127 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1128 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1130 /*
1131 * Word4
1132 */
1133 #define TXD_W4_IV FIELD32(0xffffffff)
1135 /*
1136 * Word5
1137 */
1138 #define TXD_W5_EIV FIELD32(0xffffffff)
1140 /*
1141 * Word6-9: Key
1142 */
1143 #define TXD_W6_KEY FIELD32(0xffffffff)
1144 #define TXD_W7_KEY FIELD32(0xffffffff)
1145 #define TXD_W8_KEY FIELD32(0xffffffff)
1146 #define TXD_W9_KEY FIELD32(0xffffffff)
1148 /*
1149 * Word10
1150 */
1151 #define TXD_W10_RTS FIELD32(0x00000001)
1152 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1154 /*
1155 * RX descriptor format for RX Ring.
1156 */
1158 /*
1159 * Word0
1160 */
1161 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1162 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1163 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1164 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1165 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1166 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
1167 #define RXD_W0_OFDM FIELD32(0x00000040)
1168 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1169 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1170 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1171 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1172 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1173 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1175 /*
1176 * Word1
1177 */
1178 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1180 /*
1181 * Word2
1182 */
1183 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1184 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1185 #define RXD_W2_TA FIELD32(0xffff0000)
1187 /*
1188 * Word3
1189 */
1190 #define RXD_W3_TA FIELD32(0xffffffff)
1192 /*
1193 * Word4
1194 */
1195 #define RXD_W4_IV FIELD32(0xffffffff)
1197 /*
1198 * Word5
1199 */
1200 #define RXD_W5_EIV FIELD32(0xffffffff)
1202 /*
1203 * Word6-9: Key
1204 */
1205 #define RXD_W6_KEY FIELD32(0xffffffff)
1206 #define RXD_W7_KEY FIELD32(0xffffffff)
1207 #define RXD_W8_KEY FIELD32(0xffffffff)
1208 #define RXD_W9_KEY FIELD32(0xffffffff)
1210 /*
1211 * Word10
1212 */
1213 #define RXD_W10_DROP FIELD32(0x00000001)
1215 /*
1216 * Macro's for converting txpower from EEPROM to dscape value
1217 * and from dscape value to register value.
1218 */
1219 #define MIN_TXPOWER 0
1220 #define MAX_TXPOWER 31
1221 #define DEFAULT_TXPOWER 24
1223 #define TXPOWER_FROM_DEV(__txpower) \
1224 ({ \
1225 ((__txpower) > MAX_TXPOWER) ? \
1226 DEFAULT_TXPOWER : (__txpower); \
1227 })
1229 #define TXPOWER_TO_DEV(__txpower) \
1230 ({ \
1231 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1232 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1233 (__txpower)); \
1234 })