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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / wireless / b43 / main.c
blobe0055d0fa0c894d465ca79220ba3049e15b9ca9b
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
44
45 #include "b43.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "sysfs.h"
51 #include "xmit.h"
52 #include "lo.h"
53 #include "pcmcia.h"
54
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
60
61 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
62
63
64 static int modparam_bad_frames_preempt;
65 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
66 MODULE_PARM_DESC(bad_frames_preempt,
67 "enable(1) / disable(0) Bad Frames Preemption");
68
69 static char modparam_fwpostfix[16];
70 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
71 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
72
73 static int modparam_hwpctl;
74 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
75 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
76
77 static int modparam_nohwcrypt;
78 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
79 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
80
81 static int modparam_btcoex = 1;
82 module_param_named(btcoex, modparam_btcoex, int, 0444);
83 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
84
85
86 static const struct ssb_device_id b43_ssb_tbl[] = {
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
94 SSB_DEVTABLE_END
95 };
96
97 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
98
99 /* Channel and ratetables are shared for all devices.
100 * They can't be const, because ieee80211 puts some precalculated
101 * data in there. This data is the same for all devices, so we don't
102 * get concurrency issues */
103 #define RATETAB_ENT(_rateid, _flags) \
104 { \
105 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
106 .val = (_rateid), \
107 .val2 = (_rateid), \
108 .flags = (_flags), \
109 }
110 static struct ieee80211_rate __b43_ratetable[] = {
111 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
112 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
113 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
114 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
115 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
116 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
117 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
118 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
119 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
120 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
121 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
122 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
123 };
124
125 #define b43_a_ratetable (__b43_ratetable + 4)
126 #define b43_a_ratetable_size 8
127 #define b43_b_ratetable (__b43_ratetable + 0)
128 #define b43_b_ratetable_size 4
129 #define b43_g_ratetable (__b43_ratetable + 0)
130 #define b43_g_ratetable_size 12
131
132 #define CHANTAB_ENT(_chanid, _freq) \
133 { \
134 .chan = (_chanid), \
135 .freq = (_freq), \
136 .val = (_chanid), \
137 .flag = IEEE80211_CHAN_W_SCAN | \
138 IEEE80211_CHAN_W_ACTIVE_SCAN | \
139 IEEE80211_CHAN_W_IBSS, \
140 .power_level = 0xFF, \
141 .antenna_max = 0xFF, \
142 }
143 static struct ieee80211_channel b43_2ghz_chantable[] = {
144 CHANTAB_ENT(1, 2412),
145 CHANTAB_ENT(2, 2417),
146 CHANTAB_ENT(3, 2422),
147 CHANTAB_ENT(4, 2427),
148 CHANTAB_ENT(5, 2432),
149 CHANTAB_ENT(6, 2437),
150 CHANTAB_ENT(7, 2442),
151 CHANTAB_ENT(8, 2447),
152 CHANTAB_ENT(9, 2452),
153 CHANTAB_ENT(10, 2457),
154 CHANTAB_ENT(11, 2462),
155 CHANTAB_ENT(12, 2467),
156 CHANTAB_ENT(13, 2472),
157 CHANTAB_ENT(14, 2484),
158 };
159 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
160
161 #if 0
162 static struct ieee80211_channel b43_5ghz_chantable[] = {
163 CHANTAB_ENT(36, 5180),
164 CHANTAB_ENT(40, 5200),
165 CHANTAB_ENT(44, 5220),
166 CHANTAB_ENT(48, 5240),
167 CHANTAB_ENT(52, 5260),
168 CHANTAB_ENT(56, 5280),
169 CHANTAB_ENT(60, 5300),
170 CHANTAB_ENT(64, 5320),
171 CHANTAB_ENT(149, 5745),
172 CHANTAB_ENT(153, 5765),
173 CHANTAB_ENT(157, 5785),
174 CHANTAB_ENT(161, 5805),
175 CHANTAB_ENT(165, 5825),
176 };
177 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
178 #endif
179
180 static void b43_wireless_core_exit(struct b43_wldev *dev);
181 static int b43_wireless_core_init(struct b43_wldev *dev);
182 static void b43_wireless_core_stop(struct b43_wldev *dev);
183 static int b43_wireless_core_start(struct b43_wldev *dev);
184
185 static int b43_ratelimit(struct b43_wl *wl)
186 {
187 if (!wl || !wl->current_dev)
188 return 1;
189 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
190 return 1;
191 /* We are up and running.
192 * Ratelimit the messages to avoid DoS over the net. */
193 return net_ratelimit();
194 }
195
196 void b43info(struct b43_wl *wl, const char *fmt, ...)
197 {
198 va_list args;
199
200 if (!b43_ratelimit(wl))
201 return;
202 va_start(args, fmt);
203 printk(KERN_INFO "b43-%s: ",
204 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
205 vprintk(fmt, args);
206 va_end(args);
207 }
208
209 void b43err(struct b43_wl *wl, const char *fmt, ...)
210 {
211 va_list args;
212
213 if (!b43_ratelimit(wl))
214 return;
215 va_start(args, fmt);
216 printk(KERN_ERR "b43-%s ERROR: ",
217 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
218 vprintk(fmt, args);
219 va_end(args);
220 }
221
222 void b43warn(struct b43_wl *wl, const char *fmt, ...)
223 {
224 va_list args;
225
226 if (!b43_ratelimit(wl))
227 return;
228 va_start(args, fmt);
229 printk(KERN_WARNING "b43-%s warning: ",
230 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
231 vprintk(fmt, args);
232 va_end(args);
233 }
234
235 #if B43_DEBUG
236 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
237 {
238 va_list args;
239
240 va_start(args, fmt);
241 printk(KERN_DEBUG "b43-%s debug: ",
242 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
243 vprintk(fmt, args);
244 va_end(args);
245 }
246 #endif /* DEBUG */
247
248 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
249 {
250 u32 macctl;
251
252 B43_WARN_ON(offset % 4 != 0);
253
254 macctl = b43_read32(dev, B43_MMIO_MACCTL);
255 if (macctl & B43_MACCTL_BE)
256 val = swab32(val);
257
258 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
259 mmiowb();
260 b43_write32(dev, B43_MMIO_RAM_DATA, val);
261 }
262
263 static inline void b43_shm_control_word(struct b43_wldev *dev,
264 u16 routing, u16 offset)
265 {
266 u32 control;
267
268 /* "offset" is the WORD offset. */
269 control = routing;
270 control <<= 16;
271 control |= offset;
272 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
273 }
274
275 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
276 {
277 struct b43_wl *wl = dev->wl;
278 unsigned long flags;
279 u32 ret;
280
281 spin_lock_irqsave(&wl->shm_lock, flags);
282 if (routing == B43_SHM_SHARED) {
283 B43_WARN_ON(offset & 0x0001);
284 if (offset & 0x0003) {
285 /* Unaligned access */
286 b43_shm_control_word(dev, routing, offset >> 2);
287 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
288 ret <<= 16;
289 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
290 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
291
292 goto out;
293 }
294 offset >>= 2;
295 }
296 b43_shm_control_word(dev, routing, offset);
297 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
298 out:
299 spin_unlock_irqrestore(&wl->shm_lock, flags);
300
301 return ret;
302 }
303
304 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
305 {
306 struct b43_wl *wl = dev->wl;
307 unsigned long flags;
308 u16 ret;
309
310 spin_lock_irqsave(&wl->shm_lock, flags);
311 if (routing == B43_SHM_SHARED) {
312 B43_WARN_ON(offset & 0x0001);
313 if (offset & 0x0003) {
314 /* Unaligned access */
315 b43_shm_control_word(dev, routing, offset >> 2);
316 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
317
318 goto out;
319 }
320 offset >>= 2;
321 }
322 b43_shm_control_word(dev, routing, offset);
323 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
324 out:
325 spin_unlock_irqrestore(&wl->shm_lock, flags);
326
327 return ret;
328 }
329
330 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
331 {
332 struct b43_wl *wl = dev->wl;
333 unsigned long flags;
334
335 spin_lock_irqsave(&wl->shm_lock, flags);
336 if (routing == B43_SHM_SHARED) {
337 B43_WARN_ON(offset & 0x0001);
338 if (offset & 0x0003) {
339 /* Unaligned access */
340 b43_shm_control_word(dev, routing, offset >> 2);
341 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
342 (value >> 16) & 0xffff);
343 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
344 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
345 goto out;
346 }
347 offset >>= 2;
348 }
349 b43_shm_control_word(dev, routing, offset);
350 b43_write32(dev, B43_MMIO_SHM_DATA, value);
351 out:
352 spin_unlock_irqrestore(&wl->shm_lock, flags);
353 }
354
355 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
356 {
357 struct b43_wl *wl = dev->wl;
358 unsigned long flags;
359
360 spin_lock_irqsave(&wl->shm_lock, flags);
361 if (routing == B43_SHM_SHARED) {
362 B43_WARN_ON(offset & 0x0001);
363 if (offset & 0x0003) {
364 /* Unaligned access */
365 b43_shm_control_word(dev, routing, offset >> 2);
366 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
367 goto out;
368 }
369 offset >>= 2;
370 }
371 b43_shm_control_word(dev, routing, offset);
372 b43_write16(dev, B43_MMIO_SHM_DATA, value);
373 out:
374 spin_unlock_irqrestore(&wl->shm_lock, flags);
375 }
376
377 /* Read HostFlags */
378 u32 b43_hf_read(struct b43_wldev * dev)
379 {
380 u32 ret;
381
382 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
383 ret <<= 16;
384 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
385
386 return ret;
387 }
388
389 /* Write HostFlags */
390 void b43_hf_write(struct b43_wldev *dev, u32 value)
391 {
392 b43_shm_write16(dev, B43_SHM_SHARED,
393 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
394 b43_shm_write16(dev, B43_SHM_SHARED,
395 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
396 }
397
398 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
399 {
400 /* We need to be careful. As we read the TSF from multiple
401 * registers, we should take care of register overflows.
402 * In theory, the whole tsf read process should be atomic.
403 * We try to be atomic here, by restaring the read process,
404 * if any of the high registers changed (overflew).
405 */
406 if (dev->dev->id.revision >= 3) {
407 u32 low, high, high2;
408
409 do {
410 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
411 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
412 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
413 } while (unlikely(high != high2));
414
415 *tsf = high;
416 *tsf <<= 32;
417 *tsf |= low;
418 } else {
419 u64 tmp;
420 u16 v0, v1, v2, v3;
421 u16 test1, test2, test3;
422
423 do {
424 v3 = b43_read16(dev, B43_MMIO_TSF_3);
425 v2 = b43_read16(dev, B43_MMIO_TSF_2);
426 v1 = b43_read16(dev, B43_MMIO_TSF_1);
427 v0 = b43_read16(dev, B43_MMIO_TSF_0);
428
429 test3 = b43_read16(dev, B43_MMIO_TSF_3);
430 test2 = b43_read16(dev, B43_MMIO_TSF_2);
431 test1 = b43_read16(dev, B43_MMIO_TSF_1);
432 } while (v3 != test3 || v2 != test2 || v1 != test1);
433
434 *tsf = v3;
435 *tsf <<= 48;
436 tmp = v2;
437 tmp <<= 32;
438 *tsf |= tmp;
439 tmp = v1;
440 tmp <<= 16;
441 *tsf |= tmp;
442 *tsf |= v0;
443 }
444 }
445
446 static void b43_time_lock(struct b43_wldev *dev)
447 {
448 u32 macctl;
449
450 macctl = b43_read32(dev, B43_MMIO_MACCTL);
451 macctl |= B43_MACCTL_TBTTHOLD;
452 b43_write32(dev, B43_MMIO_MACCTL, macctl);
453 /* Commit the write */
454 b43_read32(dev, B43_MMIO_MACCTL);
455 }
456
457 static void b43_time_unlock(struct b43_wldev *dev)
458 {
459 u32 macctl;
460
461 macctl = b43_read32(dev, B43_MMIO_MACCTL);
462 macctl &= ~B43_MACCTL_TBTTHOLD;
463 b43_write32(dev, B43_MMIO_MACCTL, macctl);
464 /* Commit the write */
465 b43_read32(dev, B43_MMIO_MACCTL);
466 }
467
468 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
469 {
470 /* Be careful with the in-progress timer.
471 * First zero out the low register, so we have a full
472 * register-overflow duration to complete the operation.
473 */
474 if (dev->dev->id.revision >= 3) {
475 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
476 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
477
478 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
479 mmiowb();
480 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
481 mmiowb();
482 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
483 } else {
484 u16 v0 = (tsf & 0x000000000000FFFFULL);
485 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
486 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
487 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
488
489 b43_write16(dev, B43_MMIO_TSF_0, 0);
490 mmiowb();
491 b43_write16(dev, B43_MMIO_TSF_3, v3);
492 mmiowb();
493 b43_write16(dev, B43_MMIO_TSF_2, v2);
494 mmiowb();
495 b43_write16(dev, B43_MMIO_TSF_1, v1);
496 mmiowb();
497 b43_write16(dev, B43_MMIO_TSF_0, v0);
498 }
499 }
500
501 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
502 {
503 b43_time_lock(dev);
504 b43_tsf_write_locked(dev, tsf);
505 b43_time_unlock(dev);
506 }
507
508 static
509 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
510 {
511 static const u8 zero_addr[ETH_ALEN] = { 0 };
512 u16 data;
513
514 if (!mac)
515 mac = zero_addr;
516
517 offset |= 0x0020;
518 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
519
520 data = mac[0];
521 data |= mac[1] << 8;
522 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
523 data = mac[2];
524 data |= mac[3] << 8;
525 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
526 data = mac[4];
527 data |= mac[5] << 8;
528 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
529 }
530
531 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
532 {
533 const u8 *mac;
534 const u8 *bssid;
535 u8 mac_bssid[ETH_ALEN * 2];
536 int i;
537 u32 tmp;
538
539 bssid = dev->wl->bssid;
540 mac = dev->wl->mac_addr;
541
542 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
543
544 memcpy(mac_bssid, mac, ETH_ALEN);
545 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
546
547 /* Write our MAC address and BSSID to template ram */
548 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
549 tmp = (u32) (mac_bssid[i + 0]);
550 tmp |= (u32) (mac_bssid[i + 1]) << 8;
551 tmp |= (u32) (mac_bssid[i + 2]) << 16;
552 tmp |= (u32) (mac_bssid[i + 3]) << 24;
553 b43_ram_write(dev, 0x20 + i, tmp);
554 }
555 }
556
557 static void b43_upload_card_macaddress(struct b43_wldev *dev)
558 {
559 b43_write_mac_bssid_templates(dev);
560 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
561 }
562
563 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
564 {
565 /* slot_time is in usec. */
566 if (dev->phy.type != B43_PHYTYPE_G)
567 return;
568 b43_write16(dev, 0x684, 510 + slot_time);
569 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
570 }
571
572 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
573 {
574 b43_set_slot_time(dev, 9);
575 dev->short_slot = 1;
576 }
577
578 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
579 {
580 b43_set_slot_time(dev, 20);
581 dev->short_slot = 0;
582 }
583
584 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
585 * Returns the _previously_ enabled IRQ mask.
586 */
587 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
588 {
589 u32 old_mask;
590
591 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
592 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
593
594 return old_mask;
595 }
596
597 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
598 * Returns the _previously_ enabled IRQ mask.
599 */
600 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
601 {
602 u32 old_mask;
603
604 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
605 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
606
607 return old_mask;
608 }
609
610 /* Synchronize IRQ top- and bottom-half.
611 * IRQs must be masked before calling this.
612 * This must not be called with the irq_lock held.
613 */
614 static void b43_synchronize_irq(struct b43_wldev *dev)
615 {
616 synchronize_irq(dev->dev->irq);
617 tasklet_kill(&dev->isr_tasklet);
618 }
619
620 /* DummyTransmission function, as documented on
621 * http://bcm-specs.sipsolutions.net/DummyTransmission
622 */
623 void b43_dummy_transmission(struct b43_wldev *dev)
624 {
625 struct b43_wl *wl = dev->wl;
626 struct b43_phy *phy = &dev->phy;
627 unsigned int i, max_loop;
628 u16 value;
629 u32 buffer[5] = {
630 0x00000000,
631 0x00D40000,
632 0x00000000,
633 0x01000000,
634 0x00000000,
635 };
636
637 switch (phy->type) {
638 case B43_PHYTYPE_A:
639 max_loop = 0x1E;
640 buffer[0] = 0x000201CC;
641 break;
642 case B43_PHYTYPE_B:
643 case B43_PHYTYPE_G:
644 max_loop = 0xFA;
645 buffer[0] = 0x000B846E;
646 break;
647 default:
648 B43_WARN_ON(1);
649 return;
650 }
651
652 spin_lock_irq(&wl->irq_lock);
653 write_lock(&wl->tx_lock);
654
655 for (i = 0; i < 5; i++)
656 b43_ram_write(dev, i * 4, buffer[i]);
657
658 /* Commit writes */
659 b43_read32(dev, B43_MMIO_MACCTL);
660
661 b43_write16(dev, 0x0568, 0x0000);
662 b43_write16(dev, 0x07C0, 0x0000);
663 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
664 b43_write16(dev, 0x050C, value);
665 b43_write16(dev, 0x0508, 0x0000);
666 b43_write16(dev, 0x050A, 0x0000);
667 b43_write16(dev, 0x054C, 0x0000);
668 b43_write16(dev, 0x056A, 0x0014);
669 b43_write16(dev, 0x0568, 0x0826);
670 b43_write16(dev, 0x0500, 0x0000);
671 b43_write16(dev, 0x0502, 0x0030);
672
673 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
674 b43_radio_write16(dev, 0x0051, 0x0017);
675 for (i = 0x00; i < max_loop; i++) {
676 value = b43_read16(dev, 0x050E);
677 if (value & 0x0080)
678 break;
679 udelay(10);
680 }
681 for (i = 0x00; i < 0x0A; i++) {
682 value = b43_read16(dev, 0x050E);
683 if (value & 0x0400)
684 break;
685 udelay(10);
686 }
687 for (i = 0x00; i < 0x0A; i++) {
688 value = b43_read16(dev, 0x0690);
689 if (!(value & 0x0100))
690 break;
691 udelay(10);
692 }
693 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
694 b43_radio_write16(dev, 0x0051, 0x0037);
695
696 write_unlock(&wl->tx_lock);
697 spin_unlock_irq(&wl->irq_lock);
698 }
699
700 static void key_write(struct b43_wldev *dev,
701 u8 index, u8 algorithm, const u8 * key)
702 {
703 unsigned int i;
704 u32 offset;
705 u16 value;
706 u16 kidx;
707
708 /* Key index/algo block */
709 kidx = b43_kidx_to_fw(dev, index);
710 value = ((kidx << 4) | algorithm);
711 b43_shm_write16(dev, B43_SHM_SHARED,
712 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
713
714 /* Write the key to the Key Table Pointer offset */
715 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
716 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
717 value = key[i];
718 value |= (u16) (key[i + 1]) << 8;
719 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
720 }
721 }
722
723 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
724 {
725 u32 addrtmp[2] = { 0, 0, };
726 u8 per_sta_keys_start = 8;
727
728 if (b43_new_kidx_api(dev))
729 per_sta_keys_start = 4;
730
731 B43_WARN_ON(index < per_sta_keys_start);
732 /* We have two default TX keys and possibly two default RX keys.
733 * Physical mac 0 is mapped to physical key 4 or 8, depending
734 * on the firmware version.
735 * So we must adjust the index here.
736 */
737 index -= per_sta_keys_start;
738
739 if (addr) {
740 addrtmp[0] = addr[0];
741 addrtmp[0] |= ((u32) (addr[1]) << 8);
742 addrtmp[0] |= ((u32) (addr[2]) << 16);
743 addrtmp[0] |= ((u32) (addr[3]) << 24);
744 addrtmp[1] = addr[4];
745 addrtmp[1] |= ((u32) (addr[5]) << 8);
746 }
747
748 if (dev->dev->id.revision >= 5) {
749 /* Receive match transmitter address mechanism */
750 b43_shm_write32(dev, B43_SHM_RCMTA,
751 (index * 2) + 0, addrtmp[0]);
752 b43_shm_write16(dev, B43_SHM_RCMTA,
753 (index * 2) + 1, addrtmp[1]);
754 } else {
755 /* RXE (Receive Engine) and
756 * PSM (Programmable State Machine) mechanism
757 */
758 if (index < 8) {
759 /* TODO write to RCM 16, 19, 22 and 25 */
760 } else {
761 b43_shm_write32(dev, B43_SHM_SHARED,
762 B43_SHM_SH_PSM + (index * 6) + 0,
763 addrtmp[0]);
764 b43_shm_write16(dev, B43_SHM_SHARED,
765 B43_SHM_SH_PSM + (index * 6) + 4,
766 addrtmp[1]);
767 }
768 }
769 }
770
771 static void do_key_write(struct b43_wldev *dev,
772 u8 index, u8 algorithm,
773 const u8 * key, size_t key_len, const u8 * mac_addr)
774 {
775 u8 buf[B43_SEC_KEYSIZE] = { 0, };
776 u8 per_sta_keys_start = 8;
777
778 if (b43_new_kidx_api(dev))
779 per_sta_keys_start = 4;
780
781 B43_WARN_ON(index >= dev->max_nr_keys);
782 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
783
784 if (index >= per_sta_keys_start)
785 keymac_write(dev, index, NULL); /* First zero out mac. */
786 if (key)
787 memcpy(buf, key, key_len);
788 key_write(dev, index, algorithm, buf);
789 if (index >= per_sta_keys_start)
790 keymac_write(dev, index, mac_addr);
791
792 dev->key[index].algorithm = algorithm;
793 }
794
795 static int b43_key_write(struct b43_wldev *dev,
796 int index, u8 algorithm,
797 const u8 * key, size_t key_len,
798 const u8 * mac_addr,
799 struct ieee80211_key_conf *keyconf)
800 {
801 int i;
802 int sta_keys_start;
803
804 if (key_len > B43_SEC_KEYSIZE)
805 return -EINVAL;
806 for (i = 0; i < dev->max_nr_keys; i++) {
807 /* Check that we don't already have this key. */
808 B43_WARN_ON(dev->key[i].keyconf == keyconf);
809 }
810 if (index < 0) {
811 /* Either pairwise key or address is 00:00:00:00:00:00
812 * for transmit-only keys. Search the index. */
813 if (b43_new_kidx_api(dev))
814 sta_keys_start = 4;
815 else
816 sta_keys_start = 8;
817 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
818 if (!dev->key[i].keyconf) {
819 /* found empty */
820 index = i;
821 break;
822 }
823 }
824 if (index < 0) {
825 b43err(dev->wl, "Out of hardware key memory\n");
826 return -ENOSPC;
827 }
828 } else
829 B43_WARN_ON(index > 3);
830
831 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
832 if ((index <= 3) && !b43_new_kidx_api(dev)) {
833 /* Default RX key */
834 B43_WARN_ON(mac_addr);
835 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
836 }
837 keyconf->hw_key_idx = index;
838 dev->key[index].keyconf = keyconf;
839
840 return 0;
841 }
842
843 static int b43_key_clear(struct b43_wldev *dev, int index)
844 {
845 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
846 return -EINVAL;
847 do_key_write(dev, index, B43_SEC_ALGO_NONE,
848 NULL, B43_SEC_KEYSIZE, NULL);
849 if ((index <= 3) && !b43_new_kidx_api(dev)) {
850 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
851 NULL, B43_SEC_KEYSIZE, NULL);
852 }
853 dev->key[index].keyconf = NULL;
854
855 return 0;
856 }
857
858 static void b43_clear_keys(struct b43_wldev *dev)
859 {
860 int i;
861
862 for (i = 0; i < dev->max_nr_keys; i++)
863 b43_key_clear(dev, i);
864 }
865
866 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
867 {
868 u32 macctl;
869 u16 ucstat;
870 bool hwps;
871 bool awake;
872 int i;
873
874 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
875 (ps_flags & B43_PS_DISABLED));
876 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
877
878 if (ps_flags & B43_PS_ENABLED) {
879 hwps = 1;
880 } else if (ps_flags & B43_PS_DISABLED) {
881 hwps = 0;
882 } else {
883 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
884 // and thus is not an AP and we are associated, set bit 25
885 }
886 if (ps_flags & B43_PS_AWAKE) {
887 awake = 1;
888 } else if (ps_flags & B43_PS_ASLEEP) {
889 awake = 0;
890 } else {
891 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
892 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
893 // successful, set bit26
894 }
895
896 /* FIXME: For now we force awake-on and hwps-off */
897 hwps = 0;
898 awake = 1;
899
900 macctl = b43_read32(dev, B43_MMIO_MACCTL);
901 if (hwps)
902 macctl |= B43_MACCTL_HWPS;
903 else
904 macctl &= ~B43_MACCTL_HWPS;
905 if (awake)
906 macctl |= B43_MACCTL_AWAKE;
907 else
908 macctl &= ~B43_MACCTL_AWAKE;
909 b43_write32(dev, B43_MMIO_MACCTL, macctl);
910 /* Commit write */
911 b43_read32(dev, B43_MMIO_MACCTL);
912 if (awake && dev->dev->id.revision >= 5) {
913 /* Wait for the microcode to wake up. */
914 for (i = 0; i < 100; i++) {
915 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
916 B43_SHM_SH_UCODESTAT);
917 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
918 break;
919 udelay(10);
920 }
921 }
922 }
923
924 /* Turn the Analog ON/OFF */
925 static void b43_switch_analog(struct b43_wldev *dev, int on)
926 {
927 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
928 }
929
930 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
931 {
932 u32 tmslow;
933 u32 macctl;
934
935 flags |= B43_TMSLOW_PHYCLKEN;
936 flags |= B43_TMSLOW_PHYRESET;
937 ssb_device_enable(dev->dev, flags);
938 msleep(2); /* Wait for the PLL to turn on. */
939
940 /* Now take the PHY out of Reset again */
941 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
942 tmslow |= SSB_TMSLOW_FGC;
943 tmslow &= ~B43_TMSLOW_PHYRESET;
944 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
945 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
946 msleep(1);
947 tmslow &= ~SSB_TMSLOW_FGC;
948 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
949 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
950 msleep(1);
951
952 /* Turn Analog ON */
953 b43_switch_analog(dev, 1);
954
955 macctl = b43_read32(dev, B43_MMIO_MACCTL);
956 macctl &= ~B43_MACCTL_GMODE;
957 if (flags & B43_TMSLOW_GMODE)
958 macctl |= B43_MACCTL_GMODE;
959 macctl |= B43_MACCTL_IHR_ENABLED;
960 b43_write32(dev, B43_MMIO_MACCTL, macctl);
961 }
962
963 static void handle_irq_transmit_status(struct b43_wldev *dev)
964 {
965 u32 v0, v1;
966 u16 tmp;
967 struct b43_txstatus stat;
968
969 while (1) {
970 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
971 if (!(v0 & 0x00000001))
972 break;
973 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
974
975 stat.cookie = (v0 >> 16);
976 stat.seq = (v1 & 0x0000FFFF);
977 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
978 tmp = (v0 & 0x0000FFFF);
979 stat.frame_count = ((tmp & 0xF000) >> 12);
980 stat.rts_count = ((tmp & 0x0F00) >> 8);
981 stat.supp_reason = ((tmp & 0x001C) >> 2);
982 stat.pm_indicated = !!(tmp & 0x0080);
983 stat.intermediate = !!(tmp & 0x0040);
984 stat.for_ampdu = !!(tmp & 0x0020);
985 stat.acked = !!(tmp & 0x0002);
986
987 b43_handle_txstatus(dev, &stat);
988 }
989 }
990
991 static void drain_txstatus_queue(struct b43_wldev *dev)
992 {
993 u32 dummy;
994
995 if (dev->dev->id.revision < 5)
996 return;
997 /* Read all entries from the microcode TXstatus FIFO
998 * and throw them away.
999 */
1000 while (1) {
1001 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1002 if (!(dummy & 0x00000001))
1003 break;
1004 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1005 }
1006 }
1007
1008 static u32 b43_jssi_read(struct b43_wldev *dev)
1009 {
1010 u32 val = 0;
1011
1012 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1013 val <<= 16;
1014 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1015
1016 return val;
1017 }
1018
1019 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1020 {
1021 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1022 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1023 }
1024
1025 static void b43_generate_noise_sample(struct b43_wldev *dev)
1026 {
1027 b43_jssi_write(dev, 0x7F7F7F7F);
1028 b43_write32(dev, B43_MMIO_MACCMD,
1029 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1030 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1031 }
1032
1033 static void b43_calculate_link_quality(struct b43_wldev *dev)
1034 {
1035 /* Top half of Link Quality calculation. */
1036
1037 if (dev->noisecalc.calculation_running)
1038 return;
1039 dev->noisecalc.channel_at_start = dev->phy.channel;
1040 dev->noisecalc.calculation_running = 1;
1041 dev->noisecalc.nr_samples = 0;
1042
1043 b43_generate_noise_sample(dev);
1044 }
1045
1046 static void handle_irq_noise(struct b43_wldev *dev)
1047 {
1048 struct b43_phy *phy = &dev->phy;
1049 u16 tmp;
1050 u8 noise[4];
1051 u8 i, j;
1052 s32 average;
1053
1054 /* Bottom half of Link Quality calculation. */
1055
1056 B43_WARN_ON(!dev->noisecalc.calculation_running);
1057 if (dev->noisecalc.channel_at_start != phy->channel)
1058 goto drop_calculation;
1059 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1060 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1061 noise[2] == 0x7F || noise[3] == 0x7F)
1062 goto generate_new;
1063
1064 /* Get the noise samples. */
1065 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1066 i = dev->noisecalc.nr_samples;
1067 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1068 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1069 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1070 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1071 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1072 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1073 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1074 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1075 dev->noisecalc.nr_samples++;
1076 if (dev->noisecalc.nr_samples == 8) {
1077 /* Calculate the Link Quality by the noise samples. */
1078 average = 0;
1079 for (i = 0; i < 8; i++) {
1080 for (j = 0; j < 4; j++)
1081 average += dev->noisecalc.samples[i][j];
1082 }
1083 average /= (8 * 4);
1084 average *= 125;
1085 average += 64;
1086 average /= 128;
1087 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1088 tmp = (tmp / 128) & 0x1F;
1089 if (tmp >= 8)
1090 average += 2;
1091 else
1092 average -= 25;
1093 if (tmp == 8)
1094 average -= 72;
1095 else
1096 average -= 48;
1097
1098 dev->stats.link_noise = average;
1099 drop_calculation:
1100 dev->noisecalc.calculation_running = 0;
1101 return;
1102 }
1103 generate_new:
1104 b43_generate_noise_sample(dev);
1105 }
1106
1107 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1108 {
1109 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1110 ///TODO: PS TBTT
1111 } else {
1112 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1113 b43_power_saving_ctl_bits(dev, 0);
1114 }
1115 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1116 dev->dfq_valid = 1;
1117 }
1118
1119 static void handle_irq_atim_end(struct b43_wldev *dev)
1120 {
1121 if (dev->dfq_valid) {
1122 b43_write32(dev, B43_MMIO_MACCMD,
1123 b43_read32(dev, B43_MMIO_MACCMD)
1124 | B43_MACCMD_DFQ_VALID);
1125 dev->dfq_valid = 0;
1126 }
1127 }
1128
1129 static void handle_irq_pmq(struct b43_wldev *dev)
1130 {
1131 u32 tmp;
1132
1133 //TODO: AP mode.
1134
1135 while (1) {
1136 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1137 if (!(tmp & 0x00000008))
1138 break;
1139 }
1140 /* 16bit write is odd, but correct. */
1141 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1142 }
1143
1144 static void b43_write_template_common(struct b43_wldev *dev,
1145 const u8 * data, u16 size,
1146 u16 ram_offset,
1147 u16 shm_size_offset, u8 rate)
1148 {
1149 u32 i, tmp;
1150 struct b43_plcp_hdr4 plcp;
1151
1152 plcp.data = 0;
1153 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1154 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1155 ram_offset += sizeof(u32);
1156 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1157 * So leave the first two bytes of the next write blank.
1158 */
1159 tmp = (u32) (data[0]) << 16;
1160 tmp |= (u32) (data[1]) << 24;
1161 b43_ram_write(dev, ram_offset, tmp);
1162 ram_offset += sizeof(u32);
1163 for (i = 2; i < size; i += sizeof(u32)) {
1164 tmp = (u32) (data[i + 0]);
1165 if (i + 1 < size)
1166 tmp |= (u32) (data[i + 1]) << 8;
1167 if (i + 2 < size)
1168 tmp |= (u32) (data[i + 2]) << 16;
1169 if (i + 3 < size)
1170 tmp |= (u32) (data[i + 3]) << 24;
1171 b43_ram_write(dev, ram_offset + i - 2, tmp);
1172 }
1173 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1174 size + sizeof(struct b43_plcp_hdr6));
1175 }
1176
1177 static void b43_write_beacon_template(struct b43_wldev *dev,
1178 u16 ram_offset,
1179 u16 shm_size_offset, u8 rate)
1180 {
1181 unsigned int i, len, variable_len;
1182 const struct ieee80211_mgmt *bcn;
1183 const u8 *ie;
1184 bool tim_found = 0;
1185
1186 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1187 len = min((size_t) dev->wl->current_beacon->len,
1188 0x200 - sizeof(struct b43_plcp_hdr6));
1189
1190 b43_write_template_common(dev, (const u8 *)bcn,
1191 len, ram_offset, shm_size_offset, rate);
1192
1193 /* Find the position of the TIM and the DTIM_period value
1194 * and write them to SHM. */
1195 ie = bcn->u.beacon.variable;
1196 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1197 for (i = 0; i < variable_len - 2; ) {
1198 uint8_t ie_id, ie_len;
1199
1200 ie_id = ie[i];
1201 ie_len = ie[i + 1];
1202 if (ie_id == 5) {
1203 u16 tim_position;
1204 u16 dtim_period;
1205 /* This is the TIM Information Element */
1206
1207 /* Check whether the ie_len is in the beacon data range. */
1208 if (variable_len < ie_len + 2 + i)
1209 break;
1210 /* A valid TIM is at least 4 bytes long. */
1211 if (ie_len < 4)
1212 break;
1213 tim_found = 1;
1214
1215 tim_position = sizeof(struct b43_plcp_hdr6);
1216 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1217 tim_position += i;
1218
1219 dtim_period = ie[i + 3];
1220
1221 b43_shm_write16(dev, B43_SHM_SHARED,
1222 B43_SHM_SH_TIMBPOS, tim_position);
1223 b43_shm_write16(dev, B43_SHM_SHARED,
1224 B43_SHM_SH_DTIMPER, dtim_period);
1225 break;
1226 }
1227 i += ie_len + 2;
1228 }
1229 if (!tim_found) {
1230 b43warn(dev->wl, "Did not find a valid TIM IE in "
1231 "the beacon template packet. AP or IBSS operation "
1232 "may be broken.\n");
1233 }
1234 }
1235
1236 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1237 u16 shm_offset, u16 size, u8 rate)
1238 {
1239 struct b43_plcp_hdr4 plcp;
1240 u32 tmp;
1241 __le16 dur;
1242
1243 plcp.data = 0;
1244 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1245 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1246 dev->wl->vif, size,
1247 B43_RATE_TO_BASE100KBPS(rate));
1248 /* Write PLCP in two parts and timing for packet transfer */
1249 tmp = le32_to_cpu(plcp.data);
1250 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1251 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1252 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1253 }
1254
1255 /* Instead of using custom probe response template, this function
1256 * just patches custom beacon template by:
1257 * 1) Changing packet type
1258 * 2) Patching duration field
1259 * 3) Stripping TIM
1260 */
1261 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1262 u16 *dest_size, u8 rate)
1263 {
1264 const u8 *src_data;
1265 u8 *dest_data;
1266 u16 src_size, elem_size, src_pos, dest_pos;
1267 __le16 dur;
1268 struct ieee80211_hdr *hdr;
1269 size_t ie_start;
1270
1271 src_size = dev->wl->current_beacon->len;
1272 src_data = (const u8 *)dev->wl->current_beacon->data;
1273
1274 /* Get the start offset of the variable IEs in the packet. */
1275 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1276 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1277
1278 if (B43_WARN_ON(src_size < ie_start))
1279 return NULL;
1280
1281 dest_data = kmalloc(src_size, GFP_ATOMIC);
1282 if (unlikely(!dest_data))
1283 return NULL;
1284
1285 /* Copy the static data and all Information Elements, except the TIM. */
1286 memcpy(dest_data, src_data, ie_start);
1287 src_pos = ie_start;
1288 dest_pos = ie_start;
1289 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1290 elem_size = src_data[src_pos + 1] + 2;
1291 if (src_data[src_pos] == 5) {
1292 /* This is the TIM. */
1293 continue;
1294 }
1295 memcpy(dest_data + dest_pos, src_data + src_pos,
1296 elem_size);
1297 dest_pos += elem_size;
1298 }
1299 *dest_size = dest_pos;
1300 hdr = (struct ieee80211_hdr *)dest_data;
1301
1302 /* Set the frame control. */
1303 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1304 IEEE80211_STYPE_PROBE_RESP);
1305 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1306 dev->wl->vif, *dest_size,
1307 B43_RATE_TO_BASE100KBPS(rate));
1308 hdr->duration_id = dur;
1309
1310 return dest_data;
1311 }
1312
1313 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1314 u16 ram_offset,
1315 u16 shm_size_offset, u8 rate)
1316 {
1317 const u8 *probe_resp_data;
1318 u16 size;
1319
1320 size = dev->wl->current_beacon->len;
1321 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1322 if (unlikely(!probe_resp_data))
1323 return;
1324
1325 /* Looks like PLCP headers plus packet timings are stored for
1326 * all possible basic rates
1327 */
1328 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1329 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1330 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1331 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1332
1333 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1334 b43_write_template_common(dev, probe_resp_data,
1335 size, ram_offset, shm_size_offset, rate);
1336 kfree(probe_resp_data);
1337 }
1338
1339 /* Asynchronously update the packet templates in template RAM.
1340 * Locking: Requires wl->irq_lock to be locked. */
1341 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1342 {
1343 /* This is the top half of the ansynchronous beacon update.
1344 * The bottom half is the beacon IRQ.
1345 * Beacon update must be asynchronous to avoid sending an
1346 * invalid beacon. This can happen for example, if the firmware
1347 * transmits a beacon while we are updating it. */
1348
1349 if (wl->current_beacon)
1350 dev_kfree_skb_any(wl->current_beacon);
1351 wl->current_beacon = beacon;
1352 wl->beacon0_uploaded = 0;
1353 wl->beacon1_uploaded = 0;
1354 }
1355
1356 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1357 {
1358 u32 tmp;
1359 u16 i, len;
1360
1361 len = min((u16) ssid_len, (u16) 0x100);
1362 for (i = 0; i < len; i += sizeof(u32)) {
1363 tmp = (u32) (ssid[i + 0]);
1364 if (i + 1 < len)
1365 tmp |= (u32) (ssid[i + 1]) << 8;
1366 if (i + 2 < len)
1367 tmp |= (u32) (ssid[i + 2]) << 16;
1368 if (i + 3 < len)
1369 tmp |= (u32) (ssid[i + 3]) << 24;
1370 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1371 }
1372 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1373 }
1374
1375 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1376 {
1377 b43_time_lock(dev);
1378 if (dev->dev->id.revision >= 3) {
1379 b43_write32(dev, 0x188, (beacon_int << 16));
1380 } else {
1381 b43_write16(dev, 0x606, (beacon_int >> 6));
1382 b43_write16(dev, 0x610, beacon_int);
1383 }
1384 b43_time_unlock(dev);
1385 }
1386
1387 static void handle_irq_beacon(struct b43_wldev *dev)
1388 {
1389 struct b43_wl *wl = dev->wl;
1390 u32 cmd;
1391
1392 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1393 return;
1394
1395 /* This is the bottom half of the asynchronous beacon update. */
1396
1397 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1398 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1399 if (!wl->beacon0_uploaded) {
1400 b43_write_beacon_template(dev, 0x68, 0x18,
1401 B43_CCK_RATE_1MB);
1402 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1403 B43_CCK_RATE_11MB);
1404 wl->beacon0_uploaded = 1;
1405 }
1406 cmd |= B43_MACCMD_BEACON0_VALID;
1407 }
1408 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1409 if (!wl->beacon1_uploaded) {
1410 b43_write_beacon_template(dev, 0x468, 0x1A,
1411 B43_CCK_RATE_1MB);
1412 wl->beacon1_uploaded = 1;
1413 }
1414 cmd |= B43_MACCMD_BEACON1_VALID;
1415 }
1416 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1417 }
1418
1419 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1420 {
1421 //TODO
1422 }
1423
1424 /* Interrupt handler bottom-half */
1425 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1426 {
1427 u32 reason;
1428 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1429 u32 merged_dma_reason = 0;
1430 int i;
1431 unsigned long flags;
1432
1433 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1434
1435 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1436
1437 reason = dev->irq_reason;
1438 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1439 dma_reason[i] = dev->dma_reason[i];
1440 merged_dma_reason |= dma_reason[i];
1441 }
1442
1443 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1444 b43err(dev->wl, "MAC transmission error\n");
1445
1446 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1447 b43err(dev->wl, "PHY transmission error\n");
1448 rmb();
1449 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1450 atomic_set(&dev->phy.txerr_cnt,
1451 B43_PHY_TX_BADNESS_LIMIT);
1452 b43err(dev->wl, "Too many PHY TX errors, "
1453 "restarting the controller\n");
1454 b43_controller_restart(dev, "PHY TX errors");
1455 }
1456 }
1457
1458 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1459 B43_DMAIRQ_NONFATALMASK))) {
1460 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1461 b43err(dev->wl, "Fatal DMA error: "
1462 "0x%08X, 0x%08X, 0x%08X, "
1463 "0x%08X, 0x%08X, 0x%08X\n",
1464 dma_reason[0], dma_reason[1],
1465 dma_reason[2], dma_reason[3],
1466 dma_reason[4], dma_reason[5]);
1467 b43_controller_restart(dev, "DMA error");
1468 mmiowb();
1469 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1470 return;
1471 }
1472 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1473 b43err(dev->wl, "DMA error: "
1474 "0x%08X, 0x%08X, 0x%08X, "
1475 "0x%08X, 0x%08X, 0x%08X\n",
1476 dma_reason[0], dma_reason[1],
1477 dma_reason[2], dma_reason[3],
1478 dma_reason[4], dma_reason[5]);
1479 }
1480 }
1481
1482 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1483 handle_irq_ucode_debug(dev);
1484 if (reason & B43_IRQ_TBTT_INDI)
1485 handle_irq_tbtt_indication(dev);
1486 if (reason & B43_IRQ_ATIM_END)
1487 handle_irq_atim_end(dev);
1488 if (reason & B43_IRQ_BEACON)
1489 handle_irq_beacon(dev);
1490 if (reason & B43_IRQ_PMQ)
1491 handle_irq_pmq(dev);
1492 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1493 ;/* TODO */
1494 if (reason & B43_IRQ_NOISESAMPLE_OK)
1495 handle_irq_noise(dev);
1496
1497 /* Check the DMA reason registers for received data. */
1498 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1499 b43_dma_rx(dev->dma.rx_ring0);
1500 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1501 b43_dma_rx(dev->dma.rx_ring3);
1502 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1503 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1504 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1505 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1506
1507 if (reason & B43_IRQ_TX_OK)
1508 handle_irq_transmit_status(dev);
1509
1510 b43_interrupt_enable(dev, dev->irq_savedstate);
1511 mmiowb();
1512 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1513 }
1514
1515 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1516 {
1517 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1518
1519 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1520 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1521 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1522 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1523 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1524 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1525 }
1526
1527 /* Interrupt handler top-half */
1528 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1529 {
1530 irqreturn_t ret = IRQ_NONE;
1531 struct b43_wldev *dev = dev_id;
1532 u32 reason;
1533
1534 if (!dev)
1535 return IRQ_NONE;
1536
1537 spin_lock(&dev->wl->irq_lock);
1538
1539 if (b43_status(dev) < B43_STAT_STARTED)
1540 goto out;
1541 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1542 if (reason == 0xffffffff) /* shared IRQ */
1543 goto out;
1544 ret = IRQ_HANDLED;
1545 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1546 if (!reason)
1547 goto out;
1548
1549 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1550 & 0x0001DC00;
1551 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1552 & 0x0000DC00;
1553 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1554 & 0x0000DC00;
1555 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1556 & 0x0001DC00;
1557 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1558 & 0x0000DC00;
1559 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1560 & 0x0000DC00;
1561
1562 b43_interrupt_ack(dev, reason);
1563 /* disable all IRQs. They are enabled again in the bottom half. */
1564 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1565 /* save the reason code and call our bottom half. */
1566 dev->irq_reason = reason;
1567 tasklet_schedule(&dev->isr_tasklet);
1568 out:
1569 mmiowb();
1570 spin_unlock(&dev->wl->irq_lock);
1571
1572 return ret;
1573 }
1574
1575 static void do_release_fw(struct b43_firmware_file *fw)
1576 {
1577 release_firmware(fw->data);
1578 fw->data = NULL;
1579 fw->filename = NULL;
1580 }
1581
1582 static void b43_release_firmware(struct b43_wldev *dev)
1583 {
1584 do_release_fw(&dev->fw.ucode);
1585 do_release_fw(&dev->fw.pcm);
1586 do_release_fw(&dev->fw.initvals);
1587 do_release_fw(&dev->fw.initvals_band);
1588 }
1589
1590 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1591 {
1592 const char *text;
1593
1594 text = "You must go to "
1595 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1596 "and download the latest firmware (version 4).\n";
1597 if (error)
1598 b43err(wl, text);
1599 else
1600 b43warn(wl, text);
1601 }
1602
1603 static int do_request_fw(struct b43_wldev *dev,
1604 const char *name,
1605 struct b43_firmware_file *fw)
1606 {
1607 char path[sizeof(modparam_fwpostfix) + 32];
1608 const struct firmware *blob;
1609 struct b43_fw_header *hdr;
1610 u32 size;
1611 int err;
1612
1613 if (!name) {
1614 /* Don't fetch anything. Free possibly cached firmware. */
1615 do_release_fw(fw);
1616 return 0;
1617 }
1618 if (fw->filename) {
1619 if (strcmp(fw->filename, name) == 0)
1620 return 0; /* Already have this fw. */
1621 /* Free the cached firmware first. */
1622 do_release_fw(fw);
1623 }
1624
1625 snprintf(path, ARRAY_SIZE(path),
1626 "b43%s/%s.fw",
1627 modparam_fwpostfix, name);
1628 err = request_firmware(&blob, path, dev->dev->dev);
1629 if (err) {
1630 b43err(dev->wl, "Firmware file \"%s\" not found "
1631 "or load failed.\n", path);
1632 return err;
1633 }
1634 if (blob->size < sizeof(struct b43_fw_header))
1635 goto err_format;
1636 hdr = (struct b43_fw_header *)(blob->data);
1637 switch (hdr->type) {
1638 case B43_FW_TYPE_UCODE:
1639 case B43_FW_TYPE_PCM:
1640 size = be32_to_cpu(hdr->size);
1641 if (size != blob->size - sizeof(struct b43_fw_header))
1642 goto err_format;
1643 /* fallthrough */
1644 case B43_FW_TYPE_IV:
1645 if (hdr->ver != 1)
1646 goto err_format;
1647 break;
1648 default:
1649 goto err_format;
1650 }
1651
1652 fw->data = blob;
1653 fw->filename = name;
1654
1655 return 0;
1656
1657 err_format:
1658 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1659 release_firmware(blob);
1660
1661 return -EPROTO;
1662 }
1663
1664 static int b43_request_firmware(struct b43_wldev *dev)
1665 {
1666 struct b43_firmware *fw = &dev->fw;
1667 const u8 rev = dev->dev->id.revision;
1668 const char *filename;
1669 u32 tmshigh;
1670 int err;
1671
1672 /* Get microcode */
1673 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1674 if ((rev >= 5) && (rev <= 10))
1675 filename = "ucode5";
1676 else if ((rev >= 11) && (rev <= 12))
1677 filename = "ucode11";
1678 else if (rev >= 13)
1679 filename = "ucode13";
1680 else
1681 goto err_no_ucode;
1682 err = do_request_fw(dev, filename, &fw->ucode);
1683 if (err)
1684 goto err_load;
1685
1686 /* Get PCM code */
1687 if ((rev >= 5) && (rev <= 10))
1688 filename = "pcm5";
1689 else if (rev >= 11)
1690 filename = NULL;
1691 else
1692 goto err_no_pcm;
1693 err = do_request_fw(dev, filename, &fw->pcm);
1694 if (err)
1695 goto err_load;
1696
1697 /* Get initvals */
1698 switch (dev->phy.type) {
1699 case B43_PHYTYPE_A:
1700 if ((rev >= 5) && (rev <= 10)) {
1701 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1702 filename = "a0g1initvals5";
1703 else
1704 filename = "a0g0initvals5";
1705 } else
1706 goto err_no_initvals;
1707 break;
1708 case B43_PHYTYPE_G:
1709 if ((rev >= 5) && (rev <= 10))
1710 filename = "b0g0initvals5";
1711 else if (rev >= 13)
1712 filename = "lp0initvals13";
1713 else
1714 goto err_no_initvals;
1715 break;
1716 case B43_PHYTYPE_N:
1717 if ((rev >= 11) && (rev <= 12))
1718 filename = "n0initvals11";
1719 else
1720 goto err_no_initvals;
1721 break;
1722 default:
1723 goto err_no_initvals;
1724 }
1725 err = do_request_fw(dev, filename, &fw->initvals);
1726 if (err)
1727 goto err_load;
1728
1729 /* Get bandswitch initvals */
1730 switch (dev->phy.type) {
1731 case B43_PHYTYPE_A:
1732 if ((rev >= 5) && (rev <= 10)) {
1733 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1734 filename = "a0g1bsinitvals5";
1735 else
1736 filename = "a0g0bsinitvals5";
1737 } else if (rev >= 11)
1738 filename = NULL;
1739 else
1740 goto err_no_initvals;
1741 break;
1742 case B43_PHYTYPE_G:
1743 if ((rev >= 5) && (rev <= 10))
1744 filename = "b0g0bsinitvals5";
1745 else if (rev >= 11)
1746 filename = NULL;
1747 else
1748 goto err_no_initvals;
1749 break;
1750 case B43_PHYTYPE_N:
1751 if ((rev >= 11) && (rev <= 12))
1752 filename = "n0bsinitvals11";
1753 else
1754 goto err_no_initvals;
1755 break;
1756 default:
1757 goto err_no_initvals;
1758 }
1759 err = do_request_fw(dev, filename, &fw->initvals_band);
1760 if (err)
1761 goto err_load;
1762
1763 return 0;
1764
1765 err_load:
1766 b43_print_fw_helptext(dev->wl, 1);
1767 goto error;
1768
1769 err_no_ucode:
1770 err = -ENODEV;
1771 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1772 goto error;
1773
1774 err_no_pcm:
1775 err = -ENODEV;
1776 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1777 goto error;
1778
1779 err_no_initvals:
1780 err = -ENODEV;
1781 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1782 "core rev %u\n", dev->phy.type, rev);
1783 goto error;
1784
1785 error:
1786 b43_release_firmware(dev);
1787 return err;
1788 }
1789
1790 static int b43_upload_microcode(struct b43_wldev *dev)
1791 {
1792 const size_t hdr_len = sizeof(struct b43_fw_header);
1793 const __be32 *data;
1794 unsigned int i, len;
1795 u16 fwrev, fwpatch, fwdate, fwtime;
1796 u32 tmp, macctl;
1797 int err = 0;
1798
1799 /* Jump the microcode PSM to offset 0 */
1800 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1801 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1802 macctl |= B43_MACCTL_PSM_JMP0;
1803 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1804 /* Zero out all microcode PSM registers and shared memory. */
1805 for (i = 0; i < 64; i++)
1806 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1807 for (i = 0; i < 4096; i += 2)
1808 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1809
1810 /* Upload Microcode. */
1811 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1812 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1813 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1814 for (i = 0; i < len; i++) {
1815 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1816 udelay(10);
1817 }
1818
1819 if (dev->fw.pcm.data) {
1820 /* Upload PCM data. */
1821 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1822 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1823 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1824 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1825 /* No need for autoinc bit in SHM_HW */
1826 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1827 for (i = 0; i < len; i++) {
1828 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1829 udelay(10);
1830 }
1831 }
1832
1833 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1834
1835 /* Start the microcode PSM */
1836 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1837 macctl &= ~B43_MACCTL_PSM_JMP0;
1838 macctl |= B43_MACCTL_PSM_RUN;
1839 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1840
1841 /* Wait for the microcode to load and respond */
1842 i = 0;
1843 while (1) {
1844 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1845 if (tmp == B43_IRQ_MAC_SUSPENDED)
1846 break;
1847 i++;
1848 if (i >= 20) {
1849 b43err(dev->wl, "Microcode not responding\n");
1850 b43_print_fw_helptext(dev->wl, 1);
1851 err = -ENODEV;
1852 goto error;
1853 }
1854 msleep_interruptible(50);
1855 if (signal_pending(current)) {
1856 err = -EINTR;
1857 goto error;
1858 }
1859 }
1860 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1861
1862 /* Get and check the revisions. */
1863 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1864 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1865 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1866 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1867
1868 if (fwrev <= 0x128) {
1869 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1870 "binary drivers older than version 4.x is unsupported. "
1871 "You must upgrade your firmware files.\n");
1872 b43_print_fw_helptext(dev->wl, 1);
1873 err = -EOPNOTSUPP;
1874 goto error;
1875 }
1876 b43info(dev->wl, "Loading firmware version %u.%u "
1877 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1878 fwrev, fwpatch,
1879 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1880 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1881
1882 dev->fw.rev = fwrev;
1883 dev->fw.patch = fwpatch;
1884
1885 if (b43_is_old_txhdr_format(dev)) {
1886 b43warn(dev->wl, "You are using an old firmware image. "
1887 "Support for old firmware will be removed in July 2008.\n");
1888 b43_print_fw_helptext(dev->wl, 0);
1889 }
1890
1891 return 0;
1892
1893 error:
1894 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1895 macctl &= ~B43_MACCTL_PSM_RUN;
1896 macctl |= B43_MACCTL_PSM_JMP0;
1897 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1898
1899 return err;
1900 }
1901
1902 static int b43_write_initvals(struct b43_wldev *dev,
1903 const struct b43_iv *ivals,
1904 size_t count,
1905 size_t array_size)
1906 {
1907 const struct b43_iv *iv;
1908 u16 offset;
1909 size_t i;
1910 bool bit32;
1911
1912 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1913 iv = ivals;
1914 for (i = 0; i < count; i++) {
1915 if (array_size < sizeof(iv->offset_size))
1916 goto err_format;
1917 array_size -= sizeof(iv->offset_size);
1918 offset = be16_to_cpu(iv->offset_size);
1919 bit32 = !!(offset & B43_IV_32BIT);
1920 offset &= B43_IV_OFFSET_MASK;
1921 if (offset >= 0x1000)
1922 goto err_format;
1923 if (bit32) {
1924 u32 value;
1925
1926 if (array_size < sizeof(iv->data.d32))
1927 goto err_format;
1928 array_size -= sizeof(iv->data.d32);
1929
1930 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1931 b43_write32(dev, offset, value);
1932
1933 iv = (const struct b43_iv *)((const uint8_t *)iv +
1934 sizeof(__be16) +
1935 sizeof(__be32));
1936 } else {
1937 u16 value;
1938
1939 if (array_size < sizeof(iv->data.d16))
1940 goto err_format;
1941 array_size -= sizeof(iv->data.d16);
1942
1943 value = be16_to_cpu(iv->data.d16);
1944 b43_write16(dev, offset, value);
1945
1946 iv = (const struct b43_iv *)((const uint8_t *)iv +
1947 sizeof(__be16) +
1948 sizeof(__be16));
1949 }
1950 }
1951 if (array_size)
1952 goto err_format;
1953
1954 return 0;
1955
1956 err_format:
1957 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1958 b43_print_fw_helptext(dev->wl, 1);
1959
1960 return -EPROTO;
1961 }
1962
1963 static int b43_upload_initvals(struct b43_wldev *dev)
1964 {
1965 const size_t hdr_len = sizeof(struct b43_fw_header);
1966 const struct b43_fw_header *hdr;
1967 struct b43_firmware *fw = &dev->fw;
1968 const struct b43_iv *ivals;
1969 size_t count;
1970 int err;
1971
1972 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1973 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1974 count = be32_to_cpu(hdr->size);
1975 err = b43_write_initvals(dev, ivals, count,
1976 fw->initvals.data->size - hdr_len);
1977 if (err)
1978 goto out;
1979 if (fw->initvals_band.data) {
1980 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1981 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1982 count = be32_to_cpu(hdr->size);
1983 err = b43_write_initvals(dev, ivals, count,
1984 fw->initvals_band.data->size - hdr_len);
1985 if (err)
1986 goto out;
1987 }
1988 out:
1989
1990 return err;
1991 }
1992
1993 /* Initialize the GPIOs
1994 * http://bcm-specs.sipsolutions.net/GPIO
1995 */
1996 static int b43_gpio_init(struct b43_wldev *dev)
1997 {
1998 struct ssb_bus *bus = dev->dev->bus;
1999 struct ssb_device *gpiodev, *pcidev = NULL;
2000 u32 mask, set;
2001
2002 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2003 & ~B43_MACCTL_GPOUTSMSK);
2004
2005 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2006 | 0x000F);
2007
2008 mask = 0x0000001F;
2009 set = 0x0000000F;
2010 if (dev->dev->bus->chip_id == 0x4301) {
2011 mask |= 0x0060;
2012 set |= 0x0060;
2013 }
2014 if (0 /* FIXME: conditional unknown */ ) {
2015 b43_write16(dev, B43_MMIO_GPIO_MASK,
2016 b43_read16(dev, B43_MMIO_GPIO_MASK)
2017 | 0x0100);
2018 mask |= 0x0180;
2019 set |= 0x0180;
2020 }
2021 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2022 b43_write16(dev, B43_MMIO_GPIO_MASK,
2023 b43_read16(dev, B43_MMIO_GPIO_MASK)
2024 | 0x0200);
2025 mask |= 0x0200;
2026 set |= 0x0200;
2027 }
2028 if (dev->dev->id.revision >= 2)
2029 mask |= 0x0010; /* FIXME: This is redundant. */
2030
2031 #ifdef CONFIG_SSB_DRIVER_PCICORE
2032 pcidev = bus->pcicore.dev;
2033 #endif
2034 gpiodev = bus->chipco.dev ? : pcidev;
2035 if (!gpiodev)
2036 return 0;
2037 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2038 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2039 & mask) | set);
2040
2041 return 0;
2042 }
2043
2044 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2045 static void b43_gpio_cleanup(struct b43_wldev *dev)
2046 {
2047 struct ssb_bus *bus = dev->dev->bus;
2048 struct ssb_device *gpiodev, *pcidev = NULL;
2049
2050 #ifdef CONFIG_SSB_DRIVER_PCICORE
2051 pcidev = bus->pcicore.dev;
2052 #endif
2053 gpiodev = bus->chipco.dev ? : pcidev;
2054 if (!gpiodev)
2055 return;
2056 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2057 }
2058
2059 /* http://bcm-specs.sipsolutions.net/EnableMac */
2060 void b43_mac_enable(struct b43_wldev *dev)
2061 {
2062 dev->mac_suspended--;
2063 B43_WARN_ON(dev->mac_suspended < 0);
2064 if (dev->mac_suspended == 0) {
2065 b43_write32(dev, B43_MMIO_MACCTL,
2066 b43_read32(dev, B43_MMIO_MACCTL)
2067 | B43_MACCTL_ENABLED);
2068 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2069 B43_IRQ_MAC_SUSPENDED);
2070 /* Commit writes */
2071 b43_read32(dev, B43_MMIO_MACCTL);
2072 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2073 b43_power_saving_ctl_bits(dev, 0);
2074
2075 /* Re-enable IRQs. */
2076 spin_lock_irq(&dev->wl->irq_lock);
2077 b43_interrupt_enable(dev, dev->irq_savedstate);
2078 spin_unlock_irq(&dev->wl->irq_lock);
2079 }
2080 }
2081
2082 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2083 void b43_mac_suspend(struct b43_wldev *dev)
2084 {
2085 int i;
2086 u32 tmp;
2087
2088 might_sleep();
2089 B43_WARN_ON(dev->mac_suspended < 0);
2090
2091 if (dev->mac_suspended == 0) {
2092 /* Mask IRQs before suspending MAC. Otherwise
2093 * the MAC stays busy and won't suspend. */
2094 spin_lock_irq(&dev->wl->irq_lock);
2095 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2096 spin_unlock_irq(&dev->wl->irq_lock);
2097 b43_synchronize_irq(dev);
2098 dev->irq_savedstate = tmp;
2099
2100 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2101 b43_write32(dev, B43_MMIO_MACCTL,
2102 b43_read32(dev, B43_MMIO_MACCTL)
2103 & ~B43_MACCTL_ENABLED);
2104 /* force pci to flush the write */
2105 b43_read32(dev, B43_MMIO_MACCTL);
2106 for (i = 40; i; i--) {
2107 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2108 if (tmp & B43_IRQ_MAC_SUSPENDED)
2109 goto out;
2110 msleep(1);
2111 }
2112 b43err(dev->wl, "MAC suspend failed\n");
2113 }
2114 out:
2115 dev->mac_suspended++;
2116 }
2117
2118 static void b43_adjust_opmode(struct b43_wldev *dev)
2119 {
2120 struct b43_wl *wl = dev->wl;
2121 u32 ctl;
2122 u16 cfp_pretbtt;
2123
2124 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2125 /* Reset status to STA infrastructure mode. */
2126 ctl &= ~B43_MACCTL_AP;
2127 ctl &= ~B43_MACCTL_KEEP_CTL;
2128 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2129 ctl &= ~B43_MACCTL_KEEP_BAD;
2130 ctl &= ~B43_MACCTL_PROMISC;
2131 ctl &= ~B43_MACCTL_BEACPROMISC;
2132 ctl |= B43_MACCTL_INFRA;
2133
2134 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2135 ctl |= B43_MACCTL_AP;
2136 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2137 ctl &= ~B43_MACCTL_INFRA;
2138
2139 if (wl->filter_flags & FIF_CONTROL)
2140 ctl |= B43_MACCTL_KEEP_CTL;
2141 if (wl->filter_flags & FIF_FCSFAIL)
2142 ctl |= B43_MACCTL_KEEP_BAD;
2143 if (wl->filter_flags & FIF_PLCPFAIL)
2144 ctl |= B43_MACCTL_KEEP_BADPLCP;
2145 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2146 ctl |= B43_MACCTL_PROMISC;
2147 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2148 ctl |= B43_MACCTL_BEACPROMISC;
2149
2150 /* Workaround: On old hardware the HW-MAC-address-filter
2151 * doesn't work properly, so always run promisc in filter
2152 * it in software. */
2153 if (dev->dev->id.revision <= 4)
2154 ctl |= B43_MACCTL_PROMISC;
2155
2156 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2157
2158 cfp_pretbtt = 2;
2159 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2160 if (dev->dev->bus->chip_id == 0x4306 &&
2161 dev->dev->bus->chip_rev == 3)
2162 cfp_pretbtt = 100;
2163 else
2164 cfp_pretbtt = 50;
2165 }
2166 b43_write16(dev, 0x612, cfp_pretbtt);
2167 }
2168
2169 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2170 {
2171 u16 offset;
2172
2173 if (is_ofdm) {
2174 offset = 0x480;
2175 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2176 } else {
2177 offset = 0x4C0;
2178 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2179 }
2180 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2181 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2182 }
2183
2184 static void b43_rate_memory_init(struct b43_wldev *dev)
2185 {
2186 switch (dev->phy.type) {
2187 case B43_PHYTYPE_A:
2188 case B43_PHYTYPE_G:
2189 case B43_PHYTYPE_N:
2190 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2191 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2192 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2193 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2194 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2195 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2196 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2197 if (dev->phy.type == B43_PHYTYPE_A)
2198 break;
2199 /* fallthrough */
2200 case B43_PHYTYPE_B:
2201 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2202 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2203 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2204 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2205 break;
2206 default:
2207 B43_WARN_ON(1);
2208 }
2209 }
2210
2211 /* Set the TX-Antenna for management frames sent by firmware. */
2212 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2213 {
2214 u16 ant = 0;
2215 u16 tmp;
2216
2217 switch (antenna) {
2218 case B43_ANTENNA0:
2219 ant |= B43_TXH_PHY_ANT0;
2220 break;
2221 case B43_ANTENNA1:
2222 ant |= B43_TXH_PHY_ANT1;
2223 break;
2224 case B43_ANTENNA2:
2225 ant |= B43_TXH_PHY_ANT2;
2226 break;
2227 case B43_ANTENNA3:
2228 ant |= B43_TXH_PHY_ANT3;
2229 break;
2230 case B43_ANTENNA_AUTO:
2231 ant |= B43_TXH_PHY_ANT01AUTO;
2232 break;
2233 default:
2234 B43_WARN_ON(1);
2235 }
2236
2237 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2238
2239 /* For Beacons */
2240 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2241 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2242 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2243 /* For ACK/CTS */
2244 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2245 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2246 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2247 /* For Probe Resposes */
2248 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2249 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2250 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2251 }
2252
2253 /* This is the opposite of b43_chip_init() */
2254 static void b43_chip_exit(struct b43_wldev *dev)
2255 {
2256 b43_radio_turn_off(dev, 1);
2257 b43_gpio_cleanup(dev);
2258 /* firmware is released later */
2259 }
2260
2261 /* Initialize the chip
2262 * http://bcm-specs.sipsolutions.net/ChipInit
2263 */
2264 static int b43_chip_init(struct b43_wldev *dev)
2265 {
2266 struct b43_phy *phy = &dev->phy;
2267 int err, tmp;
2268 u32 value32, macctl;
2269 u16 value16;
2270
2271 /* Initialize the MAC control */
2272 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2273 if (dev->phy.gmode)
2274 macctl |= B43_MACCTL_GMODE;
2275 macctl |= B43_MACCTL_INFRA;
2276 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2277
2278 err = b43_request_firmware(dev);
2279 if (err)
2280 goto out;
2281 err = b43_upload_microcode(dev);
2282 if (err)
2283 goto out; /* firmware is released later */
2284
2285 err = b43_gpio_init(dev);
2286 if (err)
2287 goto out; /* firmware is released later */
2288
2289 err = b43_upload_initvals(dev);
2290 if (err)
2291 goto err_gpio_clean;
2292 b43_radio_turn_on(dev);
2293
2294 b43_write16(dev, 0x03E6, 0x0000);
2295 err = b43_phy_init(dev);
2296 if (err)
2297 goto err_radio_off;
2298
2299 /* Select initial Interference Mitigation. */
2300 tmp = phy->interfmode;
2301 phy->interfmode = B43_INTERFMODE_NONE;
2302 b43_radio_set_interference_mitigation(dev, tmp);
2303
2304 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2305 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2306
2307 if (phy->type == B43_PHYTYPE_B) {
2308 value16 = b43_read16(dev, 0x005E);
2309 value16 |= 0x0004;
2310 b43_write16(dev, 0x005E, value16);
2311 }
2312 b43_write32(dev, 0x0100, 0x01000000);
2313 if (dev->dev->id.revision < 5)
2314 b43_write32(dev, 0x010C, 0x01000000);
2315
2316 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2317 & ~B43_MACCTL_INFRA);
2318 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2319 | B43_MACCTL_INFRA);
2320
2321 /* Probe Response Timeout value */
2322 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2323 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2324
2325 /* Initially set the wireless operation mode. */
2326 b43_adjust_opmode(dev);
2327
2328 if (dev->dev->id.revision < 3) {
2329 b43_write16(dev, 0x060E, 0x0000);
2330 b43_write16(dev, 0x0610, 0x8000);
2331 b43_write16(dev, 0x0604, 0x0000);
2332 b43_write16(dev, 0x0606, 0x0200);
2333 } else {
2334 b43_write32(dev, 0x0188, 0x80000000);
2335 b43_write32(dev, 0x018C, 0x02000000);
2336 }
2337 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2338 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2339 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2340 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2341 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2342 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2343 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2344
2345 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2346 value32 |= 0x00100000;
2347 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2348
2349 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2350 dev->dev->bus->chipco.fast_pwrup_delay);
2351
2352 err = 0;
2353 b43dbg(dev->wl, "Chip initialized\n");
2354 out:
2355 return err;
2356
2357 err_radio_off:
2358 b43_radio_turn_off(dev, 1);
2359 err_gpio_clean:
2360 b43_gpio_cleanup(dev);
2361 return err;
2362 }
2363
2364 static void b43_periodic_every120sec(struct b43_wldev *dev)
2365 {
2366 struct b43_phy *phy = &dev->phy;
2367
2368 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2369 return;
2370
2371 b43_mac_suspend(dev);
2372 b43_lo_g_measure(dev);
2373 b43_mac_enable(dev);
2374 if (b43_has_hardware_pctl(phy))
2375 b43_lo_g_ctl_mark_all_unused(dev);
2376 }
2377
2378 static void b43_periodic_every60sec(struct b43_wldev *dev)
2379 {
2380 struct b43_phy *phy = &dev->phy;
2381
2382 if (phy->type != B43_PHYTYPE_G)
2383 return;
2384 if (!b43_has_hardware_pctl(phy))
2385 b43_lo_g_ctl_mark_all_unused(dev);
2386 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2387 b43_mac_suspend(dev);
2388 b43_calc_nrssi_slope(dev);
2389 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2390 u8 old_chan = phy->channel;
2391
2392 /* VCO Calibration */
2393 if (old_chan >= 8)
2394 b43_radio_selectchannel(dev, 1, 0);
2395 else
2396 b43_radio_selectchannel(dev, 13, 0);
2397 b43_radio_selectchannel(dev, old_chan, 0);
2398 }
2399 b43_mac_enable(dev);
2400 }
2401 }
2402
2403 static void b43_periodic_every30sec(struct b43_wldev *dev)
2404 {
2405 /* Update device statistics. */
2406 b43_calculate_link_quality(dev);
2407 }
2408
2409 static void b43_periodic_every15sec(struct b43_wldev *dev)
2410 {
2411 struct b43_phy *phy = &dev->phy;
2412
2413 if (phy->type == B43_PHYTYPE_G) {
2414 //TODO: update_aci_moving_average
2415 if (phy->aci_enable && phy->aci_wlan_automatic) {
2416 b43_mac_suspend(dev);
2417 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2418 if (0 /*TODO: bunch of conditions */ ) {
2419 b43_radio_set_interference_mitigation
2420 (dev, B43_INTERFMODE_MANUALWLAN);
2421 }
2422 } else if (1 /*TODO*/) {
2423 /*
2424 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2425 b43_radio_set_interference_mitigation(dev,
2426 B43_INTERFMODE_NONE);
2427 }
2428 */
2429 }
2430 b43_mac_enable(dev);
2431 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2432 phy->rev == 1) {
2433 //TODO: implement rev1 workaround
2434 }
2435 }
2436 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2437 //TODO for APHY (temperature?)
2438
2439 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2440 wmb();
2441 }
2442
2443 static void do_periodic_work(struct b43_wldev *dev)
2444 {
2445 unsigned int state;
2446
2447 state = dev->periodic_state;
2448 if (state % 8 == 0)
2449 b43_periodic_every120sec(dev);
2450 if (state % 4 == 0)
2451 b43_periodic_every60sec(dev);
2452 if (state % 2 == 0)
2453 b43_periodic_every30sec(dev);
2454 b43_periodic_every15sec(dev);
2455 }
2456
2457 /* Periodic work locking policy:
2458 * The whole periodic work handler is protected by
2459 * wl->mutex. If another lock is needed somewhere in the
2460 * pwork callchain, it's aquired in-place, where it's needed.
2461 */
2462 static void b43_periodic_work_handler(struct work_struct *work)
2463 {
2464 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2465 periodic_work.work);
2466 struct b43_wl *wl = dev->wl;
2467 unsigned long delay;
2468
2469 mutex_lock(&wl->mutex);
2470
2471 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2472 goto out;
2473 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2474 goto out_requeue;
2475
2476 do_periodic_work(dev);
2477
2478 dev->periodic_state++;
2479 out_requeue:
2480 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2481 delay = msecs_to_jiffies(50);
2482 else
2483 delay = round_jiffies_relative(HZ * 15);
2484 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2485 out:
2486 mutex_unlock(&wl->mutex);
2487 }
2488
2489 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2490 {
2491 struct delayed_work *work = &dev->periodic_work;
2492
2493 dev->periodic_state = 0;
2494 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2495 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2496 }
2497
2498 /* Check if communication with the device works correctly. */
2499 static int b43_validate_chipaccess(struct b43_wldev *dev)
2500 {
2501 u32 v, backup;
2502
2503 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2504
2505 /* Check for read/write and endianness problems. */
2506 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2507 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2508 goto error;
2509 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2510 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2511 goto error;
2512
2513 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2514
2515 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2516 /* The 32bit register shadows the two 16bit registers
2517 * with update sideeffects. Validate this. */
2518 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2519 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2520 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2521 goto error;
2522 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2523 goto error;
2524 }
2525 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2526
2527 v = b43_read32(dev, B43_MMIO_MACCTL);
2528 v |= B43_MACCTL_GMODE;
2529 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2530 goto error;
2531
2532 return 0;
2533 error:
2534 b43err(dev->wl, "Failed to validate the chipaccess\n");
2535 return -ENODEV;
2536 }
2537
2538 static void b43_security_init(struct b43_wldev *dev)
2539 {
2540 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2541 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2542 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2543 /* KTP is a word address, but we address SHM bytewise.
2544 * So multiply by two.
2545 */
2546 dev->ktp *= 2;
2547 if (dev->dev->id.revision >= 5) {
2548 /* Number of RCMTA address slots */
2549 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2550 }
2551 b43_clear_keys(dev);
2552 }
2553
2554 static int b43_rng_read(struct hwrng *rng, u32 * data)
2555 {
2556 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2557 unsigned long flags;
2558
2559 /* Don't take wl->mutex here, as it could deadlock with
2560 * hwrng internal locking. It's not needed to take
2561 * wl->mutex here, anyway. */
2562
2563 spin_lock_irqsave(&wl->irq_lock, flags);
2564 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2565 spin_unlock_irqrestore(&wl->irq_lock, flags);
2566
2567 return (sizeof(u16));
2568 }
2569
2570 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2571 {
2572 if (wl->rng_initialized)
2573 __hwrng_unregister(&wl->rng, suspended);
2574 }
2575
2576 static int b43_rng_init(struct b43_wl *wl)
2577 {
2578 int err;
2579
2580 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2581 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2582 wl->rng.name = wl->rng_name;
2583 wl->rng.data_read = b43_rng_read;
2584 wl->rng.priv = (unsigned long)wl;
2585 wl->rng_initialized = 1;
2586 err = hwrng_register(&wl->rng);
2587 if (err) {
2588 wl->rng_initialized = 0;
2589 b43err(wl, "Failed to register the random "
2590 "number generator (%d)\n", err);
2591 }
2592
2593 return err;
2594 }
2595
2596 static int b43_op_tx(struct ieee80211_hw *hw,
2597 struct sk_buff *skb,
2598 struct ieee80211_tx_control *ctl)
2599 {
2600 struct b43_wl *wl = hw_to_b43_wl(hw);
2601 struct b43_wldev *dev = wl->current_dev;
2602 unsigned long flags;
2603 int err;
2604
2605 if (unlikely(!dev))
2606 return NETDEV_TX_BUSY;
2607
2608 /* Transmissions on seperate queues can run concurrently. */
2609 read_lock_irqsave(&wl->tx_lock, flags);
2610
2611 err = -ENODEV;
2612 if (likely(b43_status(dev) >= B43_STAT_STARTED))
2613 err = b43_dma_tx(dev, skb, ctl);
2614
2615 read_unlock_irqrestore(&wl->tx_lock, flags);
2616
2617 if (unlikely(err))
2618 return NETDEV_TX_BUSY;
2619 return NETDEV_TX_OK;
2620 }
2621
2622 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2623 int queue,
2624 const struct ieee80211_tx_queue_params *params)
2625 {
2626 return 0;
2627 }
2628
2629 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2630 struct ieee80211_tx_queue_stats *stats)
2631 {
2632 struct b43_wl *wl = hw_to_b43_wl(hw);
2633 struct b43_wldev *dev = wl->current_dev;
2634 unsigned long flags;
2635 int err = -ENODEV;
2636
2637 if (!dev)
2638 goto out;
2639 spin_lock_irqsave(&wl->irq_lock, flags);
2640 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2641 b43_dma_get_tx_stats(dev, stats);
2642 err = 0;
2643 }
2644 spin_unlock_irqrestore(&wl->irq_lock, flags);
2645 out:
2646 return err;
2647 }
2648
2649 static int b43_op_get_stats(struct ieee80211_hw *hw,
2650 struct ieee80211_low_level_stats *stats)
2651 {
2652 struct b43_wl *wl = hw_to_b43_wl(hw);
2653 unsigned long flags;
2654
2655 spin_lock_irqsave(&wl->irq_lock, flags);
2656 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2657 spin_unlock_irqrestore(&wl->irq_lock, flags);
2658
2659 return 0;
2660 }
2661
2662 static const char *phymode_to_string(unsigned int phymode)
2663 {
2664 switch (phymode) {
2665 case B43_PHYMODE_A:
2666 return "A";
2667 case B43_PHYMODE_B:
2668 return "B";
2669 case B43_PHYMODE_G:
2670 return "G";
2671 default:
2672 B43_WARN_ON(1);
2673 }
2674 return "";
2675 }
2676
2677 static int find_wldev_for_phymode(struct b43_wl *wl,
2678 unsigned int phymode,
2679 struct b43_wldev **dev, bool * gmode)
2680 {
2681 struct b43_wldev *d;
2682
2683 list_for_each_entry(d, &wl->devlist, list) {
2684 if (d->phy.possible_phymodes & phymode) {
2685 /* Ok, this device supports the PHY-mode.
2686 * Now figure out how the gmode bit has to be
2687 * set to support it. */
2688 if (phymode == B43_PHYMODE_A)
2689 *gmode = 0;
2690 else
2691 *gmode = 1;
2692 *dev = d;
2693
2694 return 0;
2695 }
2696 }
2697
2698 return -ESRCH;
2699 }
2700
2701 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2702 {
2703 struct ssb_device *sdev = dev->dev;
2704 u32 tmslow;
2705
2706 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2707 tmslow &= ~B43_TMSLOW_GMODE;
2708 tmslow |= B43_TMSLOW_PHYRESET;
2709 tmslow |= SSB_TMSLOW_FGC;
2710 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2711 msleep(1);
2712
2713 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2714 tmslow &= ~SSB_TMSLOW_FGC;
2715 tmslow |= B43_TMSLOW_PHYRESET;
2716 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2717 msleep(1);
2718 }
2719
2720 /* Expects wl->mutex locked */
2721 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2722 {
2723 struct b43_wldev *up_dev;
2724 struct b43_wldev *down_dev;
2725 int err;
2726 bool gmode = 0;
2727 int prev_status;
2728
2729 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2730 if (err) {
2731 b43err(wl, "Could not find a device for %s-PHY mode\n",
2732 phymode_to_string(new_mode));
2733 return err;
2734 }
2735 if ((up_dev == wl->current_dev) &&
2736 (!!wl->current_dev->phy.gmode == !!gmode)) {
2737 /* This device is already running. */
2738 return 0;
2739 }
2740 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2741 phymode_to_string(new_mode));
2742 down_dev = wl->current_dev;
2743
2744 prev_status = b43_status(down_dev);
2745 /* Shutdown the currently running core. */
2746 if (prev_status >= B43_STAT_STARTED)
2747 b43_wireless_core_stop(down_dev);
2748 if (prev_status >= B43_STAT_INITIALIZED)
2749 b43_wireless_core_exit(down_dev);
2750
2751 if (down_dev != up_dev) {
2752 /* We switch to a different core, so we put PHY into
2753 * RESET on the old core. */
2754 b43_put_phy_into_reset(down_dev);
2755 }
2756
2757 /* Now start the new core. */
2758 up_dev->phy.gmode = gmode;
2759 if (prev_status >= B43_STAT_INITIALIZED) {
2760 err = b43_wireless_core_init(up_dev);
2761 if (err) {
2762 b43err(wl, "Fatal: Could not initialize device for "
2763 "newly selected %s-PHY mode\n",
2764 phymode_to_string(new_mode));
2765 goto init_failure;
2766 }
2767 }
2768 if (prev_status >= B43_STAT_STARTED) {
2769 err = b43_wireless_core_start(up_dev);
2770 if (err) {
2771 b43err(wl, "Fatal: Coult not start device for "
2772 "newly selected %s-PHY mode\n",
2773 phymode_to_string(new_mode));
2774 b43_wireless_core_exit(up_dev);
2775 goto init_failure;
2776 }
2777 }
2778 B43_WARN_ON(b43_status(up_dev) != prev_status);
2779
2780 wl->current_dev = up_dev;
2781
2782 return 0;
2783 init_failure:
2784 /* Whoops, failed to init the new core. No core is operating now. */
2785 wl->current_dev = NULL;
2786 return err;
2787 }
2788
2789 /* Check if the use of the antenna that ieee80211 told us to
2790 * use is possible. This will fall back to DEFAULT.
2791 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2792 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2793 u8 antenna_nr)
2794 {
2795 u8 antenna_mask;
2796
2797 if (antenna_nr == 0) {
2798 /* Zero means "use default antenna". That's always OK. */
2799 return 0;
2800 }
2801
2802 /* Get the mask of available antennas. */
2803 if (dev->phy.gmode)
2804 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2805 else
2806 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2807
2808 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2809 /* This antenna is not available. Fall back to default. */
2810 return 0;
2811 }
2812
2813 return antenna_nr;
2814 }
2815
2816 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2817 {
2818 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2819 switch (antenna) {
2820 case 0: /* default/diversity */
2821 return B43_ANTENNA_DEFAULT;
2822 case 1: /* Antenna 0 */
2823 return B43_ANTENNA0;
2824 case 2: /* Antenna 1 */
2825 return B43_ANTENNA1;
2826 case 3: /* Antenna 2 */
2827 return B43_ANTENNA2;
2828 case 4: /* Antenna 3 */
2829 return B43_ANTENNA3;
2830 default:
2831 return B43_ANTENNA_DEFAULT;
2832 }
2833 }
2834
2835 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2836 {
2837 struct b43_wl *wl = hw_to_b43_wl(hw);
2838 struct b43_wldev *dev;
2839 struct b43_phy *phy;
2840 unsigned long flags;
2841 unsigned int new_phymode = 0xFFFF;
2842 int antenna;
2843 int err = 0;
2844 u32 savedirqs;
2845
2846 mutex_lock(&wl->mutex);
2847
2848 /* Switch the PHY mode (if necessary). */
2849 switch (conf->phymode) {
2850 case MODE_IEEE80211A:
2851 new_phymode = B43_PHYMODE_A;
2852 break;
2853 case MODE_IEEE80211B:
2854 new_phymode = B43_PHYMODE_B;
2855 break;
2856 case MODE_IEEE80211G:
2857 new_phymode = B43_PHYMODE_G;
2858 break;
2859 default:
2860 B43_WARN_ON(1);
2861 }
2862 err = b43_switch_phymode(wl, new_phymode);
2863 if (err)
2864 goto out_unlock_mutex;
2865 dev = wl->current_dev;
2866 phy = &dev->phy;
2867
2868 /* Disable IRQs while reconfiguring the device.
2869 * This makes it possible to drop the spinlock throughout
2870 * the reconfiguration process. */
2871 spin_lock_irqsave(&wl->irq_lock, flags);
2872 if (b43_status(dev) < B43_STAT_STARTED) {
2873 spin_unlock_irqrestore(&wl->irq_lock, flags);
2874 goto out_unlock_mutex;
2875 }
2876 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2877 spin_unlock_irqrestore(&wl->irq_lock, flags);
2878 b43_synchronize_irq(dev);
2879
2880 /* Switch to the requested channel.
2881 * The firmware takes care of races with the TX handler. */
2882 if (conf->channel_val != phy->channel)
2883 b43_radio_selectchannel(dev, conf->channel_val, 0);
2884
2885 /* Enable/Disable ShortSlot timing. */
2886 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2887 dev->short_slot) {
2888 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2889 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2890 b43_short_slot_timing_enable(dev);
2891 else
2892 b43_short_slot_timing_disable(dev);
2893 }
2894
2895 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2896
2897 /* Adjust the desired TX power level. */
2898 if (conf->power_level != 0) {
2899 if (conf->power_level != phy->power_level) {
2900 phy->power_level = conf->power_level;
2901 b43_phy_xmitpower(dev);
2902 }
2903 }
2904
2905 /* Antennas for RX and management frame TX. */
2906 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2907 b43_mgmtframe_txantenna(dev, antenna);
2908 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2909 b43_set_rx_antenna(dev, antenna);
2910
2911 /* Update templates for AP mode. */
2912 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2913 b43_set_beacon_int(dev, conf->beacon_int);
2914
2915 if (!!conf->radio_enabled != phy->radio_on) {
2916 if (conf->radio_enabled) {
2917 b43_radio_turn_on(dev);
2918 b43info(dev->wl, "Radio turned on by software\n");
2919 if (!dev->radio_hw_enable) {
2920 b43info(dev->wl, "The hardware RF-kill button "
2921 "still turns the radio physically off. "
2922 "Press the button to turn it on.\n");
2923 }
2924 } else {
2925 b43_radio_turn_off(dev, 0);
2926 b43info(dev->wl, "Radio turned off by software\n");
2927 }
2928 }
2929
2930 spin_lock_irqsave(&wl->irq_lock, flags);
2931 b43_interrupt_enable(dev, savedirqs);
2932 mmiowb();
2933 spin_unlock_irqrestore(&wl->irq_lock, flags);
2934 out_unlock_mutex:
2935 mutex_unlock(&wl->mutex);
2936
2937 return err;
2938 }
2939
2940 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2941 const u8 *local_addr, const u8 *addr,
2942 struct ieee80211_key_conf *key)
2943 {
2944 struct b43_wl *wl = hw_to_b43_wl(hw);
2945 struct b43_wldev *dev;
2946 unsigned long flags;
2947 u8 algorithm;
2948 u8 index;
2949 int err;
2950 DECLARE_MAC_BUF(mac);
2951
2952 if (modparam_nohwcrypt)
2953 return -ENOSPC; /* User disabled HW-crypto */
2954
2955 mutex_lock(&wl->mutex);
2956 spin_lock_irqsave(&wl->irq_lock, flags);
2957
2958 dev = wl->current_dev;
2959 err = -ENODEV;
2960 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2961 goto out_unlock;
2962
2963 err = -EINVAL;
2964 switch (key->alg) {
2965 case ALG_WEP:
2966 if (key->keylen == 5)
2967 algorithm = B43_SEC_ALGO_WEP40;
2968 else
2969 algorithm = B43_SEC_ALGO_WEP104;
2970 break;
2971 case ALG_TKIP:
2972 algorithm = B43_SEC_ALGO_TKIP;
2973 break;
2974 case ALG_CCMP:
2975 algorithm = B43_SEC_ALGO_AES;
2976 break;
2977 default:
2978 B43_WARN_ON(1);
2979 goto out_unlock;
2980 }
2981 index = (u8) (key->keyidx);
2982 if (index > 3)
2983 goto out_unlock;
2984
2985 switch (cmd) {
2986 case SET_KEY:
2987 if (algorithm == B43_SEC_ALGO_TKIP) {
2988 /* FIXME: No TKIP hardware encryption for now. */
2989 err = -EOPNOTSUPP;
2990 goto out_unlock;
2991 }
2992
2993 if (is_broadcast_ether_addr(addr)) {
2994 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2995 err = b43_key_write(dev, index, algorithm,
2996 key->key, key->keylen, NULL, key);
2997 } else {
2998 /*
2999 * either pairwise key or address is 00:00:00:00:00:00
3000 * for transmit-only keys
3001 */
3002 err = b43_key_write(dev, -1, algorithm,
3003 key->key, key->keylen, addr, key);
3004 }
3005 if (err)
3006 goto out_unlock;
3007
3008 if (algorithm == B43_SEC_ALGO_WEP40 ||
3009 algorithm == B43_SEC_ALGO_WEP104) {
3010 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3011 } else {
3012 b43_hf_write(dev,
3013 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3014 }
3015 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3016 break;
3017 case DISABLE_KEY: {
3018 err = b43_key_clear(dev, key->hw_key_idx);
3019 if (err)
3020 goto out_unlock;
3021 break;
3022 }
3023 default:
3024 B43_WARN_ON(1);
3025 }
3026 out_unlock:
3027 spin_unlock_irqrestore(&wl->irq_lock, flags);
3028 mutex_unlock(&wl->mutex);
3029 if (!err) {
3030 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3031 "mac: %s\n",
3032 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3033 print_mac(mac, addr));
3034 }
3035 return err;
3036 }
3037
3038 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3039 unsigned int changed, unsigned int *fflags,
3040 int mc_count, struct dev_addr_list *mc_list)
3041 {
3042 struct b43_wl *wl = hw_to_b43_wl(hw);
3043 struct b43_wldev *dev = wl->current_dev;
3044 unsigned long flags;
3045
3046 if (!dev) {
3047 *fflags = 0;
3048 return;
3049 }
3050
3051 spin_lock_irqsave(&wl->irq_lock, flags);
3052 *fflags &= FIF_PROMISC_IN_BSS |
3053 FIF_ALLMULTI |
3054 FIF_FCSFAIL |
3055 FIF_PLCPFAIL |
3056 FIF_CONTROL |
3057 FIF_OTHER_BSS |
3058 FIF_BCN_PRBRESP_PROMISC;
3059
3060 changed &= FIF_PROMISC_IN_BSS |
3061 FIF_ALLMULTI |
3062 FIF_FCSFAIL |
3063 FIF_PLCPFAIL |
3064 FIF_CONTROL |
3065 FIF_OTHER_BSS |
3066 FIF_BCN_PRBRESP_PROMISC;
3067
3068 wl->filter_flags = *fflags;
3069
3070 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3071 b43_adjust_opmode(dev);
3072 spin_unlock_irqrestore(&wl->irq_lock, flags);
3073 }
3074
3075 static int b43_op_config_interface(struct ieee80211_hw *hw,
3076 struct ieee80211_vif *vif,
3077 struct ieee80211_if_conf *conf)
3078 {
3079 struct b43_wl *wl = hw_to_b43_wl(hw);
3080 struct b43_wldev *dev = wl->current_dev;
3081 unsigned long flags;
3082
3083 if (!dev)
3084 return -ENODEV;
3085 mutex_lock(&wl->mutex);
3086 spin_lock_irqsave(&wl->irq_lock, flags);
3087 B43_WARN_ON(wl->vif != vif);
3088 if (conf->bssid)
3089 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3090 else
3091 memset(wl->bssid, 0, ETH_ALEN);
3092 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3093 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3094 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3095 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3096 if (conf->beacon)
3097 b43_update_templates(wl, conf->beacon);
3098 }
3099 b43_write_mac_bssid_templates(dev);
3100 }
3101 spin_unlock_irqrestore(&wl->irq_lock, flags);
3102 mutex_unlock(&wl->mutex);
3103
3104 return 0;
3105 }
3106
3107 /* Locking: wl->mutex */
3108 static void b43_wireless_core_stop(struct b43_wldev *dev)
3109 {
3110 struct b43_wl *wl = dev->wl;
3111 unsigned long flags;
3112
3113 if (b43_status(dev) < B43_STAT_STARTED)
3114 return;
3115
3116 /* Disable and sync interrupts. We must do this before than
3117 * setting the status to INITIALIZED, as the interrupt handler
3118 * won't care about IRQs then. */
3119 spin_lock_irqsave(&wl->irq_lock, flags);
3120 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3121 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3122 spin_unlock_irqrestore(&wl->irq_lock, flags);
3123 b43_synchronize_irq(dev);
3124
3125 write_lock_irqsave(&wl->tx_lock, flags);
3126 b43_set_status(dev, B43_STAT_INITIALIZED);
3127 write_unlock_irqrestore(&wl->tx_lock, flags);
3128
3129 mutex_unlock(&wl->mutex);
3130 /* Must unlock as it would otherwise deadlock. No races here.
3131 * Cancel the possibly running self-rearming periodic work. */
3132 cancel_delayed_work_sync(&dev->periodic_work);
3133 mutex_lock(&wl->mutex);
3134
3135 b43_mac_suspend(dev);
3136 free_irq(dev->dev->irq, dev);
3137 b43dbg(wl, "Wireless interface stopped\n");
3138 }
3139
3140 /* Locking: wl->mutex */
3141 static int b43_wireless_core_start(struct b43_wldev *dev)
3142 {
3143 int err;
3144
3145 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3146
3147 drain_txstatus_queue(dev);
3148 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3149 IRQF_SHARED, KBUILD_MODNAME, dev);
3150 if (err) {
3151 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3152 goto out;
3153 }
3154
3155 /* We are ready to run. */
3156 b43_set_status(dev, B43_STAT_STARTED);
3157
3158 /* Start data flow (TX/RX). */
3159 b43_mac_enable(dev);
3160 b43_interrupt_enable(dev, dev->irq_savedstate);
3161 ieee80211_start_queues(dev->wl->hw);
3162
3163 /* Start maintainance work */
3164 b43_periodic_tasks_setup(dev);
3165
3166 b43dbg(dev->wl, "Wireless interface started\n");
3167 out:
3168 return err;
3169 }
3170
3171 /* Get PHY and RADIO versioning numbers */
3172 static int b43_phy_versioning(struct b43_wldev *dev)
3173 {
3174 struct b43_phy *phy = &dev->phy;
3175 u32 tmp;
3176 u8 analog_type;
3177 u8 phy_type;
3178 u8 phy_rev;
3179 u16 radio_manuf;
3180 u16 radio_ver;
3181 u16 radio_rev;
3182 int unsupported = 0;
3183
3184 /* Get PHY versioning */
3185 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3186 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3187 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3188 phy_rev = (tmp & B43_PHYVER_VERSION);
3189 switch (phy_type) {
3190 case B43_PHYTYPE_A:
3191 if (phy_rev >= 4)
3192 unsupported = 1;
3193 break;
3194 case B43_PHYTYPE_B:
3195 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3196 && phy_rev != 7)
3197 unsupported = 1;
3198 break;
3199 case B43_PHYTYPE_G:
3200 if (phy_rev > 9)
3201 unsupported = 1;
3202 break;
3203 #ifdef CONFIG_B43_NPHY
3204 case B43_PHYTYPE_N:
3205 if (phy_rev > 1)
3206 unsupported = 1;
3207 break;
3208 #endif
3209 default:
3210 unsupported = 1;
3211 };
3212 if (unsupported) {
3213 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3214 "(Analog %u, Type %u, Revision %u)\n",
3215 analog_type, phy_type, phy_rev);
3216 return -EOPNOTSUPP;
3217 }
3218 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3219 analog_type, phy_type, phy_rev);
3220
3221 /* Get RADIO versioning */
3222 if (dev->dev->bus->chip_id == 0x4317) {
3223 if (dev->dev->bus->chip_rev == 0)
3224 tmp = 0x3205017F;
3225 else if (dev->dev->bus->chip_rev == 1)
3226 tmp = 0x4205017F;
3227 else
3228 tmp = 0x5205017F;
3229 } else {
3230 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3231 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3232 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3233 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3234 }
3235 radio_manuf = (tmp & 0x00000FFF);
3236 radio_ver = (tmp & 0x0FFFF000) >> 12;
3237 radio_rev = (tmp & 0xF0000000) >> 28;
3238 if (radio_manuf != 0x17F /* Broadcom */)
3239 unsupported = 1;
3240 switch (phy_type) {
3241 case B43_PHYTYPE_A:
3242 if (radio_ver != 0x2060)
3243 unsupported = 1;
3244 if (radio_rev != 1)
3245 unsupported = 1;
3246 if (radio_manuf != 0x17F)
3247 unsupported = 1;
3248 break;
3249 case B43_PHYTYPE_B:
3250 if ((radio_ver & 0xFFF0) != 0x2050)
3251 unsupported = 1;
3252 break;
3253 case B43_PHYTYPE_G:
3254 if (radio_ver != 0x2050)
3255 unsupported = 1;
3256 break;
3257 case B43_PHYTYPE_N:
3258 if (radio_ver != 0x2055)
3259 unsupported = 1;
3260 break;
3261 default:
3262 B43_WARN_ON(1);
3263 }
3264 if (unsupported) {
3265 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3266 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3267 radio_manuf, radio_ver, radio_rev);
3268 return -EOPNOTSUPP;
3269 }
3270 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3271 radio_manuf, radio_ver, radio_rev);
3272
3273 phy->radio_manuf = radio_manuf;
3274 phy->radio_ver = radio_ver;
3275 phy->radio_rev = radio_rev;
3276
3277 phy->analog = analog_type;
3278 phy->type = phy_type;
3279 phy->rev = phy_rev;
3280
3281 return 0;
3282 }
3283
3284 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3285 struct b43_phy *phy)
3286 {
3287 struct b43_txpower_lo_control *lo;
3288 int i;
3289
3290 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3291 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3292
3293 phy->aci_enable = 0;
3294 phy->aci_wlan_automatic = 0;
3295 phy->aci_hw_rssi = 0;
3296
3297 phy->radio_off_context.valid = 0;
3298
3299 lo = phy->lo_control;
3300 if (lo) {
3301 memset(lo, 0, sizeof(*(phy->lo_control)));
3302 lo->rebuild = 1;
3303 lo->tx_bias = 0xFF;
3304 }
3305 phy->max_lb_gain = 0;
3306 phy->trsw_rx_gain = 0;
3307 phy->txpwr_offset = 0;
3308
3309 /* NRSSI */
3310 phy->nrssislope = 0;
3311 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3312 phy->nrssi[i] = -1000;
3313 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3314 phy->nrssi_lt[i] = i;
3315
3316 phy->lofcal = 0xFFFF;
3317 phy->initval = 0xFFFF;
3318
3319 phy->interfmode = B43_INTERFMODE_NONE;
3320 phy->channel = 0xFF;
3321
3322 phy->hardware_power_control = !!modparam_hwpctl;
3323
3324 /* PHY TX errors counter. */
3325 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3326
3327 /* OFDM-table address caching. */
3328 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3329 }
3330
3331 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3332 {
3333 dev->dfq_valid = 0;
3334
3335 /* Assume the radio is enabled. If it's not enabled, the state will
3336 * immediately get fixed on the first periodic work run. */
3337 dev->radio_hw_enable = 1;
3338
3339 /* Stats */
3340 memset(&dev->stats, 0, sizeof(dev->stats));
3341
3342 setup_struct_phy_for_init(dev, &dev->phy);
3343
3344 /* IRQ related flags */
3345 dev->irq_reason = 0;
3346 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3347 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3348
3349 dev->mac_suspended = 1;
3350
3351 /* Noise calculation context */
3352 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3353 }
3354
3355 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3356 {
3357 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3358 u32 hf;
3359
3360 if (!modparam_btcoex)
3361 return;
3362 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3363 return;
3364 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3365 return;
3366
3367 hf = b43_hf_read(dev);
3368 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3369 hf |= B43_HF_BTCOEXALT;
3370 else
3371 hf |= B43_HF_BTCOEX;
3372 b43_hf_write(dev, hf);
3373 }
3374
3375 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3376 {
3377 if (!modparam_btcoex)
3378 return;
3379 //TODO
3380 }
3381
3382 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3383 {
3384 #ifdef CONFIG_SSB_DRIVER_PCICORE
3385 struct ssb_bus *bus = dev->dev->bus;
3386 u32 tmp;
3387
3388 if (bus->pcicore.dev &&
3389 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3390 bus->pcicore.dev->id.revision <= 5) {
3391 /* IMCFGLO timeouts workaround. */
3392 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3393 tmp &= ~SSB_IMCFGLO_REQTO;
3394 tmp &= ~SSB_IMCFGLO_SERTO;
3395 switch (bus->bustype) {
3396 case SSB_BUSTYPE_PCI:
3397 case SSB_BUSTYPE_PCMCIA:
3398 tmp |= 0x32;
3399 break;
3400 case SSB_BUSTYPE_SSB:
3401 tmp |= 0x53;
3402 break;
3403 }
3404 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3405 }
3406 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3407 }
3408
3409 /* Write the short and long frame retry limit values. */
3410 static void b43_set_retry_limits(struct b43_wldev *dev,
3411 unsigned int short_retry,
3412 unsigned int long_retry)
3413 {
3414 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3415 * the chip-internal counter. */
3416 short_retry = min(short_retry, (unsigned int)0xF);
3417 long_retry = min(long_retry, (unsigned int)0xF);
3418
3419 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3420 short_retry);
3421 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3422 long_retry);
3423 }
3424
3425 /* Shutdown a wireless core */
3426 /* Locking: wl->mutex */
3427 static void b43_wireless_core_exit(struct b43_wldev *dev)
3428 {
3429 struct b43_phy *phy = &dev->phy;
3430 u32 macctl;
3431
3432 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3433 if (b43_status(dev) != B43_STAT_INITIALIZED)
3434 return;
3435 b43_set_status(dev, B43_STAT_UNINIT);
3436
3437 /* Stop the microcode PSM. */
3438 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3439 macctl &= ~B43_MACCTL_PSM_RUN;
3440 macctl |= B43_MACCTL_PSM_JMP0;
3441 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3442
3443 if (!dev->suspend_in_progress) {
3444 b43_leds_exit(dev);
3445 b43_rng_exit(dev->wl, false);
3446 }
3447 b43_dma_free(dev);
3448 b43_chip_exit(dev);
3449 b43_radio_turn_off(dev, 1);
3450 b43_switch_analog(dev, 0);
3451 if (phy->dyn_tssi_tbl)
3452 kfree(phy->tssi2dbm);
3453 kfree(phy->lo_control);
3454 phy->lo_control = NULL;
3455 if (dev->wl->current_beacon) {
3456 dev_kfree_skb_any(dev->wl->current_beacon);
3457 dev->wl->current_beacon = NULL;
3458 }
3459
3460 ssb_device_disable(dev->dev, 0);
3461 ssb_bus_may_powerdown(dev->dev->bus);
3462 }
3463
3464 /* Initialize a wireless core */
3465 static int b43_wireless_core_init(struct b43_wldev *dev)
3466 {
3467 struct b43_wl *wl = dev->wl;
3468 struct ssb_bus *bus = dev->dev->bus;
3469 struct ssb_sprom *sprom = &bus->sprom;
3470 struct b43_phy *phy = &dev->phy;
3471 int err;
3472 u32 hf, tmp;
3473
3474 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3475
3476 err = ssb_bus_powerup(bus, 0);
3477 if (err)
3478 goto out;
3479 if (!ssb_device_is_enabled(dev->dev)) {
3480 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3481 b43_wireless_core_reset(dev, tmp);
3482 }
3483
3484 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3485 phy->lo_control =
3486 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3487 if (!phy->lo_control) {
3488 err = -ENOMEM;
3489 goto err_busdown;
3490 }
3491 }
3492 setup_struct_wldev_for_init(dev);
3493
3494 err = b43_phy_init_tssi2dbm_table(dev);
3495 if (err)
3496 goto err_kfree_lo_control;
3497
3498 /* Enable IRQ routing to this device. */
3499 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3500
3501 b43_imcfglo_timeouts_workaround(dev);
3502 b43_bluetooth_coext_disable(dev);
3503 b43_phy_early_init(dev);
3504 err = b43_chip_init(dev);
3505 if (err)
3506 goto err_kfree_tssitbl;
3507 b43_shm_write16(dev, B43_SHM_SHARED,
3508 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3509 hf = b43_hf_read(dev);
3510 if (phy->type == B43_PHYTYPE_G) {
3511 hf |= B43_HF_SYMW;
3512 if (phy->rev == 1)
3513 hf |= B43_HF_GDCW;
3514 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3515 hf |= B43_HF_OFDMPABOOST;
3516 } else if (phy->type == B43_PHYTYPE_B) {
3517 hf |= B43_HF_SYMW;
3518 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3519 hf &= ~B43_HF_GDCW;
3520 }
3521 b43_hf_write(dev, hf);
3522
3523 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3524 B43_DEFAULT_LONG_RETRY_LIMIT);
3525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3527
3528 /* Disable sending probe responses from firmware.
3529 * Setting the MaxTime to one usec will always trigger
3530 * a timeout, so we never send any probe resp.
3531 * A timeout of zero is infinite. */
3532 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3533
3534 b43_rate_memory_init(dev);
3535
3536 /* Minimum Contention Window */
3537 if (phy->type == B43_PHYTYPE_B) {
3538 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3539 } else {
3540 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3541 }
3542 /* Maximum Contention Window */
3543 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3544
3545 err = b43_dma_init(dev);
3546 if (err)
3547 goto err_chip_exit;
3548 b43_qos_init(dev);
3549
3550 //FIXME
3551 #if 1
3552 b43_write16(dev, 0x0612, 0x0050);
3553 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3554 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3555 #endif
3556
3557 b43_bluetooth_coext_enable(dev);
3558
3559 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3560 b43_upload_card_macaddress(dev);
3561 b43_security_init(dev);
3562 if (!dev->suspend_in_progress)
3563 b43_rng_init(wl);
3564
3565 b43_set_status(dev, B43_STAT_INITIALIZED);
3566
3567 if (!dev->suspend_in_progress)
3568 b43_leds_init(dev);
3569 out:
3570 return err;
3571
3572 err_chip_exit:
3573 b43_chip_exit(dev);
3574 err_kfree_tssitbl:
3575 if (phy->dyn_tssi_tbl)
3576 kfree(phy->tssi2dbm);
3577 err_kfree_lo_control:
3578 kfree(phy->lo_control);
3579 phy->lo_control = NULL;
3580 err_busdown:
3581 ssb_bus_may_powerdown(bus);
3582 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3583 return err;
3584 }
3585
3586 static int b43_op_add_interface(struct ieee80211_hw *hw,
3587 struct ieee80211_if_init_conf *conf)
3588 {
3589 struct b43_wl *wl = hw_to_b43_wl(hw);
3590 struct b43_wldev *dev;
3591 unsigned long flags;
3592 int err = -EOPNOTSUPP;
3593
3594 /* TODO: allow WDS/AP devices to coexist */
3595
3596 if (conf->type != IEEE80211_IF_TYPE_AP &&
3597 conf->type != IEEE80211_IF_TYPE_STA &&
3598 conf->type != IEEE80211_IF_TYPE_WDS &&
3599 conf->type != IEEE80211_IF_TYPE_IBSS)
3600 return -EOPNOTSUPP;
3601
3602 mutex_lock(&wl->mutex);
3603 if (wl->operating)
3604 goto out_mutex_unlock;
3605
3606 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3607
3608 dev = wl->current_dev;
3609 wl->operating = 1;
3610 wl->vif = conf->vif;
3611 wl->if_type = conf->type;
3612 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3613
3614 spin_lock_irqsave(&wl->irq_lock, flags);
3615 b43_adjust_opmode(dev);
3616 b43_upload_card_macaddress(dev);
3617 spin_unlock_irqrestore(&wl->irq_lock, flags);
3618
3619 err = 0;
3620 out_mutex_unlock:
3621 mutex_unlock(&wl->mutex);
3622
3623 return err;
3624 }
3625
3626 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3627 struct ieee80211_if_init_conf *conf)
3628 {
3629 struct b43_wl *wl = hw_to_b43_wl(hw);
3630 struct b43_wldev *dev = wl->current_dev;
3631 unsigned long flags;
3632
3633 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3634
3635 mutex_lock(&wl->mutex);
3636
3637 B43_WARN_ON(!wl->operating);
3638 B43_WARN_ON(wl->vif != conf->vif);
3639 wl->vif = NULL;
3640
3641 wl->operating = 0;
3642
3643 spin_lock_irqsave(&wl->irq_lock, flags);
3644 b43_adjust_opmode(dev);
3645 memset(wl->mac_addr, 0, ETH_ALEN);
3646 b43_upload_card_macaddress(dev);
3647 spin_unlock_irqrestore(&wl->irq_lock, flags);
3648
3649 mutex_unlock(&wl->mutex);
3650 }
3651
3652 static int b43_op_start(struct ieee80211_hw *hw)
3653 {
3654 struct b43_wl *wl = hw_to_b43_wl(hw);
3655 struct b43_wldev *dev = wl->current_dev;
3656 int did_init = 0;
3657 int err = 0;
3658 bool do_rfkill_exit = 0;
3659
3660 /* Kill all old instance specific information to make sure
3661 * the card won't use it in the short timeframe between start
3662 * and mac80211 reconfiguring it. */
3663 memset(wl->bssid, 0, ETH_ALEN);
3664 memset(wl->mac_addr, 0, ETH_ALEN);
3665 wl->filter_flags = 0;
3666 wl->radiotap_enabled = 0;
3667
3668 /* First register RFkill.
3669 * LEDs that are registered later depend on it. */
3670 b43_rfkill_init(dev);
3671
3672 mutex_lock(&wl->mutex);
3673
3674 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3675 err = b43_wireless_core_init(dev);
3676 if (err) {
3677 do_rfkill_exit = 1;
3678 goto out_mutex_unlock;
3679 }
3680 did_init = 1;
3681 }
3682
3683 if (b43_status(dev) < B43_STAT_STARTED) {
3684 err = b43_wireless_core_start(dev);
3685 if (err) {
3686 if (did_init)
3687 b43_wireless_core_exit(dev);
3688 do_rfkill_exit = 1;
3689 goto out_mutex_unlock;
3690 }
3691 }
3692
3693 out_mutex_unlock:
3694 mutex_unlock(&wl->mutex);
3695
3696 if (do_rfkill_exit)
3697 b43_rfkill_exit(dev);
3698
3699 return err;
3700 }
3701
3702 static void b43_op_stop(struct ieee80211_hw *hw)
3703 {
3704 struct b43_wl *wl = hw_to_b43_wl(hw);
3705 struct b43_wldev *dev = wl->current_dev;
3706
3707 b43_rfkill_exit(dev);
3708
3709 mutex_lock(&wl->mutex);
3710 if (b43_status(dev) >= B43_STAT_STARTED)
3711 b43_wireless_core_stop(dev);
3712 b43_wireless_core_exit(dev);
3713 mutex_unlock(&wl->mutex);
3714 }
3715
3716 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3717 u32 short_retry_limit, u32 long_retry_limit)
3718 {
3719 struct b43_wl *wl = hw_to_b43_wl(hw);
3720 struct b43_wldev *dev;
3721 int err = 0;
3722
3723 mutex_lock(&wl->mutex);
3724 dev = wl->current_dev;
3725 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3726 err = -ENODEV;
3727 goto out_unlock;
3728 }
3729 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3730 out_unlock:
3731 mutex_unlock(&wl->mutex);
3732
3733 return err;
3734 }
3735
3736 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3737 {
3738 struct b43_wl *wl = hw_to_b43_wl(hw);
3739 struct sk_buff *beacon;
3740 unsigned long flags;
3741
3742 /* We could modify the existing beacon and set the aid bit in
3743 * the TIM field, but that would probably require resizing and
3744 * moving of data within the beacon template.
3745 * Simply request a new beacon and let mac80211 do the hard work. */
3746 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3747 if (unlikely(!beacon))
3748 return -ENOMEM;
3749 spin_lock_irqsave(&wl->irq_lock, flags);
3750 b43_update_templates(wl, beacon);
3751 spin_unlock_irqrestore(&wl->irq_lock, flags);
3752
3753 return 0;
3754 }
3755
3756 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3757 struct sk_buff *beacon,
3758 struct ieee80211_tx_control *ctl)
3759 {
3760 struct b43_wl *wl = hw_to_b43_wl(hw);
3761 unsigned long flags;
3762
3763 spin_lock_irqsave(&wl->irq_lock, flags);
3764 b43_update_templates(wl, beacon);
3765 spin_unlock_irqrestore(&wl->irq_lock, flags);
3766
3767 return 0;
3768 }
3769
3770 static const struct ieee80211_ops b43_hw_ops = {
3771 .tx = b43_op_tx,
3772 .conf_tx = b43_op_conf_tx,
3773 .add_interface = b43_op_add_interface,
3774 .remove_interface = b43_op_remove_interface,
3775 .config = b43_op_config,
3776 .config_interface = b43_op_config_interface,
3777 .configure_filter = b43_op_configure_filter,
3778 .set_key = b43_op_set_key,
3779 .get_stats = b43_op_get_stats,
3780 .get_tx_stats = b43_op_get_tx_stats,
3781 .start = b43_op_start,
3782 .stop = b43_op_stop,
3783 .set_retry_limit = b43_op_set_retry_limit,
3784 .set_tim = b43_op_beacon_set_tim,
3785 .beacon_update = b43_op_ibss_beacon_update,
3786 };
3787
3788 /* Hard-reset the chip. Do not call this directly.
3789 * Use b43_controller_restart()
3790 */
3791 static void b43_chip_reset(struct work_struct *work)
3792 {
3793 struct b43_wldev *dev =
3794 container_of(work, struct b43_wldev, restart_work);
3795 struct b43_wl *wl = dev->wl;
3796 int err = 0;
3797 int prev_status;
3798
3799 mutex_lock(&wl->mutex);
3800
3801 prev_status = b43_status(dev);
3802 /* Bring the device down... */
3803 if (prev_status >= B43_STAT_STARTED)
3804 b43_wireless_core_stop(dev);
3805 if (prev_status >= B43_STAT_INITIALIZED)
3806 b43_wireless_core_exit(dev);
3807
3808 /* ...and up again. */
3809 if (prev_status >= B43_STAT_INITIALIZED) {
3810 err = b43_wireless_core_init(dev);
3811 if (err)
3812 goto out;
3813 }
3814 if (prev_status >= B43_STAT_STARTED) {
3815 err = b43_wireless_core_start(dev);
3816 if (err) {
3817 b43_wireless_core_exit(dev);
3818 goto out;
3819 }
3820 }
3821 out:
3822 mutex_unlock(&wl->mutex);
3823 if (err)
3824 b43err(wl, "Controller restart FAILED\n");
3825 else
3826 b43info(wl, "Controller restarted\n");
3827 }
3828
3829 static int b43_setup_modes(struct b43_wldev *dev,
3830 bool have_2ghz_phy, bool have_5ghz_phy)
3831 {
3832 struct ieee80211_hw *hw = dev->wl->hw;
3833 struct ieee80211_hw_mode *mode;
3834 struct b43_phy *phy = &dev->phy;
3835 int err;
3836
3837 /* XXX: This function will go away soon, when mac80211
3838 * band stuff is rewritten. So this is just a hack.
3839 * For now we always claim GPHY mode, as there is no
3840 * support for NPHY and APHY in the device, yet.
3841 * This assumption is OK, as any B, N or A PHY will already
3842 * have died a horrible sanity check death earlier. */
3843
3844 mode = &phy->hwmodes[0];
3845 mode->mode = MODE_IEEE80211G;
3846 mode->num_channels = b43_2ghz_chantable_size;
3847 mode->channels = b43_2ghz_chantable;
3848 mode->num_rates = b43_g_ratetable_size;
3849 mode->rates = b43_g_ratetable;
3850 err = ieee80211_register_hwmode(hw, mode);
3851 if (err)
3852 return err;
3853 phy->possible_phymodes |= B43_PHYMODE_G;
3854
3855 return 0;
3856 }
3857
3858 static void b43_wireless_core_detach(struct b43_wldev *dev)
3859 {
3860 /* We release firmware that late to not be required to re-request
3861 * is all the time when we reinit the core. */
3862 b43_release_firmware(dev);
3863 }
3864
3865 static int b43_wireless_core_attach(struct b43_wldev *dev)
3866 {
3867 struct b43_wl *wl = dev->wl;
3868 struct ssb_bus *bus = dev->dev->bus;
3869 struct pci_dev *pdev = bus->host_pci;
3870 int err;
3871 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3872 u32 tmp;
3873
3874 /* Do NOT do any device initialization here.
3875 * Do it in wireless_core_init() instead.
3876 * This function is for gathering basic information about the HW, only.
3877 * Also some structs may be set up here. But most likely you want to have
3878 * that in core_init(), too.
3879 */
3880
3881 err = ssb_bus_powerup(bus, 0);
3882 if (err) {
3883 b43err(wl, "Bus powerup failed\n");
3884 goto out;
3885 }
3886 /* Get the PHY type. */
3887 if (dev->dev->id.revision >= 5) {
3888 u32 tmshigh;
3889
3890 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3891 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3892 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3893 } else
3894 B43_WARN_ON(1);
3895
3896 dev->phy.gmode = have_2ghz_phy;
3897 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3898 b43_wireless_core_reset(dev, tmp);
3899
3900 err = b43_phy_versioning(dev);
3901 if (err)
3902 goto err_powerdown;
3903 /* Check if this device supports multiband. */
3904 if (!pdev ||
3905 (pdev->device != 0x4312 &&
3906 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3907 /* No multiband support. */
3908 have_2ghz_phy = 0;
3909 have_5ghz_phy = 0;
3910 switch (dev->phy.type) {
3911 case B43_PHYTYPE_A:
3912 have_5ghz_phy = 1;
3913 break;
3914 case B43_PHYTYPE_G:
3915 case B43_PHYTYPE_N:
3916 have_2ghz_phy = 1;
3917 break;
3918 default:
3919 B43_WARN_ON(1);
3920 }
3921 }
3922 if (dev->phy.type == B43_PHYTYPE_A) {
3923 /* FIXME */
3924 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3925 err = -EOPNOTSUPP;
3926 goto err_powerdown;
3927 }
3928 if (1 /* disable A-PHY */) {
3929 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
3930 if (dev->phy.type != B43_PHYTYPE_N) {
3931 have_2ghz_phy = 1;
3932 have_5ghz_phy = 0;
3933 }
3934 }
3935
3936 dev->phy.gmode = have_2ghz_phy;
3937 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3938 b43_wireless_core_reset(dev, tmp);
3939
3940 err = b43_validate_chipaccess(dev);
3941 if (err)
3942 goto err_powerdown;
3943 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3944 if (err)
3945 goto err_powerdown;
3946
3947 /* Now set some default "current_dev" */
3948 if (!wl->current_dev)
3949 wl->current_dev = dev;
3950 INIT_WORK(&dev->restart_work, b43_chip_reset);
3951
3952 b43_radio_turn_off(dev, 1);
3953 b43_switch_analog(dev, 0);
3954 ssb_device_disable(dev->dev, 0);
3955 ssb_bus_may_powerdown(bus);
3956
3957 out:
3958 return err;
3959
3960 err_powerdown:
3961 ssb_bus_may_powerdown(bus);
3962 return err;
3963 }
3964
3965 static void b43_one_core_detach(struct ssb_device *dev)
3966 {
3967 struct b43_wldev *wldev;
3968 struct b43_wl *wl;
3969
3970 wldev = ssb_get_drvdata(dev);
3971 wl = wldev->wl;
3972 cancel_work_sync(&wldev->restart_work);
3973 b43_debugfs_remove_device(wldev);
3974 b43_wireless_core_detach(wldev);
3975 list_del(&wldev->list);
3976 wl->nr_devs--;
3977 ssb_set_drvdata(dev, NULL);
3978 kfree(wldev);
3979 }
3980
3981 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3982 {
3983 struct b43_wldev *wldev;
3984 struct pci_dev *pdev;
3985 int err = -ENOMEM;
3986
3987 if (!list_empty(&wl->devlist)) {
3988 /* We are not the first core on this chip. */
3989 pdev = dev->bus->host_pci;
3990 /* Only special chips support more than one wireless
3991 * core, although some of the other chips have more than
3992 * one wireless core as well. Check for this and
3993 * bail out early.
3994 */
3995 if (!pdev ||
3996 ((pdev->device != 0x4321) &&
3997 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3998 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3999 return -ENODEV;
4000 }
4001 }
4002
4003 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4004 if (!wldev)
4005 goto out;
4006
4007 wldev->dev = dev;
4008 wldev->wl = wl;
4009 b43_set_status(wldev, B43_STAT_UNINIT);
4010 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4011 tasklet_init(&wldev->isr_tasklet,
4012 (void (*)(unsigned long))b43_interrupt_tasklet,
4013 (unsigned long)wldev);
4014 INIT_LIST_HEAD(&wldev->list);
4015
4016 err = b43_wireless_core_attach(wldev);
4017 if (err)
4018 goto err_kfree_wldev;
4019
4020 list_add(&wldev->list, &wl->devlist);
4021 wl->nr_devs++;
4022 ssb_set_drvdata(dev, wldev);
4023 b43_debugfs_add_device(wldev);
4024
4025 out:
4026 return err;
4027
4028 err_kfree_wldev:
4029 kfree(wldev);
4030 return err;
4031 }
4032
4033 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4034 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4035 (pdev->device == _device) && \
4036 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4037 (pdev->subsystem_device == _subdevice) )
4038
4039 static void b43_sprom_fixup(struct ssb_bus *bus)
4040 {
4041 struct pci_dev *pdev;
4042
4043 /* boardflags workarounds */
4044 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4045 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4046 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4047 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4048 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4049 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4050 if (bus->bustype == SSB_BUSTYPE_PCI) {
4051 pdev = bus->host_pci;
4052 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4053 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4054 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4055 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4056 }
4057 }
4058
4059 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4060 {
4061 struct ieee80211_hw *hw = wl->hw;
4062
4063 ssb_set_devtypedata(dev, NULL);
4064 ieee80211_free_hw(hw);
4065 }
4066
4067 static int b43_wireless_init(struct ssb_device *dev)
4068 {
4069 struct ssb_sprom *sprom = &dev->bus->sprom;
4070 struct ieee80211_hw *hw;
4071 struct b43_wl *wl;
4072 int err = -ENOMEM;
4073
4074 b43_sprom_fixup(dev->bus);
4075
4076 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4077 if (!hw) {
4078 b43err(NULL, "Could not allocate ieee80211 device\n");
4079 goto out;
4080 }
4081
4082 /* fill hw info */
4083 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4084 IEEE80211_HW_RX_INCLUDES_FCS;
4085 hw->max_signal = 100;
4086 hw->max_rssi = -110;
4087 hw->max_noise = -110;
4088 hw->queues = 1; /* FIXME: hardware has more queues */
4089 SET_IEEE80211_DEV(hw, dev->dev);
4090 if (is_valid_ether_addr(sprom->et1mac))
4091 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4092 else
4093 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4094
4095 /* Get and initialize struct b43_wl */
4096 wl = hw_to_b43_wl(hw);
4097 memset(wl, 0, sizeof(*wl));
4098 wl->hw = hw;
4099 spin_lock_init(&wl->irq_lock);
4100 rwlock_init(&wl->tx_lock);
4101 spin_lock_init(&wl->leds_lock);
4102 spin_lock_init(&wl->shm_lock);
4103 mutex_init(&wl->mutex);
4104 INIT_LIST_HEAD(&wl->devlist);
4105
4106 ssb_set_devtypedata(dev, wl);
4107 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4108 err = 0;
4109 out:
4110 return err;
4111 }
4112
4113 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4114 {
4115 struct b43_wl *wl;
4116 int err;
4117 int first = 0;
4118
4119 wl = ssb_get_devtypedata(dev);
4120 if (!wl) {
4121 /* Probing the first core. Must setup common struct b43_wl */
4122 first = 1;
4123 err = b43_wireless_init(dev);
4124 if (err)
4125 goto out;
4126 wl = ssb_get_devtypedata(dev);
4127 B43_WARN_ON(!wl);
4128 }
4129 err = b43_one_core_attach(dev, wl);
4130 if (err)
4131 goto err_wireless_exit;
4132
4133 if (first) {
4134 err = ieee80211_register_hw(wl->hw);
4135 if (err)
4136 goto err_one_core_detach;
4137 }
4138
4139 out:
4140 return err;
4141
4142 err_one_core_detach:
4143 b43_one_core_detach(dev);
4144 err_wireless_exit:
4145 if (first)
4146 b43_wireless_exit(dev, wl);
4147 return err;
4148 }
4149
4150 static void b43_remove(struct ssb_device *dev)
4151 {
4152 struct b43_wl *wl = ssb_get_devtypedata(dev);
4153 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4154
4155 B43_WARN_ON(!wl);
4156 if (wl->current_dev == wldev)
4157 ieee80211_unregister_hw(wl->hw);
4158
4159 b43_one_core_detach(dev);
4160
4161 if (list_empty(&wl->devlist)) {
4162 /* Last core on the chip unregistered.
4163 * We can destroy common struct b43_wl.
4164 */
4165 b43_wireless_exit(dev, wl);
4166 }
4167 }
4168
4169 /* Perform a hardware reset. This can be called from any context. */
4170 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4171 {
4172 /* Must avoid requeueing, if we are in shutdown. */
4173 if (b43_status(dev) < B43_STAT_INITIALIZED)
4174 return;
4175 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4176 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4177 }
4178
4179 #ifdef CONFIG_PM
4180
4181 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4182 {
4183 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4184 struct b43_wl *wl = wldev->wl;
4185
4186 b43dbg(wl, "Suspending...\n");
4187
4188 mutex_lock(&wl->mutex);
4189 wldev->suspend_in_progress = true;
4190 wldev->suspend_init_status = b43_status(wldev);
4191 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4192 b43_wireless_core_stop(wldev);
4193 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4194 b43_wireless_core_exit(wldev);
4195 mutex_unlock(&wl->mutex);
4196
4197 b43dbg(wl, "Device suspended.\n");
4198
4199 return 0;
4200 }
4201
4202 static int b43_resume(struct ssb_device *dev)
4203 {
4204 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4205 struct b43_wl *wl = wldev->wl;
4206 int err = 0;
4207
4208 b43dbg(wl, "Resuming...\n");
4209
4210 mutex_lock(&wl->mutex);
4211 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4212 err = b43_wireless_core_init(wldev);
4213 if (err) {
4214 b43err(wl, "Resume failed at core init\n");
4215 goto out;
4216 }
4217 }
4218 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4219 err = b43_wireless_core_start(wldev);
4220 if (err) {
4221 b43_leds_exit(wldev);
4222 b43_rng_exit(wldev->wl, true);
4223 b43_wireless_core_exit(wldev);
4224 b43err(wl, "Resume failed at core start\n");
4225 goto out;
4226 }
4227 }
4228 b43dbg(wl, "Device resumed.\n");
4229 out:
4230 wldev->suspend_in_progress = false;
4231 mutex_unlock(&wl->mutex);
4232 return err;
4233 }
4234
4235 #else /* CONFIG_PM */
4236 # define b43_suspend NULL
4237 # define b43_resume NULL
4238 #endif /* CONFIG_PM */
4239
4240 static struct ssb_driver b43_ssb_driver = {
4241 .name = KBUILD_MODNAME,
4242 .id_table = b43_ssb_tbl,
4243 .probe = b43_probe,
4244 .remove = b43_remove,
4245 .suspend = b43_suspend,
4246 .resume = b43_resume,
4247 };
4248
4249 static void b43_print_driverinfo(void)
4250 {
4251 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4252 *feat_leds = "", *feat_rfkill = "";
4253
4254 #ifdef CONFIG_B43_PCI_AUTOSELECT
4255 feat_pci = "P";
4256 #endif
4257 #ifdef CONFIG_B43_PCMCIA
4258 feat_pcmcia = "M";
4259 #endif
4260 #ifdef CONFIG_B43_NPHY
4261 feat_nphy = "N";
4262 #endif
4263 #ifdef CONFIG_B43_LEDS
4264 feat_leds = "L";
4265 #endif
4266 #ifdef CONFIG_B43_RFKILL
4267 feat_rfkill = "R";
4268 #endif
4269 printk(KERN_INFO "Broadcom 43xx driver loaded "
4270 "[ Features: %s%s%s%s%s, Firmware-ID: "
4271 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4272 feat_pci, feat_pcmcia, feat_nphy,
4273 feat_leds, feat_rfkill);
4274 }
4275
4276 static int __init b43_init(void)
4277 {
4278 int err;
4279
4280 b43_debugfs_init();
4281 err = b43_pcmcia_init();
4282 if (err)
4283 goto err_dfs_exit;
4284 err = ssb_driver_register(&b43_ssb_driver);
4285 if (err)
4286 goto err_pcmcia_exit;
4287 b43_print_driverinfo();
4288
4289 return err;
4290
4291 err_pcmcia_exit:
4292 b43_pcmcia_exit();
4293 err_dfs_exit:
4294 b43_debugfs_exit();
4295 return err;
4296 }
4297
4298 static void __exit b43_exit(void)
4299 {
4300 ssb_driver_unregister(&b43_ssb_driver);
4301 b43_pcmcia_exit();
4302 b43_debugfs_exit();
4303 }
4304
4305 module_init(b43_init)
4306 module_exit(b43_exit)
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